VirtualBox

source: vbox/trunk/src/VBox/VMM/VMM.cpp@ 13691

Last change on this file since 13691 was 13691, checked in by vboxsync, 17 years ago

pg_vmm update.
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1/* $Id: VMM.cpp 13691 2008-10-30 21:16:40Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/** @page pg_vmm VMM - The Virtual Machine Monitor
25 *
26 * The VMM component is two things at the moment, it's a component doing a few
27 * management and routing tasks, and it's the whole virtual machine monitor
28 * thing. For hysterical reasons, it is not doing all the management that one
29 * would expect, this is instead done by @ref pg_vm. We'll address this
30 * misdesign eventually.
31 *
32 * @see grp_vmm, grp_vm
33 *
34 *
35 * @section sec_vmmstate VMM State
36 *
37 * To be written.
38 *
39 * Lets see which of these links that works...
40 * @image "VM Statechart Diagram.gif"
41 * @image VM\ Statechart\ Diagram.gif
42 *
43 * @subsection subsec_vmm_init VMM Initialization
44 *
45 * To be written.
46 *
47 *
48 * @subsection subsec_vmm_term VMM Termination
49 *
50 * To be written.
51 *
52 */
53
54/*******************************************************************************
55* Header Files *
56*******************************************************************************/
57#define LOG_GROUP LOG_GROUP_VMM
58#include <VBox/vmm.h>
59#include <VBox/vmapi.h>
60#include <VBox/pgm.h>
61#include <VBox/cfgm.h>
62#include <VBox/pdmqueue.h>
63#include <VBox/pdmapi.h>
64#include <VBox/cpum.h>
65#include <VBox/mm.h>
66#include <VBox/iom.h>
67#include <VBox/trpm.h>
68#include <VBox/selm.h>
69#include <VBox/em.h>
70#include <VBox/sup.h>
71#include <VBox/dbgf.h>
72#include <VBox/csam.h>
73#include <VBox/patm.h>
74#include <VBox/rem.h>
75#include <VBox/ssm.h>
76#include <VBox/tm.h>
77#include "VMMInternal.h"
78#include "VMMSwitcher/VMMSwitcher.h"
79#include <VBox/vm.h>
80#include <VBox/err.h>
81#include <VBox/param.h>
82#include <VBox/version.h>
83#include <VBox/x86.h>
84#include <VBox/hwaccm.h>
85#include <iprt/assert.h>
86#include <iprt/alloc.h>
87#include <iprt/asm.h>
88#include <iprt/time.h>
89#include <iprt/stream.h>
90#include <iprt/string.h>
91#include <iprt/stdarg.h>
92#include <iprt/ctype.h>
93
94
95
96/** The saved state version. */
97#define VMM_SAVED_STATE_VERSION 3
98
99
100/*******************************************************************************
101* Internal Functions *
102*******************************************************************************/
103static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM);
104static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
105static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser);
106static int vmmR3ServiceCallHostRequest(PVM pVM);
107static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108
109
110/*******************************************************************************
111* Global Variables *
112*******************************************************************************/
113/** Array of switcher defininitions.
114 * The type and index shall match!
115 */
116static PVMMSWITCHERDEF s_apSwitchers[VMMSWITCHER_MAX] =
117{
118 NULL, /* invalid entry */
119#ifndef RT_ARCH_AMD64
120 &vmmR3Switcher32BitTo32Bit_Def,
121 &vmmR3Switcher32BitToPAE_Def,
122 NULL, //&vmmR3Switcher32BitToAMD64_Def,
123 &vmmR3SwitcherPAETo32Bit_Def,
124 &vmmR3SwitcherPAEToPAE_Def,
125 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
126# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
127 &vmmR3SwitcherAMD64ToPAE_Def,
128# else
129 NULL, //&vmmR3SwitcherAMD64ToPAE_Def,
130# endif
131 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
132#else
133 NULL, //&vmmR3Switcher32BitTo32Bit_Def,
134 NULL, //&vmmR3Switcher32BitToPAE_Def,
135 NULL, //&vmmR3Switcher32BitToAMD64_Def,
136 NULL, //&vmmR3SwitcherPAETo32Bit_Def,
137 NULL, //&vmmR3SwitcherPAEToPAE_Def,
138 NULL, //&vmmR3SwitcherPAEToAMD64_Def,
139 &vmmR3SwitcherAMD64ToPAE_Def,
140 NULL //&vmmR3SwitcherAMD64ToAMD64_Def,
141#endif
142};
143
144
145
146/**
147 * Initiates the core code.
148 *
149 * This is core per VM code which might need fixups and/or for ease of use
150 * are put on linear contiguous backing.
151 *
152 * @returns VBox status code.
153 * @param pVM Pointer to VM structure.
154 */
155static int vmmR3InitCoreCode(PVM pVM)
156{
157 /*
158 * Calc the size.
159 */
160 unsigned cbCoreCode = 0;
161 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
162 {
163 pVM->vmm.s.aoffSwitchers[iSwitcher] = cbCoreCode;
164 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
165 if (pSwitcher)
166 {
167 AssertRelease((unsigned)pSwitcher->enmType == iSwitcher);
168 cbCoreCode += RT_ALIGN_32(pSwitcher->cbCode + 1, 32);
169 }
170 }
171
172 /*
173 * Allocate continguous pages for switchers and deal with
174 * conflicts in the intermediate mapping of the code.
175 */
176 pVM->vmm.s.cbCoreCode = RT_ALIGN_32(cbCoreCode, PAGE_SIZE);
177 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
178 int rc = VERR_NO_MEMORY;
179 if (pVM->vmm.s.pvHCCoreCodeR3)
180 {
181 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
182 if (rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT)
183 {
184 /* try more allocations - Solaris */
185 const unsigned cTries = 4112;
186 struct VMMInitBadTry
187 {
188 RTR0PTR pvR0;
189 void *pvR3;
190 RTHCPHYS HCPhys;
191 RTUINT cb;
192 } *paBadTries = (struct VMMInitBadTry *)RTMemTmpAlloc(sizeof(*paBadTries) * cTries);
193 AssertReturn(paBadTries, VERR_NO_TMP_MEMORY);
194 unsigned i = 0;
195 do
196 {
197 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
198 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
199 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
200 i++;
201 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
202 pVM->vmm.s.HCPhysCoreCode = NIL_RTHCPHYS;
203 pVM->vmm.s.pvHCCoreCodeR3 = SUPContAlloc2(pVM->vmm.s.cbCoreCode >> PAGE_SHIFT, &pVM->vmm.s.pvHCCoreCodeR0, &pVM->vmm.s.HCPhysCoreCode);
204 if (!pVM->vmm.s.pvHCCoreCodeR3)
205 break;
206 rc = PGMR3MapIntermediate(pVM, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.HCPhysCoreCode, cbCoreCode);
207 } while ( rc == VERR_PGM_INTERMEDIATE_PAGING_CONFLICT
208 && i < cTries - 1);
209
210 /* cleanup */
211 if (VBOX_FAILURE(rc))
212 {
213 paBadTries[i].pvR3 = pVM->vmm.s.pvHCCoreCodeR3;
214 paBadTries[i].pvR0 = pVM->vmm.s.pvHCCoreCodeR0;
215 paBadTries[i].HCPhys = pVM->vmm.s.HCPhysCoreCode;
216 paBadTries[i].cb = pVM->vmm.s.cbCoreCode;
217 i++;
218 LogRel(("Failed to allocated and map core code: rc=%Vrc\n", rc));
219 }
220 while (i-- > 0)
221 {
222 LogRel(("Core code alloc attempt #%d: pvR3=%p pvR0=%p HCPhys=%VHp\n",
223 i, paBadTries[i].pvR3, paBadTries[i].pvR0, paBadTries[i].HCPhys));
224 SUPContFree(paBadTries[i].pvR3, paBadTries[i].cb >> PAGE_SHIFT);
225 }
226 RTMemTmpFree(paBadTries);
227 }
228 }
229 if (VBOX_SUCCESS(rc))
230 {
231 /*
232 * copy the code.
233 */
234 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
235 {
236 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
237 if (pSwitcher)
238 memcpy((uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + pVM->vmm.s.aoffSwitchers[iSwitcher],
239 pSwitcher->pvCode, pSwitcher->cbCode);
240 }
241
242 /*
243 * Map the code into the GC address space.
244 */
245 RTGCPTR GCPtr;
246 rc = MMR3HyperMapHCPhys(pVM, pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, "Core Code", &GCPtr);
247 if (VBOX_SUCCESS(rc))
248 {
249 pVM->vmm.s.pvGCCoreCode = GCPtr;
250 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
251 LogRel(("CoreCode: R3=%VHv R0=%VHv GC=%VRv Phys=%VHp cb=%#x\n",
252 pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.pvHCCoreCodeR0, pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, pVM->vmm.s.cbCoreCode));
253
254 /*
255 * Finally, PGM probably have selected a switcher already but we need
256 * to do get the addresses so we'll reselect it.
257 * This may legally fail so, we're ignoring the rc.
258 */
259 VMMR3SelectSwitcher(pVM, pVM->vmm.s.enmSwitcher);
260 return rc;
261 }
262
263 /* shit */
264 AssertMsgFailed(("PGMR3Map(,%VRv, %VGp, %#x, 0) failed with rc=%Vrc\n", pVM->vmm.s.pvGCCoreCode, pVM->vmm.s.HCPhysCoreCode, cbCoreCode, rc));
265 SUPContFree(pVM->vmm.s.pvHCCoreCodeR3, pVM->vmm.s.cbCoreCode >> PAGE_SHIFT);
266 }
267 else
268 VMSetError(pVM, rc, RT_SRC_POS,
269 N_("Failed to allocate %d bytes of contiguous memory for the world switcher code"),
270 cbCoreCode);
271
272 pVM->vmm.s.pvHCCoreCodeR3 = NULL;
273 pVM->vmm.s.pvHCCoreCodeR0 = NIL_RTR0PTR;
274 pVM->vmm.s.pvGCCoreCode = 0;
275 return rc;
276}
277
278
279/**
280 * Initializes the VMM.
281 *
282 * @returns VBox status code.
283 * @param pVM The VM to operate on.
284 */
285VMMR3DECL(int) VMMR3Init(PVM pVM)
286{
287 LogFlow(("VMMR3Init\n"));
288
289 /*
290 * Assert alignment, sizes and order.
291 */
292 AssertMsg(pVM->vmm.s.offVM == 0, ("Already initialized!\n"));
293 AssertMsg(sizeof(pVM->vmm.padding) >= sizeof(pVM->vmm.s),
294 ("pVM->vmm.padding is too small! vmm.padding %d while vmm.s is %d\n",
295 sizeof(pVM->vmm.padding), sizeof(pVM->vmm.s)));
296
297 /*
298 * Init basic VM VMM members.
299 */
300 pVM->vmm.s.offVM = RT_OFFSETOF(VM, vmm);
301 int rc = CFGMR3QueryU32(CFGMR3GetRoot(pVM), "YieldEMTInterval", &pVM->vmm.s.cYieldEveryMillies);
302 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
303 pVM->vmm.s.cYieldEveryMillies = 23; /* Value arrived at after experimenting with the grub boot prompt. */
304 //pVM->vmm.s.cYieldEveryMillies = 8; //debugging
305 else
306 AssertMsgRCReturn(rc, ("Configuration error. Failed to query \"YieldEMTInterval\", rc=%Vrc\n", rc), rc);
307
308 /* GC switchers are enabled by default. Turned off by HWACCM. */
309 pVM->vmm.s.fSwitcherDisabled = false;
310
311 /* Get the CPU count.*/
312 rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "NumCPUs", &pVM->cCPUs, 1);
313 AssertLogRelMsgRCReturn(rc, ("Configuration error: Querying \"NumCPUs\" as integer failed, rc=%Vrc\n", rc), rc);
314#ifdef VBOX_WITH_SMP_GUESTS
315 AssertLogRelMsgReturn(pVM->cCPUs > 0 && pVM->cCPUs <= 256,
316 ("Configuration error: \"NumCPUs\"=%RU32 is out of range [1..256]\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
317#else
318 AssertLogRelMsgReturn(pVM->cCPUs != 0,
319 ("Configuration error: \"NumCPUs\"=%RU32, expected 1\n", pVM->cCPUs), VERR_INVALID_PARAMETER);
320#endif
321
322#ifdef VBOX_WITH_SMP_GUESTS
323 LogRel(("[SMP] VMM with %RU32 CPUs\n", pVM->cCPUs));
324#endif
325
326 /*
327 * Register the saved state data unit.
328 */
329 rc = SSMR3RegisterInternal(pVM, "vmm", 1, VMM_SAVED_STATE_VERSION, VMM_STACK_SIZE + sizeof(RTGCPTR),
330 NULL, vmmR3Save, NULL,
331 NULL, vmmR3Load, NULL);
332 if (VBOX_FAILURE(rc))
333 return rc;
334
335 /*
336 * Register the Ring-0 VM handle with the session for fast ioctl calls.
337 */
338 rc = SUPSetVMForFastIOCtl(pVM->pVMR0);
339 if (VBOX_FAILURE(rc))
340 return rc;
341
342 /*
343 * Init core code.
344 */
345 rc = vmmR3InitCoreCode(pVM);
346 if (VBOX_SUCCESS(rc))
347 {
348 /*
349 * Allocate & init VMM GC stack.
350 * The stack pages are also used by the VMM R0 when VMMR0CallHost is invoked.
351 * (The page protection is modifed during R3 init completion.)
352 */
353#ifdef VBOX_STRICT_VMM_STACK
354 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE + PAGE_SIZE + PAGE_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
355#else
356 rc = MMHyperAlloc(pVM, VMM_STACK_SIZE, PAGE_SIZE, MM_TAG_VMM, (void **)&pVM->vmm.s.pbHCStack);
357#endif
358 if (VBOX_SUCCESS(rc))
359 {
360 /* Set HC and GC stack pointers to top of stack. */
361 pVM->vmm.s.CallHostR0JmpBuf.pvSavedStack = (RTR0PTR)pVM->vmm.s.pbHCStack;
362 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
363 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
364 AssertRelease(pVM->vmm.s.pbGCStack);
365
366 /* Set hypervisor eip. */
367 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStack);
368
369 /*
370 * Allocate GC & R0 Logger instances (they are finalized in the relocator).
371 */
372#ifdef LOG_ENABLED
373 PRTLOGGER pLogger = RTLogDefaultInstance();
374 if (pLogger)
375 {
376 pVM->vmm.s.cbLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pLogger->cGroups]);
377 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pLoggerHC);
378 if (VBOX_SUCCESS(rc))
379 {
380 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
381
382/*
383 * Ring-0 logging isn't 100% safe yet (thread id reuse / process exit cleanup), so
384 * you have to sign up here by adding your defined(DEBUG_<userid>) to the #if.
385 *
386 * If you want to log in non-debug modes, you'll have to remember to change SUPDRvShared.c
387 * to not stub all the log functions.
388 *
389 * You might also wish to enable the AssertMsg1/2 overrides in VMMR0.cpp when enabling this.
390 */
391# if defined(DEBUG_sandervl) || defined(DEBUG_frank)
392 rc = MMHyperAlloc(pVM, RT_OFFSETOF(VMMR0LOGGER, Logger.afGroups[pLogger->cGroups]),
393 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pR0Logger);
394 if (VBOX_SUCCESS(rc))
395 {
396 pVM->vmm.s.pR0Logger->pVM = pVM->pVMR0;
397 //pVM->vmm.s.pR0Logger->fCreated = false;
398 pVM->vmm.s.pR0Logger->cbLogger = RT_OFFSETOF(RTLOGGER, afGroups[pLogger->cGroups]);
399 }
400# endif
401 }
402 }
403#endif /* LOG_ENABLED */
404
405#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
406 /*
407 * Allocate GC Release Logger instances (finalized in the relocator).
408 */
409 if (VBOX_SUCCESS(rc))
410 {
411 PRTLOGGER pRelLogger = RTLogRelDefaultInstance();
412 if (pRelLogger)
413 {
414 pVM->vmm.s.cbRelLoggerGC = RT_OFFSETOF(RTLOGGERRC, afGroups[pRelLogger->cGroups]);
415 rc = MMHyperAlloc(pVM, pVM->vmm.s.cbRelLoggerGC, 0, MM_TAG_VMM, (void **)&pVM->vmm.s.pRelLoggerHC);
416 if (VBOX_SUCCESS(rc))
417 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
418 }
419 }
420#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
421
422#ifdef VBOX_WITH_NMI
423 /*
424 * Allocate mapping for the host APIC.
425 */
426 if (VBOX_SUCCESS(rc))
427 {
428 rc = MMR3HyperReserve(pVM, PAGE_SIZE, "Host APIC", &pVM->vmm.s.GCPtrApicBase);
429 AssertRC(rc);
430 }
431#endif
432 if (VBOX_SUCCESS(rc))
433 {
434 rc = RTCritSectInit(&pVM->vmm.s.CritSectVMLock);
435 if (VBOX_SUCCESS(rc))
436 {
437 /*
438 * Debug info.
439 */
440 DBGFR3InfoRegisterInternal(pVM, "ff", "Displays the current Forced actions Flags.", vmmR3InfoFF);
441
442 /*
443 * Statistics.
444 */
445 STAM_REG(pVM, &pVM->vmm.s.StatRunGC, STAMTYPE_COUNTER, "/VMM/RunGC", STAMUNIT_OCCURENCES, "Number of context switches.");
446 STAM_REG(pVM, &pVM->vmm.s.StatGCRetNormal, STAMTYPE_COUNTER, "/VMM/GCRet/Normal", STAMUNIT_OCCURENCES, "Number of VINF_SUCCESS returns.");
447 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterrupt, STAMTYPE_COUNTER, "/VMM/GCRet/Interrupt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT returns.");
448 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptHyper, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptHyper", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_HYPER returns.");
449 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGuestTrap, STAMTYPE_COUNTER, "/VMM/GCRet/GuestTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_GUEST_TRAP returns.");
450 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitch, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitch", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH returns.");
451 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRingSwitchInt, STAMTYPE_COUNTER, "/VMM/GCRet/RingSwitchInt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_RING_SWITCH_INT returns.");
452 STAM_REG(pVM, &pVM->vmm.s.StatGCRetExceptionPrivilege, STAMTYPE_COUNTER, "/VMM/GCRet/ExceptionPrivilege", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EXCEPTION_PRIVILEGED returns.");
453 STAM_REG(pVM, &pVM->vmm.s.StatGCRetStaleSelector, STAMTYPE_COUNTER, "/VMM/GCRet/StaleSelector", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_STALE_SELECTOR returns.");
454 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIRETTrap, STAMTYPE_COUNTER, "/VMM/GCRet/IRETTrap", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_IRET_TRAP returns.");
455 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/Emulate", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION returns.");
456 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchEmulate, STAMTYPE_COUNTER, "/VMM/GCRet/PatchEmulate", STAMUNIT_OCCURENCES, "Number of VINF_PATCH_EMULATE_INSTR returns.");
457 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIORead, STAMTYPE_COUNTER, "/VMM/GCRet/IORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_READ returns.");
458 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/IOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_IOPORT_WRITE returns.");
459 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIORead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIORead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ returns.");
460 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_WRITE returns.");
461 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOReadWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOReadWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_READ_WRITE returns.");
462 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchRead, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchRead", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_READ returns.");
463 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMMIOPatchWrite, STAMTYPE_COUNTER, "/VMM/GCRet/MMIOPatchWrite", STAMUNIT_OCCURENCES, "Number of VINF_IOM_HC_MMIO_PATCH_WRITE returns.");
464 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/LDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_GDT_FAULT returns.");
465 STAM_REG(pVM, &pVM->vmm.s.StatGCRetGDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/GDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_LDT_FAULT returns.");
466 STAM_REG(pVM, &pVM->vmm.s.StatGCRetIDTFault, STAMTYPE_COUNTER, "/VMM/GCRet/IDTFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_IDT_FAULT returns.");
467 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTSSFault, STAMTYPE_COUNTER, "/VMM/GCRet/TSSFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_TSS_FAULT returns.");
468 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDFault, STAMTYPE_COUNTER, "/VMM/GCRet/PDFault", STAMUNIT_OCCURENCES, "Number of VINF_EM_EXECUTE_INSTRUCTION_PD_FAULT returns.");
469 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCSAMTask, STAMTYPE_COUNTER, "/VMM/GCRet/CSAMTask", STAMUNIT_OCCURENCES, "Number of VINF_CSAM_PENDING_ACTION returns.");
470 STAM_REG(pVM, &pVM->vmm.s.StatGCRetSyncCR3, STAMTYPE_COUNTER, "/VMM/GCRet/SyncCR", STAMUNIT_OCCURENCES, "Number of VINF_PGM_SYNC_CR3 returns.");
471 STAM_REG(pVM, &pVM->vmm.s.StatGCRetMisc, STAMTYPE_COUNTER, "/VMM/GCRet/Misc", STAMUNIT_OCCURENCES, "Number of misc returns.");
472 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchInt3, STAMTYPE_COUNTER, "/VMM/GCRet/PatchInt3", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_INT3 returns.");
473 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchPF, STAMTYPE_COUNTER, "/VMM/GCRet/PatchPF", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_PF returns.");
474 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchGP, STAMTYPE_COUNTER, "/VMM/GCRet/PatchGP", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PATCH_TRAP_GP returns.");
475 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPatchIretIRQ, STAMTYPE_COUNTER, "/VMM/GCRet/PatchIret", STAMUNIT_OCCURENCES, "Number of VINF_PATM_PENDING_IRQ_AFTER_IRET returns.");
476 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPageOverflow, STAMTYPE_COUNTER, "/VMM/GCRet/InvlpgOverflow", STAMUNIT_OCCURENCES, "Number of VERR_REM_FLUSHED_PAGES_OVERFLOW returns.");
477 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRescheduleREM, STAMTYPE_COUNTER, "/VMM/GCRet/ScheduleREM", STAMUNIT_OCCURENCES, "Number of VINF_EM_RESCHEDULE_REM returns.");
478 STAM_REG(pVM, &pVM->vmm.s.StatGCRetToR3, STAMTYPE_COUNTER, "/VMM/GCRet/ToR3", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TO_R3 returns.");
479 STAM_REG(pVM, &pVM->vmm.s.StatGCRetTimerPending, STAMTYPE_COUNTER, "/VMM/GCRet/TimerPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_TIMER_PENDING returns.");
480 STAM_REG(pVM, &pVM->vmm.s.StatGCRetInterruptPending, STAMTYPE_COUNTER, "/VMM/GCRet/InterruptPending", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_INTERRUPT_PENDING returns.");
481 STAM_REG(pVM, &pVM->vmm.s.StatGCRetCallHost, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/Misc", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
482 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMGrowRAM, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/GrowRAM", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
483 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PDMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
484 STAM_REG(pVM, &pVM->vmm.s.StatGCRetLogFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/LogFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
485 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPDMQueueFlush, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/QueueFlush", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
486 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMPoolGrow, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMPoolGrow",STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
487 STAM_REG(pVM, &pVM->vmm.s.StatGCRetRemReplay, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/REMReplay", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
488 STAM_REG(pVM, &pVM->vmm.s.StatGCRetVMSetError, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/VMSetError", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
489 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMLock, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/PGMLock", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
490 STAM_REG(pVM, &pVM->vmm.s.StatGCRetHyperAssertion, STAMTYPE_COUNTER, "/VMM/GCRet/CallHost/HyperAssert", STAMUNIT_OCCURENCES, "Number of VINF_VMM_CALL_HOST returns.");
491 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPATMDuplicateFn, STAMTYPE_COUNTER, "/VMM/GCRet/PATMDuplicateFn", STAMUNIT_OCCURENCES, "Number of VINF_PATM_DUPLICATE_FUNCTION returns.");
492 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPGMChangeMode, STAMTYPE_COUNTER, "/VMM/GCRet/PGMChangeMode", STAMUNIT_OCCURENCES, "Number of VINF_PGM_CHANGE_MODE returns.");
493 STAM_REG(pVM, &pVM->vmm.s.StatGCRetEmulHlt, STAMTYPE_COUNTER, "/VMM/GCRet/EmulHlt", STAMUNIT_OCCURENCES, "Number of VINF_EM_RAW_EMULATE_INSTR_HLT returns.");
494 STAM_REG(pVM, &pVM->vmm.s.StatGCRetPendingRequest, STAMTYPE_COUNTER, "/VMM/GCRet/PendingRequest", STAMUNIT_OCCURENCES, "Number of VINF_EM_PENDING_REQUEST returns.");
495
496 return VINF_SUCCESS;
497 }
498 AssertRC(rc);
499 }
500 }
501 /** @todo: Need failure cleanup. */
502
503 //more todo in here?
504 //if (VBOX_SUCCESS(rc))
505 //{
506 //}
507 //int rc2 = vmmR3TermCoreCode(pVM);
508 //AssertRC(rc2));
509 }
510
511 return rc;
512}
513
514
515/**
516 * Ring-3 init finalizing.
517 *
518 * @returns VBox status code.
519 * @param pVM The VM handle.
520 */
521VMMR3DECL(int) VMMR3InitFinalize(PVM pVM)
522{
523#ifdef VBOX_STRICT_VMM_STACK
524 /*
525 * Two inaccessible pages at each sides of the stack to catch over/under-flows.
526 */
527 memset(pVM->vmm.s.pbHCStack - PAGE_SIZE, 0xcc, PAGE_SIZE);
528 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack - PAGE_SIZE), PAGE_SIZE, 0);
529 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
530
531 memset(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, 0xcc, PAGE_SIZE);
532 PGMMapSetPage(pVM, MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack + VMM_STACK_SIZE), PAGE_SIZE, 0);
533 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_NONE);
534#endif
535
536 /*
537 * Set page attributes to r/w for stack pages.
538 */
539 int rc = PGMMapSetPage(pVM, pVM->vmm.s.pbGCStack, VMM_STACK_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D | X86_PTE_RW);
540 AssertRC(rc);
541 if (VBOX_SUCCESS(rc))
542 {
543 /*
544 * Create the EMT yield timer.
545 */
546 rc = TMR3TimerCreateInternal(pVM, TMCLOCK_REAL, vmmR3YieldEMT, NULL, "EMT Yielder", &pVM->vmm.s.pYieldTimer);
547 if (VBOX_SUCCESS(rc))
548 rc = TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldEveryMillies);
549 }
550#ifdef VBOX_WITH_NMI
551 /*
552 * Map the host APIC into GC - This may be host os specific!
553 */
554 if (VBOX_SUCCESS(rc))
555 rc = PGMMap(pVM, pVM->vmm.s.GCPtrApicBase, 0xfee00000, PAGE_SIZE,
556 X86_PTE_P | X86_PTE_RW | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_A | X86_PTE_D);
557#endif
558 return rc;
559}
560
561
562/**
563 * Initializes the R0 VMM.
564 *
565 * @returns VBox status code.
566 * @param pVM The VM to operate on.
567 */
568VMMR3DECL(int) VMMR3InitR0(PVM pVM)
569{
570 int rc;
571
572 /*
573 * Initialize the ring-0 logger if we haven't done so yet.
574 */
575 if ( pVM->vmm.s.pR0Logger
576 && !pVM->vmm.s.pR0Logger->fCreated)
577 {
578 rc = VMMR3UpdateLoggers(pVM);
579 if (VBOX_FAILURE(rc))
580 return rc;
581 }
582
583 /*
584 * Call Ring-0 entry with init code.
585 */
586 for (;;)
587 {
588#ifdef NO_SUPCALLR0VMM
589 //rc = VERR_GENERAL_FAILURE;
590 rc = VINF_SUCCESS;
591#else
592 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_INIT, VMMGetSvnRev(), NULL);
593#endif
594 if ( pVM->vmm.s.pR0Logger
595 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
596 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
597 if (rc != VINF_VMM_CALL_HOST)
598 break;
599 rc = vmmR3ServiceCallHostRequest(pVM);
600 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
601 break;
602 /* Resume R0 */
603 }
604
605 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
606 {
607 LogRel(("R0 init failed, rc=%Vra\n", rc));
608 if (VBOX_SUCCESS(rc))
609 rc = VERR_INTERNAL_ERROR;
610 }
611 return rc;
612}
613
614
615/**
616 * Initializes the GC VMM.
617 *
618 * @returns VBox status code.
619 * @param pVM The VM to operate on.
620 */
621VMMR3DECL(int) VMMR3InitGC(PVM pVM)
622{
623 /* In VMX mode, there's no need to init GC. */
624 if (pVM->vmm.s.fSwitcherDisabled)
625 return VINF_SUCCESS;
626
627 /*
628 * Call VMMGCInit():
629 * -# resolve the address.
630 * -# setup stackframe and EIP to use the trampoline.
631 * -# do a generic hypervisor call.
632 */
633 RTGCPTR32 GCPtrEP;
634 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &GCPtrEP);
635 if (VBOX_SUCCESS(rc))
636 {
637 CPUMHyperSetCtxCore(pVM, NULL);
638 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom); /* Clear the stack. */
639 uint64_t u64TS = RTTimeProgramStartNanoTS();
640 CPUMPushHyper(pVM, (uint32_t)(u64TS >> 32)); /* Param 3: The program startup TS - Hi. */
641 CPUMPushHyper(pVM, (uint32_t)u64TS); /* Param 3: The program startup TS - Lo. */
642 CPUMPushHyper(pVM, VMMGetSvnRev()); /* Param 2: Version argument. */
643 CPUMPushHyper(pVM, VMMGC_DO_VMMGC_INIT); /* Param 1: Operation. */
644 CPUMPushHyper(pVM, pVM->pVMGC); /* Param 0: pVM */
645 CPUMPushHyper(pVM, 3 * sizeof(RTGCPTR32)); /* trampoline param: stacksize. */
646 CPUMPushHyper(pVM, GCPtrEP); /* Call EIP. */
647 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
648
649 for (;;)
650 {
651#ifdef NO_SUPCALLR0VMM
652 //rc = VERR_GENERAL_FAILURE;
653 rc = VINF_SUCCESS;
654#else
655 rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_CALL_HYPERVISOR, NULL);
656#endif
657#ifdef LOG_ENABLED
658 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
659 if ( pLogger
660 && pLogger->offScratch > 0)
661 RTLogFlushGC(NULL, pLogger);
662#endif
663#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
664 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
665 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
666 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
667#endif
668 if (rc != VINF_VMM_CALL_HOST)
669 break;
670 rc = vmmR3ServiceCallHostRequest(pVM);
671 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
672 break;
673 }
674
675 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
676 {
677 VMMR3FatalDump(pVM, rc);
678 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
679 rc = VERR_INTERNAL_ERROR;
680 }
681 AssertRC(rc);
682 }
683 return rc;
684}
685
686
687/**
688 * Terminate the VMM bits.
689 *
690 * @returns VINF_SUCCESS.
691 * @param pVM The VM handle.
692 */
693VMMR3DECL(int) VMMR3Term(PVM pVM)
694{
695 /*
696 * Call Ring-0 entry with termination code.
697 */
698 int rc;
699 for (;;)
700 {
701#ifdef NO_SUPCALLR0VMM
702 //rc = VERR_GENERAL_FAILURE;
703 rc = VINF_SUCCESS;
704#else
705 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_VMMR0_TERM, 0, NULL);
706#endif
707 if ( pVM->vmm.s.pR0Logger
708 && pVM->vmm.s.pR0Logger->Logger.offScratch > 0)
709 RTLogFlushToLogger(&pVM->vmm.s.pR0Logger->Logger, NULL);
710 if (rc != VINF_VMM_CALL_HOST)
711 break;
712 rc = vmmR3ServiceCallHostRequest(pVM);
713 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
714 break;
715 /* Resume R0 */
716 }
717 if (VBOX_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
718 {
719 LogRel(("VMMR3Term: R0 term failed, rc=%Vra. (warning)\n", rc));
720 if (VBOX_SUCCESS(rc))
721 rc = VERR_INTERNAL_ERROR;
722 }
723
724#ifdef VBOX_STRICT_VMM_STACK
725 /*
726 * Make the two stack guard pages present again.
727 */
728 RTMemProtect(pVM->vmm.s.pbHCStack - PAGE_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
729 RTMemProtect(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE, PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
730#endif
731 return rc;
732}
733
734
735/**
736 * Applies relocations to data and code managed by this
737 * component. This function will be called at init and
738 * whenever the VMM need to relocate it self inside the GC.
739 *
740 * The VMM will need to apply relocations to the core code.
741 *
742 * @param pVM The VM handle.
743 * @param offDelta The relocation delta.
744 */
745VMMR3DECL(void) VMMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
746{
747 LogFlow(("VMMR3Relocate: offDelta=%VGv\n", offDelta));
748
749 /*
750 * Recalc the GC address.
751 */
752 pVM->vmm.s.pvGCCoreCode = MMHyperHC2GC(pVM, pVM->vmm.s.pvHCCoreCodeR3);
753
754 /*
755 * The stack.
756 */
757 CPUMSetHyperESP(pVM, CPUMGetHyperESP(pVM) + offDelta);
758 pVM->vmm.s.pbGCStack = MMHyperHC2GC(pVM, pVM->vmm.s.pbHCStack);
759 pVM->vmm.s.pbGCStackBottom = pVM->vmm.s.pbGCStack + VMM_STACK_SIZE;
760
761 /*
762 * All the switchers.
763 */
764 for (unsigned iSwitcher = 0; iSwitcher < RT_ELEMENTS(s_apSwitchers); iSwitcher++)
765 {
766 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[iSwitcher];
767 if (pSwitcher && pSwitcher->pfnRelocate)
768 {
769 unsigned off = pVM->vmm.s.aoffSwitchers[iSwitcher];
770 pSwitcher->pfnRelocate(pVM,
771 pSwitcher,
772 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR0 + off,
773 (uint8_t *)pVM->vmm.s.pvHCCoreCodeR3 + off,
774 pVM->vmm.s.pvGCCoreCode + off,
775 pVM->vmm.s.HCPhysCoreCode + off);
776 }
777 }
778
779 /*
780 * Recalc the GC address for the current switcher.
781 */
782 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[pVM->vmm.s.enmSwitcher];
783 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[pVM->vmm.s.enmSwitcher];
784 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
785 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
786 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
787 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
788 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
789
790 /*
791 * Get other GC entry points.
792 */
793 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuest", &pVM->vmm.s.pfnCPUMGCResumeGuest);
794 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuest not found! rc=%Vra\n", rc));
795
796 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "CPUMGCResumeGuestV86", &pVM->vmm.s.pfnCPUMGCResumeGuestV86);
797 AssertReleaseMsgRC(rc, ("CPUMGCResumeGuestV86 not found! rc=%Vra\n", rc));
798
799 /*
800 * Update the logger.
801 */
802 VMMR3UpdateLoggers(pVM);
803}
804
805
806/**
807 * Updates the settings for the GC and R0 loggers.
808 *
809 * @returns VBox status code.
810 * @param pVM The VM handle.
811 */
812VMMR3DECL(int) VMMR3UpdateLoggers(PVM pVM)
813{
814 /*
815 * Simply clone the logger instance (for GC).
816 */
817 int rc = VINF_SUCCESS;
818 RTGCPTR32 GCPtrLoggerFlush = 0;
819
820 if (pVM->vmm.s.pLoggerHC
821#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
822 || pVM->vmm.s.pRelLoggerHC
823#endif
824 )
825 {
826 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerFlush", &GCPtrLoggerFlush);
827 AssertReleaseMsgRC(rc, ("vmmGCLoggerFlush not found! rc=%Vra\n", rc));
828 }
829
830 if (pVM->vmm.s.pLoggerHC)
831 {
832 RTGCPTR32 GCPtrLoggerWrapper = 0;
833 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCLoggerWrapper", &GCPtrLoggerWrapper);
834 AssertReleaseMsgRC(rc, ("vmmGCLoggerWrapper not found! rc=%Vra\n", rc));
835 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
836 rc = RTLogCloneRC(NULL /* default */, pVM->vmm.s.pLoggerHC, pVM->vmm.s.cbLoggerGC,
837 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
838 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
839 }
840
841#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
842 if (pVM->vmm.s.pRelLoggerHC)
843 {
844 RTGCPTR32 GCPtrLoggerWrapper = 0;
845 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "vmmGCRelLoggerWrapper", &GCPtrLoggerWrapper);
846 AssertReleaseMsgRC(rc, ("vmmGCRelLoggerWrapper not found! rc=%Vra\n", rc));
847 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
848 rc = RTLogCloneRC(RTLogRelDefaultInstance(), pVM->vmm.s.pRelLoggerHC, pVM->vmm.s.cbRelLoggerGC,
849 GCPtrLoggerWrapper, GCPtrLoggerFlush, RTLOGFLAGS_BUFFERED);
850 AssertReleaseMsgRC(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc));
851 }
852#endif /* VBOX_WITH_GC_AND_R0_RELEASE_LOG */
853
854 /*
855 * For the ring-0 EMT logger, we use a per-thread logger
856 * instance in ring-0. Only initialize it once.
857 */
858 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
859 if (pR0Logger)
860 {
861 if (!pR0Logger->fCreated)
862 {
863 RTR0PTR pfnLoggerWrapper = NIL_RTR0PTR;
864 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerWrapper", &pfnLoggerWrapper);
865 AssertReleaseMsgRCReturn(rc, ("VMMLoggerWrapper not found! rc=%Vra\n", rc), rc);
866
867 RTR0PTR pfnLoggerFlush = NIL_RTR0PTR;
868 rc = PDMR3LdrGetSymbolR0(pVM, VMMR0_MAIN_MODULE_NAME, "vmmR0LoggerFlush", &pfnLoggerFlush);
869 AssertReleaseMsgRCReturn(rc, ("VMMLoggerFlush not found! rc=%Vra\n", rc), rc);
870
871 rc = RTLogCreateForR0(&pR0Logger->Logger, pR0Logger->cbLogger,
872 *(PFNRTLOGGER *)&pfnLoggerWrapper, *(PFNRTLOGFLUSH *)&pfnLoggerFlush,
873 RTLOGFLAGS_BUFFERED, RTLOGDEST_DUMMY);
874 AssertReleaseMsgRCReturn(rc, ("RTLogCloneGC failed! rc=%Vra\n", rc), rc);
875 pR0Logger->fCreated = true;
876 }
877
878 rc = RTLogCopyGroupsAndFlags(&pR0Logger->Logger, NULL /* default */, pVM->vmm.s.pLoggerHC->fFlags, RTLOGFLAGS_BUFFERED);
879 AssertRC(rc);
880 }
881
882 return rc;
883}
884
885
886/**
887 * Generic switch code relocator.
888 *
889 * @param pVM The VM handle.
890 * @param pSwitcher The switcher definition.
891 * @param pu8CodeR3 Pointer to the core code block for the switcher, ring-3 mapping.
892 * @param pu8CodeR0 Pointer to the core code block for the switcher, ring-0 mapping.
893 * @param GCPtrCode The guest context address corresponding to pu8Code.
894 * @param u32IDCode The identity mapped (ID) address corresponding to pu8Code.
895 * @param SelCS The hypervisor CS selector.
896 * @param SelDS The hypervisor DS selector.
897 * @param SelTSS The hypervisor TSS selector.
898 * @param GCPtrGDT The GC address of the hypervisor GDT.
899 * @param SelCS64 The 64-bit mode hypervisor CS selector.
900 */
901static void vmmR3SwitcherGenericRelocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode,
902 RTSEL SelCS, RTSEL SelDS, RTSEL SelTSS, RTGCPTR GCPtrGDT, RTSEL SelCS64)
903{
904 union
905 {
906 const uint8_t *pu8;
907 const uint16_t *pu16;
908 const uint32_t *pu32;
909 const uint64_t *pu64;
910 const void *pv;
911 uintptr_t u;
912 } u;
913 u.pv = pSwitcher->pvFixups;
914
915 /*
916 * Process fixups.
917 */
918 uint8_t u8;
919 while ((u8 = *u.pu8++) != FIX_THE_END)
920 {
921 /*
922 * Get the source (where to write the fixup).
923 */
924 uint32_t offSrc = *u.pu32++;
925 Assert(offSrc < pSwitcher->cbCode);
926 union
927 {
928 uint8_t *pu8;
929 uint16_t *pu16;
930 uint32_t *pu32;
931 uint64_t *pu64;
932 uintptr_t u;
933 } uSrc;
934 uSrc.pu8 = pu8CodeR3 + offSrc;
935
936 /* The fixup target and method depends on the type. */
937 switch (u8)
938 {
939 /*
940 * 32-bit relative, source in HC and target in GC.
941 */
942 case FIX_HC_2_GC_NEAR_REL:
943 {
944 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
945 uint32_t offTrg = *u.pu32++;
946 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
947 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (uSrc.u + 4));
948 break;
949 }
950
951 /*
952 * 32-bit relative, source in HC and target in ID.
953 */
954 case FIX_HC_2_ID_NEAR_REL:
955 {
956 Assert(offSrc - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offSrc - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
957 uint32_t offTrg = *u.pu32++;
958 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
959 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - ((uintptr_t)pu8CodeR0 + offSrc + 4));
960 break;
961 }
962
963 /*
964 * 32-bit relative, source in GC and target in HC.
965 */
966 case FIX_GC_2_HC_NEAR_REL:
967 {
968 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
969 uint32_t offTrg = *u.pu32++;
970 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
971 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (GCPtrCode + offSrc + 4));
972 break;
973 }
974
975 /*
976 * 32-bit relative, source in GC and target in ID.
977 */
978 case FIX_GC_2_ID_NEAR_REL:
979 {
980 Assert(offSrc - pSwitcher->offGCCode < pSwitcher->cbGCCode);
981 uint32_t offTrg = *u.pu32++;
982 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
983 *uSrc.pu32 = (uint32_t)((u32IDCode + offTrg) - (GCPtrCode + offSrc + 4));
984 break;
985 }
986
987 /*
988 * 32-bit relative, source in ID and target in HC.
989 */
990 case FIX_ID_2_HC_NEAR_REL:
991 {
992 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
993 uint32_t offTrg = *u.pu32++;
994 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
995 *uSrc.pu32 = (uint32_t)(((uintptr_t)pu8CodeR0 + offTrg) - (u32IDCode + offSrc + 4));
996 break;
997 }
998
999 /*
1000 * 32-bit relative, source in ID and target in HC.
1001 */
1002 case FIX_ID_2_GC_NEAR_REL:
1003 {
1004 Assert(offSrc - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offSrc - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1005 uint32_t offTrg = *u.pu32++;
1006 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1007 *uSrc.pu32 = (uint32_t)((GCPtrCode + offTrg) - (u32IDCode + offSrc + 4));
1008 break;
1009 }
1010
1011 /*
1012 * 16:32 far jump, target in GC.
1013 */
1014 case FIX_GC_FAR32:
1015 {
1016 uint32_t offTrg = *u.pu32++;
1017 Assert(offTrg - pSwitcher->offGCCode < pSwitcher->cbGCCode);
1018 *uSrc.pu32++ = (uint32_t)(GCPtrCode + offTrg);
1019 *uSrc.pu16++ = SelCS;
1020 break;
1021 }
1022
1023 /*
1024 * Make 32-bit GC pointer given CPUM offset.
1025 */
1026 case FIX_GC_CPUM_OFF:
1027 {
1028 uint32_t offCPUM = *u.pu32++;
1029 Assert(offCPUM < sizeof(pVM->cpum));
1030 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, &pVM->cpum) + offCPUM);
1031 break;
1032 }
1033
1034 /*
1035 * Make 32-bit GC pointer given VM offset.
1036 */
1037 case FIX_GC_VM_OFF:
1038 {
1039 uint32_t offVM = *u.pu32++;
1040 Assert(offVM < sizeof(VM));
1041 *uSrc.pu32 = (uint32_t)(VM_GUEST_ADDR(pVM, pVM) + offVM);
1042 break;
1043 }
1044
1045 /*
1046 * Make 32-bit HC pointer given CPUM offset.
1047 */
1048 case FIX_HC_CPUM_OFF:
1049 {
1050 uint32_t offCPUM = *u.pu32++;
1051 Assert(offCPUM < sizeof(pVM->cpum));
1052 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + RT_OFFSETOF(VM, cpum) + offCPUM;
1053 break;
1054 }
1055
1056 /*
1057 * Make 32-bit R0 pointer given VM offset.
1058 */
1059 case FIX_HC_VM_OFF:
1060 {
1061 uint32_t offVM = *u.pu32++;
1062 Assert(offVM < sizeof(VM));
1063 *uSrc.pu32 = (uint32_t)pVM->pVMR0 + offVM;
1064 break;
1065 }
1066
1067 /*
1068 * Store the 32-Bit CR3 (32-bit) for the intermediate memory context.
1069 */
1070 case FIX_INTER_32BIT_CR3:
1071 {
1072
1073 *uSrc.pu32 = PGMGetInter32BitCR3(pVM);
1074 break;
1075 }
1076
1077 /*
1078 * Store the PAE CR3 (32-bit) for the intermediate memory context.
1079 */
1080 case FIX_INTER_PAE_CR3:
1081 {
1082
1083 *uSrc.pu32 = PGMGetInterPaeCR3(pVM);
1084 break;
1085 }
1086
1087 /*
1088 * Store the AMD64 CR3 (32-bit) for the intermediate memory context.
1089 */
1090 case FIX_INTER_AMD64_CR3:
1091 {
1092
1093 *uSrc.pu32 = PGMGetInterAmd64CR3(pVM);
1094 break;
1095 }
1096
1097 /*
1098 * Store the 32-Bit CR3 (32-bit) for the hypervisor (shadow) memory context.
1099 */
1100 case FIX_HYPER_32BIT_CR3:
1101 {
1102
1103 *uSrc.pu32 = PGMGetHyper32BitCR3(pVM);
1104 break;
1105 }
1106
1107 /*
1108 * Store the PAE CR3 (32-bit) for the hypervisor (shadow) memory context.
1109 */
1110 case FIX_HYPER_PAE_CR3:
1111 {
1112
1113 *uSrc.pu32 = PGMGetHyperPaeCR3(pVM);
1114 break;
1115 }
1116
1117 /*
1118 * Store the AMD64 CR3 (32-bit) for the hypervisor (shadow) memory context.
1119 */
1120 case FIX_HYPER_AMD64_CR3:
1121 {
1122
1123 *uSrc.pu32 = PGMGetHyperAmd64CR3(pVM);
1124 break;
1125 }
1126
1127 /*
1128 * Store Hypervisor CS (16-bit).
1129 */
1130 case FIX_HYPER_CS:
1131 {
1132 *uSrc.pu16 = SelCS;
1133 break;
1134 }
1135
1136 /*
1137 * Store Hypervisor DS (16-bit).
1138 */
1139 case FIX_HYPER_DS:
1140 {
1141 *uSrc.pu16 = SelDS;
1142 break;
1143 }
1144
1145 /*
1146 * Store Hypervisor TSS (16-bit).
1147 */
1148 case FIX_HYPER_TSS:
1149 {
1150 *uSrc.pu16 = SelTSS;
1151 break;
1152 }
1153
1154 /*
1155 * Store the 32-bit GC address of the 2nd dword of the TSS descriptor (in the GDT).
1156 */
1157 case FIX_GC_TSS_GDTE_DW2:
1158 {
1159 RTGCPTR GCPtr = GCPtrGDT + (SelTSS & ~7) + 4;
1160 *uSrc.pu32 = (uint32_t)GCPtr;
1161 break;
1162 }
1163
1164
1165 ///@todo case FIX_CR4_MASK:
1166 ///@todo case FIX_CR4_OSFSXR:
1167
1168 /*
1169 * Insert relative jump to specified target it FXSAVE/FXRSTOR isn't supported by the cpu.
1170 */
1171 case FIX_NO_FXSAVE_JMP:
1172 {
1173 uint32_t offTrg = *u.pu32++;
1174 Assert(offTrg < pSwitcher->cbCode);
1175 if (!CPUMSupportsFXSR(pVM))
1176 {
1177 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1178 *uSrc.pu32++ = offTrg - (offSrc + 5);
1179 }
1180 else
1181 {
1182 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1183 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1184 }
1185 break;
1186 }
1187
1188 /*
1189 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1190 */
1191 case FIX_NO_SYSENTER_JMP:
1192 {
1193 uint32_t offTrg = *u.pu32++;
1194 Assert(offTrg < pSwitcher->cbCode);
1195 if (!CPUMIsHostUsingSysEnter(pVM))
1196 {
1197 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1198 *uSrc.pu32++ = offTrg - (offSrc + 5);
1199 }
1200 else
1201 {
1202 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1203 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1204 }
1205 break;
1206 }
1207
1208 /*
1209 * Insert relative jump to specified target it SYSENTER isn't used by the host.
1210 */
1211 case FIX_NO_SYSCALL_JMP:
1212 {
1213 uint32_t offTrg = *u.pu32++;
1214 Assert(offTrg < pSwitcher->cbCode);
1215 if (!CPUMIsHostUsingSysEnter(pVM))
1216 {
1217 *uSrc.pu8++ = 0xe9; /* jmp rel32 */
1218 *uSrc.pu32++ = offTrg - (offSrc + 5);
1219 }
1220 else
1221 {
1222 *uSrc.pu8++ = *((uint8_t *)pSwitcher->pvCode + offSrc);
1223 *uSrc.pu32++ = *(uint32_t *)((uint8_t *)pSwitcher->pvCode + offSrc + 1);
1224 }
1225 break;
1226 }
1227
1228 /*
1229 * 32-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1230 */
1231 case FIX_HC_32BIT:
1232 {
1233 uint32_t offTrg = *u.pu32++;
1234 Assert(offSrc < pSwitcher->cbCode);
1235 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1236 *uSrc.pu32 = (uintptr_t)pu8CodeR0 + offTrg;
1237 break;
1238 }
1239
1240#if defined(RT_ARCH_AMD64) || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1241 /*
1242 * 64-bit HC pointer fixup to (HC) target within the code (32-bit offset).
1243 */
1244 case FIX_HC_64BIT:
1245 {
1246 uint32_t offTrg = *u.pu32++;
1247 Assert(offSrc < pSwitcher->cbCode);
1248 Assert(offTrg - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0 || offTrg - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1);
1249 *uSrc.pu64 = (uintptr_t)pu8CodeR0 + offTrg;
1250 break;
1251 }
1252
1253 /*
1254 * 64-bit HC Code Selector (no argument).
1255 */
1256 case FIX_HC_64BIT_CS:
1257 {
1258 Assert(offSrc < pSwitcher->cbCode);
1259#if defined(RT_OS_DARWIN) && defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1260 *uSrc.pu16 = 0x80; /* KERNEL64_CS from i386/seg.h */
1261#else
1262 AssertFatalMsgFailed(("FIX_HC_64BIT_CS not implemented for this host\n"));
1263#endif
1264 break;
1265 }
1266
1267 /*
1268 * 64-bit HC pointer to the CPUM instance data (no argument).
1269 */
1270 case FIX_HC_64BIT_CPUM:
1271 {
1272 Assert(offSrc < pSwitcher->cbCode);
1273 *uSrc.pu64 = pVM->pVMR0 + RT_OFFSETOF(VM, cpum);
1274 break;
1275 }
1276#endif
1277
1278 /*
1279 * 32-bit ID pointer to (ID) target within the code (32-bit offset).
1280 */
1281 case FIX_ID_32BIT:
1282 {
1283 uint32_t offTrg = *u.pu32++;
1284 Assert(offSrc < pSwitcher->cbCode);
1285 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1286 *uSrc.pu32 = u32IDCode + offTrg;
1287 break;
1288 }
1289
1290 /*
1291 * 64-bit ID pointer to (ID) target within the code (32-bit offset).
1292 */
1293 case FIX_ID_64BIT:
1294 {
1295 uint32_t offTrg = *u.pu32++;
1296 Assert(offSrc < pSwitcher->cbCode);
1297 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1298 *uSrc.pu64 = u32IDCode + offTrg;
1299 break;
1300 }
1301
1302 /*
1303 * Far 16:32 ID pointer to 64-bit mode (ID) target within the code (32-bit offset).
1304 */
1305 case FIX_ID_FAR32_TO_64BIT_MODE:
1306 {
1307 uint32_t offTrg = *u.pu32++;
1308 Assert(offSrc < pSwitcher->cbCode);
1309 Assert(offTrg - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0 || offTrg - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1);
1310 *uSrc.pu32++ = u32IDCode + offTrg;
1311 *uSrc.pu16 = SelCS64;
1312 AssertRelease(SelCS64);
1313 break;
1314 }
1315
1316#ifdef VBOX_WITH_NMI
1317 /*
1318 * 32-bit address to the APIC base.
1319 */
1320 case FIX_GC_APIC_BASE_32BIT:
1321 {
1322 *uSrc.pu32 = pVM->vmm.s.GCPtrApicBase;
1323 break;
1324 }
1325#endif
1326
1327 default:
1328 AssertReleaseMsgFailed(("Unknown fixup %d in switcher %s\n", u8, pSwitcher->pszDesc));
1329 break;
1330 }
1331 }
1332
1333#ifdef LOG_ENABLED
1334 /*
1335 * If Log2 is enabled disassemble the switcher code.
1336 *
1337 * The switcher code have 1-2 HC parts, 1 GC part and 0-2 ID parts.
1338 */
1339 if (LogIs2Enabled())
1340 {
1341 RTLogPrintf("*** Disassembly of switcher %d '%s' %#x bytes ***\n"
1342 " pu8CodeR0 = %p\n"
1343 " pu8CodeR3 = %p\n"
1344 " GCPtrCode = %VGv\n"
1345 " u32IDCode = %08x\n"
1346 " pVMGC = %VGv\n"
1347 " pCPUMGC = %VGv\n"
1348 " pVMHC = %p\n"
1349 " pCPUMHC = %p\n"
1350 " GCPtrGDT = %VGv\n"
1351 " InterCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1352 " HyperCR3s = %08x, %08x, %08x (32-Bit, PAE, AMD64)\n"
1353 " SelCS = %04x\n"
1354 " SelDS = %04x\n"
1355 " SelCS64 = %04x\n"
1356 " SelTSS = %04x\n",
1357 pSwitcher->enmType, pSwitcher->pszDesc, pSwitcher->cbCode,
1358 pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode, VM_GUEST_ADDR(pVM, pVM),
1359 VM_GUEST_ADDR(pVM, &pVM->cpum), pVM, &pVM->cpum,
1360 GCPtrGDT,
1361 PGMGetHyper32BitCR3(pVM), PGMGetHyperPaeCR3(pVM), PGMGetHyperAmd64CR3(pVM),
1362 PGMGetInter32BitCR3(pVM), PGMGetInterPaeCR3(pVM), PGMGetInterAmd64CR3(pVM),
1363 SelCS, SelDS, SelCS64, SelTSS);
1364
1365 uint32_t offCode = 0;
1366 while (offCode < pSwitcher->cbCode)
1367 {
1368 /*
1369 * Figure out where this is.
1370 */
1371 const char *pszDesc = NULL;
1372 RTUINTPTR uBase;
1373 uint32_t cbCode;
1374 if (offCode - pSwitcher->offHCCode0 < pSwitcher->cbHCCode0)
1375 {
1376 pszDesc = "HCCode0";
1377 uBase = (RTUINTPTR)pu8CodeR0;
1378 offCode = pSwitcher->offHCCode0;
1379 cbCode = pSwitcher->cbHCCode0;
1380 }
1381 else if (offCode - pSwitcher->offHCCode1 < pSwitcher->cbHCCode1)
1382 {
1383 pszDesc = "HCCode1";
1384 uBase = (RTUINTPTR)pu8CodeR0;
1385 offCode = pSwitcher->offHCCode1;
1386 cbCode = pSwitcher->cbHCCode1;
1387 }
1388 else if (offCode - pSwitcher->offGCCode < pSwitcher->cbGCCode)
1389 {
1390 pszDesc = "GCCode";
1391 uBase = GCPtrCode;
1392 offCode = pSwitcher->offGCCode;
1393 cbCode = pSwitcher->cbGCCode;
1394 }
1395 else if (offCode - pSwitcher->offIDCode0 < pSwitcher->cbIDCode0)
1396 {
1397 pszDesc = "IDCode0";
1398 uBase = u32IDCode;
1399 offCode = pSwitcher->offIDCode0;
1400 cbCode = pSwitcher->cbIDCode0;
1401 }
1402 else if (offCode - pSwitcher->offIDCode1 < pSwitcher->cbIDCode1)
1403 {
1404 pszDesc = "IDCode1";
1405 uBase = u32IDCode;
1406 offCode = pSwitcher->offIDCode1;
1407 cbCode = pSwitcher->cbIDCode1;
1408 }
1409 else
1410 {
1411 RTLogPrintf(" %04x: %02x '%c' (nowhere)\n",
1412 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1413 offCode++;
1414 continue;
1415 }
1416
1417 /*
1418 * Disassemble it.
1419 */
1420 RTLogPrintf(" %s: offCode=%#x cbCode=%#x\n", pszDesc, offCode, cbCode);
1421 DISCPUSTATE Cpu;
1422
1423 memset(&Cpu, 0, sizeof(Cpu));
1424 Cpu.mode = CPUMODE_32BIT;
1425 while (cbCode > 0)
1426 {
1427 /* try label it */
1428 if (pSwitcher->offR0HostToGuest == offCode)
1429 RTLogPrintf(" *R0HostToGuest:\n");
1430 if (pSwitcher->offGCGuestToHost == offCode)
1431 RTLogPrintf(" *GCGuestToHost:\n");
1432 if (pSwitcher->offGCCallTrampoline == offCode)
1433 RTLogPrintf(" *GCCallTrampoline:\n");
1434 if (pSwitcher->offGCGuestToHostAsm == offCode)
1435 RTLogPrintf(" *GCGuestToHostAsm:\n");
1436 if (pSwitcher->offGCGuestToHostAsmHyperCtx == offCode)
1437 RTLogPrintf(" *GCGuestToHostAsmHyperCtx:\n");
1438 if (pSwitcher->offGCGuestToHostAsmGuestCtx == offCode)
1439 RTLogPrintf(" *GCGuestToHostAsmGuestCtx:\n");
1440
1441 /* disas */
1442 uint32_t cbInstr = 0;
1443 char szDisas[256];
1444 if (RT_SUCCESS(DISInstr(&Cpu, (RTUINTPTR)pu8CodeR3 + offCode, uBase - (RTUINTPTR)pu8CodeR3, &cbInstr, szDisas)))
1445 RTLogPrintf(" %04x: %s", offCode, szDisas); //for whatever reason szDisas includes '\n'.
1446 else
1447 {
1448 RTLogPrintf(" %04x: %02x '%c'\n",
1449 offCode, pu8CodeR3[offCode], isprint(pu8CodeR3[offCode]) ? pu8CodeR3[offCode] : ' ');
1450 cbInstr = 1;
1451 }
1452 offCode += cbInstr;
1453 cbCode -= RT_MIN(cbInstr, cbCode);
1454 }
1455 }
1456 }
1457#endif
1458}
1459
1460
1461/**
1462 * Relocator for the 32-Bit to 32-Bit world switcher.
1463 */
1464DECLCALLBACK(void) vmmR3Switcher32BitTo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1465{
1466 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1467 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1468}
1469
1470
1471/**
1472 * Relocator for the 32-Bit to PAE world switcher.
1473 */
1474DECLCALLBACK(void) vmmR3Switcher32BitToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1475{
1476 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1477 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1478}
1479
1480
1481/**
1482 * Relocator for the PAE to 32-Bit world switcher.
1483 */
1484DECLCALLBACK(void) vmmR3SwitcherPAETo32Bit_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1485{
1486 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1487 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1488}
1489
1490
1491/**
1492 * Relocator for the PAE to PAE world switcher.
1493 */
1494DECLCALLBACK(void) vmmR3SwitcherPAEToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1495{
1496 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1497 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), 0);
1498}
1499
1500
1501/**
1502 * Relocator for the AMD64 to PAE world switcher.
1503 */
1504DECLCALLBACK(void) vmmR3SwitcherAMD64ToPAE_Relocate(PVM pVM, PVMMSWITCHERDEF pSwitcher, uint8_t *pu8CodeR0, uint8_t *pu8CodeR3, RTGCPTR GCPtrCode, uint32_t u32IDCode)
1505{
1506 vmmR3SwitcherGenericRelocate(pVM, pSwitcher, pu8CodeR0, pu8CodeR3, GCPtrCode, u32IDCode,
1507 SELMGetHyperCS(pVM), SELMGetHyperDS(pVM), SELMGetHyperTSS(pVM), SELMGetHyperGDT(pVM), SELMGetHyperCS64(pVM));
1508}
1509
1510
1511/**
1512 * Gets the pointer to g_szRTAssertMsg1 in GC.
1513 * @returns Pointer to VMMGC::g_szRTAssertMsg1.
1514 * Returns NULL if not present.
1515 * @param pVM The VM handle.
1516 */
1517VMMR3DECL(const char *) VMMR3GetGCAssertMsg1(PVM pVM)
1518{
1519 RTGCPTR32 GCPtr;
1520 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg1", &GCPtr);
1521 if (VBOX_SUCCESS(rc))
1522 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1523 return NULL;
1524}
1525
1526
1527/**
1528 * Gets the pointer to g_szRTAssertMsg2 in GC.
1529 * @returns Pointer to VMMGC::g_szRTAssertMsg2.
1530 * Returns NULL if not present.
1531 * @param pVM The VM handle.
1532 */
1533VMMR3DECL(const char *) VMMR3GetGCAssertMsg2(PVM pVM)
1534{
1535 RTGCPTR32 GCPtr;
1536 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_szRTAssertMsg2", &GCPtr);
1537 if (VBOX_SUCCESS(rc))
1538 return (const char *)MMHyperGC2HC(pVM, GCPtr);
1539 return NULL;
1540}
1541
1542
1543/**
1544 * Execute state save operation.
1545 *
1546 * @returns VBox status code.
1547 * @param pVM VM Handle.
1548 * @param pSSM SSM operation handle.
1549 */
1550static DECLCALLBACK(int) vmmR3Save(PVM pVM, PSSMHANDLE pSSM)
1551{
1552 LogFlow(("vmmR3Save:\n"));
1553
1554 /*
1555 * The hypervisor stack.
1556 */
1557 SSMR3PutRCPtr(pSSM, pVM->vmm.s.pbGCStackBottom);
1558 RTRCPTR GCPtrESP = CPUMGetHyperESP(pVM);
1559 AssertMsg(pVM->vmm.s.pbGCStackBottom - GCPtrESP <= VMM_STACK_SIZE, ("Bottom %VGv ESP=%VGv\n", pVM->vmm.s.pbGCStackBottom, GCPtrESP));
1560 SSMR3PutRCPtr(pSSM, GCPtrESP);
1561 SSMR3PutMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1562 return SSMR3PutU32(pSSM, ~0); /* terminator */
1563}
1564
1565
1566/**
1567 * Execute state load operation.
1568 *
1569 * @returns VBox status code.
1570 * @param pVM VM Handle.
1571 * @param pSSM SSM operation handle.
1572 * @param u32Version Data layout version.
1573 */
1574static DECLCALLBACK(int) vmmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1575{
1576 LogFlow(("vmmR3Load:\n"));
1577
1578 /*
1579 * Validate version.
1580 */
1581 if (u32Version != VMM_SAVED_STATE_VERSION)
1582 {
1583 AssertMsgFailed(("vmmR3Load: Invalid version u32Version=%d!\n", u32Version));
1584 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1585 }
1586
1587 /*
1588 * Check that the stack is in the same place, or that it's fearly empty.
1589 */
1590 RTRCPTR GCPtrStackBottom;
1591 SSMR3GetRCPtr(pSSM, &GCPtrStackBottom);
1592 RTRCPTR GCPtrESP;
1593 int rc = SSMR3GetRCPtr(pSSM, &GCPtrESP);
1594 if (VBOX_FAILURE(rc))
1595 return rc;
1596
1597 /* Previously we checked if the location of the stack was identical or that the stack was empty.
1598 * This is not required as we can never initiate a save when GC context code performs a ring 3 call.
1599 */
1600 /* restore the stack. (not necessary; just consistency checking) */
1601 SSMR3GetMem(pSSM, pVM->vmm.s.pbHCStack, VMM_STACK_SIZE);
1602
1603 /* terminator */
1604 uint32_t u32;
1605 rc = SSMR3GetU32(pSSM, &u32);
1606 if (VBOX_FAILURE(rc))
1607 return rc;
1608 if (u32 != ~0U)
1609 {
1610 AssertMsgFailed(("u32=%#x\n", u32));
1611 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1612 }
1613 return VINF_SUCCESS;
1614}
1615
1616
1617/**
1618 * Selects the switcher to be used for switching to GC.
1619 *
1620 * @returns VBox status code.
1621 * @param pVM VM handle.
1622 * @param enmSwitcher The new switcher.
1623 * @remark This function may be called before the VMM is initialized.
1624 */
1625VMMR3DECL(int) VMMR3SelectSwitcher(PVM pVM, VMMSWITCHER enmSwitcher)
1626{
1627 /*
1628 * Validate input.
1629 */
1630 if ( enmSwitcher < VMMSWITCHER_INVALID
1631 || enmSwitcher >= VMMSWITCHER_MAX)
1632 {
1633 AssertMsgFailed(("Invalid input enmSwitcher=%d\n", enmSwitcher));
1634 return VERR_INVALID_PARAMETER;
1635 }
1636
1637 /* Do nothing if the switcher is disabled. */
1638 if (pVM->vmm.s.fSwitcherDisabled)
1639 return VINF_SUCCESS;
1640
1641 /*
1642 * Select the new switcher.
1643 */
1644 PVMMSWITCHERDEF pSwitcher = s_apSwitchers[enmSwitcher];
1645 if (pSwitcher)
1646 {
1647 Log(("VMMR3SelectSwitcher: enmSwitcher %d -> %d %s\n", pVM->vmm.s.enmSwitcher, enmSwitcher, pSwitcher->pszDesc));
1648 pVM->vmm.s.enmSwitcher = enmSwitcher;
1649
1650 RTR0PTR pbCodeR0 = (RTR0PTR)pVM->vmm.s.pvHCCoreCodeR0 + pVM->vmm.s.aoffSwitchers[enmSwitcher]; /** @todo fix the pvHCCoreCodeR0 type */
1651 pVM->vmm.s.pfnR0HostToGuest = pbCodeR0 + pSwitcher->offR0HostToGuest;
1652
1653 RTGCPTR GCPtr = pVM->vmm.s.pvGCCoreCode + pVM->vmm.s.aoffSwitchers[enmSwitcher];
1654 pVM->vmm.s.pfnGCGuestToHost = GCPtr + pSwitcher->offGCGuestToHost;
1655 pVM->vmm.s.pfnGCCallTrampoline = GCPtr + pSwitcher->offGCCallTrampoline;
1656 pVM->pfnVMMGCGuestToHostAsm = GCPtr + pSwitcher->offGCGuestToHostAsm;
1657 pVM->pfnVMMGCGuestToHostAsmHyperCtx = GCPtr + pSwitcher->offGCGuestToHostAsmHyperCtx;
1658 pVM->pfnVMMGCGuestToHostAsmGuestCtx = GCPtr + pSwitcher->offGCGuestToHostAsmGuestCtx;
1659 return VINF_SUCCESS;
1660 }
1661 return VERR_NOT_IMPLEMENTED;
1662}
1663
1664/**
1665 * Disable the switcher logic permanently.
1666 *
1667 * @returns VBox status code.
1668 * @param pVM VM handle.
1669 */
1670VMMR3DECL(int) VMMR3DisableSwitcher(PVM pVM)
1671{
1672/** @todo r=bird: I would suggest that we create a dummy switcher which just does something like:
1673 * @code
1674 * mov eax, VERR_INTERNAL_ERROR
1675 * ret
1676 * @endcode
1677 * And then check for fSwitcherDisabled in VMMR3SelectSwitcher() in order to prevent it from being removed.
1678 */
1679 pVM->vmm.s.fSwitcherDisabled = true;
1680 return VINF_SUCCESS;
1681}
1682
1683
1684/**
1685 * Resolve a builtin GC symbol.
1686 * Called by PDM when loading or relocating GC modules.
1687 *
1688 * @returns VBox status
1689 * @param pVM VM Handle.
1690 * @param pszSymbol Symbol to resolv
1691 * @param pGCPtrValue Where to store the symbol value.
1692 * @remark This has to work before VMMR3Relocate() is called.
1693 */
1694VMMR3DECL(int) VMMR3GetImportGC(PVM pVM, const char *pszSymbol, PRTGCPTR pGCPtrValue)
1695{
1696 if (!strcmp(pszSymbol, "g_Logger"))
1697 {
1698 if (pVM->vmm.s.pLoggerHC)
1699 pVM->vmm.s.pLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pLoggerHC);
1700 *pGCPtrValue = pVM->vmm.s.pLoggerGC;
1701 }
1702 else if (!strcmp(pszSymbol, "g_RelLogger"))
1703 {
1704#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1705 if (pVM->vmm.s.pRelLoggerHC)
1706 pVM->vmm.s.pRelLoggerGC = MMHyperHC2GC(pVM, pVM->vmm.s.pRelLoggerHC);
1707 *pGCPtrValue = pVM->vmm.s.pRelLoggerGC;
1708#else
1709 *pGCPtrValue = NIL_RTGCPTR;
1710#endif
1711 }
1712 else
1713 return VERR_SYMBOL_NOT_FOUND;
1714 return VINF_SUCCESS;
1715}
1716
1717
1718/**
1719 * Suspends the the CPU yielder.
1720 *
1721 * @param pVM The VM handle.
1722 */
1723VMMR3DECL(void) VMMR3YieldSuspend(PVM pVM)
1724{
1725 if (!pVM->vmm.s.cYieldResumeMillies)
1726 {
1727 uint64_t u64Now = TMTimerGet(pVM->vmm.s.pYieldTimer);
1728 uint64_t u64Expire = TMTimerGetExpire(pVM->vmm.s.pYieldTimer);
1729 if (u64Now >= u64Expire || u64Expire == ~(uint64_t)0)
1730 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1731 else
1732 pVM->vmm.s.cYieldResumeMillies = TMTimerToMilli(pVM->vmm.s.pYieldTimer, u64Expire - u64Now);
1733 TMTimerStop(pVM->vmm.s.pYieldTimer);
1734 }
1735 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1736}
1737
1738
1739/**
1740 * Stops the the CPU yielder.
1741 *
1742 * @param pVM The VM handle.
1743 */
1744VMMR3DECL(void) VMMR3YieldStop(PVM pVM)
1745{
1746 if (!pVM->vmm.s.cYieldResumeMillies)
1747 TMTimerStop(pVM->vmm.s.pYieldTimer);
1748 pVM->vmm.s.cYieldResumeMillies = pVM->vmm.s.cYieldEveryMillies;
1749 pVM->vmm.s.u64LastYield = RTTimeNanoTS();
1750}
1751
1752
1753/**
1754 * Resumes the CPU yielder when it has been a suspended or stopped.
1755 *
1756 * @param pVM The VM handle.
1757 */
1758VMMR3DECL(void) VMMR3YieldResume(PVM pVM)
1759{
1760 if (pVM->vmm.s.cYieldResumeMillies)
1761 {
1762 TMTimerSetMillies(pVM->vmm.s.pYieldTimer, pVM->vmm.s.cYieldResumeMillies);
1763 pVM->vmm.s.cYieldResumeMillies = 0;
1764 }
1765}
1766
1767
1768/**
1769 * Internal timer callback function.
1770 *
1771 * @param pVM The VM.
1772 * @param pTimer The timer handle.
1773 * @param pvUser User argument specified upon timer creation.
1774 */
1775static DECLCALLBACK(void) vmmR3YieldEMT(PVM pVM, PTMTIMER pTimer, void *pvUser)
1776{
1777 /*
1778 * This really needs some careful tuning. While we shouldn't be too gready since
1779 * that'll cause the rest of the system to stop up, we shouldn't be too nice either
1780 * because that'll cause us to stop up.
1781 *
1782 * The current logic is to use the default interval when there is no lag worth
1783 * mentioning, but when we start accumulating lag we don't bother yielding at all.
1784 *
1785 * (This depends on the TMCLOCK_VIRTUAL_SYNC to be scheduled before TMCLOCK_REAL
1786 * so the lag is up to date.)
1787 */
1788 const uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
1789 if ( u64Lag < 50000000 /* 50ms */
1790 || ( u64Lag < 1000000000 /* 1s */
1791 && RTTimeNanoTS() - pVM->vmm.s.u64LastYield < 500000000 /* 500 ms */)
1792 )
1793 {
1794 uint64_t u64Elapsed = RTTimeNanoTS();
1795 pVM->vmm.s.u64LastYield = u64Elapsed;
1796
1797 RTThreadYield();
1798
1799#ifdef LOG_ENABLED
1800 u64Elapsed = RTTimeNanoTS() - u64Elapsed;
1801 Log(("vmmR3YieldEMT: %RI64 ns\n", u64Elapsed));
1802#endif
1803 }
1804 TMTimerSetMillies(pTimer, pVM->vmm.s.cYieldEveryMillies);
1805}
1806
1807
1808/**
1809 * Acquire global VM lock.
1810 *
1811 * @returns VBox status code
1812 * @param pVM The VM to operate on.
1813 */
1814VMMR3DECL(int) VMMR3Lock(PVM pVM)
1815{
1816 return RTCritSectEnter(&pVM->vmm.s.CritSectVMLock);
1817}
1818
1819
1820/**
1821 * Release global VM lock.
1822 *
1823 * @returns VBox status code
1824 * @param pVM The VM to operate on.
1825 */
1826VMMR3DECL(int) VMMR3Unlock(PVM pVM)
1827{
1828 return RTCritSectLeave(&pVM->vmm.s.CritSectVMLock);
1829}
1830
1831
1832/**
1833 * Return global VM lock owner.
1834 *
1835 * @returns Thread id of owner.
1836 * @returns NIL_RTTHREAD if no owner.
1837 * @param pVM The VM to operate on.
1838 */
1839VMMR3DECL(RTNATIVETHREAD) VMMR3LockGetOwner(PVM pVM)
1840{
1841 return RTCritSectGetOwner(&pVM->vmm.s.CritSectVMLock);
1842}
1843
1844
1845/**
1846 * Checks if the current thread is the owner of the global VM lock.
1847 *
1848 * @returns true if owner.
1849 * @returns false if not owner.
1850 * @param pVM The VM to operate on.
1851 */
1852VMMR3DECL(bool) VMMR3LockIsOwner(PVM pVM)
1853{
1854 return RTCritSectIsOwner(&pVM->vmm.s.CritSectVMLock);
1855}
1856
1857
1858/**
1859 * Executes guest code.
1860 *
1861 * @param pVM VM handle.
1862 */
1863VMMR3DECL(int) VMMR3RawRunGC(PVM pVM)
1864{
1865 Log2(("VMMR3RawRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1866
1867 /*
1868 * Set the EIP and ESP.
1869 */
1870 CPUMSetHyperEIP(pVM, CPUMGetGuestEFlags(pVM) & X86_EFL_VM
1871 ? pVM->vmm.s.pfnCPUMGCResumeGuestV86
1872 : pVM->vmm.s.pfnCPUMGCResumeGuest);
1873 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom);
1874
1875 /*
1876 * We hide log flushes (outer) and hypervisor interrupts (inner).
1877 */
1878 for (;;)
1879 {
1880 int rc;
1881 do
1882 {
1883#ifdef NO_SUPCALLR0VMM
1884 rc = VERR_GENERAL_FAILURE;
1885#else
1886 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
1887 if (RT_LIKELY(rc == VINF_SUCCESS))
1888 rc = pVM->vmm.s.iLastGCRc;
1889#endif
1890 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1891
1892 /*
1893 * Flush the logs.
1894 */
1895#ifdef LOG_ENABLED
1896 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
1897 if ( pLogger
1898 && pLogger->offScratch > 0)
1899 RTLogFlushGC(NULL, pLogger);
1900#endif
1901#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
1902 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
1903 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
1904 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
1905#endif
1906 if (rc != VINF_VMM_CALL_HOST)
1907 {
1908 Log2(("VMMR3RawRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1909 return rc;
1910 }
1911 rc = vmmR3ServiceCallHostRequest(pVM);
1912 if (VBOX_FAILURE(rc))
1913 return rc;
1914 /* Resume GC */
1915 }
1916}
1917
1918
1919/**
1920 * Executes guest code (Intel VT-x and AMD-V).
1921 *
1922 * @param pVM VM handle.
1923 */
1924VMMR3DECL(int) VMMR3HwAccRunGC(PVM pVM)
1925{
1926 Log2(("VMMR3HwAccRunGC: (cs:eip=%04x:%08x)\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1927
1928 for (;;)
1929 {
1930 int rc;
1931 do
1932 {
1933#ifdef NO_SUPCALLR0VMM
1934 rc = VERR_GENERAL_FAILURE;
1935#else
1936 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN);
1937 if (RT_LIKELY(rc == VINF_SUCCESS))
1938 rc = pVM->vmm.s.iLastGCRc;
1939#endif
1940 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
1941
1942#ifdef LOG_ENABLED
1943 /*
1944 * Flush the log
1945 */
1946 PVMMR0LOGGER pR0Logger = pVM->vmm.s.pR0Logger;
1947 if ( pR0Logger
1948 && pR0Logger->Logger.offScratch > 0)
1949 RTLogFlushToLogger(&pR0Logger->Logger, NULL);
1950#endif /* !LOG_ENABLED */
1951 if (rc != VINF_VMM_CALL_HOST)
1952 {
1953 Log2(("VMMR3HwAccRunGC: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
1954 return rc;
1955 }
1956 rc = vmmR3ServiceCallHostRequest(pVM);
1957 if (VBOX_FAILURE(rc) || rc == VINF_EM_DBG_HYPER_ASSERTION)
1958 return rc;
1959 /* Resume R0 */
1960 }
1961}
1962
1963/**
1964 * Calls GC a function.
1965 *
1966 * @param pVM The VM handle.
1967 * @param GCPtrEntry The GC function address.
1968 * @param cArgs The number of arguments in the ....
1969 * @param ... Arguments to the function.
1970 */
1971VMMR3DECL(int) VMMR3CallGC(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, ...)
1972{
1973 va_list args;
1974 va_start(args, cArgs);
1975 int rc = VMMR3CallGCV(pVM, GCPtrEntry, cArgs, args);
1976 va_end(args);
1977 return rc;
1978}
1979
1980
1981/**
1982 * Calls GC a function.
1983 *
1984 * @param pVM The VM handle.
1985 * @param GCPtrEntry The GC function address.
1986 * @param cArgs The number of arguments in the ....
1987 * @param args Arguments to the function.
1988 */
1989VMMR3DECL(int) VMMR3CallGCV(PVM pVM, RTRCPTR GCPtrEntry, unsigned cArgs, va_list args)
1990{
1991 Log2(("VMMR3CallGCV: GCPtrEntry=%VRv cArgs=%d\n", GCPtrEntry, cArgs));
1992
1993 /*
1994 * Setup the call frame using the trampoline.
1995 */
1996 CPUMHyperSetCtxCore(pVM, NULL);
1997 memset(pVM->vmm.s.pbHCStack, 0xaa, VMM_STACK_SIZE); /* Clear the stack. */
1998 CPUMSetHyperESP(pVM, pVM->vmm.s.pbGCStackBottom - cArgs * sizeof(RTGCUINTPTR32));
1999 PRTGCUINTPTR32 pFrame = (PRTGCUINTPTR32)(pVM->vmm.s.pbHCStack + VMM_STACK_SIZE) - cArgs;
2000 int i = cArgs;
2001 while (i-- > 0)
2002 *pFrame++ = va_arg(args, RTGCUINTPTR32);
2003
2004 CPUMPushHyper(pVM, cArgs * sizeof(RTGCUINTPTR32)); /* stack frame size */
2005 CPUMPushHyper(pVM, GCPtrEntry); /* what to call */
2006 CPUMSetHyperEIP(pVM, pVM->vmm.s.pfnGCCallTrampoline);
2007
2008 /*
2009 * We hide log flushes (outer) and hypervisor interrupts (inner).
2010 */
2011 for (;;)
2012 {
2013 int rc;
2014 do
2015 {
2016#ifdef NO_SUPCALLR0VMM
2017 rc = VERR_GENERAL_FAILURE;
2018#else
2019 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2020 if (RT_LIKELY(rc == VINF_SUCCESS))
2021 rc = pVM->vmm.s.iLastGCRc;
2022#endif
2023 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2024
2025 /*
2026 * Flush the logs.
2027 */
2028#ifdef LOG_ENABLED
2029 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2030 if ( pLogger
2031 && pLogger->offScratch > 0)
2032 RTLogFlushGC(NULL, pLogger);
2033#endif
2034#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2035 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2036 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2037 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2038#endif
2039 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2040 VMMR3FatalDump(pVM, rc);
2041 if (rc != VINF_VMM_CALL_HOST)
2042 {
2043 Log2(("VMMR3CallGCV: returns %Vrc (cs:eip=%04x:%08x)\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
2044 return rc;
2045 }
2046 rc = vmmR3ServiceCallHostRequest(pVM);
2047 if (VBOX_FAILURE(rc))
2048 return rc;
2049 }
2050}
2051
2052
2053/**
2054 * Resumes executing hypervisor code when interrupted
2055 * by a queue flush or a debug event.
2056 *
2057 * @returns VBox status code.
2058 * @param pVM VM handle.
2059 */
2060VMMR3DECL(int) VMMR3ResumeHyper(PVM pVM)
2061{
2062 Log(("VMMR3ResumeHyper: eip=%VGv esp=%VGv\n", CPUMGetHyperEIP(pVM), CPUMGetHyperESP(pVM)));
2063
2064 /*
2065 * We hide log flushes (outer) and hypervisor interrupts (inner).
2066 */
2067 for (;;)
2068 {
2069 int rc;
2070 do
2071 {
2072#ifdef NO_SUPCALLR0VMM
2073 rc = VERR_GENERAL_FAILURE;
2074#else
2075 rc = SUPCallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN);
2076 if (RT_LIKELY(rc == VINF_SUCCESS))
2077 rc = pVM->vmm.s.iLastGCRc;
2078#endif
2079 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
2080
2081 /*
2082 * Flush the loggers,
2083 */
2084#ifdef LOG_ENABLED
2085 PRTLOGGERRC pLogger = pVM->vmm.s.pLoggerHC;
2086 if ( pLogger
2087 && pLogger->offScratch > 0)
2088 RTLogFlushGC(NULL, pLogger);
2089#endif
2090#ifdef VBOX_WITH_GC_AND_R0_RELEASE_LOG
2091 PRTLOGGERRC pRelLogger = pVM->vmm.s.pRelLoggerHC;
2092 if (RT_UNLIKELY(pRelLogger && pRelLogger->offScratch > 0))
2093 RTLogFlushGC(RTLogRelDefaultInstance(), pRelLogger);
2094#endif
2095 if (rc == VERR_TRPM_PANIC || rc == VERR_TRPM_DONT_PANIC)
2096 VMMR3FatalDump(pVM, rc);
2097 if (rc != VINF_VMM_CALL_HOST)
2098 {
2099 Log(("VMMR3ResumeHyper: returns %Vrc\n", rc));
2100 return rc;
2101 }
2102 rc = vmmR3ServiceCallHostRequest(pVM);
2103 if (VBOX_FAILURE(rc))
2104 return rc;
2105 }
2106}
2107
2108
2109/**
2110 * Service a call to the ring-3 host code.
2111 *
2112 * @returns VBox status code.
2113 * @param pVM VM handle.
2114 * @remark Careful with critsects.
2115 */
2116static int vmmR3ServiceCallHostRequest(PVM pVM)
2117{
2118 switch (pVM->vmm.s.enmCallHostOperation)
2119 {
2120 /*
2121 * Acquire the PDM lock.
2122 */
2123 case VMMCALLHOST_PDM_LOCK:
2124 {
2125 pVM->vmm.s.rcCallHost = PDMR3LockCall(pVM);
2126 break;
2127 }
2128
2129 /*
2130 * Flush a PDM queue.
2131 */
2132 case VMMCALLHOST_PDM_QUEUE_FLUSH:
2133 {
2134 PDMR3QueueFlushWorker(pVM, NULL);
2135 pVM->vmm.s.rcCallHost = VINF_SUCCESS;
2136 break;
2137 }
2138
2139 /*
2140 * Grow the PGM pool.
2141 */
2142 case VMMCALLHOST_PGM_POOL_GROW:
2143 {
2144 pVM->vmm.s.rcCallHost = PGMR3PoolGrow(pVM);
2145 break;
2146 }
2147
2148 /*
2149 * Maps an page allocation chunk into ring-3 so ring-0 can use it.
2150 */
2151 case VMMCALLHOST_PGM_MAP_CHUNK:
2152 {
2153 pVM->vmm.s.rcCallHost = PGMR3PhysChunkMap(pVM, pVM->vmm.s.u64CallHostArg);
2154 break;
2155 }
2156
2157 /*
2158 * Allocates more handy pages.
2159 */
2160 case VMMCALLHOST_PGM_ALLOCATE_HANDY_PAGES:
2161 {
2162 pVM->vmm.s.rcCallHost = PGMR3PhysAllocateHandyPages(pVM);
2163 break;
2164 }
2165#ifndef VBOX_WITH_NEW_PHYS_CODE
2166
2167 case VMMCALLHOST_PGM_RAM_GROW_RANGE:
2168 {
2169 const RTGCPHYS GCPhys = pVM->vmm.s.u64CallHostArg;
2170 pVM->vmm.s.rcCallHost = PGM3PhysGrowRange(pVM, &GCPhys);
2171 break;
2172 }
2173#endif
2174
2175 /*
2176 * Acquire the PGM lock.
2177 */
2178 case VMMCALLHOST_PGM_LOCK:
2179 {
2180 pVM->vmm.s.rcCallHost = PGMR3LockCall(pVM);
2181 break;
2182 }
2183
2184 /*
2185 * Flush REM handler notifications.
2186 */
2187 case VMMCALLHOST_REM_REPLAY_HANDLER_NOTIFICATIONS:
2188 {
2189 REMR3ReplayHandlerNotifications(pVM);
2190 break;
2191 }
2192
2193 /*
2194 * This is a noop. We just take this route to avoid unnecessary
2195 * tests in the loops.
2196 */
2197 case VMMCALLHOST_VMM_LOGGER_FLUSH:
2198 break;
2199
2200 /*
2201 * Set the VM error message.
2202 */
2203 case VMMCALLHOST_VM_SET_ERROR:
2204 VMR3SetErrorWorker(pVM);
2205 break;
2206
2207 /*
2208 * Set the VM runtime error message.
2209 */
2210 case VMMCALLHOST_VM_SET_RUNTIME_ERROR:
2211 VMR3SetRuntimeErrorWorker(pVM);
2212 break;
2213
2214 /*
2215 * Signal a ring 0 hypervisor assertion.
2216 * Cancel the longjmp operation that's in progress.
2217 */
2218 case VMMCALLHOST_VM_R0_HYPER_ASSERTION:
2219 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2220 pVM->vmm.s.CallHostR0JmpBuf.fInRing3Call = false;
2221#ifdef RT_ARCH_X86
2222 pVM->vmm.s.CallHostR0JmpBuf.eip = 0;
2223#else
2224 pVM->vmm.s.CallHostR0JmpBuf.rip = 0;
2225#endif
2226 LogRel((pVM->vmm.s.szRing0AssertMsg1));
2227 LogRel((pVM->vmm.s.szRing0AssertMsg2));
2228 return VINF_EM_DBG_HYPER_ASSERTION;
2229
2230 default:
2231 AssertMsgFailed(("enmCallHostOperation=%d\n", pVM->vmm.s.enmCallHostOperation));
2232 return VERR_INTERNAL_ERROR;
2233 }
2234
2235 pVM->vmm.s.enmCallHostOperation = VMMCALLHOST_INVALID;
2236 return VINF_SUCCESS;
2237}
2238
2239
2240
2241/**
2242 * Structure to pass to DBGFR3Info() and for doing all other
2243 * output during fatal dump.
2244 */
2245typedef struct VMMR3FATALDUMPINFOHLP
2246{
2247 /** The helper core. */
2248 DBGFINFOHLP Core;
2249 /** The release logger instance. */
2250 PRTLOGGER pRelLogger;
2251 /** The saved release logger flags. */
2252 RTUINT fRelLoggerFlags;
2253 /** The logger instance. */
2254 PRTLOGGER pLogger;
2255 /** The saved logger flags. */
2256 RTUINT fLoggerFlags;
2257 /** The saved logger destination flags. */
2258 RTUINT fLoggerDestFlags;
2259 /** Whether to output to stderr or not. */
2260 bool fStdErr;
2261} VMMR3FATALDUMPINFOHLP, *PVMMR3FATALDUMPINFOHLP;
2262typedef const VMMR3FATALDUMPINFOHLP *PCVMMR3FATALDUMPINFOHLP;
2263
2264
2265/**
2266 * Print formatted string.
2267 *
2268 * @param pHlp Pointer to this structure.
2269 * @param pszFormat The format string.
2270 * @param ... Arguments.
2271 */
2272static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintf(PCDBGFINFOHLP pHlp, const char *pszFormat, ...)
2273{
2274 va_list args;
2275 va_start(args, pszFormat);
2276 pHlp->pfnPrintfV(pHlp, pszFormat, args);
2277 va_end(args);
2278}
2279
2280
2281/**
2282 * Print formatted string.
2283 *
2284 * @param pHlp Pointer to this structure.
2285 * @param pszFormat The format string.
2286 * @param args Argument list.
2287 */
2288static DECLCALLBACK(void) vmmR3FatalDumpInfoHlp_pfnPrintfV(PCDBGFINFOHLP pHlp, const char *pszFormat, va_list args)
2289{
2290 PCVMMR3FATALDUMPINFOHLP pMyHlp = (PCVMMR3FATALDUMPINFOHLP)pHlp;
2291
2292 if (pMyHlp->pRelLogger)
2293 {
2294 va_list args2;
2295 va_copy(args2, args);
2296 RTLogLoggerV(pMyHlp->pRelLogger, pszFormat, args2);
2297 va_end(args2);
2298 }
2299 if (pMyHlp->pLogger)
2300 {
2301 va_list args2;
2302 va_copy(args2, args);
2303 RTLogLoggerV(pMyHlp->pLogger, pszFormat, args);
2304 va_end(args2);
2305 }
2306 if (pMyHlp->fStdErr)
2307 {
2308 va_list args2;
2309 va_copy(args2, args);
2310 RTStrmPrintfV(g_pStdErr, pszFormat, args);
2311 va_end(args2);
2312 }
2313}
2314
2315
2316/**
2317 * Initializes the fatal dump output helper.
2318 *
2319 * @param pHlp The structure to initialize.
2320 */
2321static void vmmR3FatalDumpInfoHlpInit(PVMMR3FATALDUMPINFOHLP pHlp)
2322{
2323 memset(pHlp, 0, sizeof(*pHlp));
2324
2325 pHlp->Core.pfnPrintf = vmmR3FatalDumpInfoHlp_pfnPrintf;
2326 pHlp->Core.pfnPrintfV = vmmR3FatalDumpInfoHlp_pfnPrintfV;
2327
2328 /*
2329 * The loggers.
2330 */
2331 pHlp->pRelLogger = RTLogRelDefaultInstance();
2332#ifndef LOG_ENABLED
2333 if (!pHlp->pRelLogger)
2334#endif
2335 pHlp->pLogger = RTLogDefaultInstance();
2336
2337 if (pHlp->pRelLogger)
2338 {
2339 pHlp->fRelLoggerFlags = pHlp->pRelLogger->fFlags;
2340 pHlp->pRelLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2341 }
2342
2343 if (pHlp->pLogger)
2344 {
2345 pHlp->fLoggerFlags = pHlp->pLogger->fFlags;
2346 pHlp->fLoggerDestFlags = pHlp->pLogger->fDestFlags;
2347 pHlp->pLogger->fFlags &= ~(RTLOGFLAGS_BUFFERED | RTLOGFLAGS_DISABLED);
2348#ifndef DEBUG_sandervl
2349 pHlp->pLogger->fDestFlags |= RTLOGDEST_DEBUGGER;
2350#endif
2351 }
2352
2353 /*
2354 * Check if we need write to stderr.
2355 */
2356#ifdef DEBUG_sandervl
2357 pHlp->fStdErr = false; /* takes too long to display here */
2358#else
2359 pHlp->fStdErr = (!pHlp->pRelLogger || !(pHlp->pRelLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)))
2360 && (!pHlp->pLogger || !(pHlp->pLogger->fDestFlags & (RTLOGDEST_STDOUT | RTLOGDEST_STDERR)));
2361#endif
2362}
2363
2364
2365/**
2366 * Deletes the fatal dump output helper.
2367 *
2368 * @param pHlp The structure to delete.
2369 */
2370static void vmmR3FatalDumpInfoHlpDelete(PVMMR3FATALDUMPINFOHLP pHlp)
2371{
2372 if (pHlp->pRelLogger)
2373 {
2374 RTLogFlush(pHlp->pRelLogger);
2375 pHlp->pRelLogger->fFlags = pHlp->fRelLoggerFlags;
2376 }
2377
2378 if (pHlp->pLogger)
2379 {
2380 RTLogFlush(pHlp->pLogger);
2381 pHlp->pLogger->fFlags = pHlp->fLoggerFlags;
2382 pHlp->pLogger->fDestFlags = pHlp->fLoggerDestFlags;
2383 }
2384}
2385
2386
2387/**
2388 * Dumps the VM state on a fatal error.
2389 *
2390 * @param pVM VM Handle.
2391 * @param rcErr VBox status code.
2392 */
2393VMMR3DECL(void) VMMR3FatalDump(PVM pVM, int rcErr)
2394{
2395 /*
2396 * Create our output helper and sync it with the log settings.
2397 * This helper will be used for all the output.
2398 */
2399 VMMR3FATALDUMPINFOHLP Hlp;
2400 PCDBGFINFOHLP pHlp = &Hlp.Core;
2401 vmmR3FatalDumpInfoHlpInit(&Hlp);
2402
2403 /*
2404 * Header.
2405 */
2406 pHlp->pfnPrintf(pHlp,
2407 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
2408 "!!\n"
2409 "!! Guru Meditation %d (%Vrc)\n"
2410 "!!\n",
2411 rcErr, rcErr);
2412
2413 /*
2414 * Continue according to context.
2415 */
2416 bool fDoneHyper = false;
2417 switch (rcErr)
2418 {
2419 /*
2420 * Hypervisor errors.
2421 */
2422 case VINF_EM_DBG_HYPER_ASSERTION:
2423 {
2424 const char *pszMsg1 = HWACCMR3IsActive(pVM) ? pVM->vmm.s.szRing0AssertMsg1 : VMMR3GetGCAssertMsg1(pVM);
2425 while (pszMsg1 && *pszMsg1 == '\n')
2426 pszMsg1++;
2427 const char *pszMsg2 = HWACCMR3IsActive(pVM) ? pVM->vmm.s.szRing0AssertMsg2 : VMMR3GetGCAssertMsg2(pVM);
2428 while (pszMsg2 && *pszMsg2 == '\n')
2429 pszMsg2++;
2430 pHlp->pfnPrintf(pHlp,
2431 "%s"
2432 "%s",
2433 pszMsg1,
2434 pszMsg2);
2435 if ( !pszMsg2
2436 || !*pszMsg2
2437 || strchr(pszMsg2, '\0')[-1] != '\n')
2438 pHlp->pfnPrintf(pHlp, "\n");
2439 pHlp->pfnPrintf(pHlp, "!!\n");
2440 /* fall thru */
2441 }
2442 case VERR_TRPM_DONT_PANIC:
2443 case VERR_TRPM_PANIC:
2444 case VINF_EM_RAW_STALE_SELECTOR:
2445 case VINF_EM_RAW_IRET_TRAP:
2446 case VINF_EM_DBG_HYPER_BREAKPOINT:
2447 case VINF_EM_DBG_HYPER_STEPPED:
2448 {
2449 /*
2450 * Active trap? This is only of partial interest when in hardware
2451 * assisted virtualization mode, thus the different messages.
2452 */
2453 uint32_t uEIP = CPUMGetHyperEIP(pVM);
2454 TRPMEVENT enmType;
2455 uint8_t u8TrapNo = 0xce;
2456 RTGCUINT uErrorCode = 0xdeadface;
2457 RTGCUINTPTR uCR2 = 0xdeadface;
2458 int rc2 = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
2459 if (!HWACCMR3IsActive(pVM))
2460 {
2461 if (RT_SUCCESS(rc2))
2462 pHlp->pfnPrintf(pHlp,
2463 "!! TRAP=%02x ERRCD=%RGv CR2=%RGv EIP=%RX32 Type=%d\n",
2464 u8TrapNo, uErrorCode, uCR2, uEIP, enmType);
2465 else
2466 pHlp->pfnPrintf(pHlp,
2467 "!! EIP=%RX32 NOTRAP\n",
2468 uEIP);
2469 }
2470 else if (RT_SUCCESS(rc2))
2471 pHlp->pfnPrintf(pHlp,
2472 "!! ACTIVE TRAP=%02x ERRCD=%RGv CR2=%RGv PC=%RGr Type=%d (Guest!)\n",
2473 u8TrapNo, uErrorCode, uCR2, CPUMGetGuestRIP(pVM), enmType);
2474
2475 /*
2476 * The hypervisor dump is not relevant when we're in VT-x/AMD-V mode.
2477 */
2478 if (HWACCMR3IsActive(pVM))
2479 pHlp->pfnPrintf(pHlp, "\n");
2480 else
2481 {
2482 /*
2483 * Try figure out where eip is.
2484 */
2485 /* core code? */
2486 if (uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode < pVM->vmm.s.cbCoreCode)
2487 pHlp->pfnPrintf(pHlp,
2488 "!! EIP is in CoreCode, offset %#x\n",
2489 uEIP - (RTGCUINTPTR)pVM->vmm.s.pvGCCoreCode);
2490 else
2491 { /* ask PDM */ /** @todo ask DBGFR3Sym later? */
2492 char szModName[64];
2493 RTRCPTR RCPtrMod;
2494 char szNearSym1[260];
2495 RTRCPTR RCPtrNearSym1;
2496 char szNearSym2[260];
2497 RTRCPTR RCPtrNearSym2;
2498 int rc = PDMR3LdrQueryRCModFromPC(pVM, uEIP,
2499 &szModName[0], sizeof(szModName), &RCPtrMod,
2500 &szNearSym1[0], sizeof(szNearSym1), &RCPtrNearSym1,
2501 &szNearSym2[0], sizeof(szNearSym2), &RCPtrNearSym2);
2502 if (VBOX_SUCCESS(rc))
2503 pHlp->pfnPrintf(pHlp,
2504 "!! EIP in %s (%RRv) at rva %x near symbols:\n"
2505 "!! %RRv rva %RRv off %08x %s\n"
2506 "!! %RRv rva %RRv off -%08x %s\n",
2507 szModName, RCPtrMod, (unsigned)(uEIP - RCPtrMod),
2508 RCPtrNearSym1, RCPtrNearSym1 - RCPtrMod, (unsigned)(uEIP - RCPtrNearSym1), szNearSym1,
2509 RCPtrNearSym2, RCPtrNearSym2 - RCPtrMod, (unsigned)(RCPtrNearSym2 - uEIP), szNearSym2);
2510 else
2511 pHlp->pfnPrintf(pHlp,
2512 "!! EIP is not in any code known to VMM!\n");
2513 }
2514
2515 /* Disassemble the instruction. */
2516 char szInstr[256];
2517 rc2 = DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_HYPER, &szInstr[0], sizeof(szInstr), NULL);
2518 if (VBOX_SUCCESS(rc2))
2519 pHlp->pfnPrintf(pHlp,
2520 "!! %s\n", szInstr);
2521
2522 /* Dump the hypervisor cpu state. */
2523 pHlp->pfnPrintf(pHlp,
2524 "!!\n"
2525 "!!\n"
2526 "!!\n");
2527 rc2 = DBGFR3Info(pVM, "cpumhyper", "verbose", pHlp);
2528 fDoneHyper = true;
2529
2530 /* Callstack. */
2531 DBGFSTACKFRAME Frame = {0};
2532 rc2 = DBGFR3StackWalkBeginHyper(pVM, &Frame);
2533 if (VBOX_SUCCESS(rc2))
2534 {
2535 pHlp->pfnPrintf(pHlp,
2536 "!!\n"
2537 "!! Call Stack:\n"
2538 "!!\n"
2539 "EBP Ret EBP Ret CS:EIP Arg0 Arg1 Arg2 Arg3 CS:EIP Symbol [line]\n");
2540 do
2541 {
2542 pHlp->pfnPrintf(pHlp,
2543 "%08RX32 %08RX32 %04RX32:%08RX32 %08RX32 %08RX32 %08RX32 %08RX32",
2544 (uint32_t)Frame.AddrFrame.off,
2545 (uint32_t)Frame.AddrReturnFrame.off,
2546 (uint32_t)Frame.AddrReturnPC.Sel,
2547 (uint32_t)Frame.AddrReturnPC.off,
2548 Frame.Args.au32[0],
2549 Frame.Args.au32[1],
2550 Frame.Args.au32[2],
2551 Frame.Args.au32[3]);
2552 pHlp->pfnPrintf(pHlp, " %RTsel:%08RGv", Frame.AddrPC.Sel, Frame.AddrPC.off);
2553 if (Frame.pSymPC)
2554 {
2555 RTGCINTPTR offDisp = Frame.AddrPC.FlatPtr - Frame.pSymPC->Value;
2556 if (offDisp > 0)
2557 pHlp->pfnPrintf(pHlp, " %s+%llx", Frame.pSymPC->szName, (int64_t)offDisp);
2558 else if (offDisp < 0)
2559 pHlp->pfnPrintf(pHlp, " %s-%llx", Frame.pSymPC->szName, -(int64_t)offDisp);
2560 else
2561 pHlp->pfnPrintf(pHlp, " %s", Frame.pSymPC->szName);
2562 }
2563 if (Frame.pLinePC)
2564 pHlp->pfnPrintf(pHlp, " [%s @ 0i%d]", Frame.pLinePC->szFilename, Frame.pLinePC->uLineNo);
2565 pHlp->pfnPrintf(pHlp, "\n");
2566
2567 /* next */
2568 rc2 = DBGFR3StackWalkNext(pVM, &Frame);
2569 } while (VBOX_SUCCESS(rc2));
2570 DBGFR3StackWalkEnd(pVM, &Frame);
2571 }
2572
2573 /* raw stack */
2574 pHlp->pfnPrintf(pHlp,
2575 "!!\n"
2576 "!! Raw stack (mind the direction).\n"
2577 "!!\n"
2578 "%.*Vhxd\n",
2579 VMM_STACK_SIZE, (char *)pVM->vmm.s.pbHCStack);
2580 } /* !HWACCMR3IsActive */
2581 break;
2582 }
2583
2584 default:
2585 {
2586 break;
2587 }
2588
2589 } /* switch (rcErr) */
2590
2591
2592 /*
2593 * Generic info dumper loop.
2594 */
2595 static struct
2596 {
2597 const char *pszInfo;
2598 const char *pszArgs;
2599 } const aInfo[] =
2600 {
2601 { "mappings", NULL },
2602 { "hma", NULL },
2603 { "cpumguest", "verbose" },
2604 { "cpumguestinstr", "verbose" },
2605 { "cpumhyper", "verbose" },
2606 { "cpumhost", "verbose" },
2607 { "mode", "all" },
2608 { "cpuid", "verbose" },
2609 { "gdt", NULL },
2610 { "ldt", NULL },
2611 //{ "tss", NULL },
2612 { "ioport", NULL },
2613 { "mmio", NULL },
2614 { "phys", NULL },
2615 //{ "pgmpd", NULL }, - doesn't always work at init time...
2616 { "timers", NULL },
2617 { "activetimers", NULL },
2618 { "handlers", "phys virt hyper stats" },
2619 { "cfgm", NULL },
2620 };
2621 for (unsigned i = 0; i < RT_ELEMENTS(aInfo); i++)
2622 {
2623 if (fDoneHyper && !strcmp(aInfo[i].pszInfo, "cpumhyper"))
2624 continue;
2625 pHlp->pfnPrintf(pHlp,
2626 "!!\n"
2627 "!! {%s, %s}\n"
2628 "!!\n",
2629 aInfo[i].pszInfo, aInfo[i].pszArgs);
2630 DBGFR3Info(pVM, aInfo[i].pszInfo, aInfo[i].pszArgs, pHlp);
2631 }
2632
2633 /* done */
2634 pHlp->pfnPrintf(pHlp,
2635 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
2636
2637
2638 /*
2639 * Delete the output instance (flushing and restoring of flags).
2640 */
2641 vmmR3FatalDumpInfoHlpDelete(&Hlp);
2642}
2643
2644
2645
2646/**
2647 * Displays the Force action Flags.
2648 *
2649 * @param pVM The VM handle.
2650 * @param pHlp The output helpers.
2651 * @param pszArgs The additional arguments (ignored).
2652 */
2653static DECLCALLBACK(void) vmmR3InfoFF(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2654{
2655 const uint32_t fForcedActions = pVM->fForcedActions;
2656
2657 pHlp->pfnPrintf(pHlp, "Forced action Flags: %#RX32", fForcedActions);
2658
2659 /* show the flag mnemonics */
2660 int c = 0;
2661 uint32_t f = fForcedActions;
2662#define PRINT_FLAG(flag) do { \
2663 if (f & (flag)) \
2664 { \
2665 static const char *s_psz = #flag; \
2666 if (!(c % 6)) \
2667 pHlp->pfnPrintf(pHlp, "%s\n %s", c ? "," : "", s_psz + 6); \
2668 else \
2669 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2670 c++; \
2671 f &= ~(flag); \
2672 } \
2673 } while (0)
2674 PRINT_FLAG(VM_FF_INTERRUPT_APIC);
2675 PRINT_FLAG(VM_FF_INTERRUPT_PIC);
2676 PRINT_FLAG(VM_FF_TIMER);
2677 PRINT_FLAG(VM_FF_PDM_QUEUES);
2678 PRINT_FLAG(VM_FF_PDM_DMA);
2679 PRINT_FLAG(VM_FF_PDM_CRITSECT);
2680 PRINT_FLAG(VM_FF_DBGF);
2681 PRINT_FLAG(VM_FF_REQUEST);
2682 PRINT_FLAG(VM_FF_TERMINATE);
2683 PRINT_FLAG(VM_FF_RESET);
2684 PRINT_FLAG(VM_FF_PGM_SYNC_CR3);
2685 PRINT_FLAG(VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2686 PRINT_FLAG(VM_FF_TRPM_SYNC_IDT);
2687 PRINT_FLAG(VM_FF_SELM_SYNC_TSS);
2688 PRINT_FLAG(VM_FF_SELM_SYNC_GDT);
2689 PRINT_FLAG(VM_FF_SELM_SYNC_LDT);
2690 PRINT_FLAG(VM_FF_INHIBIT_INTERRUPTS);
2691 PRINT_FLAG(VM_FF_CSAM_SCAN_PAGE);
2692 PRINT_FLAG(VM_FF_CSAM_PENDING_ACTION);
2693 PRINT_FLAG(VM_FF_TO_R3);
2694 PRINT_FLAG(VM_FF_DEBUG_SUSPEND);
2695 if (f)
2696 pHlp->pfnPrintf(pHlp, "%s\n Unknown bits: %#RX32\n", c ? "," : "", f);
2697 else
2698 pHlp->pfnPrintf(pHlp, "\n");
2699#undef PRINT_FLAG
2700
2701 /* the groups */
2702 c = 0;
2703#define PRINT_GROUP(grp) do { \
2704 if (fForcedActions & (grp)) \
2705 { \
2706 static const char *s_psz = #grp; \
2707 if (!(c % 5)) \
2708 pHlp->pfnPrintf(pHlp, "%s %s", c ? ",\n" : "Groups:\n", s_psz + 6); \
2709 else \
2710 pHlp->pfnPrintf(pHlp, ", %s", s_psz + 6); \
2711 c++; \
2712 } \
2713 } while (0)
2714 PRINT_GROUP(VM_FF_EXTERNAL_SUSPENDED_MASK);
2715 PRINT_GROUP(VM_FF_EXTERNAL_HALTED_MASK);
2716 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_MASK);
2717 PRINT_GROUP(VM_FF_HIGH_PRIORITY_PRE_RAW_MASK);
2718 PRINT_GROUP(VM_FF_HIGH_PRIORITY_POST_MASK);
2719 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_POST_MASK);
2720 PRINT_GROUP(VM_FF_NORMAL_PRIORITY_MASK);
2721 PRINT_GROUP(VM_FF_RESUME_GUEST_MASK);
2722 PRINT_GROUP(VM_FF_ALL_BUT_RAW_MASK);
2723 if (c)
2724 pHlp->pfnPrintf(pHlp, "\n");
2725#undef PRINT_GROUP
2726}
2727
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