VirtualBox

source: vbox/trunk/src/VBox/VMM/TRPM.cpp@ 28800

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1/* $Id: TRPM.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * TRPM - The Trap Monitor.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_trpm TRPM - The Trap Monitor
19 *
20 * The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21 * the VMM. It plays a major role in raw-mode execution and a lesser one in the
22 * hardware assisted mode.
23 *
24 * Note first, the following will use trap as a collective term for faults,
25 * aborts and traps.
26 *
27 * @see grp_trpm
28 *
29 *
30 * @section sec_trpm_rc Raw-Mode Context
31 *
32 * When executing in the raw-mode context, TRPM will be managing the IDT and
33 * processing all traps and interrupts. It will also monitor the guest IDT
34 * because CSAM wishes to know about changes to it (trap/interrupt/syscall
35 * handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36 * considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37 *
38 * External interrupts will be forwarded to the host context by the quickest
39 * possible route where they will be reasserted. The other events will be
40 * categorized into virtualization traps, genuine guest traps and hypervisor
41 * traps. The latter group may be recoverable depending on when they happen and
42 * whether there is a handler for it, otherwise it will cause a guru meditation.
43 *
44 * TRPM disgishishes the between the first two (virt and guest traps) and the
45 * latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46 * it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47 * dispatcher tables, one ad-hoc for one time traps registered via
48 * TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49 * The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50 *
51 * The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52 * part), will call up the other VMM sub-systems depending on what it things
53 * happens. The two most busy traps are page faults (\#PF) and general
54 * protection fault/trap (\#GP).
55 *
56 * Before resuming guest code after having taken a virtualization trap or
57 * injected a guest trap, TRPM will check for pending forced action and
58 * every now and again let TM check for timed out timers. This allows code that
59 * is being executed as part of virtualization traps to signal ring-3 exits,
60 * page table resyncs and similar without necessarily using the status code. It
61 * also make sure we're more responsive to timers and requests from other
62 * threads (necessarily running on some different core/cpu in most cases).
63 *
64 *
65 * @section sec_trpm_all All Contexts
66 *
67 * TRPM will also dispatch / inject interrupts and traps to the guest, both when
68 * in raw-mode and when in hardware assisted mode. See TRPMInject().
69 *
70 */
71
72/*******************************************************************************
73* Header Files *
74*******************************************************************************/
75#define LOG_GROUP LOG_GROUP_TRPM
76#include <VBox/trpm.h>
77#include <VBox/cpum.h>
78#include <VBox/selm.h>
79#include <VBox/ssm.h>
80#include <VBox/pdmapi.h>
81#include <VBox/pgm.h>
82#include <VBox/dbgf.h>
83#include <VBox/mm.h>
84#include <VBox/stam.h>
85#include <VBox/csam.h>
86#include <VBox/patm.h>
87#include "TRPMInternal.h"
88#include <VBox/vm.h>
89#include <VBox/em.h>
90#include <VBox/rem.h>
91#include <VBox/hwaccm.h>
92
93#include <VBox/err.h>
94#include <VBox/param.h>
95#include <VBox/log.h>
96#include <iprt/assert.h>
97#include <iprt/asm.h>
98#include <iprt/string.h>
99#include <iprt/alloc.h>
100
101
102/*******************************************************************************
103* Structures and Typedefs *
104*******************************************************************************/
105/**
106 * Trap handler function.
107 * @todo need to specialize this as we go along.
108 */
109typedef enum TRPMHANDLER
110{
111 /** Generic Interrupt handler. */
112 TRPM_HANDLER_INT = 0,
113 /** Generic Trap handler. */
114 TRPM_HANDLER_TRAP,
115 /** Trap 8 (\#DF) handler. */
116 TRPM_HANDLER_TRAP_08,
117 /** Trap 12 (\#MC) handler. */
118 TRPM_HANDLER_TRAP_12,
119 /** Max. */
120 TRPM_HANDLER_MAX
121} TRPMHANDLER, *PTRPMHANDLER;
122
123
124/*******************************************************************************
125* Global Variables *
126*******************************************************************************/
127/** Preinitialized IDT.
128 * The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
129 * will use to pick the right address. The u16SegSel is always VMM CS.
130 */
131static VBOXIDTE_GENERIC g_aIdt[256] =
132{
133/* special trap handler - still, this is an interrupt gate not a trap gate... */
134#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
135/* generic trap handler. */
136#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
137/* special interrupt handler. */
138#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
139/* generic interrupt handler. */
140#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
141/* special task gate IDT entry (for critical exceptions like #DF). */
142#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
143/* draft, fixme later when the handler is written. */
144#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
145
146 /* N - M M - T - C - D i */
147 /* o - n o - y - o - e p */
148 /* - e n - p - d - s t */
149 /* - i - e - e - c . */
150 /* - c - - - r */
151 /* ============================================================= */
152 IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
153 IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
154#ifdef VBOX_WITH_NMI
155 IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
156#else
157 IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
158#endif
159 IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
160 IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
161 IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
162 IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
163 IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
164 IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
165 IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
166 IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
167 IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
168 IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
169 IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
170 IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
171 IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
172 IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
173 IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
174 IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
175 IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
176 IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
177 IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
178 IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
179 IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
180 IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
181 IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
182 IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
183 IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
184 IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
185 IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
186 IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
187 IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
188 IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
189 IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
190 IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
191 IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
192 IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
193 IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
194 IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
195 IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
196 IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
197 IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
198 IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
199 IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
200 IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
201 IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
202 IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
203 IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
204 IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
205 IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
206 IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
207 IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
208 IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
209 IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
210 IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
211 IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
212 IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
213 IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
214 IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
215 IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
216 IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
217 IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
218 IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
219 IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
220 IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
221 IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
222 IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
223 IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
224 IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
225 IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
226 IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
227 IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
228 IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
229 IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
230 IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
231 IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
232 IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
233 IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
234 IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
235 IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
236 IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
237 IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
238 IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
239 IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
240 IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
241 IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
242 IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
243 IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
244 IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
245 IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
246 IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
247 IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
248 IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
249 IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
250 IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
251 IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
252 IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
253 IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
254 IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
255 IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
256 IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
257 IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
258 IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
259 IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
260 IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
261 IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
262 IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
263 IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
264 IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
265 IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
266 IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
267 IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
268 IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
269 IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
270 IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
271 IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
272 IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
273 IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
274 IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
275 IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
276 IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
277 IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
278 IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
279 IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
280 IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
281 IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
282 IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
283 IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
284 IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
285 IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
286 IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
287 IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
288 IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
289 IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
290 IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
291 IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
292 IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
293 IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
294 IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
295 IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
296 IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
297 IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
298 IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
299 IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
300 IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
301 IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
302 IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
303 IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
304 IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
305 IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
306 IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
307 IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
308 IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
309 IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
310 IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
311 IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
312 IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
313 IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
314 IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
315 IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
316 IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
317 IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
318 IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
319 IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
320 IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
321 IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
322 IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
323 IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
324 IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
325 IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
326 IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
327 IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
328 IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
329 IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
330 IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
331 IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
332 IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
333 IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
334 IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
335 IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
336 IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
337 IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
338 IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
339 IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
340 IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
341 IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
342 IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
343 IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
344 IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
345 IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
346 IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
347 IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
348 IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
349 IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
350 IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
351 IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
352 IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
353 IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
354 IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
355 IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
356 IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
357 IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
358 IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
359 IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
360 IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
361 IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
362 IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
363 IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
364 IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
365 IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
366 IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
367 IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
368 IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
369 IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
370 IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
371 IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
372 IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
373 IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
374 IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
375 IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
376 IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
377 IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
378 IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
379 IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
380 IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
381 IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
382 IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
383 IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
384 IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
385 IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
386 IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
387 IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
388 IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
389 IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
390 IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
391 IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
392 IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
393 IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
394 IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
395 IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
396 IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
397 IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
398 IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
399 IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
400 IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
401 IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
402 IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
403 IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
404 IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
405 IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
406 IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
407 IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
408 IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
409 IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
410 IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
411 IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
412#undef IDTE_TRAP
413#undef IDTE_TRAP_GEN
414#undef IDTE_INT
415#undef IDTE_INT_GEN
416#undef IDTE_TASK
417#undef IDTE_UNUSED
418#undef IDTE_RESERVED
419};
420
421
422/** Enable or disable tracking of Guest's IDT. */
423#define TRPM_TRACK_GUEST_IDT_CHANGES
424
425/** Enable or disable tracking of Shadow IDT. */
426#define TRPM_TRACK_SHADOW_IDT_CHANGES
427
428/** TRPM saved state version. */
429#define TRPM_SAVED_STATE_VERSION 9
430#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
431
432
433/*******************************************************************************
434* Internal Functions *
435*******************************************************************************/
436static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
437static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
438static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
439
440
441/**
442 * Initializes the Trap Manager
443 *
444 * @returns VBox status code.
445 * @param pVM The VM to operate on.
446 */
447VMMR3DECL(int) TRPMR3Init(PVM pVM)
448{
449 LogFlow(("TRPMR3Init\n"));
450
451 /*
452 * Assert sizes and alignments.
453 */
454 AssertRelease(!(RT_OFFSETOF(VM, trpm.s) & 31));
455 AssertRelease(!(RT_OFFSETOF(VM, trpm.s.aIdt) & 15));
456 AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
457 AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
458
459 /*
460 * Initialize members.
461 */
462 pVM->trpm.s.offVM = RT_OFFSETOF(VM, trpm);
463 pVM->trpm.s.offTRPMCPU = RT_OFFSETOF(VM, aCpus[0].trpm) - RT_OFFSETOF(VM, trpm);
464
465 for (VMCPUID i = 0; i < pVM->cCpus; i++)
466 {
467 PVMCPU pVCpu = &pVM->aCpus[i];
468
469 pVCpu->trpm.s.offVM = RT_OFFSETOF(VM, aCpus[i].trpm);
470 pVCpu->trpm.s.offVMCpu = RT_OFFSETOF(VMCPU, trpm);
471 pVCpu->trpm.s.uActiveVector = ~0;
472 }
473
474 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
475 pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
476 pVM->trpm.s.fDisableMonitoring = false;
477 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
478
479 /*
480 * Read the configuration (if any).
481 */
482 PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
483 if (pTRPMNode)
484 {
485 bool f;
486 int rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
487 if (RT_SUCCESS(rc))
488 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
489 }
490
491 /* write config summary to log */
492 if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
493 LogRel(("TRPM: Dropping Guest IDT Monitoring.\n"));
494
495 /*
496 * Initialize the IDT.
497 * The handler addresses will be set in the TRPMR3Relocate() function.
498 */
499 Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
500 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
501
502 /*
503 * Register the saved state data unit.
504 */
505 int rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
506 NULL, NULL, NULL,
507 NULL, trpmR3Save, NULL,
508 NULL, trpmR3Load, NULL);
509 if (RT_FAILURE(rc))
510 return rc;
511
512 /*
513 * Statistics.
514 */
515 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
516 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
517 STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
518
519 /* traps */
520 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
521 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
522 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
523 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
524 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
525 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
526 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
527 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
528 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
529 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
530 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
531 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segemnt not present.");
532 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
533 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
534 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
535 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
536 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
537 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
538 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
539 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
540
541#ifdef VBOX_WITH_STATISTICS
542 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 255, 8, MM_TAG_STAM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
543 AssertRCReturn(rc, rc);
544 pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
545 pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
546 for (unsigned i = 0; i < 255; i++)
547 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
548 i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
549#endif
550
551 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
552 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
553 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
554 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
555 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
556 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
557
558 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
559 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
560
561 /*
562 * Default action when entering raw mode for the first time
563 */
564 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
565 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
566 return 0;
567}
568
569
570/**
571 * Applies relocations to data and code managed by this component.
572 *
573 * This function will be called at init and whenever the VMM need
574 * to relocate itself inside the GC.
575 *
576 * @param pVM The VM handle.
577 * @param offDelta Relocation delta relative to old location.
578 */
579VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
580{
581 /* Only applies to raw mode which supports only 1 VCPU. */
582 PVMCPU pVCpu = &pVM->aCpus[0];
583
584 LogFlow(("TRPMR3Relocate\n"));
585 /*
586 * Get the trap handler addresses.
587 *
588 * If VMMGC.gc is screwed, so are we. We'll assert here since it elsewise
589 * would make init order impossible if we should assert the presence of these
590 * exports in TRPMR3Init().
591 */
592 RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
593 RT_ZERO(aRCPtrs);
594 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
595 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
596
597 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
598 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMGC.gc!\n"));
599
600 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
601 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMGC.gc!\n"));
602
603 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
604 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMGC.gc!\n"));
605
606 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
607
608 /*
609 * Iterate the idt and set the addresses.
610 */
611 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
612 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
613 for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
614 {
615 if ( pIdte->Gen.u1Present
616 && !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
617 )
618 {
619 Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
620 RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
621 switch (pIdteTemplate->u16OffsetLow)
622 {
623 /*
624 * Generic handlers have different entrypoints for each possible
625 * vector number. These entrypoints makes a sort of an array with
626 * 8 byte entries where the vector number is the index.
627 * See TRPMGCHandlersA.asm for details.
628 */
629 case TRPM_HANDLER_INT:
630 case TRPM_HANDLER_TRAP:
631 Offset += i * 8;
632 break;
633 case TRPM_HANDLER_TRAP_12:
634 break;
635 case TRPM_HANDLER_TRAP_08:
636 /* Handle #DF Task Gate in special way. */
637 pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
638 pIdte->Gen.u16OffsetLow = 0;
639 pIdte->Gen.u16OffsetHigh = 0;
640 SELMSetTrap8EIP(pVM, Offset);
641 continue;
642 }
643 /* (non-task gates only ) */
644 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
645 pIdte->Gen.u16OffsetHigh = Offset >> 16;
646 pIdte->Gen.u16SegSel = SelCS;
647 }
648 }
649
650 /*
651 * Update IDTR (limit is including!).
652 */
653 CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
654
655 if (!pVM->trpm.s.fDisableMonitoring)
656 {
657#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
658 if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
659 {
660 rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
661 AssertRC(rc);
662 }
663 pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
664 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
665 0, 0, "trpmRCShadowIDTWriteHandler", 0, "Shadow IDT write access handler");
666 AssertRC(rc);
667#endif
668 }
669
670 /* Relocate IDT handlers for forwarding guest traps/interrupts. */
671 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
672 {
673 if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
674 {
675 Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
676 pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
677 }
678
679 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
680 {
681 PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
682 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
683
684 Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
685 pHandler += offDelta;
686
687 pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
688 pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
689 }
690 }
691
692#ifdef VBOX_WITH_STATISTICS
693 pVM->trpm.s.paStatForwardedIRQRC += offDelta;
694 pVM->trpm.s.paStatForwardedIRQR0 = MMHyperR3ToR0(pVM, pVM->trpm.s.paStatForwardedIRQR3);
695#endif
696}
697
698
699/**
700 * Terminates the Trap Manager
701 *
702 * @returns VBox status code.
703 * @param pVM The VM to operate on.
704 */
705VMMR3DECL(int) TRPMR3Term(PVM pVM)
706{
707 NOREF(pVM);
708 return 0;
709}
710
711
712/**
713 * Resets a virtual CPU.
714 *
715 * Used by TRPMR3Reset and CPU hot plugging.
716 *
717 * @param pVCpu The virtual CPU handle.
718 */
719VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
720{
721 pVCpu->trpm.s.uActiveVector = ~0;
722}
723
724
725/**
726 * The VM is being reset.
727 *
728 * For the TRPM component this means that any IDT write monitors
729 * needs to be removed, any pending trap cleared, and the IDT reset.
730 *
731 * @param pVM VM handle.
732 */
733VMMR3DECL(void) TRPMR3Reset(PVM pVM)
734{
735 /*
736 * Deregister any virtual handlers.
737 */
738#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
739 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
740 {
741 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
742 {
743 int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
744 AssertRC(rc);
745 }
746 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
747 }
748 pVM->trpm.s.GuestIdtr.cbIdt = 0;
749#endif
750
751 /*
752 * Reinitialize other members calling the relocator to get things right.
753 */
754 for (VMCPUID i = 0; i < pVM->cCpus; i++)
755 TRPMR3ResetCpu(&pVM->aCpus[i]);
756 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
757 memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
758 TRPMR3Relocate(pVM, 0);
759
760 /*
761 * Default action when entering raw mode for the first time
762 */
763 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
764 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
765}
766
767
768/**
769 * Execute state save operation.
770 *
771 * @returns VBox status code.
772 * @param pVM VM Handle.
773 * @param pSSM SSM operation handle.
774 */
775static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
776{
777 PTRPM pTrpm = &pVM->trpm.s;
778 LogFlow(("trpmR3Save:\n"));
779
780 /*
781 * Active and saved traps.
782 */
783 for (VMCPUID i = 0; i < pVM->cCpus; i++)
784 {
785 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
786 SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
787 SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
788 SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
789 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
790 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
791 SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
792 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
793 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
794 SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
795 }
796 SSMR3PutBool(pSSM, pTrpm->fDisableMonitoring);
797 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
798 SSMR3PutUInt(pSSM, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT));
799 SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
800 SSMR3PutU32(pSSM, ~0); /* separator. */
801
802 /*
803 * Save any trampoline gates.
804 */
805 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
806 {
807 if (pTrpm->aGuestTrapHandler[iTrap])
808 {
809 SSMR3PutU32(pSSM, iTrap);
810 SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
811 SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
812 }
813 }
814
815 return SSMR3PutU32(pSSM, ~0); /* terminator */
816}
817
818
819/**
820 * Execute state load operation.
821 *
822 * @returns VBox status code.
823 * @param pVM VM Handle.
824 * @param pSSM SSM operation handle.
825 * @param uVersion Data layout version.
826 * @param uPass The data pass.
827 */
828static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
829{
830 LogFlow(("trpmR3Load:\n"));
831 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
832
833 /*
834 * Validate version.
835 */
836 if ( uVersion != TRPM_SAVED_STATE_VERSION
837 && uVersion != TRPM_SAVED_STATE_VERSION_UNI)
838 {
839 AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
840 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
841 }
842
843 /*
844 * Call the reset function to kick out any handled gates and other potential trouble.
845 */
846 TRPMR3Reset(pVM);
847
848 /*
849 * Active and saved traps.
850 */
851 PTRPM pTrpm = &pVM->trpm.s;
852
853 if (uVersion == TRPM_SAVED_STATE_VERSION)
854 {
855 for (VMCPUID i = 0; i < pVM->cCpus; i++)
856 {
857 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
858 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
859 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
860 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
861 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
862 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
863 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
864 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
865 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
866 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
867 }
868
869 SSMR3GetBool(pSSM, &pVM->trpm.s.fDisableMonitoring);
870 }
871 else
872 {
873 PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
874 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
875 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
876 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
877 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
878 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
879 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
880 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
881 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
882 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
883
884 RTGCUINT fDisableMonitoring;
885 SSMR3GetGCUInt(pSSM, &fDisableMonitoring);
886 pTrpm->fDisableMonitoring = !!fDisableMonitoring;
887 }
888
889 RTUINT fSyncIDT;
890 int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
891 if (RT_FAILURE(rc))
892 return rc;
893 if (fSyncIDT & ~1)
894 {
895 AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
896 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
897 }
898 if (fSyncIDT)
899 {
900 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
901 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
902 }
903 /* else: cleared by reset call above. */
904
905 SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
906
907 /* check the separator */
908 uint32_t u32Sep;
909 rc = SSMR3GetU32(pSSM, &u32Sep);
910 if (RT_FAILURE(rc))
911 return rc;
912 if (u32Sep != (uint32_t)~0)
913 {
914 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
915 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
916 }
917
918 /*
919 * Restore any trampoline gates.
920 */
921 for (;;)
922 {
923 /* gate number / terminator */
924 uint32_t iTrap;
925 rc = SSMR3GetU32(pSSM, &iTrap);
926 if (RT_FAILURE(rc))
927 return rc;
928 if (iTrap == (uint32_t)~0)
929 break;
930 if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
931 || pTrpm->aGuestTrapHandler[iTrap])
932 {
933 AssertMsgFailed(("iTrap=%#x\n", iTrap));
934 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
935 }
936
937 /* restore the IDT entry. */
938 RTGCPTR GCPtrHandler;
939 SSMR3GetGCPtr(pSSM, &GCPtrHandler);
940 VBOXIDTE Idte;
941 rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
942 if (RT_FAILURE(rc))
943 return rc;
944 Assert(GCPtrHandler);
945 pTrpm->aIdt[iTrap] = Idte;
946 }
947
948 return VINF_SUCCESS;
949}
950
951
952/**
953 * Check if gate handlers were updated
954 * (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
955 *
956 * @returns VBox status code.
957 * @param pVM The VM handle.
958 * @param pVCpu The VMCPU handle.
959 */
960VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
961{
962 STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
963 const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
964 int rc;
965
966 if (pVM->trpm.s.fDisableMonitoring)
967 {
968 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
969 return VINF_SUCCESS; /* Nothing to do */
970 }
971
972 if (fRawRing0 && CSAMIsEnabled(pVM))
973 {
974 /* Clear all handlers */
975 Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
976 /** @todo inefficient, but simple */
977 for (unsigned iGate = 0; iGate < 256; iGate++)
978 trpmClearGuestTrapHandler(pVM, iGate);
979
980 /* Scan them all (only the first time) */
981 CSAMR3CheckGates(pVM, 0, 256);
982 }
983
984 /*
985 * Get the IDTR.
986 */
987 VBOXIDTR IDTR;
988 IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
989 if (!IDTR.cbIdt)
990 {
991 Log(("No IDT entries...\n"));
992 return DBGFSTOP(pVM);
993 }
994
995#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
996 /*
997 * Check if Guest's IDTR has changed.
998 */
999 if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1000 || IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1001 {
1002 Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1003 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1004 {
1005 /*
1006 * [Re]Register write virtual handler for guest's IDT.
1007 */
1008 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1009 {
1010 rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1011 AssertRCReturn(rc, rc);
1012 }
1013 /* limit is including */
1014 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1015 0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1016
1017 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1018 {
1019 /* Could be a conflict with CSAM */
1020 CSAMR3RemovePage(pVM, IDTR.pIdt);
1021 if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1022 CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1023
1024 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1025 0, trpmR3GuestIDTWriteHandler, "trpmRCGuestIDTWriteHandler", 0, "Guest IDT write access handler");
1026 }
1027
1028 AssertRCReturn(rc, rc);
1029 }
1030
1031 /* Update saved Guest IDTR. */
1032 pVM->trpm.s.GuestIdtr = IDTR;
1033 }
1034#endif
1035
1036 /*
1037 * Sync the interrupt gate.
1038 * Should probably check/sync the others too, but for now we'll handle that in #GP.
1039 */
1040 X86DESC Idte3;
1041 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1042 if (RT_FAILURE(rc))
1043 {
1044 AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1045 return DBGFSTOP(pVM);
1046 }
1047 AssertRCReturn(rc, rc);
1048 if (fRawRing0)
1049 pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1050 else
1051 pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1052
1053 /*
1054 * Clear the FF and we're done.
1055 */
1056 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1057 STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1058 return VINF_SUCCESS;
1059}
1060
1061
1062/**
1063 * Disable IDT monitoring and syncing
1064 *
1065 * @param pVM The VM to operate on.
1066 */
1067VMMR3DECL(void) TRPMR3DisableMonitoring(PVM pVM)
1068{
1069 /*
1070 * Deregister any virtual handlers.
1071 */
1072#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1073 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1074 {
1075 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1076 {
1077 int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.GuestIdtr.pIdt);
1078 AssertRC(rc);
1079 }
1080 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
1081 }
1082 pVM->trpm.s.GuestIdtr.cbIdt = 0;
1083#endif
1084
1085#ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
1086 if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
1087 {
1088 int rc = PGMHandlerVirtualDeregister(pVM, pVM->trpm.s.pvMonShwIdtRC);
1089 AssertRC(rc);
1090 pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
1091 }
1092#endif
1093
1094 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
1095 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1096
1097 pVM->trpm.s.fDisableMonitoring = true;
1098}
1099
1100
1101/**
1102 * \#PF Handler callback for virtual access handler ranges.
1103 *
1104 * Important to realize that a physical page in a range can have aliases, and
1105 * for ALL and WRITE handlers these will also trigger.
1106 *
1107 * @returns VINF_SUCCESS if the handler have carried out the operation.
1108 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1109 * @param pVM VM Handle.
1110 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1111 * @param pvPtr The HC mapping of that address.
1112 * @param pvBuf What the guest is reading/writing.
1113 * @param cbBuf How much it's reading/writing.
1114 * @param enmAccessType The access type.
1115 * @param pvUser User argument.
1116 */
1117static DECLCALLBACK(int) trpmR3GuestIDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1118{
1119 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1120 Log(("trpmR3GuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1121 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_TRPM_SYNC_IDT);
1122 return VINF_PGM_HANDLER_DO_DEFAULT;
1123}
1124
1125
1126/**
1127 * Clear passthrough interrupt gate handler (reset to default handler)
1128 *
1129 * @returns VBox status code.
1130 * @param pVM The VM to operate on.
1131 * @param iTrap Trap/interrupt gate number.
1132 */
1133VMMR3DECL(int) trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1134{
1135 /* Only applies to raw mode which supports only 1 VCPU. */
1136 PVMCPU pVCpu = &pVM->aCpus[0];
1137
1138 /** @todo cleanup trpmR3ClearPassThroughHandler()! */
1139 RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1140 int rc;
1141
1142 memset(aGCPtrs, 0, sizeof(aGCPtrs));
1143
1144 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1145 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMGC.gc!\n"));
1146
1147 if ( iTrap < TRPM_HANDLER_INT_BASE
1148 || iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1149 {
1150 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1151 return VERR_INVALID_PARAMETER;
1152 }
1153 memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1154
1155 /* Unmark it for relocation purposes. */
1156 ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1157
1158 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1159 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1160 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1161 if (pIdte->Gen.u1Present)
1162 {
1163 Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1164 Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1165 RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1166
1167 /*
1168 * Generic handlers have different entrypoints for each possible
1169 * vector number. These entrypoints make a sort of an array with
1170 * 8 byte entries where the vector number is the index.
1171 * See TRPMGCHandlersA.asm for details.
1172 */
1173 Offset += iTrap * 8;
1174
1175 if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1176 {
1177 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1178 pIdte->Gen.u16OffsetHigh = Offset >> 16;
1179 pIdte->Gen.u16SegSel = SelCS;
1180 }
1181 }
1182
1183 return VINF_SUCCESS;
1184}
1185
1186
1187/**
1188 * Check if address is a gate handler (interrupt or trap).
1189 *
1190 * @returns gate nr or ~0 is not found
1191 *
1192 * @param pVM VM handle.
1193 * @param GCPtr GC address to check.
1194 */
1195VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1196{
1197 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1198 {
1199 if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1200 return iTrap;
1201
1202 /* redundant */
1203 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1204 {
1205 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1206 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1207
1208 if (pHandler == GCPtr)
1209 return iTrap;
1210 }
1211 }
1212 return ~0;
1213}
1214
1215
1216/**
1217 * Get guest trap/interrupt gate handler
1218 *
1219 * @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1220 * @param pVM The VM to operate on.
1221 * @param iTrap Interrupt/trap number.
1222 */
1223VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1224{
1225 AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1226
1227 return pVM->trpm.s.aGuestTrapHandler[iTrap];
1228}
1229
1230
1231/**
1232 * Set guest trap/interrupt gate handler
1233 * Used for setting up trap gates used for kernel calls.
1234 *
1235 * @returns VBox status code.
1236 * @param pVM The VM to operate on.
1237 * @param iTrap Interrupt/trap number.
1238 * @param pHandler GC handler pointer
1239 */
1240VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1241{
1242 /* Only valid in raw mode which implies 1 VCPU */
1243 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1244 PVMCPU pVCpu = &pVM->aCpus[0];
1245
1246 /*
1247 * Validate.
1248 */
1249 if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1250 {
1251 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1252 return VERR_INVALID_PARAMETER;
1253 }
1254
1255 AssertReturn(pHandler == TRPM_INVALID_HANDLER || PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1256
1257 uint16_t cbIDT;
1258 RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1259 if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1260 return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1261
1262 if (pHandler == TRPM_INVALID_HANDLER)
1263 {
1264 /* clear trap handler */
1265 Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1266 return trpmClearGuestTrapHandler(pVM, iTrap);
1267 }
1268
1269 /*
1270 * Read the guest IDT entry.
1271 */
1272 VBOXIDTE GuestIdte;
1273 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1274 if (RT_FAILURE(rc))
1275 {
1276 AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1277 return rc;
1278 }
1279
1280 if (EMIsRawRing0Enabled(pVM))
1281 {
1282 /*
1283 * Only replace handlers for which we are 100% certain there won't be
1284 * any host interrupts.
1285 *
1286 * 0x2E is safe on Windows because it's the system service interrupt gate. Not
1287 * quite certain if this is safe or not on 64-bit Vista, it probably is.
1288 *
1289 * 0x80 is safe on Linux because it's the syscall vector and is part of the
1290 * 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1291 * and will therefor never assign hardware interrupts to 0x80.
1292 *
1293 * Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1294 * to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1295 * Booting Linux/BSD guest will cause system lockups on most of the computers.
1296 * -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1297 * defect #3604.
1298 *
1299 * PORTME - Check if your host keeps any of these gates free from hw ints.
1300 *
1301 * Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1302 */
1303 /** @todo handle those dependencies better! */
1304 /** @todo Solve this in a proper manner. see defect #1186 */
1305#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1306 if (iTrap == 0x2E)
1307#elif defined(RT_OS_LINUX)
1308 if (iTrap == 0x80)
1309#else
1310 if (0)
1311#endif
1312 {
1313 if ( GuestIdte.Gen.u1Present
1314 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1315 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1316 && GuestIdte.Gen.u2DPL == 3)
1317 {
1318 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1319
1320 GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1321 GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1322 GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1323 GuestIdte.Gen.u16SegSel |= 1; //ring 1
1324 *pIdte = GuestIdte;
1325
1326 /* Mark it for relocation purposes. */
1327 ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1328
1329 /* Also store it in our guest trap array. */
1330 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1331
1332 Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1333 return VINF_SUCCESS;
1334 }
1335 /* ok, let's try to install a trampoline handler then. */
1336 }
1337 }
1338
1339 if ( GuestIdte.Gen.u1Present
1340 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1341 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1342 && (GuestIdte.Gen.u2DPL == 3 || GuestIdte.Gen.u2DPL == 0))
1343 {
1344 /*
1345 * Save handler which can be used for a trampoline call inside the GC
1346 */
1347 Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1348 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1349 return VINF_SUCCESS;
1350 }
1351 return VERR_INVALID_PARAMETER;
1352}
1353
1354
1355/**
1356 * Check if address is a gate handler (interrupt/trap/task/anything).
1357 *
1358 * @returns True is gate handler, false if not.
1359 *
1360 * @param pVM VM handle.
1361 * @param GCPtr GC address to check.
1362 */
1363VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1364{
1365 /* Only valid in raw mode which implies 1 VCPU */
1366 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1367 PVMCPU pVCpu = &pVM->aCpus[0];
1368
1369 /*
1370 * Read IDTR and calc last entry.
1371 */
1372 uint16_t cbIDT;
1373 RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1374 unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1375 if (!cEntries)
1376 return false;
1377 RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1378
1379 /*
1380 * Outer loop: interate pages.
1381 */
1382 while (GCPtrIDTE <= GCPtrIDTELast)
1383 {
1384 /*
1385 * Convert this page to a HC address.
1386 * (This function checks for not-present pages.)
1387 */
1388 PCVBOXIDTE pIDTE;
1389 PGMPAGEMAPLOCK Lock;
1390 int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1391 if (RT_SUCCESS(rc))
1392 {
1393 /*
1394 * Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1395 * N.B. Member of the Flat Earth Society...
1396 */
1397 while (GCPtrIDTE <= GCPtrIDTELast)
1398 {
1399 if (pIDTE->Gen.u1Present)
1400 {
1401 RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1402 if (GCPtr == GCPtrHandler)
1403 {
1404 PGMPhysReleasePageMappingLock(pVM, &Lock);
1405 return true;
1406 }
1407 }
1408
1409 /* next entry */
1410 if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1411 {
1412 AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1413 ("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1414 GCPtrIDTE += sizeof(VBOXIDTE);
1415 break;
1416 }
1417 GCPtrIDTE += sizeof(VBOXIDTE);
1418 pIDTE++;
1419 }
1420 PGMPhysReleasePageMappingLock(pVM, &Lock);
1421 }
1422 else
1423 {
1424 /* Skip to the next page (if any). Take care not to wrap around the address space. */
1425 if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1426 return false;
1427 GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1428 }
1429 }
1430 return false;
1431}
1432
1433
1434/**
1435 * Inject event (such as external irq or trap)
1436 *
1437 * @returns VBox status code.
1438 * @param pVM The VM to operate on.
1439 * @param pVCpu The VMCPU to operate on.
1440 * @param enmEvent Trpm event type
1441 */
1442VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1443{
1444 PCPUMCTX pCtx;
1445 int rc;
1446
1447 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1448 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1449 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1450
1451 /* Currently only useful for external hardware interrupts. */
1452 Assert(enmEvent == TRPM_HARDWARE_INT);
1453
1454 if (REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ)
1455 {
1456#ifdef TRPM_FORWARD_TRAPS_IN_GC
1457
1458# ifdef LOG_ENABLED
1459 DBGFR3InfoLog(pVM, "cpumguest", "TRPMInject");
1460 DBGFR3DisasInstrCurrentLog(pVCpu, "TRPMInject");
1461# endif
1462
1463 uint8_t u8Interrupt;
1464 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1465 Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1466 if (RT_SUCCESS(rc))
1467 {
1468 if (HWACCMIsEnabled(pVM))
1469 {
1470 rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1471 AssertRC(rc);
1472 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1473 return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM;
1474 }
1475 /* If the guest gate is not patched, then we will check (again) if we can patch it. */
1476 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1477 {
1478 CSAMR3CheckGates(pVM, u8Interrupt, 1);
1479 Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1480 }
1481
1482 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1483 {
1484 /* Must check pending forced actions as our IDT or GDT might be out of sync */
1485 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1486 if (rc == VINF_SUCCESS)
1487 {
1488 /* There's a handler -> let's execute it in raw mode */
1489 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1490 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1491 {
1492 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
1493
1494 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1495 return VINF_EM_RESCHEDULE_RAW;
1496 }
1497 }
1498 }
1499 else
1500 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1501 REMR3NotifyPendingInterrupt(pVM, pVCpu, u8Interrupt);
1502 }
1503 else
1504 {
1505 AssertRC(rc);
1506 return HWACCMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HWACC : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1507 }
1508#else
1509 if (HWACCMR3IsActive(pVM))
1510 {
1511 uint8_t u8Interrupt;
1512 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1513 Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1514 if (RT_SUCCESS(rc))
1515 {
1516 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
1517 AssertRC(rc);
1518 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1519 return VINF_EM_RESCHEDULE_HWACC;
1520 }
1521 }
1522 else
1523 AssertRC(rc);
1524#endif
1525 }
1526 /** @todo check if it's safe to translate the patch address to the original guest address.
1527 * this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1528 */
1529 /* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return code below. */
1530
1531 /* Fall back to the recompiler */
1532 return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1533}
1534
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