VirtualBox

source: vbox/trunk/src/VBox/VMM/SELM.cpp@ 25414

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1/* $Id: SELM.cpp 25233 2009-12-08 12:09:17Z vboxsync $ */
2/** @file
3 * SELM - The Selector Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_selm SELM - The Selector Manager
23 *
24 * SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
25 * of a few hyper selector for the raw-mode context. In the hardware assisted
26 * virtualization mode its only task is to decode entries in the guest GDT or
27 * LDT once in a while.
28 *
29 * @see grp_selm
30 *
31 *
32 * @section seg_selm_shadowing Shadowing
33 *
34 * SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
35 * work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
36 * The idea is to do it in a more on-demand fashion when we get time. There
37 * also a whole bunch of issues with the current synchronization of all three
38 * tables, see notes and todos in the code.
39 *
40 * When the guest makes changes to the GDT we will try update the shadow copy
41 * without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
42 *
43 * When the guest make LDT changes we'll trigger a full resync of the LDT
44 * (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
45 *
46 * The TSS shadowing is limited to the fields we need to care about, namely SS0
47 * and ESP0. The Patch Manager makes use of these. We monitor updates to the
48 * guest TSS and will try keep our SS0 and ESP0 copies up to date this way
49 * rather than go the SELMR3SyncTSS() route.
50 *
51 * When in raw-mode SELM also injects a few extra GDT selectors which are used
52 * by the raw-mode (hyper) context. These start their life at the high end of
53 * the table and will be relocated when the guest tries to make use of them...
54 * Well, that was that idea at least, only the code isn't quite there yet which
55 * is why we have trouble with guests which actually have a full sized GDT.
56 *
57 * So, the summary of the current GDT, LDT and TSS shadowing is that there is a
58 * lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
59 *
60 */
61
62/*******************************************************************************
63* Header Files *
64*******************************************************************************/
65#define LOG_GROUP LOG_GROUP_SELM
66#include <VBox/selm.h>
67#include <VBox/cpum.h>
68#include <VBox/stam.h>
69#include <VBox/mm.h>
70#include <VBox/ssm.h>
71#include <VBox/pgm.h>
72#include <VBox/trpm.h>
73#include <VBox/dbgf.h>
74#include "SELMInternal.h"
75#include <VBox/vm.h>
76#include <VBox/err.h>
77#include <VBox/param.h>
78
79#include <iprt/assert.h>
80#include <VBox/log.h>
81#include <iprt/asm.h>
82#include <iprt/string.h>
83#include <iprt/thread.h>
84#include <iprt/string.h>
85
86
87/**
88 * Enable or disable tracking of Guest's GDT/LDT/TSS.
89 * @{
90 */
91#define SELM_TRACK_GUEST_GDT_CHANGES
92#define SELM_TRACK_GUEST_LDT_CHANGES
93#define SELM_TRACK_GUEST_TSS_CHANGES
94/** @} */
95
96/**
97 * Enable or disable tracking of Shadow GDT/LDT/TSS.
98 * @{
99 */
100#define SELM_TRACK_SHADOW_GDT_CHANGES
101#define SELM_TRACK_SHADOW_LDT_CHANGES
102#define SELM_TRACK_SHADOW_TSS_CHANGES
103/** @} */
104
105
106/** SELM saved state version. */
107#define SELM_SAVED_STATE_VERSION 5
108
109
110/*******************************************************************************
111* Internal Functions *
112*******************************************************************************/
113static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
114static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
115static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
116static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
117static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
118static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
119static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
120static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
121static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
122static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
123//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
124//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125
126
127
128/**
129 * Initializes the SELM.
130 *
131 * @returns VBox status code.
132 * @param pVM The VM to operate on.
133 */
134VMMR3DECL(int) SELMR3Init(PVM pVM)
135{
136 LogFlow(("SELMR3Init\n"));
137
138 /*
139 * Assert alignment and sizes.
140 * (The TSS block requires contiguous back.)
141 */
142 AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
143 AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
144#if 0 /* doesn't work */
145 AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
146 AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
147#endif
148 AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
149 AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
150 AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
151
152 /*
153 * Init the structure.
154 */
155 pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
156 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
157 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
158 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
159 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
160 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
161
162 /*
163 * Allocate GDT table.
164 */
165 int rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
166 PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
167 AssertRCReturn(rc, rc);
168
169 /*
170 * Allocate LDT area.
171 */
172 rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
173 AssertRCReturn(rc, rc);
174
175 /*
176 * Init Guest's and Shadow GDT, LDT, TSS changes control variables.
177 */
178 pVM->selm.s.cbEffGuestGdtLimit = 0;
179 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
180 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
181 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
182
183 pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
184 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
185 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
186 pVM->selm.s.GCSelTss = RTSEL_MAX;
187
188 pVM->selm.s.fDisableMonitoring = false;
189 pVM->selm.s.fSyncTSSRing0Stack = false;
190
191 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
192 * for I/O operations. */
193 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
194 /* bit set to 1 means no redirection */
195 memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
196
197 /*
198 * Register the saved state data unit.
199 */
200 rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
201 NULL, NULL, NULL,
202 NULL, selmR3Save, NULL,
203 NULL, selmR3Load, selmR3LoadDone);
204 if (RT_FAILURE(rc))
205 return rc;
206
207 /*
208 * Statistics.
209 */
210 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
211 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
212 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
213 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
214 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
215 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
216 STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
217 STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
218 STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
219
220 STAM_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
221 STAM_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
222
223 /*
224 * Default action when entering raw mode for the first time
225 */
226 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
227 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
228 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
229 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
230
231 /*
232 * Register info handlers.
233 */
234 DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
235 DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
236 DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
237 DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
238 //DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
239 //DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
240
241 return rc;
242}
243
244
245/**
246 * Finalizes HMA page attributes.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM handle.
250 */
251VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
252{
253 /** @cfgm{/DoubleFault,bool,false}
254 * Enables catching of double faults in the raw-mode context VMM code. This can
255 * be used when the tripple faults or hangs occure and one suspect an unhandled
256 * double fault. This is not enabled by default because it means making the
257 * hyper selectors writeable for all supervisor code, including the guest's.
258 * The double fault is a task switch and thus requires write access to the GDT
259 * of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
260 * 8 TSS for the back link.
261 */
262 bool f;
263#if defined(DEBUG_bird)
264 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
265#else
266 int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
267#endif
268 AssertLogRelRCReturn(rc, rc);
269 if (f)
270 {
271 PX86DESC paGdt = pVM->selm.s.paGdtR3;
272 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
273 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
274 AssertRC(rc);
275 rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
276 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
277 AssertRC(rc);
278 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
279 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
280 AssertRC(rc);
281 rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
282 X86_PTE_RW | X86_PTE_P | X86_PTE_A | X86_PTE_D);
283 AssertRC(rc);
284 }
285 return VINF_SUCCESS;
286}
287
288
289/**
290 * Setup the hypervisor GDT selectors in our shadow table
291 *
292 * @param pVM The VM handle.
293 */
294static void selmR3SetupHyperGDTSelectors(PVM pVM)
295{
296 PX86DESC paGdt = pVM->selm.s.paGdtR3;
297
298 /*
299 * Set up global code and data descriptors for use in the guest context.
300 * Both are wide open (base 0, limit 4GB)
301 */
302 PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
303 pDesc->Gen.u16LimitLow = 0xffff;
304 pDesc->Gen.u4LimitHigh = 0xf;
305 pDesc->Gen.u16BaseLow = 0;
306 pDesc->Gen.u8BaseHigh1 = 0;
307 pDesc->Gen.u8BaseHigh2 = 0;
308 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
309 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
310 pDesc->Gen.u2Dpl = 0; /* supervisor */
311 pDesc->Gen.u1Present = 1;
312 pDesc->Gen.u1Available = 0;
313 pDesc->Gen.u1Long = 0;
314 pDesc->Gen.u1DefBig = 1; /* def 32 bit */
315 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
316
317 /* data */
318 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
319 pDesc->Gen.u16LimitLow = 0xffff;
320 pDesc->Gen.u4LimitHigh = 0xf;
321 pDesc->Gen.u16BaseLow = 0;
322 pDesc->Gen.u8BaseHigh1 = 0;
323 pDesc->Gen.u8BaseHigh2 = 0;
324 pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
325 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
326 pDesc->Gen.u2Dpl = 0; /* supervisor */
327 pDesc->Gen.u1Present = 1;
328 pDesc->Gen.u1Available = 0;
329 pDesc->Gen.u1Long = 0;
330 pDesc->Gen.u1DefBig = 1; /* big */
331 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
332
333 /* 64-bit mode code (& data?) */
334 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
335 pDesc->Gen.u16LimitLow = 0xffff;
336 pDesc->Gen.u4LimitHigh = 0xf;
337 pDesc->Gen.u16BaseLow = 0;
338 pDesc->Gen.u8BaseHigh1 = 0;
339 pDesc->Gen.u8BaseHigh2 = 0;
340 pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
341 pDesc->Gen.u1DescType = 1; /* not system, but code/data */
342 pDesc->Gen.u2Dpl = 0; /* supervisor */
343 pDesc->Gen.u1Present = 1;
344 pDesc->Gen.u1Available = 0;
345 pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
346 pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
347 pDesc->Gen.u1Granularity = 1; /* 4KB limit */
348
349 /*
350 * TSS descriptor
351 */
352 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
353 RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
354 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
355 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
356 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
357 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
358 pDesc->Gen.u4LimitHigh = 0;
359 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
360 pDesc->Gen.u1DescType = 0; /* system */
361 pDesc->Gen.u2Dpl = 0; /* supervisor */
362 pDesc->Gen.u1Present = 1;
363 pDesc->Gen.u1Available = 0;
364 pDesc->Gen.u1Long = 0;
365 pDesc->Gen.u1DefBig = 0;
366 pDesc->Gen.u1Granularity = 0; /* byte limit */
367
368 /*
369 * TSS descriptor for trap 08
370 */
371 pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
372 pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
373 pDesc->Gen.u4LimitHigh = 0;
374 RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
375 pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
376 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
377 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
378 pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
379 pDesc->Gen.u1DescType = 0; /* system */
380 pDesc->Gen.u2Dpl = 0; /* supervisor */
381 pDesc->Gen.u1Present = 1;
382 pDesc->Gen.u1Available = 0;
383 pDesc->Gen.u1Long = 0;
384 pDesc->Gen.u1DefBig = 0;
385 pDesc->Gen.u1Granularity = 0; /* byte limit */
386}
387
388/**
389 * Applies relocations to data and code managed by this
390 * component. This function will be called at init and
391 * whenever the VMM need to relocate it self inside the GC.
392 *
393 * @param pVM The VM.
394 */
395VMMR3DECL(void) SELMR3Relocate(PVM pVM)
396{
397 PX86DESC paGdt = pVM->selm.s.paGdtR3;
398 LogFlow(("SELMR3Relocate\n"));
399
400 for (VMCPUID i = 0; i < pVM->cCpus; i++)
401 {
402 PVMCPU pVCpu = &pVM->aCpus[i];
403
404 /*
405 * Update GDTR and selector.
406 */
407 CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
408
409 /** @todo selector relocations should be a seperate operation? */
410 CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
411 CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
412 CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
413 CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
414 CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
415 }
416
417 selmR3SetupHyperGDTSelectors(pVM);
418
419/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
420/** @todo PGM knows the proper CR3 values these days, not CPUM. */
421 /*
422 * Update the TSSes.
423 */
424 /* Only applies to raw mode which supports only 1 VCPU */
425 PVMCPU pVCpu = &pVM->aCpus[0];
426
427 /* Current TSS */
428 pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
429 pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
430 pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVM);
431 pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
432 pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
433 pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
434 pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
435
436 /* trap 08 */
437 pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
438 pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
439 pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
440 pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVM) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
441 pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
442 pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
443 pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
444 pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
445 pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
446 pVM->selm.s.TssTrap08.fs = 0;
447 pVM->selm.s.TssTrap08.gs = 0;
448 pVM->selm.s.TssTrap08.selLdt = 0;
449 pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
450 pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
451 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
452 pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
453 pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
454 pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
455 pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
456 pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
457 /* TRPM will be updating the eip */
458
459 if (!pVM->selm.s.fDisableMonitoring)
460 {
461 /*
462 * Update shadow GDT/LDT/TSS write access handlers.
463 */
464 int rc;
465#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
466 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
467 {
468 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
469 AssertRC(rc);
470 }
471 pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
472 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.paGdtRC,
473 pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
474 0, 0, "selmRCShadowGDTWriteHandler", 0, "Shadow GDT write access handler");
475 AssertRC(rc);
476#endif
477#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
478 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
479 {
480 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
481 AssertRC(rc);
482 }
483 pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
484 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvMonShwTssRC,
485 pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
486 0, 0, "selmRCShadowTSSWriteHandler", 0, "Shadow TSS write access handler");
487 AssertRC(rc);
488#endif
489
490 /*
491 * Update the GC LDT region handler and address.
492 */
493#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
494 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
495 {
496 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
497 AssertRC(rc);
498 }
499#endif
500 pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
501#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
502 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_HYPERVISOR, pVM->selm.s.pvLdtRC,
503 pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
504 0, 0, "selmRCShadowLDTWriteHandler", 0, "Shadow LDT write access handler");
505 AssertRC(rc);
506#endif
507 }
508}
509
510
511/**
512 * Terminates the SELM.
513 *
514 * Termination means cleaning up and freeing all resources,
515 * the VM it self is at this point powered off or suspended.
516 *
517 * @returns VBox status code.
518 * @param pVM The VM to operate on.
519 */
520VMMR3DECL(int) SELMR3Term(PVM pVM)
521{
522 return 0;
523}
524
525
526/**
527 * The VM is being reset.
528 *
529 * For the SELM component this means that any GDT/LDT/TSS monitors
530 * needs to be removed.
531 *
532 * @param pVM VM handle.
533 */
534VMMR3DECL(void) SELMR3Reset(PVM pVM)
535{
536 LogFlow(("SELMR3Reset:\n"));
537 VM_ASSERT_EMT(pVM);
538
539 /*
540 * Uninstall guest GDT/LDT/TSS write access handlers.
541 */
542 int rc;
543#ifdef SELM_TRACK_GUEST_GDT_CHANGES
544 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
545 {
546 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
547 AssertRC(rc);
548 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
549 pVM->selm.s.GuestGdtr.cbGdt = 0;
550 }
551 pVM->selm.s.fGDTRangeRegistered = false;
552#endif
553#ifdef SELM_TRACK_GUEST_LDT_CHANGES
554 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
555 {
556 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
557 AssertRC(rc);
558 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
559 }
560#endif
561#ifdef SELM_TRACK_GUEST_TSS_CHANGES
562 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
563 {
564 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
565 AssertRC(rc);
566 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
567 pVM->selm.s.GCSelTss = RTSEL_MAX;
568 }
569#endif
570
571 /*
572 * Re-initialize other members.
573 */
574 pVM->selm.s.cbLdtLimit = 0;
575 pVM->selm.s.offLdtHyper = 0;
576 pVM->selm.s.cbMonitoredGuestTss = 0;
577
578 pVM->selm.s.fSyncTSSRing0Stack = false;
579
580 /*
581 * Default action when entering raw mode for the first time
582 */
583 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
584 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
585 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
586 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
587}
588
589/**
590 * Disable GDT/LDT/TSS monitoring and syncing
591 *
592 * @param pVM The VM to operate on.
593 */
594VMMR3DECL(void) SELMR3DisableMonitoring(PVM pVM)
595{
596 /*
597 * Uninstall guest GDT/LDT/TSS write access handlers.
598 */
599 int rc;
600#ifdef SELM_TRACK_GUEST_GDT_CHANGES
601 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
602 {
603 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
604 AssertRC(rc);
605 pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
606 pVM->selm.s.GuestGdtr.cbGdt = 0;
607 }
608 pVM->selm.s.fGDTRangeRegistered = false;
609#endif
610#ifdef SELM_TRACK_GUEST_LDT_CHANGES
611 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
612 {
613 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
614 AssertRC(rc);
615 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
616 }
617#endif
618#ifdef SELM_TRACK_GUEST_TSS_CHANGES
619 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
620 {
621 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
622 AssertRC(rc);
623 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
624 pVM->selm.s.GCSelTss = RTSEL_MAX;
625 }
626#endif
627
628 /*
629 * Unregister shadow GDT/LDT/TSS write access handlers.
630 */
631#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
632 if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
633 {
634 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.paGdtRC);
635 AssertRC(rc);
636 pVM->selm.s.paGdtRC = NIL_RTRCPTR;
637 }
638#endif
639#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
640 if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
641 {
642 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvMonShwTssRC);
643 AssertRC(rc);
644 pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
645 }
646#endif
647#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
648 if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
649 {
650 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.pvLdtRC);
651 AssertRC(rc);
652 pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
653 }
654#endif
655
656 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
657 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
658 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
659 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
660
661 pVM->selm.s.fDisableMonitoring = true;
662}
663
664
665/**
666 * Execute state save operation.
667 *
668 * @returns VBox status code.
669 * @param pVM VM Handle.
670 * @param pSSM SSM operation handle.
671 */
672static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
673{
674 LogFlow(("selmR3Save:\n"));
675
676 /*
677 * Save the basic bits - fortunately all the other things can be resynced on load.
678 */
679 PSELM pSelm = &pVM->selm.s;
680
681 SSMR3PutBool(pSSM, pSelm->fDisableMonitoring);
682 SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
683 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
684 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
685 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
686 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
687 SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
688 return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
689}
690
691
692/**
693 * Execute state load operation.
694 *
695 * @returns VBox status code.
696 * @param pVM VM Handle.
697 * @param pSSM SSM operation handle.
698 * @param uVersion Data layout version.
699 * @param uPass The data pass.
700 */
701static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
702{
703 LogFlow(("selmR3Load:\n"));
704 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
705
706 /*
707 * Validate version.
708 */
709 if (uVersion != SELM_SAVED_STATE_VERSION)
710 {
711 AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
712 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
713 }
714
715 /*
716 * Do a reset.
717 */
718 SELMR3Reset(pVM);
719
720 /* Get the monitoring flag. */
721 SSMR3GetBool(pSSM, &pVM->selm.s.fDisableMonitoring);
722
723 /* Get the TSS state flag. */
724 SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
725
726 /*
727 * Get the selectors.
728 */
729 RTSEL SelCS;
730 SSMR3GetSel(pSSM, &SelCS);
731 RTSEL SelDS;
732 SSMR3GetSel(pSSM, &SelDS);
733 RTSEL SelCS64;
734 SSMR3GetSel(pSSM, &SelCS64);
735 RTSEL SelDS64;
736 SSMR3GetSel(pSSM, &SelDS64);
737 RTSEL SelTSS;
738 SSMR3GetSel(pSSM, &SelTSS);
739 RTSEL SelTSSTrap08;
740 SSMR3GetSel(pSSM, &SelTSSTrap08);
741
742 /* Copy the selectors; they will be checked during relocation. */
743 PSELM pSelm = &pVM->selm.s;
744 pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
745 pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
746 pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
747 pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
748 pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
749
750 return VINF_SUCCESS;
751}
752
753
754/**
755 * Sync the GDT, LDT and TSS after loading the state.
756 *
757 * Just to play save, we set the FFs to force syncing before
758 * executing GC code.
759 *
760 * @returns VBox status code.
761 * @param pVM VM Handle.
762 * @param pSSM SSM operation handle.
763 */
764static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
765{
766 PVMCPU pVCpu = VMMGetCpu(pVM);
767
768 LogFlow(("selmR3LoadDone:\n"));
769
770 /*
771 * Don't do anything if it's a load failure.
772 */
773 int rc = SSMR3HandleGetStatus(pSSM);
774 if (RT_FAILURE(rc))
775 return VINF_SUCCESS;
776
777 /*
778 * Do the syncing if we're in protected mode.
779 */
780 if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
781 {
782 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
783 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
784 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
785 SELMR3UpdateFromCPUM(pVM, pVCpu);
786 }
787
788 /*
789 * Flag everything for resync on next raw mode entry.
790 */
791 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
792 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
793 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
794
795 return VINF_SUCCESS;
796}
797
798
799/**
800 * Updates the Guest GDT & LDT virtualization based on current CPU state.
801 *
802 * @returns VBox status code.
803 * @param pVM The VM to operate on.
804 * @param pVCpu The VMCPU to operate on.
805 */
806VMMR3DECL(int) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
807{
808 int rc = VINF_SUCCESS;
809
810 if (pVM->selm.s.fDisableMonitoring)
811 {
812 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
813 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
814 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
815
816 return VINF_SUCCESS;
817 }
818
819 STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
820
821 /*
822 * GDT sync
823 */
824 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
825 {
826 /*
827 * Always assume the best
828 */
829 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
830
831 /* If the GDT was changed, then make sure the LDT is checked too */
832 /** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
833 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
834 /* Same goes for the TSS selector */
835 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
836
837 /*
838 * Get the GDTR and check if there is anything to do (there usually is).
839 */
840 VBOXGDTR GDTR;
841 CPUMGetGuestGDTR(pVCpu, &GDTR);
842 if (GDTR.cbGdt < sizeof(X86DESC))
843 {
844 Log(("No GDT entries...\n"));
845 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
846 return VINF_SUCCESS;
847 }
848
849 /*
850 * Read the Guest GDT.
851 * ASSUMES that the entire GDT is in memory.
852 */
853 RTUINT cbEffLimit = GDTR.cbGdt;
854 PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
855 rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
856 if (RT_FAILURE(rc))
857 {
858 /*
859 * Read it page by page.
860 *
861 * Keep track of the last valid page and delay memsets and
862 * adjust cbEffLimit to reflect the effective size. The latter
863 * is something we do in the belief that the guest will probably
864 * never actually commit the last page, thus allowing us to keep
865 * our selectors in the high end of the GDT.
866 */
867 RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
868 RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
869 uint8_t *pu8Dst = (uint8_t *)&pVM->selm.s.paGdtR3[1];
870 uint8_t *pu8DstInvalid = pu8Dst;
871
872 while (cbLeft)
873 {
874 RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
875 cb = RT_MIN(cb, cbLeft);
876 rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
877 if (RT_SUCCESS(rc))
878 {
879 if (pu8DstInvalid != pu8Dst)
880 memset(pu8DstInvalid, 0, pu8Dst - pu8DstInvalid);
881 GCPtrSrc += cb;
882 pu8Dst += cb;
883 pu8DstInvalid = pu8Dst;
884 }
885 else if ( rc == VERR_PAGE_NOT_PRESENT
886 || rc == VERR_PAGE_TABLE_NOT_PRESENT)
887 {
888 GCPtrSrc += cb;
889 pu8Dst += cb;
890 }
891 else
892 {
893 AssertReleaseMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
894 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
895 return VERR_NOT_IMPLEMENTED;
896 }
897 cbLeft -= cb;
898 }
899
900 /* any invalid pages at the end? */
901 if (pu8DstInvalid != pu8Dst)
902 {
903 cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
904 /* If any GDTEs was invalidated, zero them. */
905 if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
906 memset(pu8DstInvalid + cbEffLimit + 1, 0, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
907 }
908
909 /* keep track of the effective limit. */
910 if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
911 {
912 Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
913 pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
914 pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
915 }
916 }
917
918 /*
919 * Check if the Guest GDT intrudes on our GDT entries.
920 */
921 /** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
922 RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
923 if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
924 {
925 PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
926 PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
927 int iGDT = 0;
928
929 Log(("Internal SELM GDT conflict: use non-present entries\n"));
930 STAM_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
931 while (pGDTECur > pGDTEStart)
932 {
933 /* We can reuse non-present entries */
934 if (!pGDTECur->Gen.u1Present)
935 {
936 aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
937 aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
938 Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
939 iGDT++;
940 if (iGDT >= SELM_HYPER_SEL_MAX)
941 break;
942 }
943
944 pGDTECur--;
945 }
946 if (iGDT != SELM_HYPER_SEL_MAX)
947 {
948 AssertReleaseMsgFailed(("Internal SELM GDT conflict.\n"));
949 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
950 return VERR_NOT_IMPLEMENTED;
951 }
952 }
953 else
954 {
955 aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
956 aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
957 aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
958 aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
959 aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
960 }
961
962 /*
963 * Work thru the copied GDT entries adjusting them for correct virtualization.
964 */
965 PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
966 while (pGDTE < pGDTEEnd)
967 {
968 if (pGDTE->Gen.u1Present)
969 {
970 /*
971 * Code and data selectors are generally 1:1, with the
972 * 'little' adjustment we do for DPL 0 selectors.
973 */
974 if (pGDTE->Gen.u1DescType)
975 {
976 /*
977 * Hack for A-bit against Trap E on read-only GDT.
978 */
979 /** @todo Fix this by loading ds and cs before turning off WP. */
980 pGDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
981
982 /*
983 * All DPL 0 code and data segments are squeezed into DPL 1.
984 *
985 * We're skipping conforming segments here because those
986 * cannot give us any trouble.
987 */
988 if ( pGDTE->Gen.u2Dpl == 0
989 && (pGDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
990 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
991 pGDTE->Gen.u2Dpl = 1;
992 }
993 else
994 {
995 /*
996 * System type selectors are marked not present.
997 * Recompiler or special handling is required for these.
998 */
999 /** @todo what about interrupt gates and rawr0? */
1000 pGDTE->Gen.u1Present = 0;
1001 }
1002 }
1003
1004 /* Next GDT entry. */
1005 pGDTE++;
1006 }
1007
1008 /*
1009 * Check if our hypervisor selectors were changed.
1010 */
1011 if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
1012 || aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
1013 || aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
1014 || aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1015 || aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1016 {
1017 /* Reinitialize our hypervisor GDTs */
1018 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1019 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1020 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1021 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1022 pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1023
1024 STAM_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1025
1026 /*
1027 * Do the relocation callbacks to let everyone update their hyper selector dependencies.
1028 * (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1029 */
1030 VMR3Relocate(pVM, 0);
1031 }
1032 else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1033 /* We overwrote all entries above, so we have to save them again. */
1034 selmR3SetupHyperGDTSelectors(pVM);
1035
1036 /*
1037 * Adjust the cached GDT limit.
1038 * Any GDT entries which have been removed must be cleared.
1039 */
1040 if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1041 {
1042 if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1043 memset(pGDTE, 0, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1044#ifndef SELM_TRACK_GUEST_GDT_CHANGES
1045 pVM->selm.s.GuestGdtr.cbGdt = GDTR.cbGdt;
1046#endif
1047 }
1048
1049#ifdef SELM_TRACK_GUEST_GDT_CHANGES
1050 /*
1051 * Check if Guest's GDTR is changed.
1052 */
1053 if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1054 || GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1055 {
1056 Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1057
1058 /*
1059 * [Re]Register write virtual handler for guest's GDT.
1060 */
1061 if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1062 {
1063 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GuestGdtr.pGdt);
1064 AssertRC(rc);
1065 }
1066
1067 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1068 0, selmR3GuestGDTWriteHandler, "selmRCGuestGDTWriteHandler", 0, "Guest GDT write access handler");
1069 if (RT_FAILURE(rc))
1070 return rc;
1071
1072 /* Update saved Guest GDTR. */
1073 pVM->selm.s.GuestGdtr = GDTR;
1074 pVM->selm.s.fGDTRangeRegistered = true;
1075 }
1076#endif
1077 }
1078
1079 /*
1080 * TSS sync
1081 */
1082 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1083 {
1084 SELMR3SyncTSS(pVM, pVCpu);
1085 }
1086
1087 /*
1088 * LDT sync
1089 */
1090 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1091 {
1092 /*
1093 * Always assume the best
1094 */
1095 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1096
1097 /*
1098 * LDT handling is done similarly to the GDT handling with a shadow
1099 * array. However, since the LDT is expected to be swappable (at least
1100 * some ancient OSes makes it swappable) it must be floating and
1101 * synced on a per-page basis.
1102 *
1103 * Eventually we will change this to be fully on demand. Meaning that
1104 * we will only sync pages containing LDT selectors actually used and
1105 * let the #PF handler lazily sync pages as they are used.
1106 * (This applies to GDT too, when we start making OS/2 fast.)
1107 */
1108
1109 /*
1110 * First, determin the current LDT selector.
1111 */
1112 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1113 if ((SelLdt & X86_SEL_MASK) == 0)
1114 {
1115 /* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1116 CPUMSetHyperLDTR(pVCpu, 0);
1117#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1118 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1119 {
1120 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1121 AssertRC(rc);
1122 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1123 }
1124#endif
1125 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1126 return VINF_SUCCESS;
1127 }
1128
1129 /*
1130 * Get the LDT selector.
1131 */
1132 PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1133 RTGCPTR GCPtrLdt = X86DESC_BASE(*pDesc);
1134 unsigned cbLdt = X86DESC_LIMIT(*pDesc);
1135 if (pDesc->Gen.u1Granularity)
1136 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1137
1138 /*
1139 * Validate it.
1140 */
1141 if ( !cbLdt
1142 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1143 || pDesc->Gen.u1DescType
1144 || pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1145 {
1146 AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1147
1148 /* cbLdt > 0:
1149 * This is quite impossible, so we do as most people do when faced with
1150 * the impossible, we simply ignore it.
1151 */
1152 CPUMSetHyperLDTR(pVCpu, 0);
1153#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1154 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1155 {
1156 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1157 AssertRC(rc);
1158 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1159 }
1160#endif
1161 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1162 return VINF_SUCCESS;
1163 }
1164 /** @todo check what intel does about odd limits. */
1165 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1166
1167 /*
1168 * Use the cached guest ldt address if the descriptor has already been modified (see below)
1169 * (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1170 */
1171 if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1172 GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1173
1174
1175#ifdef SELM_TRACK_GUEST_LDT_CHANGES
1176 /** @todo Handle only present LDT segments. */
1177 // if (pDesc->Gen.u1Present)
1178 {
1179 /*
1180 * Check if Guest's LDT address/limit is changed.
1181 */
1182 if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1183 || cbLdt != pVM->selm.s.cbLdtLimit)
1184 {
1185 Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1186 pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1187
1188 /*
1189 * [Re]Register write virtual handler for guest's GDT.
1190 * In the event of LDT overlapping something, don't install it just assume it's being updated.
1191 */
1192 if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1193 {
1194 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestLdt);
1195 AssertRC(rc);
1196 }
1197#ifdef DEBUG
1198 if (pDesc->Gen.u1Present)
1199 Log(("LDT selector marked not present!!\n"));
1200#endif
1201 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1202 0, selmR3GuestLDTWriteHandler, "selmRCGuestLDTWriteHandler", 0, "Guest LDT write access handler");
1203 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1204 {
1205 /** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1206 pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1207 Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1208 GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1209 }
1210 else if (RT_SUCCESS(rc))
1211 pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1212 else
1213 {
1214 CPUMSetHyperLDTR(pVCpu, 0);
1215 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1216 return rc;
1217 }
1218
1219 pVM->selm.s.cbLdtLimit = cbLdt;
1220 }
1221 }
1222#else
1223 pVM->selm.s.cbLdtLimit = cbLdt;
1224#endif
1225
1226 /*
1227 * Calc Shadow LDT base.
1228 */
1229 unsigned off;
1230 pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1231 RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1232 PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1233
1234 /*
1235 * Enable the LDT selector in the shadow GDT.
1236 */
1237 pDesc->Gen.u1Present = 1;
1238 pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1239 pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1240 pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1241 pDesc->Gen.u1Available = 0;
1242 pDesc->Gen.u1Long = 0;
1243 if (cbLdt > 0xffff)
1244 {
1245 cbLdt = 0xffff;
1246 pDesc->Gen.u4LimitHigh = 0;
1247 pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1248 }
1249
1250 /*
1251 * Set Hyper LDTR and notify TRPM.
1252 */
1253 CPUMSetHyperLDTR(pVCpu, SelLdt);
1254
1255 /*
1256 * Loop synchronising the LDT page by page.
1257 */
1258 /** @todo investigate how intel handle various operations on half present cross page entries. */
1259 off = GCPtrLdt & (sizeof(X86DESC) - 1);
1260 AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1261
1262 /* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1263 unsigned cbLeft = cbLdt + 1;
1264 PX86DESC pLDTE = pShadowLDT;
1265 while (cbLeft)
1266 {
1267 /*
1268 * Read a chunk.
1269 */
1270 unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1271 if (cbChunk > cbLeft)
1272 cbChunk = cbLeft;
1273 rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1274 if (RT_SUCCESS(rc))
1275 {
1276 /*
1277 * Mark page
1278 */
1279 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P | X86_PTE_A | X86_PTE_D);
1280 AssertRC(rc);
1281
1282 /*
1283 * Loop thru the available LDT entries.
1284 * Figure out where to start and end and the potential cross pageness of
1285 * things adds a little complexity. pLDTE is updated there and not in the
1286 * 'next' part of the loop. The pLDTEEnd is inclusive.
1287 */
1288 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1289 if (pLDTE + 1 < pShadowLDT)
1290 pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1291 while (pLDTE <= pLDTEEnd)
1292 {
1293 if (pLDTE->Gen.u1Present)
1294 {
1295 /*
1296 * Code and data selectors are generally 1:1, with the
1297 * 'little' adjustment we do for DPL 0 selectors.
1298 */
1299 if (pLDTE->Gen.u1DescType)
1300 {
1301 /*
1302 * Hack for A-bit against Trap E on read-only GDT.
1303 */
1304 /** @todo Fix this by loading ds and cs before turning off WP. */
1305 if (!(pLDTE->Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1306 pLDTE->Gen.u4Type |= X86_SEL_TYPE_ACCESSED;
1307
1308 /*
1309 * All DPL 0 code and data segments are squeezed into DPL 1.
1310 *
1311 * We're skipping conforming segments here because those
1312 * cannot give us any trouble.
1313 */
1314 if ( pLDTE->Gen.u2Dpl == 0
1315 && (pLDTE->Gen.u4Type & (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF))
1316 != (X86_SEL_TYPE_CODE | X86_SEL_TYPE_CONF) )
1317 pLDTE->Gen.u2Dpl = 1;
1318 }
1319 else
1320 {
1321 /*
1322 * System type selectors are marked not present.
1323 * Recompiler or special handling is required for these.
1324 */
1325 /** @todo what about interrupt gates and rawr0? */
1326 pLDTE->Gen.u1Present = 0;
1327 }
1328 }
1329
1330 /* Next LDT entry. */
1331 pLDTE++;
1332 }
1333 }
1334 else
1335 {
1336 AssertMsg(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1337 rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1338 AssertRC(rc);
1339 }
1340
1341 /*
1342 * Advance to the next page.
1343 */
1344 cbLeft -= cbChunk;
1345 GCPtrShadowLDT += cbChunk;
1346 pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1347 GCPtrLdt += cbChunk;
1348 }
1349 }
1350
1351 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1352 return VINF_SUCCESS;
1353}
1354
1355
1356/**
1357 * \#PF Handler callback for virtual access handler ranges.
1358 *
1359 * Important to realize that a physical page in a range can have aliases, and
1360 * for ALL and WRITE handlers these will also trigger.
1361 *
1362 * @returns VINF_SUCCESS if the handler have carried out the operation.
1363 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1364 * @param pVM VM Handle.
1365 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1366 * @param pvPtr The HC mapping of that address.
1367 * @param pvBuf What the guest is reading/writing.
1368 * @param cbBuf How much it's reading/writing.
1369 * @param enmAccessType The access type.
1370 * @param pvUser User argument.
1371 */
1372static DECLCALLBACK(int) selmR3GuestGDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1373{
1374 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1375 Log(("selmR3GuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1376
1377 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_GDT);
1378 return VINF_PGM_HANDLER_DO_DEFAULT;
1379}
1380
1381
1382/**
1383 * \#PF Handler callback for virtual access handler ranges.
1384 *
1385 * Important to realize that a physical page in a range can have aliases, and
1386 * for ALL and WRITE handlers these will also trigger.
1387 *
1388 * @returns VINF_SUCCESS if the handler have carried out the operation.
1389 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1390 * @param pVM VM Handle.
1391 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1392 * @param pvPtr The HC mapping of that address.
1393 * @param pvBuf What the guest is reading/writing.
1394 * @param cbBuf How much it's reading/writing.
1395 * @param enmAccessType The access type.
1396 * @param pvUser User argument.
1397 */
1398static DECLCALLBACK(int) selmR3GuestLDTWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1399{
1400 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1401 Log(("selmR3GuestLDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
1402 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_LDT);
1403 return VINF_PGM_HANDLER_DO_DEFAULT;
1404}
1405
1406
1407/**
1408 * \#PF Handler callback for virtual access handler ranges.
1409 *
1410 * Important to realize that a physical page in a range can have aliases, and
1411 * for ALL and WRITE handlers these will also trigger.
1412 *
1413 * @returns VINF_SUCCESS if the handler have carried out the operation.
1414 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1415 * @param pVM VM Handle.
1416 * @param GCPtr The virtual address the guest is writing to. (not correct if it's an alias!)
1417 * @param pvPtr The HC mapping of that address.
1418 * @param pvBuf What the guest is reading/writing.
1419 * @param cbBuf How much it's reading/writing.
1420 * @param enmAccessType The access type.
1421 * @param pvUser User argument.
1422 */
1423static DECLCALLBACK(int) selmR3GuestTSSWriteHandler(PVM pVM, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
1424{
1425 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
1426 Log(("selmR3GuestTSSWriteHandler: write %.*Rhxs to %RGv size %d\n", RT_MIN(8, cbBuf), pvBuf, GCPtr, cbBuf));
1427
1428 /** @todo This can be optimized by checking for the ESP0 offset and tracking TR
1429 * reloads in REM (setting VM_FF_SELM_SYNC_TSS if TR is reloaded). We
1430 * should probably also deregister the virtual handler if TR.base/size
1431 * changes while we're in REM. */
1432
1433 VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_SELM_SYNC_TSS);
1434
1435 return VINF_PGM_HANDLER_DO_DEFAULT;
1436}
1437
1438
1439/**
1440 * Synchronize the shadowed fields in the TSS.
1441 *
1442 * At present we're shadowing the ring-0 stack selector & pointer, and the
1443 * interrupt redirection bitmap (if present). We take the lazy approach wrt to
1444 * REM and this function is called both if REM made any changes to the TSS or
1445 * loaded TR.
1446 *
1447 * @returns VBox status code.
1448 * @param pVM The VM to operate on.
1449 * @param pVCpu The VMCPU to operate on.
1450 */
1451VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1452{
1453 int rc;
1454
1455 if (pVM->selm.s.fDisableMonitoring)
1456 {
1457 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1458 return VINF_SUCCESS;
1459 }
1460
1461 STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1462 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1463
1464 /*
1465 * Get TR and extract and store the basic info.
1466 *
1467 * Note! The TSS limit is not checked by the LTR code, so we
1468 * have to be a bit careful with it. We make sure cbTss
1469 * won't be zero if TR is valid and if it's NULL we'll
1470 * make sure cbTss is 0.
1471 */
1472 CPUMSELREGHID trHid;
1473 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1474 RTGCPTR GCPtrTss = trHid.u64Base;
1475 uint32_t cbTss = trHid.u32Limit;
1476 Assert( (SelTss & X86_SEL_MASK)
1477 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1478 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1479 if (SelTss & X86_SEL_MASK)
1480 {
1481 Assert(!(SelTss & X86_SEL_LDT));
1482 Assert(trHid.Attr.n.u1DescType == 0);
1483 Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1484 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1485 if (!++cbTss)
1486 cbTss = UINT32_MAX;
1487 }
1488 else
1489 {
1490 Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1491 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1492 cbTss = 0; /* the reset case. */
1493 }
1494 pVM->selm.s.cbGuestTss = cbTss;
1495 pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1496 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1497
1498 /*
1499 * Figure out the size of what need to monitor.
1500 */
1501 /* We're not interested in any 16-bit TSSes. */
1502 uint32_t cbMonitoredTss = cbTss;
1503 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1504 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1505 cbMonitoredTss = 0;
1506
1507 pVM->selm.s.offGuestIoBitmap = 0;
1508 bool fNoRing1Stack = true;
1509 if (cbMonitoredTss)
1510 {
1511 /*
1512 * 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1513 * If VME is enabled we also want to keep an eye on the interrupt
1514 * redirection bitmap.
1515 */
1516 VBOXTSS Tss;
1517 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1518 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1519 if ( !(cr4 & X86_CR4_VME)
1520 || ( VBOX_SUCCESS(rc)
1521 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1522 && Tss.offIoBitmap > cbTss) /* beyond the end */ /** @todo not sure how the partial case is handled; probably not allowed. */
1523 )
1524 /* No interrupt redirection bitmap, just ESP0 and SS0. */
1525 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1526 else if (RT_SUCCESS(rc))
1527 {
1528 /*
1529 * Everything up to and including the interrupt redirection bitmap. Unfortunately
1530 * this can be quite a large chunk. We use to skip it earlier and just hope it
1531 * was kind of static...
1532 *
1533 * Update the virtual interrupt redirection bitmap while we're here.
1534 * (It is located in the 32 bytes before TR:offIoBitmap.)
1535 */
1536 cbMonitoredTss = Tss.offIoBitmap;
1537 pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1538
1539 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1540 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1541 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1542 AssertRC(rc);
1543 /** @todo memset the bitmap on failure? */
1544 Log2(("Redirection bitmap:\n"));
1545 Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1546 }
1547 else
1548 {
1549 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1550 pVM->selm.s.offGuestIoBitmap = 0;
1551 /** @todo memset the bitmap? */
1552 }
1553
1554 /*
1555 * Update the ring 0 stack selector and base address.
1556 */
1557 if (RT_SUCCESS(rc))
1558 {
1559#ifdef LOG_ENABLED
1560 if (LogIsEnabled())
1561 {
1562 uint32_t ssr0, espr0;
1563 SELMGetRing1Stack(pVM, &ssr0, &espr0);
1564 if ((ssr0 & ~1) != Tss.ss0 || espr0 != Tss.esp0)
1565 {
1566 RTGCPHYS GCPhys = NIL_RTGCPHYS;
1567 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1568 Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1569 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1570 AssertMsg(ssr0 != Tss.ss0,
1571 ("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%VGp)\n",
1572 Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1573 }
1574 Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1575 }
1576#endif /* LOG_ENABLED */
1577 AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1578
1579 /* Update our TSS structure for the guest's ring 1 stack */
1580 selmSetRing1Stack(pVM, Tss.ss0 | 1, Tss.esp0);
1581 pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1582 }
1583 }
1584
1585 /*
1586 * Flush the ring-1 stack and the direct syscall dispatching if we
1587 * cannot obtain SS0:ESP0.
1588 */
1589 if (fNoRing1Stack)
1590 {
1591 selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1592 pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1593
1594 /** @todo handle these dependencies better! */
1595 TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1596 TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1597 }
1598
1599 /*
1600 * Check for monitor changes and apply them.
1601 */
1602 if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1603 || cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1604 {
1605 Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1606 GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1607
1608 /* Release the old range first. */
1609 if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1610 {
1611 rc = PGMHandlerVirtualDeregister(pVM, pVM->selm.s.GCPtrGuestTss);
1612 AssertRC(rc);
1613 }
1614
1615 /* Register the write handler if TS != 0. */
1616 if (cbMonitoredTss != 0)
1617 {
1618 rc = PGMR3HandlerVirtualRegister(pVM, PGMVIRTHANDLERTYPE_WRITE, GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1619 0, selmR3GuestTSSWriteHandler,
1620 "selmRCGuestTSSWriteHandler", 0, "Guest TSS write access handler");
1621 if (RT_FAILURE(rc))
1622 {
1623 STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1624 return rc;
1625 }
1626
1627 /* Update saved Guest TSS info. */
1628 pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1629 pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1630 pVM->selm.s.GCSelTss = SelTss;
1631 }
1632 else
1633 {
1634 pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1635 pVM->selm.s.cbMonitoredGuestTss = 0;
1636 pVM->selm.s.GCSelTss = 0;
1637 }
1638 }
1639
1640 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1641
1642 STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1643 return VINF_SUCCESS;
1644}
1645
1646
1647/**
1648 * Compares the Guest GDT and LDT with the shadow tables.
1649 * This is a VBOX_STRICT only function.
1650 *
1651 * @returns VBox status code.
1652 * @param pVM The VM Handle.
1653 */
1654VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1655{
1656#ifdef VBOX_STRICT
1657 PVMCPU pVCpu = VMMGetCpu(pVM);
1658
1659 /*
1660 * Get GDTR and check for conflict.
1661 */
1662 VBOXGDTR GDTR;
1663 CPUMGetGuestGDTR(pVCpu, &GDTR);
1664 if (GDTR.cbGdt == 0)
1665 return VINF_SUCCESS;
1666
1667 if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1668 Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1669
1670 if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1671 Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1672
1673 /*
1674 * Loop thru the GDT checking each entry.
1675 */
1676 RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1677 PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1678 PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1679 while (pGDTE < pGDTEEnd)
1680 {
1681 X86DESC GDTEGuest;
1682 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1683 if (RT_SUCCESS(rc))
1684 {
1685 if (pGDTE->Gen.u1DescType || pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1686 {
1687 if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1688 || pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1689 || pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1690 || pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1691 || pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1692 || pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1693 || pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1694 {
1695 unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1696 SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1697 SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1698 }
1699 }
1700 }
1701
1702 /* Advance to the next descriptor. */
1703 GCPtrGDTEGuest += sizeof(X86DESC);
1704 pGDTE++;
1705 }
1706
1707
1708 /*
1709 * LDT?
1710 */
1711 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1712 if ((SelLdt & X86_SEL_MASK) == 0)
1713 return VINF_SUCCESS;
1714 if (SelLdt > GDTR.cbGdt)
1715 {
1716 Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1717 return VERR_INTERNAL_ERROR;
1718 }
1719 X86DESC LDTDesc;
1720 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1721 if (RT_FAILURE(rc))
1722 {
1723 Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1724 return rc;
1725 }
1726 RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(LDTDesc);
1727 unsigned cbLdt = X86DESC_LIMIT(LDTDesc);
1728 if (LDTDesc.Gen.u1Granularity)
1729 cbLdt = (cbLdt << PAGE_SHIFT) | PAGE_OFFSET_MASK;
1730
1731 /*
1732 * Validate it.
1733 */
1734 if (!cbLdt)
1735 return VINF_SUCCESS;
1736 /** @todo check what intel does about odd limits. */
1737 AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1738 if ( LDTDesc.Gen.u1DescType
1739 || LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1740 || SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1741 {
1742 Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1743 return VERR_INTERNAL_ERROR;
1744 }
1745
1746 /*
1747 * Loop thru the LDT checking each entry.
1748 */
1749 unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1750 PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1751 PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1752 while (pLDTE < pLDTEEnd)
1753 {
1754 X86DESC LDTEGuest;
1755 rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1756 if (RT_SUCCESS(rc))
1757 {
1758 if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1759 || pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1760 || pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1761 || pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1762 || pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1763 || pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1764 || pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1765 {
1766 unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1767 SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1768 SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1769 }
1770 }
1771
1772 /* Advance to the next descriptor. */
1773 GCPtrLDTEGuest += sizeof(X86DESC);
1774 pLDTE++;
1775 }
1776
1777#else /* !VBOX_STRICT */
1778 NOREF(pVM);
1779#endif /* !VBOX_STRICT */
1780
1781 return VINF_SUCCESS;
1782}
1783
1784
1785/**
1786 * Validates the RawR0 TSS values against the one in the Guest TSS.
1787 *
1788 * @returns true if it matches.
1789 * @returns false and assertions on mismatch..
1790 * @param pVM VM Handle.
1791 */
1792VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1793{
1794#ifdef VBOX_STRICT
1795 PVMCPU pVCpu = VMMGetCpu(pVM);
1796
1797 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1798 return true;
1799
1800 /*
1801 * Get TR and extract the basic info.
1802 */
1803 CPUMSELREGHID trHid;
1804 RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1805 RTGCPTR GCPtrTss = trHid.u64Base;
1806 uint32_t cbTss = trHid.u32Limit;
1807 Assert( (SelTss & X86_SEL_MASK)
1808 || (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1809 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */));
1810 if (SelTss & X86_SEL_MASK)
1811 {
1812 AssertReturn(!(SelTss & X86_SEL_LDT), false);
1813 AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1814 AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1815 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1816 false);
1817 if (!++cbTss)
1818 cbTss = UINT32_MAX;
1819 }
1820 else
1821 {
1822 AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1823 || (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY /* RESET */),
1824 false);
1825 cbTss = 0; /* the reset case. */
1826 }
1827 AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1828 AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1829 || trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1830 ("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1831 false);
1832 AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1833 || (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1834 ("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1835 false);
1836 AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1837 || (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1838 ("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1839 false);
1840
1841
1842 /*
1843 * Figure out the size of what need to monitor.
1844 */
1845 bool fNoRing1Stack = true;
1846 /* We're not interested in any 16-bit TSSes. */
1847 uint32_t cbMonitoredTss = cbTss;
1848 if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1849 && trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1850 cbMonitoredTss = 0;
1851 if (cbMonitoredTss)
1852 {
1853 VBOXTSS Tss;
1854 uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1855 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1856 AssertReturn( rc == VINF_SUCCESS
1857 /* Happends early in XP boot during page table switching. */
1858 || ( (rc == VERR_PAGE_TABLE_NOT_PRESENT || rc == VERR_PAGE_NOT_PRESENT)
1859 && !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1860 false);
1861 if ( !(cr4 & X86_CR4_VME)
1862 || ( VBOX_SUCCESS(rc)
1863 && Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1864 && Tss.offIoBitmap > cbTss)
1865 )
1866 cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1867 else if (RT_SUCCESS(rc))
1868 {
1869 cbMonitoredTss = Tss.offIoBitmap;
1870 AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1871 ("#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1872 false);
1873
1874 /* check the bitmap */
1875 uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1876 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1877 GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1878 AssertRCReturn(rc, false);
1879 AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1880 ("offIoBitmap=%#x cbTss=%#x\n"
1881 " Guest: %.32Rhxs\n"
1882 "Shadow: %.32Rhxs\n",
1883 Tss.offIoBitmap, cbTss,
1884 &Tss.IntRedirBitmap[0],
1885 &pVM->selm.s.Tss.IntRedirBitmap[0]),
1886 false);
1887 }
1888 else
1889 cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1890
1891 /*
1892 * Check SS0 and ESP0.
1893 */
1894 if ( !pVM->selm.s.fSyncTSSRing0Stack
1895 && RT_SUCCESS(rc))
1896 {
1897 if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1898 || Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1899 {
1900 RTGCPHYS GCPhys;
1901 rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1902 AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1903 (pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1904 Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1905 return false;
1906 }
1907 }
1908 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1909 }
1910 else
1911 {
1912 AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1913 AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1914 AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1915 }
1916
1917
1918
1919 return true;
1920
1921#else /* !VBOX_STRICT */
1922 NOREF(pVM);
1923 return true;
1924#endif /* !VBOX_STRICT */
1925}
1926
1927
1928/**
1929 * Returns flat address and limit of LDT by LDT selector from guest GDTR.
1930 *
1931 * Fully validate selector.
1932 *
1933 * @returns VBox status.
1934 * @param pVM VM Handle.
1935 * @param SelLdt LDT selector.
1936 * @param ppvLdt Where to store the flat address of LDT.
1937 * @param pcbLimit Where to store LDT limit.
1938 */
1939VMMDECL(int) SELMGetLDTFromSel(PVM pVM, RTSEL SelLdt, PRTGCPTR ppvLdt, unsigned *pcbLimit)
1940{
1941 PVMCPU pVCpu = VMMGetCpu(pVM);
1942
1943 /* Get guest GDTR. */
1944 VBOXGDTR GDTR;
1945 CPUMGetGuestGDTR(pVCpu, &GDTR);
1946
1947 /* Check selector TI and GDT limit. */
1948 if ( SelLdt & X86_SEL_LDT
1949 || (SelLdt > GDTR.cbGdt))
1950 return VERR_INVALID_SELECTOR;
1951
1952 /* Read descriptor from GC. */
1953 X86DESC Desc;
1954 int rc = PGMPhysSimpleReadGCPtr(pVCpu, (void *)&Desc, (RTGCPTR)(GDTR.pGdt + (SelLdt & X86_SEL_MASK)), sizeof(Desc));
1955 if (RT_FAILURE(rc))
1956 {
1957 /* fatal */
1958 AssertMsgFailed(("Can't read LDT descriptor for selector=%04X\n", SelLdt));
1959 return VERR_SELECTOR_NOT_PRESENT;
1960 }
1961
1962 /* Check if LDT descriptor is not present. */
1963 if (Desc.Gen.u1Present == 0)
1964 return VERR_SELECTOR_NOT_PRESENT;
1965
1966 /* Check LDT descriptor type. */
1967 if ( Desc.Gen.u1DescType == 1
1968 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1969 return VERR_INVALID_SELECTOR;
1970
1971 /* LDT descriptor is ok. */
1972 if (ppvLdt)
1973 {
1974 *ppvLdt = (RTGCPTR)X86DESC_BASE(Desc);
1975 *pcbLimit = X86DESC_LIMIT(Desc);
1976 }
1977 return VINF_SUCCESS;
1978}
1979
1980
1981/**
1982 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
1983 *
1984 * See SELMR3GetSelectorInfo for details.
1985 *
1986 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
1987 *
1988 * @param pVM VM handle.
1989 * @param pVCpu VMCPU handle.
1990 * @param Sel The selector to get info about.
1991 * @param pSelInfo Where to store the information.
1992 */
1993static int selmR3GetSelectorInfo64(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
1994{
1995 /*
1996 * Read it from the guest descriptor table.
1997 */
1998 X86DESC64 Desc;
1999 VBOXGDTR Gdtr;
2000 RTGCPTR GCPtrDesc;
2001 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2002 if (!(Sel & X86_SEL_LDT))
2003 {
2004 /* GDT */
2005 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2006 return VERR_INVALID_SELECTOR;
2007 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2008 }
2009 else
2010 {
2011 /*
2012 * LDT - must locate the LDT first.
2013 */
2014 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2015 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2016 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2017 return VERR_INVALID_SELECTOR;
2018 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2019 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2020 if (RT_FAILURE(rc))
2021 return rc;
2022
2023 /* validate the LDT descriptor. */
2024 if (Desc.Gen.u1Present == 0)
2025 return VERR_SELECTOR_NOT_PRESENT;
2026 if ( Desc.Gen.u1DescType == 1
2027 || Desc.Gen.u4Type != AMD64_SEL_TYPE_SYS_LDT)
2028 return VERR_INVALID_SELECTOR;
2029
2030 uint32_t cbLimit = X86DESC_LIMIT(Desc);
2031 if (Desc.Gen.u1Granularity)
2032 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2033 if ((uint32_t)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2034 return VERR_INVALID_SELECTOR;
2035
2036 /* calc the descriptor location. */
2037 GCPtrDesc = X86DESC64_BASE(Desc);
2038 GCPtrDesc += (Sel & X86_SEL_MASK);
2039 }
2040
2041 /* read the descriptor. */
2042 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2043 if (RT_FAILURE(rc))
2044 {
2045 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2046 if (RT_FAILURE(rc))
2047 return rc;
2048 Desc.au64[1] = 0;
2049 }
2050
2051 /*
2052 * Extract the base and limit
2053 * (We ignore the present bit here, which is probably a bit silly...)
2054 */
2055 pSelInfo->Sel = Sel;
2056 pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2057 pSelInfo->u.Raw64 = Desc;
2058 if (Desc.Gen.u1DescType)
2059 {
2060 /*
2061 * 64-bit code selectors are wide open, it's not possible to detect
2062 * 64-bit data or stack selectors without also dragging in assumptions
2063 * about current CS (i.e. that's we're executing in 64-bit mode). So,
2064 * the selinfo user needs to deal with this in the context the info is
2065 * used unfortunately.
2066 */
2067 if ( Desc.Gen.u1Long
2068 && !Desc.Gen.u1DefBig
2069 && (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2070 {
2071 /* Note! We ignore the segment limit hacks that was added by AMD. */
2072 pSelInfo->GCPtrBase = 0;
2073 pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2074 }
2075 else
2076 {
2077 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2078 if (Desc.Gen.u1Granularity)
2079 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2080 pSelInfo->GCPtrBase = X86DESC_BASE(Desc);
2081 }
2082 pSelInfo->SelGate = 0;
2083 }
2084 else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2085 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2086 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2087 {
2088 /* Note. LDT descriptors are weird in long mode, we ignore the footnote
2089 in the AMD manual here as a simplification. */
2090 pSelInfo->GCPtrBase = X86DESC64_BASE(Desc);
2091 pSelInfo->cbLimit = X86DESC_LIMIT(Desc);
2092 if (Desc.Gen.u1Granularity)
2093 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2094 pSelInfo->SelGate = 0;
2095 }
2096 else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2097 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2098 || Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2099 {
2100 pSelInfo->cbLimit = X86DESC64_BASE(Desc);
2101 pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2102 | ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2103 | ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2104 pSelInfo->SelGate = Desc.Gate.u16Sel;
2105 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
2106 }
2107 else
2108 {
2109 pSelInfo->cbLimit = 0;
2110 pSelInfo->GCPtrBase = 0;
2111 pSelInfo->SelGate = 0;
2112 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
2113 }
2114 if (!Desc.Gen.u1Present)
2115 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
2116
2117 return VINF_SUCCESS;
2118}
2119
2120
2121/**
2122 * Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2123 * interprets a legacy descriptor table entry and fills in the selector info
2124 * structure from it.
2125 *
2126 * @param pSelInfo Where to store the selector info. Only the fFlags and
2127 * Sel members have been initialized.
2128 * @param pDesc The legacy descriptor to parse.
2129 */
2130DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2131{
2132 pSelInfo->u.Raw64.au64[1] = 0;
2133 pSelInfo->u.Raw = *pDesc;
2134 if ( pDesc->Gen.u1DescType
2135 || !(pDesc->Gen.u4Type & 4))
2136 {
2137 pSelInfo->cbLimit = X86DESC_LIMIT(*pDesc);
2138 if (pDesc->Gen.u1Granularity)
2139 pSelInfo->cbLimit = (pSelInfo->cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2140 pSelInfo->GCPtrBase = X86DESC_BASE(*pDesc);
2141 pSelInfo->SelGate = 0;
2142 }
2143 else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2144 {
2145 pSelInfo->cbLimit = 0;
2146 if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2147 pSelInfo->GCPtrBase = 0;
2148 else
2149 pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2150 | (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2151 pSelInfo->SelGate = pDesc->Gate.u16Sel;
2152 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_GATE;
2153 }
2154 else
2155 {
2156 pSelInfo->cbLimit = 0;
2157 pSelInfo->GCPtrBase = 0;
2158 pSelInfo->SelGate = 0;
2159 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_INVALID;
2160 }
2161 if (!pDesc->Gen.u1Present)
2162 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_NOT_PRESENT;
2163}
2164
2165
2166/**
2167 * Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2168 *
2169 * See SELMR3GetSelectorInfo for details.
2170 *
2171 * @returns VBox status code, see SELMR3GetSelectorInfo for details.
2172 *
2173 * @param pVM VM handle.
2174 * @param pVCpu VMCPU handle.
2175 * @param Sel The selector to get info about.
2176 * @param pSelInfo Where to store the information.
2177 */
2178static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2179{
2180 /*
2181 * Read the descriptor entry
2182 */
2183 pSelInfo->fFlags = 0;
2184 X86DESC Desc;
2185 if ( !(Sel & X86_SEL_LDT)
2186 && ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2187 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2188 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2189 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2190 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK))
2191 )
2192 {
2193 /*
2194 * Hypervisor descriptor.
2195 */
2196 pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2197 if (CPUMIsGuestInProtectedMode(pVCpu))
2198 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
2199 else
2200 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
2201
2202 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2203 }
2204 else if (CPUMIsGuestInProtectedMode(pVCpu))
2205 {
2206 /*
2207 * Read it from the guest descriptor table.
2208 */
2209 pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2210
2211 VBOXGDTR Gdtr;
2212 RTGCPTR GCPtrDesc;
2213 CPUMGetGuestGDTR(pVCpu, &Gdtr);
2214 if (!(Sel & X86_SEL_LDT))
2215 {
2216 /* GDT */
2217 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2218 return VERR_INVALID_SELECTOR;
2219 GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2220 }
2221 else
2222 {
2223 /*
2224 * LDT - must locate the LDT first...
2225 */
2226 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2227 if ( (unsigned)(SelLdt & X86_SEL_MASK) < sizeof(X86DESC) /* the first selector is invalid, right? */
2228 || (unsigned)(SelLdt & X86_SEL_MASK) + sizeof(X86DESC) - 1 > (unsigned)Gdtr.cbGdt)
2229 return VERR_INVALID_SELECTOR;
2230 GCPtrDesc = Gdtr.pGdt + (SelLdt & X86_SEL_MASK);
2231 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2232 if (RT_FAILURE(rc))
2233 return rc;
2234
2235 /* validate the LDT descriptor. */
2236 if (Desc.Gen.u1Present == 0)
2237 return VERR_SELECTOR_NOT_PRESENT;
2238 if ( Desc.Gen.u1DescType == 1
2239 || Desc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
2240 return VERR_INVALID_SELECTOR;
2241
2242 unsigned cbLimit = X86DESC_LIMIT(Desc);
2243 if (Desc.Gen.u1Granularity)
2244 cbLimit = (cbLimit << PAGE_SHIFT) | PAGE_OFFSET_MASK;
2245 if ((unsigned)(Sel & X86_SEL_MASK) + sizeof(X86DESC) - 1 > cbLimit)
2246 return VERR_INVALID_SELECTOR;
2247
2248 /* calc the descriptor location. */
2249 GCPtrDesc = X86DESC_BASE(Desc);
2250 GCPtrDesc += (Sel & X86_SEL_MASK);
2251 }
2252
2253 /* read the descriptor. */
2254 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2255 if (RT_FAILURE(rc))
2256 return rc;
2257 }
2258 else
2259 {
2260 /*
2261 * We're in real mode.
2262 */
2263 pSelInfo->Sel = Sel;
2264 pSelInfo->GCPtrBase = Sel << 4;
2265 pSelInfo->cbLimit = 0xffff;
2266 pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2267 pSelInfo->u.Raw64.au64[0] = 0;
2268 pSelInfo->u.Raw64.au64[1] = 0;
2269 pSelInfo->SelGate = 0;
2270 return VINF_SUCCESS;
2271 }
2272
2273 /*
2274 * Extract the base and limit or sel:offset for gates.
2275 */
2276 pSelInfo->Sel = Sel;
2277 selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2278
2279 return VINF_SUCCESS;
2280}
2281
2282
2283/**
2284 * Gets information about a selector.
2285 *
2286 * Intended for the debugger mostly and will prefer the guest descriptor tables
2287 * over the shadow ones.
2288 *
2289 * @retval VINF_SUCCESS on success.
2290 * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2291 * descriptor table.
2292 * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2293 * is not returned if the selector itself isn't present, you have to
2294 * check that for yourself (see DBGFSELINFO::fFlags).
2295 * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2296 * pagetable or page backing the selector table wasn't present.
2297 * @returns Other VBox status code on other errors.
2298 *
2299 * @param pVM VM handle.
2300 * @param pVCpu The virtual CPU handle.
2301 * @param Sel The selector to get info about.
2302 * @param pSelInfo Where to store the information.
2303 */
2304VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2305{
2306 AssertPtr(pSelInfo);
2307 if (CPUMIsGuestInLongMode(pVCpu))
2308 return selmR3GetSelectorInfo64(pVM, pVCpu, Sel, pSelInfo);
2309 return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2310}
2311
2312
2313/**
2314 * Gets information about a selector from the shadow tables.
2315 *
2316 * This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2317 * requires that the caller ensures that the shadow tables are up to date.
2318 *
2319 * @retval VINF_SUCCESS on success.
2320 * @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2321 * descriptor table.
2322 * @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2323 * is not returned if the selector itself isn't present, you have to
2324 * check that for yourself (see DBGFSELINFO::fFlags).
2325 * @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2326 * pagetable or page backing the selector table wasn't present.
2327 * @returns Other VBox status code on other errors.
2328 *
2329 * @param pVM VM handle.
2330 * @param Sel The selector to get info about.
2331 * @param pSelInfo Where to store the information.
2332 *
2333 * @remarks Don't use this when in hardware assisted virtualization mode.
2334 */
2335VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2336{
2337 Assert(pSelInfo);
2338
2339 /*
2340 * Read the descriptor entry
2341 */
2342 X86DESC Desc;
2343 if (!(Sel & X86_SEL_LDT))
2344 {
2345 /*
2346 * Global descriptor.
2347 */
2348 Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2349 pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK)
2350 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK)
2351 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK)
2352 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK)
2353 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK)
2354 ? DBGFSELINFO_FLAGS_HYPER
2355 : 0;
2356 /** @todo check that the GDT offset is valid. */
2357 }
2358 else
2359 {
2360 /*
2361 * Local Descriptor.
2362 */
2363 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2364 Desc = paLDT[Sel >> X86_SEL_SHIFT];
2365 /** @todo check if the LDT page is actually available. */
2366 /** @todo check that the LDT offset is valid. */
2367 pSelInfo->fFlags = 0;
2368 }
2369 if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2370 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_PROT_MODE;
2371 else
2372 pSelInfo->fFlags |= DBGFSELINFO_FLAGS_REAL_MODE;
2373
2374 /*
2375 * Extract the base and limit or sel:offset for gates.
2376 */
2377 pSelInfo->Sel = Sel;
2378 selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2379
2380 return VINF_SUCCESS;
2381}
2382
2383
2384/**
2385 * Formats a descriptor.
2386 *
2387 * @param Desc Descriptor to format.
2388 * @param Sel Selector number.
2389 * @param pszOutput Output buffer.
2390 * @param cchOutput Size of output buffer.
2391 */
2392static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2393{
2394 /*
2395 * Make variable description string.
2396 */
2397 static struct
2398 {
2399 unsigned cch;
2400 const char *psz;
2401 } const aTypes[32] =
2402 {
2403#define STRENTRY(str) { sizeof(str) - 1, str }
2404 /* system */
2405 STRENTRY("Reserved0 "), /* 0x00 */
2406 STRENTRY("TSS16Avail "), /* 0x01 */
2407 STRENTRY("LDT "), /* 0x02 */
2408 STRENTRY("TSS16Busy "), /* 0x03 */
2409 STRENTRY("Call16 "), /* 0x04 */
2410 STRENTRY("Task "), /* 0x05 */
2411 STRENTRY("Int16 "), /* 0x06 */
2412 STRENTRY("Trap16 "), /* 0x07 */
2413 STRENTRY("Reserved8 "), /* 0x08 */
2414 STRENTRY("TSS32Avail "), /* 0x09 */
2415 STRENTRY("ReservedA "), /* 0x0a */
2416 STRENTRY("TSS32Busy "), /* 0x0b */
2417 STRENTRY("Call32 "), /* 0x0c */
2418 STRENTRY("ReservedD "), /* 0x0d */
2419 STRENTRY("Int32 "), /* 0x0e */
2420 STRENTRY("Trap32 "), /* 0x0f */
2421 /* non system */
2422 STRENTRY("DataRO "), /* 0x10 */
2423 STRENTRY("DataRO Accessed "), /* 0x11 */
2424 STRENTRY("DataRW "), /* 0x12 */
2425 STRENTRY("DataRW Accessed "), /* 0x13 */
2426 STRENTRY("DataDownRO "), /* 0x14 */
2427 STRENTRY("DataDownRO Accessed "), /* 0x15 */
2428 STRENTRY("DataDownRW "), /* 0x16 */
2429 STRENTRY("DataDownRW Accessed "), /* 0x17 */
2430 STRENTRY("CodeEO "), /* 0x18 */
2431 STRENTRY("CodeEO Accessed "), /* 0x19 */
2432 STRENTRY("CodeER "), /* 0x1a */
2433 STRENTRY("CodeER Accessed "), /* 0x1b */
2434 STRENTRY("CodeConfEO "), /* 0x1c */
2435 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2436 STRENTRY("CodeConfER "), /* 0x1e */
2437 STRENTRY("CodeConfER Accessed ") /* 0x1f */
2438#undef SYSENTRY
2439 };
2440#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2441 char szMsg[128];
2442 char *psz = &szMsg[0];
2443 unsigned i = Desc.Gen.u1DescType << 4 | Desc.Gen.u4Type;
2444 memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2445 psz += aTypes[i].cch;
2446
2447 if (Desc.Gen.u1Present)
2448 ADD_STR(psz, "Present ");
2449 else
2450 ADD_STR(psz, "Not-Present ");
2451 if (Desc.Gen.u1Granularity)
2452 ADD_STR(psz, "Page ");
2453 if (Desc.Gen.u1DefBig)
2454 ADD_STR(psz, "32-bit ");
2455 else
2456 ADD_STR(psz, "16-bit ");
2457#undef ADD_STR
2458 *psz = '\0';
2459
2460 /*
2461 * Limit and Base and format the output.
2462 */
2463 uint32_t u32Limit = X86DESC_LIMIT(Desc);
2464 if (Desc.Gen.u1Granularity)
2465 u32Limit = u32Limit << PAGE_SHIFT | PAGE_OFFSET_MASK;
2466 uint32_t u32Base = X86DESC_BASE(Desc);
2467
2468 RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2469 Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2470}
2471
2472
2473/**
2474 * Dumps a descriptor.
2475 *
2476 * @param Desc Descriptor to dump.
2477 * @param Sel Selector number.
2478 * @param pszMsg Message to prepend the log entry with.
2479 */
2480VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2481{
2482 char szOutput[128];
2483 selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2484 Log(("%s: %s\n", pszMsg, szOutput));
2485 NOREF(szOutput[0]);
2486}
2487
2488
2489/**
2490 * Display the shadow gdt.
2491 *
2492 * @param pVM VM Handle.
2493 * @param pHlp The info helpers.
2494 * @param pszArgs Arguments, ignored.
2495 */
2496static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2497{
2498 pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2499 for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2500 {
2501 if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2502 {
2503 char szOutput[128];
2504 selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2505 const char *psz = "";
2506 if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2507 psz = " HyperCS";
2508 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2509 psz = " HyperDS";
2510 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2511 psz = " HyperCS64";
2512 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2513 psz = " HyperTSS";
2514 else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2515 psz = " HyperTSSTrap08";
2516 pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2517 }
2518 }
2519}
2520
2521
2522/**
2523 * Display the guest gdt.
2524 *
2525 * @param pVM VM Handle.
2526 * @param pHlp The info helpers.
2527 * @param pszArgs Arguments, ignored.
2528 */
2529static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2530{
2531 /** @todo SMP support! */
2532 PVMCPU pVCpu = &pVM->aCpus[0];
2533
2534 VBOXGDTR GDTR;
2535 CPUMGetGuestGDTR(pVCpu, &GDTR);
2536 RTGCPTR GCPtrGDT = GDTR.pGdt;
2537 unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2538
2539 pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2540 for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2541 {
2542 X86DESC GDTE;
2543 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2544 if (RT_SUCCESS(rc))
2545 {
2546 if (GDTE.Gen.u1Present)
2547 {
2548 char szOutput[128];
2549 selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2550 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2551 }
2552 }
2553 else if (rc == VERR_PAGE_NOT_PRESENT)
2554 {
2555 if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2556 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2557 }
2558 else
2559 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2560 }
2561}
2562
2563
2564/**
2565 * Display the shadow ldt.
2566 *
2567 * @param pVM VM Handle.
2568 * @param pHlp The info helpers.
2569 * @param pszArgs Arguments, ignored.
2570 */
2571static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2572{
2573 unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2574 PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2575 pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2576 for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2577 {
2578 if (paLDT[iLDT].Gen.u1Present)
2579 {
2580 char szOutput[128];
2581 selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2582 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2583 }
2584 }
2585}
2586
2587
2588/**
2589 * Display the guest ldt.
2590 *
2591 * @param pVM VM Handle.
2592 * @param pHlp The info helpers.
2593 * @param pszArgs Arguments, ignored.
2594 */
2595static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2596{
2597 /** @todo SMP support! */
2598 PVMCPU pVCpu = &pVM->aCpus[0];
2599
2600 RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
2601 if (!(SelLdt & X86_SEL_MASK))
2602 {
2603 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2604 return;
2605 }
2606
2607 RTGCPTR GCPtrLdt;
2608 unsigned cbLdt;
2609 int rc = SELMGetLDTFromSel(pVM, SelLdt, &GCPtrLdt, &cbLdt);
2610 if (RT_FAILURE(rc))
2611 {
2612 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): rc=%Rrc\n", SelLdt, rc);
2613 return;
2614 }
2615
2616 pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RGv limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2617 unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2618 for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2619 {
2620 X86DESC LdtE;
2621 rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2622 if (RT_SUCCESS(rc))
2623 {
2624 if (LdtE.Gen.u1Present)
2625 {
2626 char szOutput[128];
2627 selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2628 pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2629 }
2630 }
2631 else if (rc == VERR_PAGE_NOT_PRESENT)
2632 {
2633 if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2634 pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, GCPtrLdt);
2635 }
2636 else
2637 pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) | X86_SEL_LDT, rc, GCPtrLdt);
2638 }
2639}
2640
2641
2642/**
2643 * Dumps the hypervisor GDT
2644 *
2645 * @param pVM VM handle.
2646 */
2647VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2648{
2649 DBGFR3Info(pVM, "gdt", NULL, NULL);
2650}
2651
2652
2653/**
2654 * Dumps the hypervisor LDT
2655 *
2656 * @param pVM VM handle.
2657 */
2658VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2659{
2660 DBGFR3Info(pVM, "ldt", NULL, NULL);
2661}
2662
2663
2664/**
2665 * Dumps the guest GDT
2666 *
2667 * @param pVM VM handle.
2668 */
2669VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2670{
2671 DBGFR3Info(pVM, "gdtguest", NULL, NULL);
2672}
2673
2674
2675/**
2676 * Dumps the guest LDT
2677 *
2678 * @param pVM VM handle.
2679 */
2680VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2681{
2682 DBGFR3Info(pVM, "ldtguest", NULL, NULL);
2683}
2684
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