VirtualBox

source: vbox/trunk/src/VBox/VMM/PGMShw.h@ 25414

Last change on this file since 25414 was 24077, checked in by vboxsync, 15 years ago

Fixed nested paging for 64 bits guests on 32 bits hosts (AMD-V only).
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File size: 10.0 KB
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1/* $Id: PGMShw.h 24077 2009-10-26 14:08:59Z vboxsync $ */
2/** @file
3 * VBox - Page Manager / Monitor, Shadow Paging Template.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Defined Constants And Macros *
24*******************************************************************************/
25#undef SHWPT
26#undef PSHWPT
27#undef SHWPTE
28#undef PSHWPTE
29#undef SHWPD
30#undef PSHWPD
31#undef SHWPDE
32#undef PSHWPDE
33#undef SHW_PDE_PG_MASK
34#undef SHW_PD_SHIFT
35#undef SHW_PD_MASK
36#undef SHW_PTE_PG_MASK
37#undef SHW_PT_SHIFT
38#undef SHW_PT_MASK
39#undef SHW_TOTAL_PD_ENTRIES
40#undef SHW_PDPT_SHIFT
41#undef SHW_PDPT_MASK
42#undef SHW_PDPE_PG_MASK
43#undef SHW_POOL_ROOT_IDX
44
45#if PGM_SHW_TYPE == PGM_TYPE_32BIT
46# define SHWPT X86PT
47# define PSHWPT PX86PT
48# define SHWPTE X86PTE
49# define PSHWPTE PX86PTE
50# define SHWPD X86PD
51# define PSHWPD PX86PD
52# define SHWPDE X86PDE
53# define PSHWPDE PX86PDE
54# define SHW_PDE_PG_MASK X86_PDE_PG_MASK
55# define SHW_PD_SHIFT X86_PD_SHIFT
56# define SHW_PD_MASK X86_PD_MASK
57# define SHW_TOTAL_PD_ENTRIES X86_PG_ENTRIES
58# define SHW_PTE_PG_MASK X86_PTE_PG_MASK
59# define SHW_PT_SHIFT X86_PT_SHIFT
60# define SHW_PT_MASK X86_PT_MASK
61# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PD
62
63#elif PGM_SHW_TYPE == PGM_TYPE_EPT
64# define SHWPT EPTPT
65# define PSHWPT PEPTPT
66# define SHWPTE EPTPTE
67# define PSHWPTE PEPTPTE
68# define SHWPD EPTPD
69# define PSHWPD PEPTPD
70# define SHWPDE EPTPDE
71# define PSHWPDE PEPTPDE
72# define SHW_PDE_PG_MASK EPT_PDE_PG_MASK
73# define SHW_PD_SHIFT EPT_PD_SHIFT
74# define SHW_PD_MASK EPT_PD_MASK
75# define SHW_PTE_PG_MASK EPT_PTE_PG_MASK
76# define SHW_PT_SHIFT EPT_PT_SHIFT
77# define SHW_PT_MASK EPT_PT_MASK
78# define SHW_PDPT_SHIFT EPT_PDPT_SHIFT
79# define SHW_PDPT_MASK EPT_PDPT_MASK
80# define SHW_PDPE_PG_MASK EPT_PDPE_PG_MASK
81# define SHW_TOTAL_PD_ENTRIES (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
82# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_NESTED_ROOT /* do not use! exception is real mode & protected mode without paging. */
83
84#else
85# define SHWPT X86PTPAE
86# define PSHWPT PX86PTPAE
87# define SHWPTE X86PTEPAE
88# define PSHWPTE PX86PTEPAE
89# define SHWPD X86PDPAE
90# define PSHWPD PX86PDPAE
91# define SHWPDE X86PDEPAE
92# define PSHWPDE PX86PDEPAE
93# define SHW_PDE_PG_MASK X86_PDE_PAE_PG_MASK
94# define SHW_PD_SHIFT X86_PD_PAE_SHIFT
95# define SHW_PD_MASK X86_PD_PAE_MASK
96# define SHW_PTE_PG_MASK X86_PTE_PAE_PG_MASK
97# define SHW_PT_SHIFT X86_PT_PAE_SHIFT
98# define SHW_PT_MASK X86_PT_PAE_MASK
99
100# if PGM_SHW_TYPE == PGM_TYPE_AMD64
101# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
102# define SHW_PDPT_MASK X86_PDPT_MASK_AMD64
103# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
104# define SHW_TOTAL_PD_ENTRIES (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
105# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_AMD64_CR3
106
107# else /* 32 bits PAE mode */
108# define SHW_PDPT_SHIFT X86_PDPT_SHIFT
109# define SHW_PDPT_MASK X86_PDPT_MASK_PAE
110# define SHW_PDPE_PG_MASK X86_PDPE_PG_MASK
111# define SHW_TOTAL_PD_ENTRIES (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
112# define SHW_POOL_ROOT_IDX PGMPOOL_IDX_PDPT
113# endif
114#endif
115
116
117/*******************************************************************************
118* Internal Functions *
119*******************************************************************************/
120RT_C_DECLS_BEGIN
121/* r3 */
122PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0);
123PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
124PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta);
125PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu);
126
127/* all */
128PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
129PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask);
130RT_C_DECLS_END
131
132
133/**
134 * Initializes the guest bit of the paging mode data.
135 *
136 * @returns VBox status code.
137 * @param pVM The VM handle.
138 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
139 * This is used early in the init process to avoid trouble with PDM
140 * not being initialized yet.
141 */
142PGM_SHW_DECL(int, InitData)(PVM pVM, PPGMMODEDATA pModeData, bool fResolveGCAndR0)
143{
144 Assert(pModeData->uShwType == PGM_SHW_TYPE || pModeData->uShwType == PGM_TYPE_NESTED);
145
146 /* Ring-3 */
147 pModeData->pfnR3ShwRelocate = PGM_SHW_NAME(Relocate);
148 pModeData->pfnR3ShwExit = PGM_SHW_NAME(Exit);
149 pModeData->pfnR3ShwGetPage = PGM_SHW_NAME(GetPage);
150 pModeData->pfnR3ShwModifyPage = PGM_SHW_NAME(ModifyPage);
151
152 if (fResolveGCAndR0)
153 {
154 int rc;
155
156#if PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT /* No AMD64 for traditional virtualization, only VT-x and AMD-V. */
157 /* GC */
158 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(GetPage), &pModeData->pfnRCShwGetPage);
159 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(GetPage), rc), rc);
160 rc = PDMR3LdrGetSymbolRC(pVM, NULL, PGM_SHW_NAME_RC_STR(ModifyPage), &pModeData->pfnRCShwModifyPage);
161 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_RC_STR(ModifyPage), rc), rc);
162#endif /* Not AMD64 shadow paging. */
163
164 /* Ring-0 */
165 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(GetPage), &pModeData->pfnR0ShwGetPage);
166 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(GetPage), rc), rc);
167 rc = PDMR3LdrGetSymbolR0(pVM, NULL, PGM_SHW_NAME_R0_STR(ModifyPage), &pModeData->pfnR0ShwModifyPage);
168 AssertMsgRCReturn(rc, ("%s -> rc=%Rrc\n", PGM_SHW_NAME_R0_STR(ModifyPage), rc), rc);
169 }
170 return VINF_SUCCESS;
171}
172
173/**
174 * Enters the shadow mode.
175 *
176 * @returns VBox status code.
177 * @param pVCpu The VMCPU to operate on.
178 * @param fIs64BitsPagingMode New shadow paging mode is for 64 bits? (only relevant for 64 bits guests on a 32 bits AMD-V nested paging host)
179 */
180PGM_SHW_DECL(int, Enter)(PVMCPU pVCpu, bool fIs64BitsPagingMode)
181{
182#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
183
184# if PGM_SHW_TYPE == PGM_TYPE_NESTED && HC_ARCH_BITS == 32
185 /* Must distinguish between 32 and 64 bits guest paging modes as we'll use a different shadow paging root/mode in both cases. */
186 RTGCPHYS GCPhysCR3 = (fIs64BitsPagingMode) ? RT_BIT_64(63) : RT_BIT_64(62);
187# else
188 RTGCPHYS GCPhysCR3 = RT_BIT_64(63);
189# endif
190 PPGMPOOLPAGE pNewShwPageCR3;
191 PVM pVM = pVCpu->pVMR3;
192 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
193
194 Assert(HWACCMIsNestedPagingActive(pVM));
195 Assert(!pVCpu->pgm.s.pShwPageCR3R3);
196
197 pgmLock(pVM);
198
199 int rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_NESTED, PGMPOOL_IDX_NESTED_ROOT, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
200 AssertFatalRC(rc);
201
202 pVCpu->pgm.s.iShwUser = PGMPOOL_IDX_NESTED_ROOT;
203 pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
204 pVCpu->pgm.s.pShwPageCR3R3 = pNewShwPageCR3;
205
206 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.pShwPageCR3R3);
207 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.pShwPageCR3R3);
208
209 pgmUnlock(pVM);
210
211 Log(("Enter nested shadow paging mode: root %RHv phys %RHp\n", pVCpu->pgm.s.pShwPageCR3R3, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key));
212#endif
213 return VINF_SUCCESS;
214}
215
216
217/**
218 * Relocate any GC pointers related to shadow mode paging.
219 *
220 * @returns VBox status code.
221 * @param pVCpu The VMCPU to operate on.
222 * @param offDelta The reloation offset.
223 */
224PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
225{
226 pVCpu->pgm.s.pShwPageCR3RC += offDelta;
227 return VINF_SUCCESS;
228}
229
230
231/**
232 * Exits the shadow mode.
233 *
234 * @returns VBox status code.
235 * @param pVCpu The VMCPU to operate on.
236 */
237PGM_SHW_DECL(int, Exit)(PVMCPU pVCpu)
238{
239 PVM pVM = pVCpu->pVMR3;
240
241 if ( ( pVCpu->pgm.s.enmShadowMode == PGMMODE_NESTED
242 || pVCpu->pgm.s.enmShadowMode == PGMMODE_EPT)
243 && pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
244 {
245 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
246
247 Assert(pVCpu->pgm.s.iShwUser == PGMPOOL_IDX_NESTED_ROOT);
248
249 pgmLock(pVM);
250
251 /* Mark the page as unlocked; allow flushing again. */
252 pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
253
254 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
255 pVCpu->pgm.s.pShwPageCR3R3 = 0;
256 pVCpu->pgm.s.pShwPageCR3R0 = 0;
257 pVCpu->pgm.s.pShwPageCR3RC = 0;
258 pVCpu->pgm.s.iShwUser = 0;
259 pVCpu->pgm.s.iShwUserTable = 0;
260
261 pgmUnlock(pVM);
262
263 Log(("Leave nested shadow paging mode\n"));
264 }
265 return VINF_SUCCESS;
266}
267
268
269
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