VirtualBox

About
Screenshots
Downloads
Documentation
End-user docs
Technical docs
Contribute
Community

Browse Source

Context Navigation

source: vbox/trunk/src/VBox/VMM/PGMSavedState.cpp@ 24912

Last change on this file since 24912 was 24876, checked in by vboxsync, 15 years ago
PGMSavedState: refinement.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 110.8 KB

Line
1	/* $Id: PGMSavedState.cpp 24876 2009-11-23 16:07:22Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor, The Saved State Part.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM
27	#include <VBox/pgm.h>
28	#include <VBox/stam.h>
29	#include <VBox/ssm.h>
30	#include <VBox/pdm.h>
31	#include "PGMInternal.h"
32	#include <VBox/vm.h>
33
34	#include <VBox/param.h>
35	#include <VBox/err.h>
36
37	#include <iprt/asm.h>
38	#include <iprt/assert.h>
39	#include <iprt/crc32.h>
40	#include <iprt/mem.h>
41	#include <iprt/sha.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44
45
46	/*******************************************************************************
47	* Defined Constants And Macros *
48	*******************************************************************************/
49	/** Saved state data unit version. */
50	#define PGM_SAVED_STATE_VERSION 11
51	/** Saved state data unit version used during 3.1 development, misses the RAM
52	* config. */
53	#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
54	/** Saved state data unit version for 3.0 (pre teleportation). */
55	#define PGM_SAVED_STATE_VERSION_3_0_0 9
56	/** Saved state data unit version for 2.2.2 and later. */
57	#define PGM_SAVED_STATE_VERSION_2_2_2 8
58	/** Saved state data unit version for 2.2.0. */
59	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
60	/** Saved state data unit version. */
61	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
62
63
64	/** @name Sparse state record types
65	* @{ */
66	/** Zero page. No data. */
67	#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
68	/** Raw page. */
69	#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
70	/** Raw MMIO2 page. */
71	#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
72	/** Zero MMIO2 page. */
73	#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
74	/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
75	#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
76	/** Raw shadowed ROM page. The protection (8-bit) preceeds the raw bits. */
77	#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
78	/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
79	#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
80	/** ROM protection (8-bit). */
81	#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
82	/** The last record type. */
83	#define PGM_STATE_REC_LAST PGM_STATE_REC_ROM_PROT
84	/** End marker. */
85	#define PGM_STATE_REC_END UINT8_C(0xff)
86	/** Flag indicating that the data is preceeded by the page address.
87	* For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
88	* range ID and a 32-bit page index.
89	*/
90	#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
91	/** @} */
92
93	/** The CRC-32 for a zero page. */
94	#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
95	/** The CRC-32 for a zero half page. */
96	#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
97
98
99	/*******************************************************************************
100	* Structures and Typedefs *
101	*******************************************************************************/
102	/** For loading old saved states. (pre-smp) */
103	typedef struct
104	{
105	/** If set no conflict checks are required. (boolean) */
106	bool fMappingsFixed;
107	/** Size of fixed mapping */
108	uint32_t cbMappingFixed;
109	/** Base address (GC) of fixed mapping */
110	RTGCPTR GCPtrMappingFixed;
111	/** A20 gate mask.
112	* Our current approach to A20 emulation is to let REM do it and don't bother
113	* anywhere else. The interesting Guests will be operating with it enabled anyway.
114	* But whould need arrise, we'll subject physical addresses to this mask. */
115	RTGCPHYS GCPhysA20Mask;
116	/** A20 gate state - boolean! */
117	bool fA20Enabled;
118	/** The guest paging mode. */
119	PGMMODE enmGuestMode;
120	} PGMOLD;
121
122
123	/*******************************************************************************
124	* Global Variables *
125	*******************************************************************************/
126	/** PGM fields to save/load. */
127	static const SSMFIELD s_aPGMFields[] =
128	{
129	SSMFIELD_ENTRY( PGM, fMappingsFixed),
130	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
131	SSMFIELD_ENTRY( PGM, cbMappingFixed),
132	SSMFIELD_ENTRY_TERM()
133	};
134
135	static const SSMFIELD s_aPGMCpuFields[] =
136	{
137	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
138	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
139	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
140	SSMFIELD_ENTRY_TERM()
141	};
142
143	static const SSMFIELD s_aPGMFields_Old[] =
144	{
145	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
146	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
147	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
148	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
149	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
150	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
151	SSMFIELD_ENTRY_TERM()
152	};
153
154
155	/**
156	* Find the ROM tracking structure for the given page.
157	*
158	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
159	* that it's a ROM page.
160	* @param pVM The VM handle.
161	* @param GCPhys The address of the ROM page.
162	*/
163	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
164	{
165	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
166	pRomRange;
167	pRomRange = pRomRange->CTX_SUFF(pNext))
168	{
169	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
170	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
171	return &pRomRange->aPages[off >> PAGE_SHIFT];
172	}
173	return NULL;
174	}
175
176
177	/**
178	* Prepares the ROM pages for a live save.
179	*
180	* @returns VBox status code.
181	* @param pVM The VM handle.
182	*/
183	static int pgmR3PrepRomPages(PVM pVM)
184	{
185	/*
186	* Initialize the live save tracking in the ROM page descriptors.
187	*/
188	pgmLock(pVM);
189	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
190	{
191	PPGMRAMRANGE pRamHint = NULL;;
192	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
193
194	for (uint32_t iPage = 0; iPage < cPages; iPage++)
195	{
196	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
197	pRom->aPages[iPage].LiveSave.fWrittenTo = false;
198	pRom->aPages[iPage].LiveSave.fDirty = true;
199	pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
200	if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
201	{
202	if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
203	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
204	else
205	{
206	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
207	PPGMPAGE pPage;
208	int rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
209	AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
210	if (RT_SUCCESS(rc))
211	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage);
212	else
213	pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow);
214	}
215	}
216	}
217
218	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
219	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
220	pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
221	}
222	pgmUnlock(pVM);
223
224	return VINF_SUCCESS;
225	}
226
227
228	/**
229	* Assigns IDs to the ROM ranges and saves them.
230	*
231	* @returns VBox status code.
232	* @param pVM The VM handle.
233	* @param pSSM Saved state handle.
234	*/
235	static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
236	{
237	pgmLock(pVM);
238	uint8_t id = 1;
239	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
240	{
241	pRom->idSavedState = id;
242	SSMR3PutU8(pSSM, id);
243	SSMR3PutStrZ(pSSM, ""); /* device name */
244	SSMR3PutU32(pSSM, 0); /* device instance */
245	SSMR3PutU8(pSSM, 0); /* region */
246	SSMR3PutStrZ(pSSM, pRom->pszDesc);
247	SSMR3PutGCPhys(pSSM, pRom->GCPhys);
248	int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
249	if (RT_FAILURE(rc))
250	break;
251	}
252	pgmUnlock(pVM);
253	return SSMR3PutU8(pSSM, UINT8_MAX);
254	}
255
256
257	/**
258	* Loads the ROM range ID assignments.
259	*
260	* @returns VBox status code.
261	*
262	* @param pVM The VM handle.
263	* @param pSSM The saved state handle.
264	*/
265	static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
266	{
267	Assert(PGMIsLockOwner(pVM));
268
269	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
270	pRom->idSavedState = UINT8_MAX;
271
272	for (;;)
273	{
274	/*
275	* Read the data.
276	*/
277	uint8_t id;
278	int rc = SSMR3GetU8(pSSM, &id);
279	if (RT_FAILURE(rc))
280	return rc;
281	if (id == UINT8_MAX)
282	{
283	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
284	AssertLogRelMsg(pRom->idSavedState != UINT8_MAX, ("%s\n", pRom->pszDesc));
285	return VINF_SUCCESS; /* the end */
286	}
287	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
288
289	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
290	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
291	AssertLogRelRCReturn(rc, rc);
292
293	uint32_t uInstance;
294	SSMR3GetU32(pSSM, &uInstance);
295	uint8_t iRegion;
296	SSMR3GetU8(pSSM, &iRegion);
297
298	char szDesc[64];
299	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
300	AssertLogRelRCReturn(rc, rc);
301
302	RTGCPHYS GCPhys;
303	SSMR3GetGCPhys(pSSM, &GCPhys);
304	RTGCPHYS cb;
305	rc = SSMR3GetGCPhys(pSSM, &cb);
306	if (RT_FAILURE(rc))
307	return rc;
308	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
309	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
310
311	/*
312	* Locate a matching ROM range.
313	*/
314	AssertLogRelMsgReturn( uInstance == 0
315	&& iRegion == 0
316	&& szDevName[0] == '\0',
317	("GCPhys=%RGp %s\n", GCPhys, szDesc),
318	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
319	PPGMROMRANGE pRom;
320	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
321	{
322	if ( pRom->idSavedState == UINT8_MAX
323	&& !strcmp(pRom->pszDesc, szDesc))
324	{
325	pRom->idSavedState = id;
326	break;
327	}
328	}
329	if (!pRom)
330	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
331	} /* forever */
332	}
333
334
335	/**
336	* Scan ROM pages.
337	*
338	* @param pVM The VM handle.
339	*/
340	static void pgmR3ScanRomPages(PVM pVM)
341	{
342	/*
343	* The shadow ROMs.
344	*/
345	pgmLock(pVM);
346	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
347	{
348	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
349	{
350	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
351	for (uint32_t iPage = 0; iPage < cPages; iPage++)
352	{
353	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
354	if (pRomPage->LiveSave.fWrittenTo)
355	{
356	pRomPage->LiveSave.fWrittenTo = false;
357	if (!pRomPage->LiveSave.fDirty)
358	{
359	pRomPage->LiveSave.fDirty = true;
360	pVM->pgm.s.LiveSave.Rom.cReadyPages--;
361	pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
362	}
363	pRomPage->LiveSave.fDirtiedRecently = true;
364	}
365	else
366	pRomPage->LiveSave.fDirtiedRecently = false;
367	}
368	}
369	}
370	pgmUnlock(pVM);
371	}
372
373
374	/**
375	* Takes care of the virgin ROM pages in the first pass.
376	*
377	* This is an attempt at simplifying the handling of ROM pages a little bit.
378	* This ASSUMES that no new ROM ranges will be added and that they won't be
379	* relinked in any way.
380	*
381	* @param pVM The VM handle.
382	* @param pSSM The SSM handle.
383	* @param fLiveSave Whether we're in a live save or not.
384	*/
385	static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
386	{
387	pgmLock(pVM);
388	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
389	{
390	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
391	for (uint32_t iPage = 0; iPage < cPages; iPage++)
392	{
393	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
394	PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
395
396	/* Get the virgin page descriptor. */
397	PPGMPAGE pPage;
398	if (PGMROMPROT_IS_ROM(enmProt))
399	pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
400	else
401	pPage = &pRom->aPages[iPage].Virgin;
402
403	/* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
404	int rc = VINF_SUCCESS;
405	char abPage[PAGE_SIZE];
406	if (!PGM_PAGE_IS_ZERO(pPage))
407	{
408	void const *pvPage;
409	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
410	if (RT_SUCCESS(rc))
411	memcpy(abPage, pvPage, PAGE_SIZE);
412	}
413	else
414	ASMMemZeroPage(abPage);
415	pgmUnlock(pVM);
416	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
417
418	/* Save it. */
419	if (iPage > 0)
420	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
421	else
422	{
423	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN \| PGM_STATE_REC_FLAG_ADDR);
424	SSMR3PutU8(pSSM, pRom->idSavedState);
425	SSMR3PutU32(pSSM, iPage);
426	}
427	SSMR3PutU8(pSSM, (uint8_t)enmProt);
428	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
429	if (RT_FAILURE(rc))
430	return rc;
431
432	/* Update state. */
433	pgmLock(pVM);
434	pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
435	if (fLiveSave)
436	{
437	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
438	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
439	pVM->pgm.s.LiveSave.cSavedPages++;
440	}
441	}
442	}
443	pgmUnlock(pVM);
444	return VINF_SUCCESS;
445	}
446
447
448	/**
449	* Saves dirty pages in the shadowed ROM ranges.
450	*
451	* Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
452	*
453	* @returns VBox status code.
454	* @param pVM The VM handle.
455	* @param pSSM The SSM handle.
456	* @param fLiveSave Whether it's a live save or not.
457	* @param fFinalPass Whether this is the final pass or not.
458	*/
459	static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
460	{
461	/*
462	* The Shadowed ROMs.
463	*
464	* ASSUMES that the ROM ranges are fixed.
465	* ASSUMES that all the ROM ranges are mapped.
466	*/
467	pgmLock(pVM);
468	for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
469	{
470	if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
471	{
472	uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
473	uint32_t iPrevPage = cPages;
474	for (uint32_t iPage = 0; iPage < cPages; iPage++)
475	{
476	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
477	if ( !fLiveSave
478	\|\| ( pRomPage->LiveSave.fDirty
479	&& ( ( !pRomPage->LiveSave.fDirtiedRecently
480	&& !pRomPage->LiveSave.fWrittenTo)
481	\|\| fFinalPass
482	)
483	)
484	)
485	{
486	uint8_t abPage[PAGE_SIZE];
487	PGMROMPROT enmProt = pRomPage->enmProt;
488	RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
489	PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(&pVM->pgm.s, GCPhys);
490	bool fZero = PGM_PAGE_IS_ZERO(pPage);
491	int rc = VINF_SUCCESS;
492	if (!fZero)
493	{
494	void const *pvPage;
495	rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
496	if (RT_SUCCESS(rc))
497	memcpy(abPage, pvPage, PAGE_SIZE);
498	}
499	if (fLiveSave && RT_SUCCESS(rc))
500	{
501	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
502	pRomPage->LiveSave.fDirty = false;
503	pVM->pgm.s.LiveSave.Rom.cReadyPages++;
504	pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
505	pVM->pgm.s.LiveSave.cSavedPages++;
506	}
507	pgmUnlock(pVM);
508	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
509
510	if (iPage - 1U == iPrevPage && iPage > 0)
511	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
512	else
513	{
514	SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) \| PGM_STATE_REC_FLAG_ADDR);
515	SSMR3PutU8(pSSM, pRom->idSavedState);
516	SSMR3PutU32(pSSM, iPage);
517	}
518	rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
519	if (!fZero)
520	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
521	if (RT_FAILURE(rc))
522	return rc;
523
524	pgmLock(pVM);
525	iPrevPage = iPage;
526	}
527	/*
528	* In the final pass, make sure the protection is in sync.
529	*/
530	else if ( fFinalPass
531	&& pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
532	{
533	PGMROMPROT enmProt = pRomPage->enmProt;
534	pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
535	pgmUnlock(pVM);
536
537	if (iPage - 1U == iPrevPage && iPage > 0)
538	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
539	else
540	{
541	SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT \| PGM_STATE_REC_FLAG_ADDR);
542	SSMR3PutU8(pSSM, pRom->idSavedState);
543	SSMR3PutU32(pSSM, iPage);
544	}
545	int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
546	if (RT_FAILURE(rc))
547	return rc;
548
549	pgmLock(pVM);
550	iPrevPage = iPage;
551	}
552	}
553	}
554	}
555	pgmUnlock(pVM);
556	return VINF_SUCCESS;
557	}
558
559
560	/**
561	* Cleans up ROM pages after a live save.
562	*
563	* @param pVM The VM handle.
564	*/
565	static void pgmR3DoneRomPages(PVM pVM)
566	{
567	NOREF(pVM);
568	}
569
570
571	/**
572	* Prepares the MMIO2 pages for a live save.
573	*
574	* @returns VBox status code.
575	* @param pVM The VM handle.
576	*/
577	static int pgmR3PrepMmio2Pages(PVM pVM)
578	{
579	/*
580	* Initialize the live save tracking in the MMIO2 ranges.
581	* ASSUME nothing changes here.
582	*/
583	pgmLock(pVM);
584	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
585	{
586	uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
587	pgmUnlock(pVM);
588
589	PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
590	if (!paLSPages)
591	return VERR_NO_MEMORY;
592	for (uint32_t iPage = 0; iPage < cPages; iPage++)
593	{
594	/* Initialize it as a dirty zero page. */
595	paLSPages[iPage].fDirty = true;
596	paLSPages[iPage].cUnchangedScans = 0;
597	paLSPages[iPage].fZero = true;
598	paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
599	paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
600	}
601
602	pgmLock(pVM);
603	pMmio2->paLSPages = paLSPages;
604	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
605	}
606	pgmUnlock(pVM);
607	return VINF_SUCCESS;
608	}
609
610
611	/**
612	* Assigns IDs to the MMIO2 ranges and saves them.
613	*
614	* @returns VBox status code.
615	* @param pVM The VM handle.
616	* @param pSSM Saved state handle.
617	*/
618	static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
619	{
620	pgmLock(pVM);
621	uint8_t id = 1;
622	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
623	{
624	pMmio2->idSavedState = id;
625	SSMR3PutU8(pSSM, id);
626	SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pDevReg->szDeviceName);
627	SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
628	SSMR3PutU8(pSSM, pMmio2->iRegion);
629	SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
630	int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
631	if (RT_FAILURE(rc))
632	break;
633	}
634	pgmUnlock(pVM);
635	return SSMR3PutU8(pSSM, UINT8_MAX);
636	}
637
638
639	/**
640	* Loads the MMIO2 range ID assignments.
641	*
642	* @returns VBox status code.
643	*
644	* @param pVM The VM handle.
645	* @param pSSM The saved state handle.
646	*/
647	static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
648	{
649	Assert(PGMIsLockOwner(pVM));
650
651	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
652	pMmio2->idSavedState = UINT8_MAX;
653
654	for (;;)
655	{
656	/*
657	* Read the data.
658	*/
659	uint8_t id;
660	int rc = SSMR3GetU8(pSSM, &id);
661	if (RT_FAILURE(rc))
662	return rc;
663	if (id == UINT8_MAX)
664	{
665	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
666	AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
667	return VINF_SUCCESS; /* the end */
668	}
669	AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
670
671	char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szDeviceName)];
672	rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
673	AssertLogRelRCReturn(rc, rc);
674
675	uint32_t uInstance;
676	SSMR3GetU32(pSSM, &uInstance);
677	uint8_t iRegion;
678	SSMR3GetU8(pSSM, &iRegion);
679
680	char szDesc[64];
681	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
682	AssertLogRelRCReturn(rc, rc);
683
684	RTGCPHYS cb;
685	rc = SSMR3GetGCPhys(pSSM, &cb);
686	AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
687
688	/*
689	* Locate a matching MMIO2 range.
690	*/
691	PPGMMMIO2RANGE pMmio2;
692	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
693	{
694	if ( pMmio2->idSavedState == UINT8_MAX
695	&& pMmio2->iRegion == iRegion
696	&& pMmio2->pDevInsR3->iInstance == uInstance
697	&& !strcmp(pMmio2->pDevInsR3->pDevReg->szDeviceName, szDevName))
698	{
699	pMmio2->idSavedState = id;
700	break;
701	}
702	}
703	if (!pMmio2)
704	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
705	szDesc, szDevName, uInstance, iRegion);
706
707	/*
708	* Validate the configuration, the size of the MMIO2 region should be
709	* the same.
710	*/
711	if (cb != pMmio2->RamRange.cb)
712	{
713	LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
714	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
715	if (cb > pMmio2->RamRange.cb) /* bad idea? */
716	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
717	pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
718	}
719	} /* forever */
720	}
721
722
723	/**
724	* Scans one MMIO2 page.
725	*
726	* @returns True if changed, false if unchanged.
727	*
728	* @param pVM The VM handle
729	* @param pbPage The page bits.
730	* @param pLSPage The live save tracking structure for the page.
731	*
732	*/
733	DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
734	{
735	/*
736	* Special handling of zero pages.
737	*/
738	bool const fZero = pLSPage->fZero;
739	if (fZero)
740	{
741	if (ASMMemIsZeroPage(pbPage))
742	{
743	/* Not modified. */
744	if (pLSPage->fDirty)
745	pLSPage->cUnchangedScans++;
746	return false;
747	}
748
749	pLSPage->fZero = false;
750	pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
751	}
752	else
753	{
754	/*
755	* CRC the first half, if it doesn't match the page is dirty and
756	* we won't check the 2nd half (we'll do that next time).
757	*/
758	uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
759	if (u32CrcH1 == pLSPage->u32CrcH1)
760	{
761	uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
762	if (u32CrcH2 == pLSPage->u32CrcH2)
763	{
764	/* Probably not modified. */
765	if (pLSPage->fDirty)
766	pLSPage->cUnchangedScans++;
767	return false;
768	}
769
770	pLSPage->u32CrcH2 = u32CrcH2;
771	}
772	else
773	{
774	pLSPage->u32CrcH1 = u32CrcH1;
775	if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
776	&& ASMMemIsZeroPage(pbPage))
777	{
778	pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
779	pLSPage->fZero = true;
780	}
781	}
782	}
783
784	/* dirty page path */
785	pLSPage->cUnchangedScans = 0;
786	if (!pLSPage->fDirty)
787	{
788	pLSPage->fDirty = true;
789	pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
790	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
791	if (fZero)
792	pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
793	}
794	return true;
795	}
796
797
798	/**
799	* Scan for MMIO2 page modifications.
800	*
801	* @param pVM The VM handle.
802	* @param uPass The pass number.
803	*/
804	static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
805	{
806	/*
807	* Since this is a bit expensive we lower the scan rate after a little while.
808	*/
809	if ( ( (uPass & 3) != 0
810	&& uPass > 10)
811	\|\| uPass == SSM_PASS_FINAL)
812	return;
813
814	pgmLock(pVM); /* paranoia */
815	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
816	{
817	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
818	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
819	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
820	pgmUnlock(pVM);
821
822	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
823	{
824	uint8_t const pbPage = (uint8_t const )pMmio2->pvR3 + iPage * PAGE_SIZE;
825	pgmR3ScanMmio2Page(pVM,pbPage, &paLSPages[iPage]);
826	}
827
828	pgmLock(pVM);
829	}
830	pgmUnlock(pVM);
831
832	}
833
834
835	/**
836	* Save quiescent MMIO2 pages.
837	*
838	* @returns VBox status code.
839	* @param pVM The VM handle.
840	* @param pSSM The SSM handle.
841	* @param fLiveSave Whether it's a live save or not.
842	* @param uPass The pass number.
843	*/
844	static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
845	{
846	/** @todo implement live saving of MMIO2 pages. (Need some way of telling the
847	* device that we wish to know about changes.) */
848
849	int rc = VINF_SUCCESS;
850	if (uPass == SSM_PASS_FINAL)
851	{
852	/*
853	* The mop up round.
854	*/
855	pgmLock(pVM);
856	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
857	pMmio2 && RT_SUCCESS(rc);
858	pMmio2 = pMmio2->pNextR3)
859	{
860	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
861	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
862	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
863	uint32_t iPageLast = cPages;
864	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
865	{
866	uint8_t u8Type;
867	if (!fLiveSave)
868	u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
869	else
870	{
871	/* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
872	if ( !paLSPages[iPage].fDirty
873	&& !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
874	{
875	if (paLSPages[iPage].fZero)
876	continue;
877
878	uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
879	RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
880	if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
881	continue;
882	}
883	u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
884	pVM->pgm.s.LiveSave.cSavedPages++;
885	}
886
887	if (iPage != 0 && iPage == iPageLast + 1)
888	rc = SSMR3PutU8(pSSM, u8Type);
889	else
890	{
891	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
892	SSMR3PutU8(pSSM, pMmio2->idSavedState);
893	rc = SSMR3PutU32(pSSM, iPage);
894	}
895	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
896	rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
897	if (RT_FAILURE(rc))
898	break;
899	iPageLast = iPage;
900	}
901	}
902	pgmUnlock(pVM);
903	}
904	/*
905	* Reduce the rate after a little while since the current MMIO2 approach is
906	* a bit expensive.
907	* We position it two passes after the scan pass to avoid saving busy pages.
908	*/
909	else if ( uPass <= 10
910	\|\| (uPass & 3) == 2)
911	{
912	pgmLock(pVM);
913	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
914	pMmio2 && RT_SUCCESS(rc);
915	pMmio2 = pMmio2->pNextR3)
916	{
917	PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
918	uint8_t const pbPage = (uint8_t const )pMmio2->RamRange.pvR3;
919	uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
920	uint32_t iPageLast = cPages;
921	pgmUnlock(pVM);
922
923	for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
924	{
925	/* Skip clean pages and pages which hasn't quiesced. */
926	if (!paLSPages[iPage].fDirty)
927	continue;
928	if (paLSPages[iPage].cUnchangedScans < 3)
929	continue;
930	if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
931	continue;
932
933	/* Save it. */
934	bool const fZero = paLSPages[iPage].fZero;
935	uint8_t abPage[PAGE_SIZE];
936	if (!fZero)
937	{
938	memcpy(abPage, pbPage, PAGE_SIZE);
939	RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
940	}
941
942	uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
943	if (iPage != 0 && iPage == iPageLast + 1)
944	rc = SSMR3PutU8(pSSM, u8Type);
945	else
946	{
947	SSMR3PutU8(pSSM, u8Type \| PGM_STATE_REC_FLAG_ADDR);
948	SSMR3PutU8(pSSM, pMmio2->idSavedState);
949	rc = SSMR3PutU32(pSSM, iPage);
950	}
951	if (u8Type == PGM_STATE_REC_MMIO2_RAW)
952	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
953	if (RT_FAILURE(rc))
954	break;
955
956	/* Housekeeping. */
957	paLSPages[iPage].fDirty = false;
958	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
959	pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
960	if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
961	pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
962	pVM->pgm.s.LiveSave.cSavedPages++;
963	iPageLast = iPage;
964	}
965
966	pgmLock(pVM);
967	}
968	pgmUnlock(pVM);
969	}
970
971	return rc;
972	}
973
974
975	/**
976	* Cleans up MMIO2 pages after a live save.
977	*
978	* @param pVM The VM handle.
979	*/
980	static void pgmR3DoneMmio2Pages(PVM pVM)
981	{
982	/*
983	* Free the tracking structures for the MMIO2 pages.
984	* We do the freeing outside the lock in case the VM is running.
985	*/
986	pgmLock(pVM);
987	for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
988	{
989	void *pvMmio2ToFree = pMmio2->paLSPages;
990	if (pvMmio2ToFree)
991	{
992	pMmio2->paLSPages = NULL;
993	pgmUnlock(pVM);
994	MMR3HeapFree(pvMmio2ToFree);
995	pgmLock(pVM);
996	}
997	}
998	pgmUnlock(pVM);
999	}
1000
1001
1002	/**
1003	* Prepares the RAM pages for a live save.
1004	*
1005	* @returns VBox status code.
1006	* @param pVM The VM handle.
1007	*/
1008	static int pgmR3PrepRamPages(PVM pVM)
1009	{
1010
1011	/*
1012	* Try allocating tracking structures for the ram ranges.
1013	*
1014	* To avoid lock contention, we leave the lock every time we're allocating
1015	* a new array. This means we'll have to ditch the allocation and start
1016	* all over again if the RAM range list changes in-between.
1017	*
1018	* Note! pgmR3SaveDone will always be called and it is therefore responsible
1019	* for cleaning up.
1020	*/
1021	PPGMRAMRANGE pCur;
1022	pgmLock(pVM);
1023	do
1024	{
1025	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1026	{
1027	if ( !pCur->paLSPages
1028	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1029	{
1030	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1031	uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1032	pgmUnlock(pVM);
1033	PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1034	if (!paLSPages)
1035	return VERR_NO_MEMORY;
1036	pgmLock(pVM);
1037	if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1038	{
1039	pgmUnlock(pVM);
1040	MMR3HeapFree(paLSPages);
1041	pgmLock(pVM);
1042	break; /* try again */
1043	}
1044	pCur->paLSPages = paLSPages;
1045
1046	/*
1047	* Initialize the array.
1048	*/
1049	uint32_t iPage = cPages;
1050	while (iPage-- > 0)
1051	{
1052	/** @todo yield critsect! (after moving this away from EMT0) */
1053	PCPGMPAGE pPage = &pCur->aPages[iPage];
1054	paLSPages[iPage].cDirtied = 0;
1055	paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1056	paLSPages[iPage].fWriteMonitored = 0;
1057	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1058	paLSPages[iPage].u2Reserved = 0;
1059	switch (PGM_PAGE_GET_TYPE(pPage))
1060	{
1061	case PGMPAGETYPE_RAM:
1062	if (PGM_PAGE_IS_ZERO(pPage))
1063	{
1064	paLSPages[iPage].fZero = 1;
1065	paLSPages[iPage].fShared = 0;
1066	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1067	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1068	#endif
1069	}
1070	else if (PGM_PAGE_IS_SHARED(pPage))
1071	{
1072	paLSPages[iPage].fZero = 0;
1073	paLSPages[iPage].fShared = 1;
1074	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1075	paLSPages[iPage].u32Crc = UINT32_MAX;
1076	#endif
1077	}
1078	else
1079	{
1080	paLSPages[iPage].fZero = 0;
1081	paLSPages[iPage].fShared = 0;
1082	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1083	paLSPages[iPage].u32Crc = UINT32_MAX;
1084	#endif
1085	}
1086	paLSPages[iPage].fIgnore = 0;
1087	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1088	break;
1089
1090	case PGMPAGETYPE_ROM_SHADOW:
1091	case PGMPAGETYPE_ROM:
1092	{
1093	paLSPages[iPage].fZero = 0;
1094	paLSPages[iPage].fShared = 0;
1095	paLSPages[iPage].fDirty = 0;
1096	paLSPages[iPage].fIgnore = 1;
1097	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1098	paLSPages[iPage].u32Crc = UINT32_MAX;
1099	#endif
1100	pVM->pgm.s.LiveSave.cIgnoredPages++;
1101	break;
1102	}
1103
1104	default:
1105	AssertMsgFailed(("%R[pgmpage]", pPage));
1106	case PGMPAGETYPE_MMIO2:
1107	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1108	paLSPages[iPage].fZero = 0;
1109	paLSPages[iPage].fShared = 0;
1110	paLSPages[iPage].fDirty = 0;
1111	paLSPages[iPage].fIgnore = 1;
1112	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1113	paLSPages[iPage].u32Crc = UINT32_MAX;
1114	#endif
1115	pVM->pgm.s.LiveSave.cIgnoredPages++;
1116	break;
1117
1118	case PGMPAGETYPE_MMIO:
1119	paLSPages[iPage].fZero = 0;
1120	paLSPages[iPage].fShared = 0;
1121	paLSPages[iPage].fDirty = 0;
1122	paLSPages[iPage].fIgnore = 1;
1123	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1124	paLSPages[iPage].u32Crc = UINT32_MAX;
1125	#endif
1126	pVM->pgm.s.LiveSave.cIgnoredPages++;
1127	break;
1128	}
1129	}
1130	}
1131	}
1132	} while (pCur);
1133	pgmUnlock(pVM);
1134
1135	return VINF_SUCCESS;
1136	}
1137
1138
1139	/**
1140	* Saves the RAM configuration.
1141	*
1142	* @returns VBox status code.
1143	* @param pVM The VM handle.
1144	* @param pSSM The saved state handle.
1145	*/
1146	static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1147	{
1148	uint32_t cbRamHole = 0;
1149	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1150	AssertRCReturn(rc, rc);
1151
1152	uint64_t cbRam = 0;
1153	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1154	AssertRCReturn(rc, rc);
1155
1156	SSMR3PutU32(pSSM, cbRamHole);
1157	return SSMR3PutU64(pSSM, cbRam);
1158	}
1159
1160
1161	/**
1162	* Loads and verifies the RAM configuration.
1163	*
1164	* @returns VBox status code.
1165	* @param pVM The VM handle.
1166	* @param pSSM The saved state handle.
1167	*/
1168	static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1169	{
1170	uint32_t cbRamHoleCfg = 0;
1171	int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1172	AssertRCReturn(rc, rc);
1173
1174	uint64_t cbRamCfg = 0;
1175	rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1176	AssertRCReturn(rc, rc);
1177
1178	uint32_t cbRamHoleSaved;
1179	SSMR3GetU32(pSSM, &cbRamHoleSaved);
1180
1181	uint64_t cbRamSaved;
1182	rc = SSMR3GetU64(pSSM, &cbRamSaved);
1183	AssertRCReturn(rc, rc);
1184
1185	if ( cbRamHoleCfg != cbRamHoleSaved
1186	\|\| cbRamCfg != cbRamSaved)
1187	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1188	cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1189	return VINF_SUCCESS;
1190	}
1191
1192	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1193
1194	/**
1195	* Calculates the CRC-32 for a RAM page and updates the live save page tracking
1196	* info with it.
1197	*
1198	* @param pVM The VM handle.
1199	* @param pCur The current RAM range.
1200	* @param paLSPages The current array of live save page tracking
1201	* structures.
1202	* @param iPage The page index.
1203	*/
1204	static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1205	{
1206	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1207	void const *pvPage;
1208	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1209	if (RT_SUCCESS(rc))
1210	paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1211	else
1212	paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1213	}
1214
1215
1216	/**
1217	* Verifies the CRC-32 for a page given it's raw bits.
1218	*
1219	* @param pvPage The page bits.
1220	* @param pCur The current RAM range.
1221	* @param paLSPages The current array of live save page tracking
1222	* structures.
1223	* @param iPage The page index.
1224	*/
1225	static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1226	{
1227	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1228	{
1229	uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1230	Assert(!PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]) \|\| u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1231	AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1232	("%08x != %08x for %RGp %R[pgmpage]\n", paLSPages[iPage].u32Crc, u32Crc,
1233	pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1234	}
1235	}
1236
1237
1238	/**
1239	* Verfies the CRC-32 for a RAM page.
1240	*
1241	* @param pVM The VM handle.
1242	* @param pCur The current RAM range.
1243	* @param paLSPages The current array of live save page tracking
1244	* structures.
1245	* @param iPage The page index.
1246	*/
1247	static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1248	{
1249	if (paLSPages[iPage].u32Crc != UINT32_MAX)
1250	{
1251	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1252	void const *pvPage;
1253	int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1254	if (RT_SUCCESS(rc))
1255	pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage);
1256	}
1257	}
1258
1259	#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1260
1261	/**
1262	* Scan for RAM page modifications and reprotect them.
1263	*
1264	* @param pVM The VM handle.
1265	* @param fFinalPass Whether this is the final pass or not.
1266	*/
1267	static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1268	{
1269	/*
1270	* The RAM.
1271	*/
1272	RTGCPHYS GCPhysCur = 0;
1273	PPGMRAMRANGE pCur;
1274	pgmLock(pVM);
1275	do
1276	{
1277	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1278	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1279	{
1280	if ( pCur->GCPhysLast > GCPhysCur
1281	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1282	{
1283	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1284	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1285	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1286	GCPhysCur = 0;
1287	for (; iPage < cPages; iPage++)
1288	{
1289	/* Do yield first. */
1290	if ( !fFinalPass
1291	#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1292	&& (iPage & 0x7ff) == 0x100
1293	#endif
1294	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1295	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1296	{
1297	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1298	break; /* restart */
1299	}
1300
1301	/* Skip already ignored pages. */
1302	if (paLSPages[iPage].fIgnore)
1303	continue;
1304
1305	if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1306	{
1307	/*
1308	* A RAM page.
1309	*/
1310	switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1311	{
1312	case PGM_PAGE_STATE_ALLOCATED:
1313	/** @todo Optimize this: Don't always re-enable write
1314	* monitoring if the page is known to be very busy. */
1315	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1316	{
1317	Assert(paLSPages[iPage].fWriteMonitored);
1318	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1319	Assert(pVM->pgm.s.cWrittenToPages > 0);
1320	pVM->pgm.s.cWrittenToPages--;
1321	}
1322	else
1323	{
1324	Assert(!paLSPages[iPage].fWriteMonitored);
1325	pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1326	}
1327
1328	if (!paLSPages[iPage].fDirty)
1329	{
1330	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1331	if (paLSPages[iPage].fZero)
1332	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1333	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1334	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1335	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1336	}
1337
1338	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_WRITE_MONITORED);
1339	pVM->pgm.s.cMonitoredPages++;
1340	paLSPages[iPage].fWriteMonitored = 1;
1341	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1342	paLSPages[iPage].fDirty = 1;
1343	paLSPages[iPage].fZero = 0;
1344	paLSPages[iPage].fShared = 0;
1345	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1346	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1347	#endif
1348	break;
1349
1350	case PGM_PAGE_STATE_WRITE_MONITORED:
1351	Assert(paLSPages[iPage].fWriteMonitored);
1352	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1353	{
1354	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1355	if (paLSPages[iPage].fWriteMonitoredJustNow)
1356	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1357	else
1358	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1359	#endif
1360	paLSPages[iPage].fWriteMonitoredJustNow = 0;
1361	}
1362	else
1363	{
1364	paLSPages[iPage].fWriteMonitoredJustNow = 1;
1365	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1366	paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1367	#endif
1368	if (!paLSPages[iPage].fDirty)
1369	{
1370	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1371	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1372	if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1373	paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1374	}
1375	}
1376	break;
1377
1378	case PGM_PAGE_STATE_ZERO:
1379	if (!paLSPages[iPage].fZero)
1380	{
1381	if (!paLSPages[iPage].fDirty)
1382	{
1383	paLSPages[iPage].fDirty = 1;
1384	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1385	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1386	}
1387	paLSPages[iPage].fZero = 1;
1388	paLSPages[iPage].fShared = 0;
1389	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1390	paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1391	#endif
1392	}
1393	break;
1394
1395	case PGM_PAGE_STATE_SHARED:
1396	if (!paLSPages[iPage].fShared)
1397	{
1398	if (!paLSPages[iPage].fDirty)
1399	{
1400	paLSPages[iPage].fDirty = 1;
1401	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1402	if (paLSPages[iPage].fZero)
1403	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1404	pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1405	}
1406	paLSPages[iPage].fZero = 0;
1407	paLSPages[iPage].fShared = 1;
1408	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1409	pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1410	#endif
1411	}
1412	break;
1413	}
1414	}
1415	else
1416	{
1417	/*
1418	* All other types => Ignore the page.
1419	*/
1420	Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1421	paLSPages[iPage].fIgnore = 1;
1422	if (paLSPages[iPage].fWriteMonitored)
1423	{
1424	/** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1425	* pages! */
1426	if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1427	{
1428	AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1429	PGM_PAGE_SET_STATE(&pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1430	Assert(pVM->pgm.s.cMonitoredPages > 0);
1431	pVM->pgm.s.cMonitoredPages--;
1432	}
1433	if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1434	{
1435	PGM_PAGE_CLEAR_WRITTEN_TO(&pCur->aPages[iPage]);
1436	Assert(pVM->pgm.s.cWrittenToPages > 0);
1437	pVM->pgm.s.cWrittenToPages--;
1438	}
1439	pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1440	}
1441
1442	/** @todo the counting doesn't quite work out here. fix later? */
1443	if (paLSPages[iPage].fDirty)
1444	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1445	else
1446	{
1447	pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1448	if (paLSPages[iPage].fZero)
1449	pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1450	}
1451	pVM->pgm.s.LiveSave.cIgnoredPages++;
1452	}
1453	} /* for each page in range */
1454
1455	if (GCPhysCur != 0)
1456	break; /* Yield + ramrange change */
1457	GCPhysCur = pCur->GCPhysLast;
1458	}
1459	} /* for each range */
1460	} while (pCur);
1461	pgmUnlock(pVM);
1462	}
1463
1464
1465	/**
1466	* Save quiescent RAM pages.
1467	*
1468	* @returns VBox status code.
1469	* @param pVM The VM handle.
1470	* @param pSSM The SSM handle.
1471	* @param fLiveSave Whether it's a live save or not.
1472	* @param uPass The pass number.
1473	*/
1474	static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1475	{
1476	/*
1477	* The RAM.
1478	*/
1479	RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1480	RTGCPHYS GCPhysCur = 0;
1481	PPGMRAMRANGE pCur;
1482	pgmLock(pVM);
1483	do
1484	{
1485	uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1486	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1487	{
1488	if ( pCur->GCPhysLast > GCPhysCur
1489	&& !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1490	{
1491	PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1492	uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1493	uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1494	GCPhysCur = 0;
1495	for (; iPage < cPages; iPage++)
1496	{
1497	/* Do yield first. */
1498	if ( uPass != SSM_PASS_FINAL
1499	&& (iPage & 0x7ff) == 0x100
1500	&& PDMR3CritSectYield(&pVM->pgm.s.CritSect)
1501	&& pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1502	{
1503	GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1504	break; /* restart */
1505	}
1506
1507	/*
1508	* Only save pages that hasn't changed since last scan and are dirty.
1509	*/
1510	if ( uPass != SSM_PASS_FINAL
1511	&& paLSPages)
1512	{
1513	if (!paLSPages[iPage].fDirty)
1514	continue;
1515	if (paLSPages[iPage].fWriteMonitoredJustNow)
1516	continue;
1517	if (paLSPages[iPage].fIgnore)
1518	continue;
1519	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM) /* in case of recent ramppings */
1520	continue;
1521	if ( PGM_PAGE_GET_STATE(&pCur->aPages[iPage])
1522	!= ( paLSPages[iPage].fZero
1523	? PGM_PAGE_STATE_ZERO
1524	: paLSPages[iPage].fShared
1525	? PGM_PAGE_STATE_SHARED
1526	: PGM_PAGE_STATE_WRITE_MONITORED))
1527	continue;
1528	if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1529	continue;
1530	}
1531	else
1532	{
1533	if ( paLSPages
1534	&& !paLSPages[iPage].fDirty
1535	&& !paLSPages[iPage].fIgnore)
1536	{
1537	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1538	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1539	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1540	#endif
1541	continue;
1542	}
1543	if (PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) != PGMPAGETYPE_RAM)
1544	continue;
1545	}
1546
1547	/*
1548	* Do the saving outside the PGM critsect since SSM may block on I/O.
1549	*/
1550	int rc;
1551	RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1552	bool fZero = PGM_PAGE_IS_ZERO(&pCur->aPages[iPage]);
1553
1554	if (!fZero)
1555	{
1556	/*
1557	* Copy the page and then save it outside the lock (since any
1558	* SSM call may block).
1559	*/
1560	uint8_t abPage[PAGE_SIZE];
1561	void const *pvPage;
1562	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage);
1563	if (RT_SUCCESS(rc))
1564	{
1565	memcpy(abPage, pvPage, PAGE_SIZE);
1566	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1567	if (paLSPages)
1568	pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage);
1569	#endif
1570	}
1571	pgmUnlock(pVM);
1572	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1573
1574	if (GCPhys == GCPhysLast + PAGE_SIZE)
1575	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1576	else
1577	{
1578	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW \| PGM_STATE_REC_FLAG_ADDR);
1579	SSMR3PutGCPhys(pSSM, GCPhys);
1580	}
1581	rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1582	}
1583	else
1584	{
1585	/*
1586	* Dirty zero page.
1587	*/
1588	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1589	if (paLSPages)
1590	pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1591	#endif
1592	pgmUnlock(pVM);
1593
1594	if (GCPhys == GCPhysLast + PAGE_SIZE)
1595	rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1596	else
1597	{
1598	SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO \| PGM_STATE_REC_FLAG_ADDR);
1599	rc = SSMR3PutGCPhys(pSSM, GCPhys);
1600	}
1601	}
1602	if (RT_FAILURE(rc))
1603	return rc;
1604
1605	pgmLock(pVM);
1606	GCPhysLast = GCPhys;
1607	if (paLSPages)
1608	{
1609	paLSPages[iPage].fDirty = 0;
1610	pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1611	if (fZero)
1612	pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1613	pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1614	pVM->pgm.s.LiveSave.cSavedPages++;
1615	}
1616	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1617	{
1618	GCPhysCur = GCPhys \| PAGE_OFFSET_MASK;
1619	break; /* restart */
1620	}
1621
1622	} /* for each page in range */
1623
1624	if (GCPhysCur != 0)
1625	break; /* Yield + ramrange change */
1626	GCPhysCur = pCur->GCPhysLast;
1627	}
1628	} /* for each range */
1629	} while (pCur);
1630	pgmUnlock(pVM);
1631
1632	return VINF_SUCCESS;
1633	}
1634
1635
1636	/**
1637	* Cleans up RAM pages after a live save.
1638	*
1639	* @param pVM The VM handle.
1640	*/
1641	static void pgmR3DoneRamPages(PVM pVM)
1642	{
1643	/*
1644	* Free the tracking arrays and disable write monitoring.
1645	*
1646	* Play nice with the PGM lock in case we're called while the VM is still
1647	* running. This means we have to delay the freeing since we wish to use
1648	* paLSPages as an indicator of which RAM ranges which we need to scan for
1649	* write monitored pages.
1650	*/
1651	void *pvToFree = NULL;
1652	PPGMRAMRANGE pCur;
1653	uint32_t cMonitoredPages = 0;
1654	pgmLock(pVM);
1655	do
1656	{
1657	for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1658	{
1659	if (pCur->paLSPages)
1660	{
1661	if (pvToFree)
1662	{
1663	uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1664	pgmUnlock(pVM);
1665	MMR3HeapFree(pvToFree);
1666	pvToFree = NULL;
1667	pgmLock(pVM);
1668	if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1669	break; /* start over again. */
1670	}
1671
1672	pvToFree = pCur->paLSPages;
1673	pCur->paLSPages = NULL;
1674
1675	uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1676	while (iPage--)
1677	{
1678	PPGMPAGE pPage = &pCur->aPages[iPage];
1679	PGM_PAGE_CLEAR_WRITTEN_TO(pPage);
1680	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1681	{
1682	PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
1683	cMonitoredPages++;
1684	}
1685	}
1686	}
1687	}
1688	} while (pCur);
1689
1690	Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1691	if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1692	pVM->pgm.s.cMonitoredPages = 0;
1693	else
1694	pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1695
1696	pgmUnlock(pVM);
1697
1698	MMR3HeapFree(pvToFree);
1699	pvToFree = NULL;
1700	}
1701
1702
1703	/**
1704	* Execute a live save pass.
1705	*
1706	* @returns VBox status code.
1707	*
1708	* @param pVM The VM handle.
1709	* @param pSSM The SSM handle.
1710	*/
1711	static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1712	{
1713	int rc;
1714
1715	/*
1716	* Save the MMIO2 and ROM range IDs in pass 0.
1717	*/
1718	if (uPass == 0)
1719	{
1720	rc = pgmR3SaveRamConfig(pVM, pSSM);
1721	if (RT_FAILURE(rc))
1722	return rc;
1723	rc = pgmR3SaveRomRanges(pVM, pSSM);
1724	if (RT_FAILURE(rc))
1725	return rc;
1726	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1727	if (RT_FAILURE(rc))
1728	return rc;
1729	}
1730	/*
1731	* Reset the page-per-second estimate to avoid inflation by the initial
1732	* load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1733	*/
1734	else if (uPass == 7)
1735	{
1736	pVM->pgm.s.LiveSave.cSavedPages = 0;
1737	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1738	}
1739
1740	/*
1741	* Do the scanning.
1742	*/
1743	pgmR3ScanRomPages(pVM);
1744	pgmR3ScanMmio2Pages(pVM, uPass);
1745	pgmR3ScanRamPages(pVM, false /fFinalPass/);
1746	pgmR3PoolClearAll(pVM); /** @todo this could perhaps be optimized a bit. */
1747
1748	/*
1749	* Save the pages.
1750	*/
1751	if (uPass == 0)
1752	rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /fLiveSave/);
1753	else
1754	rc = VINF_SUCCESS;
1755	if (RT_SUCCESS(rc))
1756	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /fLiveSave/, false /fFinalPass/);
1757	if (RT_SUCCESS(rc))
1758	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, uPass);
1759	if (RT_SUCCESS(rc))
1760	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, uPass);
1761	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1762
1763	return rc;
1764	}
1765
1766
1767	/**
1768	* Votes on whether the live save phase is done or not.
1769	*
1770	* @returns VBox status code.
1771	*
1772	* @param pVM The VM handle.
1773	* @param pSSM The SSM handle.
1774	* @param uPass The data pass.
1775	*/
1776	static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1777	{
1778	/*
1779	* Update and calculate parameters used in the decision making.
1780	*/
1781	const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1782
1783	/* update history. */
1784	pgmLock(pVM);
1785	uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1786	pgmUnlock(pVM);
1787	uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1788	+ pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1789	+ pVM->pgm.s.LiveSave.Ram.cDirtyPages
1790	+ cWrittenToPages;
1791	uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1792	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1793	pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1794
1795	/* calc shortterm average (4 passes). */
1796	AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1797	uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1798	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1799	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1800	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1801	uint32_t const cDirtyPagesShort = cTotal / 4;
1802	pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1803
1804	/* calc longterm average. */
1805	cTotal = 0;
1806	if (uPass < cHistoryEntries)
1807	for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1808	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1809	else
1810	for (i = 0; i < cHistoryEntries; i++)
1811	cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1812	uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1813	pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1814
1815	/* estimate the speed */
1816	uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1817	uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1818	/ ((long double)cNsElapsed / 1000000000.0) );
1819	pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1820
1821	/*
1822	* Try make a decision.
1823	*/
1824	if ( cDirtyPagesShort <= cDirtyPagesLong
1825	&& ( cDirtyNow <= cDirtyPagesShort
1826	\|\| cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1827	)
1828	)
1829	{
1830	if (uPass > 10)
1831	{
1832	uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1833	uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1834	uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1835	if (cMsMaxDowntime < 32)
1836	cMsMaxDowntime = 32;
1837	if ( ( cMsLeftLong <= cMsMaxDowntime
1838	&& cMsLeftShort < cMsMaxDowntime)
1839	\|\| cMsLeftShort < cMsMaxDowntime / 2
1840	)
1841	{
1842	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u\|%ums cDirtyPagesLong=%u\|%ums cMsMaxDowntime=%u\n",
1843	uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1844	return VINF_SUCCESS;
1845	}
1846	}
1847	else
1848	{
1849	if ( ( cDirtyPagesShort <= 128
1850	&& cDirtyPagesLong <= 1024)
1851	\|\| cDirtyPagesLong <= 256
1852	)
1853	{
1854	Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1855	return VINF_SUCCESS;
1856	}
1857	}
1858	}
1859	return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1860	}
1861
1862
1863	/**
1864	* Prepare for a live save operation.
1865	*
1866	* This will attempt to allocate and initialize the tracking structures. It
1867	* will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1868	* pgmR3SaveDone will do the cleanups.
1869	*
1870	* @returns VBox status code.
1871	*
1872	* @param pVM The VM handle.
1873	* @param pSSM The SSM handle.
1874	*/
1875	static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1876	{
1877	/*
1878	* Indicate that we will be using the write monitoring.
1879	*/
1880	pgmLock(pVM);
1881	/** @todo find a way of mediating this when more users are added. */
1882	if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1883	{
1884	pgmUnlock(pVM);
1885	AssertLogRelFailedReturn(VERR_INTERNAL_ERROR_2);
1886	}
1887	pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
1888	pgmUnlock(pVM);
1889
1890	/*
1891	* Initialize the statistics.
1892	*/
1893	pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
1894	pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
1895	pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
1896	pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
1897	pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
1898	pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
1899	pVM->pgm.s.LiveSave.cIgnoredPages = 0;
1900	pVM->pgm.s.LiveSave.fActive = true;
1901	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
1902	pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
1903	pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
1904	pVM->pgm.s.LiveSave.cSavedPages = 0;
1905	pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1906	pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
1907
1908	/*
1909	* Per page type.
1910	*/
1911	int rc = pgmR3PrepRomPages(pVM);
1912	if (RT_SUCCESS(rc))
1913	rc = pgmR3PrepMmio2Pages(pVM);
1914	if (RT_SUCCESS(rc))
1915	rc = pgmR3PrepRamPages(pVM);
1916	return rc;
1917	}
1918
1919
1920	/**
1921	* Execute state save operation.
1922	*
1923	* @returns VBox status code.
1924	* @param pVM VM Handle.
1925	* @param pSSM SSM operation handle.
1926	*/
1927	static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1928	{
1929	int rc;
1930	unsigned i;
1931	PPGM pPGM = &pVM->pgm.s;
1932
1933	/*
1934	* Lock PGM and set the no-more-writes indicator.
1935	*/
1936	pgmLock(pVM);
1937	pVM->pgm.s.fNoMorePhysWrites = true;
1938
1939	/*
1940	* Save basic data (required / unaffected by relocation).
1941	*/
1942	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
1943
1944	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1945	{
1946	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1947	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
1948	}
1949
1950	/*
1951	* The guest mappings.
1952	*/
1953	i = 0;
1954	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1955	{
1956	SSMR3PutU32( pSSM, i);
1957	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1958	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
1959	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1960	}
1961	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
1962
1963	/*
1964	* Save the (remainder of the) memory.
1965	*/
1966	if (RT_SUCCESS(rc))
1967	{
1968	if (pVM->pgm.s.LiveSave.fActive)
1969	{
1970	pgmR3ScanRomPages(pVM);
1971	pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
1972	pgmR3ScanRamPages(pVM, true /fFinalPass/);
1973
1974	rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /fLiveSave/, true /fFinalPass/);
1975	if (RT_SUCCESS(rc))
1976	rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1977	if (RT_SUCCESS(rc))
1978	rc = pgmR3SaveRamPages( pVM, pSSM, true /fLiveSave/, SSM_PASS_FINAL);
1979	}
1980	else
1981	{
1982	rc = pgmR3SaveRamConfig(pVM, pSSM);
1983	if (RT_SUCCESS(rc))
1984	rc = pgmR3SaveRomRanges(pVM, pSSM);
1985	if (RT_SUCCESS(rc))
1986	rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1987	if (RT_SUCCESS(rc))
1988	rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /fLiveSave/);
1989	if (RT_SUCCESS(rc))
1990	rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /fLiveSave/, true /fFinalPass/);
1991	if (RT_SUCCESS(rc))
1992	rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1993	if (RT_SUCCESS(rc))
1994	rc = pgmR3SaveRamPages( pVM, pSSM, false /fLiveSave/, SSM_PASS_FINAL);
1995	}
1996	SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
1997	}
1998
1999	pgmUnlock(pVM);
2000	return rc;
2001	}
2002
2003
2004	/**
2005	* Cleans up after an save state operation.
2006	*
2007	* @returns VBox status code.
2008	* @param pVM VM Handle.
2009	* @param pSSM SSM operation handle.
2010	*/
2011	static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2012	{
2013	/*
2014	* Do per page type cleanups first.
2015	*/
2016	if (pVM->pgm.s.LiveSave.fActive)
2017	{
2018	pgmR3DoneRomPages(pVM);
2019	pgmR3DoneMmio2Pages(pVM);
2020	pgmR3DoneRamPages(pVM);
2021	}
2022
2023	/*
2024	* Clear the live save indicator and disengage write monitoring.
2025	*/
2026	pgmLock(pVM);
2027	pVM->pgm.s.LiveSave.fActive = false;
2028	/** @todo this is blindly assuming that we're the only user of write
2029	* monitoring. Fix this when more users are added. */
2030	pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2031	pgmUnlock(pVM);
2032
2033	return VINF_SUCCESS;
2034	}
2035
2036
2037	/**
2038	* Prepare state load operation.
2039	*
2040	* @returns VBox status code.
2041	* @param pVM VM Handle.
2042	* @param pSSM SSM operation handle.
2043	*/
2044	static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2045	{
2046	/*
2047	* Call the reset function to make sure all the memory is cleared.
2048	*/
2049	PGMR3Reset(pVM);
2050	pVM->pgm.s.LiveSave.fActive = false;
2051	NOREF(pSSM);
2052	return VINF_SUCCESS;
2053	}
2054
2055
2056	/**
2057	* Load an ignored page.
2058	*
2059	* @returns VBox status code.
2060	* @param pSSM The saved state handle.
2061	*/
2062	static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2063	{
2064	uint8_t abPage[PAGE_SIZE];
2065	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2066	}
2067
2068
2069	/**
2070	* Loads a page without any bits in the saved state, i.e. making sure it's
2071	* really zero.
2072	*
2073	* @returns VBox status code.
2074	* @param pVM The VM handle.
2075	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2076	* state).
2077	* @param pPage The guest page tracking structure.
2078	* @param GCPhys The page address.
2079	* @param pRam The ram range (logging).
2080	*/
2081	static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2082	{
2083	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2084	&& uType != PGMPAGETYPE_INVALID)
2085	return VERR_SSM_UNEXPECTED_DATA;
2086
2087	/* I think this should be sufficient. */
2088	if (!PGM_PAGE_IS_ZERO(pPage))
2089	return VERR_SSM_UNEXPECTED_DATA;
2090
2091	NOREF(pVM);
2092	NOREF(GCPhys);
2093	NOREF(pRam);
2094	return VINF_SUCCESS;
2095	}
2096
2097
2098	/**
2099	* Loads a page from the saved state.
2100	*
2101	* @returns VBox status code.
2102	* @param pVM The VM handle.
2103	* @param pSSM The SSM handle.
2104	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2105	* state).
2106	* @param pPage The guest page tracking structure.
2107	* @param GCPhys The page address.
2108	* @param pRam The ram range (logging).
2109	*/
2110	static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2111	{
2112	/*
2113	* Match up the type, dealing with MMIO2 aliases (dropped).
2114	*/
2115	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2116	\|\| uType == PGMPAGETYPE_INVALID,
2117	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2118	VERR_SSM_UNEXPECTED_DATA);
2119
2120	/*
2121	* Load the page.
2122	*/
2123	void *pvPage;
2124	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2125	if (RT_SUCCESS(rc))
2126	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2127
2128	return rc;
2129	}
2130
2131
2132	/**
2133	* Loads a page (counter part to pgmR3SavePage).
2134	*
2135	* @returns VBox status code, fully bitched errors.
2136	* @param pVM The VM handle.
2137	* @param pSSM The SSM handle.
2138	* @param uType The page type.
2139	* @param pPage The page.
2140	* @param GCPhys The page address.
2141	* @param pRam The RAM range (for error messages).
2142	*/
2143	static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2144	{
2145	uint8_t uState;
2146	int rc = SSMR3GetU8(pSSM, &uState);
2147	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2148	if (uState == 0 /* zero */)
2149	rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2150	else if (uState == 1)
2151	rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2152	else
2153	rc = VERR_INTERNAL_ERROR;
2154	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2155	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2156	rc);
2157	return VINF_SUCCESS;
2158	}
2159
2160
2161	/**
2162	* Loads a shadowed ROM page.
2163	*
2164	* @returns VBox status code, errors are fully bitched.
2165	* @param pVM The VM handle.
2166	* @param pSSM The saved state handle.
2167	* @param pPage The page.
2168	* @param GCPhys The page address.
2169	* @param pRam The RAM range (for error messages).
2170	*/
2171	static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2172	{
2173	/*
2174	* Load and set the protection first, then load the two pages, the first
2175	* one is the active the other is the passive.
2176	*/
2177	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2178	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2179
2180	uint8_t uProt;
2181	int rc = SSMR3GetU8(pSSM, &uProt);
2182	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2183	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2184	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2185	&& enmProt < PGMROMPROT_END,
2186	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2187	VERR_SSM_UNEXPECTED_DATA);
2188
2189	if (pRomPage->enmProt != enmProt)
2190	{
2191	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2192	AssertLogRelRCReturn(rc, rc);
2193	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2194	}
2195
2196	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2197	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2198	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2199	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2200
2201	/** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2202	* used down the line (will the 2nd page will be written to the first
2203	* one because of a false TLB hit since the TLB is using GCPhys and
2204	* doesn't check the HCPhys of the desired page). */
2205	rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2206	if (RT_SUCCESS(rc))
2207	{
2208	pPageActive = pPage;
2209	rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2210	}
2211	return rc;
2212	}
2213
2214	/**
2215	* Ram range flags and bits for older versions of the saved state.
2216	*
2217	* @returns VBox status code.
2218	*
2219	* @param pVM The VM handle
2220	* @param pSSM The SSM handle.
2221	* @param uVersion The saved state version.
2222	*/
2223	static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2224	{
2225	PPGM pPGM = &pVM->pgm.s;
2226
2227	/*
2228	* Ram range flags and bits.
2229	*/
2230	uint32_t i = 0;
2231	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2232	{
2233	/* Check the seqence number / separator. */
2234	uint32_t u32Sep;
2235	int rc = SSMR3GetU32(pSSM, &u32Sep);
2236	if (RT_FAILURE(rc))
2237	return rc;
2238	if (u32Sep == ~0U)
2239	break;
2240	if (u32Sep != i)
2241	{
2242	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2243	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2244	}
2245	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2246
2247	/* Get the range details. */
2248	RTGCPHYS GCPhys;
2249	SSMR3GetGCPhys(pSSM, &GCPhys);
2250	RTGCPHYS GCPhysLast;
2251	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2252	RTGCPHYS cb;
2253	SSMR3GetGCPhys(pSSM, &cb);
2254	uint8_t fHaveBits;
2255	rc = SSMR3GetU8(pSSM, &fHaveBits);
2256	if (RT_FAILURE(rc))
2257	return rc;
2258	if (fHaveBits & ~1)
2259	{
2260	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2261	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2262	}
2263	size_t cchDesc = 0;
2264	char szDesc[256];
2265	szDesc[0] = '\0';
2266	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2267	{
2268	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2269	if (RT_FAILURE(rc))
2270	return rc;
2271	/* Since we've modified the description strings in r45878, only compare
2272	them if the saved state is more recent. */
2273	if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2274	cchDesc = strlen(szDesc);
2275	}
2276
2277	/*
2278	* Match it up with the current range.
2279	*
2280	* Note there is a hack for dealing with the high BIOS mapping
2281	* in the old saved state format, this means we might not have
2282	* a 1:1 match on success.
2283	*/
2284	if ( ( GCPhys != pRam->GCPhys
2285	\|\| GCPhysLast != pRam->GCPhysLast
2286	\|\| cb != pRam->cb
2287	\|\| ( cchDesc
2288	&& strcmp(szDesc, pRam->pszDesc)) )
2289	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2290	&& ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2291	\|\| GCPhys != UINT32_C(0xfff80000)
2292	\|\| GCPhysLast != UINT32_C(0xffffffff)
2293	\|\| pRam->GCPhysLast != GCPhysLast
2294	\|\| pRam->GCPhys < GCPhys
2295	\|\| !fHaveBits)
2296	)
2297	{
2298	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2299	"State : %RGp-%RGp %RGp bytes %s %s\n",
2300	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2301	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2302	/*
2303	* If we're loading a state for debugging purpose, don't make a fuss if
2304	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2305	*/
2306	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2307	\|\| GCPhys < 8 * _1M)
2308	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2309	N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2310	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2311	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2312
2313	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2314	continue;
2315	}
2316
2317	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2318	if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2319	{
2320	/*
2321	* Load the pages one by one.
2322	*/
2323	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2324	{
2325	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2326	PPGMPAGE pPage = &pRam->aPages[iPage];
2327	uint8_t uType;
2328	rc = SSMR3GetU8(pSSM, &uType);
2329	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2330	if (uType == PGMPAGETYPE_ROM_SHADOW)
2331	rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2332	else
2333	rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2334	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2335	}
2336	}
2337	else
2338	{
2339	/*
2340	* Old format.
2341	*/
2342
2343	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2344	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2345	uint32_t fFlags = 0;
2346	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2347	{
2348	uint16_t u16Flags;
2349	rc = SSMR3GetU16(pSSM, &u16Flags);
2350	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2351	fFlags \|= u16Flags;
2352	}
2353
2354	/* Load the bits */
2355	if ( !fHaveBits
2356	&& GCPhysLast < UINT32_C(0xe0000000))
2357	{
2358	/*
2359	* Dynamic chunks.
2360	*/
2361	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2362	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2363	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2364	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2365
2366	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2367	{
2368	uint8_t fPresent;
2369	rc = SSMR3GetU8(pSSM, &fPresent);
2370	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2371	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2372	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2373	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2374
2375	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2376	{
2377	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2378	PPGMPAGE pPage = &pRam->aPages[iPage];
2379	if (fPresent)
2380	{
2381	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2382	rc = pgmR3LoadPageToDevNullOld(pSSM);
2383	else
2384	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2385	}
2386	else
2387	rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2388	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2389	}
2390	}
2391	}
2392	else if (pRam->pvR3)
2393	{
2394	/*
2395	* MMIO2.
2396	*/
2397	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2398	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2399	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2400	AssertLogRelMsgReturn(pRam->pvR3,
2401	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2402	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2403
2404	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2405	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2406	}
2407	else if (GCPhysLast < UINT32_C(0xfff80000))
2408	{
2409	/*
2410	* PCI MMIO, no pages saved.
2411	*/
2412	}
2413	else
2414	{
2415	/*
2416	* Load the 0xfff80000..0xffffffff BIOS range.
2417	* It starts with X reserved pages that we have to skip over since
2418	* the RAMRANGE create by the new code won't include those.
2419	*/
2420	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2421	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2422	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2423	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2424	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2425	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2426	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2427
2428	/* Skip wasted reserved pages before the ROM. */
2429	while (GCPhys < pRam->GCPhys)
2430	{
2431	rc = pgmR3LoadPageToDevNullOld(pSSM);
2432	GCPhys += PAGE_SIZE;
2433	}
2434
2435	/* Load the bios pages. */
2436	cPages = pRam->cb >> PAGE_SHIFT;
2437	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2438	{
2439	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2440	PPGMPAGE pPage = &pRam->aPages[iPage];
2441
2442	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2443	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2444	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2445	rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2446	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2447	}
2448	}
2449	}
2450	}
2451
2452	return VINF_SUCCESS;
2453	}
2454
2455
2456	/**
2457	* Worker for pgmR3Load and pgmR3LoadLocked.
2458	*
2459	* @returns VBox status code.
2460	*
2461	* @param pVM The VM handle.
2462	* @param pSSM The SSM handle.
2463	* @param uVersion The saved state version.
2464	*
2465	* @todo This needs splitting up if more record types or code twists are
2466	* added...
2467	*/
2468	static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2469	{
2470	/*
2471	* Process page records until we hit the terminator.
2472	*/
2473	RTGCPHYS GCPhys = NIL_RTGCPHYS;
2474	PPGMRAMRANGE pRamHint = NULL;
2475	uint8_t id = UINT8_MAX;
2476	uint32_t iPage = UINT32_MAX - 10;
2477	PPGMROMRANGE pRom = NULL;
2478	PPGMMMIO2RANGE pMmio2 = NULL;
2479	for (;;)
2480	{
2481	/*
2482	* Get the record type and flags.
2483	*/
2484	uint8_t u8;
2485	int rc = SSMR3GetU8(pSSM, &u8);
2486	if (RT_FAILURE(rc))
2487	return rc;
2488	if (u8 == PGM_STATE_REC_END)
2489	return VINF_SUCCESS;
2490	AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2491	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2492	{
2493	/*
2494	* RAM page.
2495	*/
2496	case PGM_STATE_REC_RAM_ZERO:
2497	case PGM_STATE_REC_RAM_RAW:
2498	{
2499	/*
2500	* Get the address and resolve it into a page descriptor.
2501	*/
2502	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2503	GCPhys += PAGE_SIZE;
2504	else
2505	{
2506	rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2507	if (RT_FAILURE(rc))
2508	return rc;
2509	}
2510	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2511
2512	PPGMPAGE pPage;
2513	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pPage, &pRamHint);
2514	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2515
2516	/*
2517	* Take action according to the record type.
2518	*/
2519	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2520	{
2521	case PGM_STATE_REC_RAM_ZERO:
2522	{
2523	if (PGM_PAGE_IS_ZERO(pPage))
2524	break;
2525	/** @todo implement zero page replacing. */
2526	AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_INTERNAL_ERROR_5);
2527	void *pvDstPage;
2528	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2529	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2530	ASMMemZeroPage(pvDstPage);
2531	break;
2532	}
2533
2534	case PGM_STATE_REC_RAM_RAW:
2535	{
2536	void *pvDstPage;
2537	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage);
2538	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2539	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2540	if (RT_FAILURE(rc))
2541	return rc;
2542	break;
2543	}
2544
2545	default:
2546	AssertMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2547	}
2548	id = UINT8_MAX;
2549	break;
2550	}
2551
2552	/*
2553	* MMIO2 page.
2554	*/
2555	case PGM_STATE_REC_MMIO2_RAW:
2556	case PGM_STATE_REC_MMIO2_ZERO:
2557	{
2558	/*
2559	* Get the ID + page number and resolved that into a MMIO2 page.
2560	*/
2561	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2562	iPage++;
2563	else
2564	{
2565	SSMR3GetU8(pSSM, &id);
2566	rc = SSMR3GetU32(pSSM, &iPage);
2567	if (RT_FAILURE(rc))
2568	return rc;
2569	}
2570	if ( !pMmio2
2571	\|\| pMmio2->idSavedState != id)
2572	{
2573	for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2574	if (pMmio2->idSavedState == id)
2575	break;
2576	AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2577	}
2578	AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_INTERNAL_ERROR);
2579	void pvDstPage = (uint8_t )pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2580
2581	/*
2582	* Load the page bits.
2583	*/
2584	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2585	ASMMemZeroPage(pvDstPage);
2586	else
2587	{
2588	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2589	if (RT_FAILURE(rc))
2590	return rc;
2591	}
2592	GCPhys = NIL_RTGCPHYS;
2593	break;
2594	}
2595
2596	/*
2597	* ROM pages.
2598	*/
2599	case PGM_STATE_REC_ROM_VIRGIN:
2600	case PGM_STATE_REC_ROM_SHW_RAW:
2601	case PGM_STATE_REC_ROM_SHW_ZERO:
2602	case PGM_STATE_REC_ROM_PROT:
2603	{
2604	/*
2605	* Get the ID + page number and resolved that into a ROM page descriptor.
2606	*/
2607	if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2608	iPage++;
2609	else
2610	{
2611	SSMR3GetU8(pSSM, &id);
2612	rc = SSMR3GetU32(pSSM, &iPage);
2613	if (RT_FAILURE(rc))
2614	return rc;
2615	}
2616	if ( !pRom
2617	\|\| pRom->idSavedState != id)
2618	{
2619	for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2620	if (pRom->idSavedState == id)
2621	break;
2622	AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_INTERNAL_ERROR);
2623	}
2624	AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_INTERNAL_ERROR);
2625	PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2626	GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2627
2628	/*
2629	* Get and set the protection.
2630	*/
2631	uint8_t u8Prot;
2632	rc = SSMR3GetU8(pSSM, &u8Prot);
2633	if (RT_FAILURE(rc))
2634	return rc;
2635	PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2636	AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_INTERNAL_ERROR);
2637
2638	if (enmProt != pRomPage->enmProt)
2639	{
2640	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2641	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2642	N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2643	GCPhys, enmProt, pRom->pszDesc);
2644	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2645	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2646	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2647	}
2648	if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2649	break; /* done */
2650
2651	/*
2652	* Get the right page descriptor.
2653	*/
2654	PPGMPAGE pRealPage;
2655	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2656	{
2657	case PGM_STATE_REC_ROM_VIRGIN:
2658	if (!PGMROMPROT_IS_ROM(enmProt))
2659	pRealPage = &pRomPage->Virgin;
2660	else
2661	pRealPage = NULL;
2662	break;
2663
2664	case PGM_STATE_REC_ROM_SHW_RAW:
2665	case PGM_STATE_REC_ROM_SHW_ZERO:
2666	if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2667	return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2668	N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2669	GCPhys, enmProt, pRom->pszDesc);
2670	if (PGMROMPROT_IS_ROM(enmProt))
2671	pRealPage = &pRomPage->Shadow;
2672	else
2673	pRealPage = NULL;
2674	break;
2675
2676	default: AssertLogRelFailedReturn(VERR_INTERNAL_ERROR); /* shut up gcc */
2677	}
2678	if (!pRealPage)
2679	{
2680	rc = pgmPhysGetPageWithHintEx(&pVM->pgm.s, GCPhys, &pRealPage, &pRamHint);
2681	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2682	}
2683
2684	/*
2685	* Make it writable and map it (if necessary).
2686	*/
2687	void *pvDstPage = NULL;
2688	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2689	{
2690	case PGM_STATE_REC_ROM_SHW_ZERO:
2691	if (PGM_PAGE_IS_ZERO(pRealPage))
2692	break;
2693	/** @todo implement zero page replacing. */
2694	/* fall thru */
2695	case PGM_STATE_REC_ROM_VIRGIN:
2696	case PGM_STATE_REC_ROM_SHW_RAW:
2697	{
2698	rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2699	AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2700	break;
2701	}
2702	}
2703
2704	/*
2705	* Load the bits.
2706	*/
2707	switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2708	{
2709	case PGM_STATE_REC_ROM_SHW_ZERO:
2710	if (pvDstPage)
2711	ASMMemZeroPage(pvDstPage);
2712	break;
2713
2714	case PGM_STATE_REC_ROM_VIRGIN:
2715	case PGM_STATE_REC_ROM_SHW_RAW:
2716	rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2717	if (RT_FAILURE(rc))
2718	return rc;
2719	break;
2720	}
2721	GCPhys = NIL_RTGCPHYS;
2722	break;
2723	}
2724
2725	/*
2726	* Unknown type.
2727	*/
2728	default:
2729	AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_INTERNAL_ERROR);
2730	}
2731	} /* forever */
2732	}
2733
2734
2735	/**
2736	* Worker for pgmR3Load.
2737	*
2738	* @returns VBox status code.
2739	*
2740	* @param pVM The VM handle.
2741	* @param pSSM The SSM handle.
2742	* @param uVersion The saved state version.
2743	*/
2744	static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2745	{
2746	PPGM pPGM = &pVM->pgm.s;
2747	int rc;
2748	uint32_t u32Sep;
2749
2750	/*
2751	* Load basic data (required / unaffected by relocation).
2752	*/
2753	if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2754	{
2755	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2756	AssertLogRelRCReturn(rc, rc);
2757
2758	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2759	{
2760	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2761	AssertLogRelRCReturn(rc, rc);
2762	}
2763	}
2764	else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2765	{
2766	AssertRelease(pVM->cCpus == 1);
2767
2768	PGMOLD pgmOld;
2769	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2770	AssertLogRelRCReturn(rc, rc);
2771
2772	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2773	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2774	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2775
2776	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2777	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2778	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2779	}
2780	else
2781	{
2782	AssertRelease(pVM->cCpus == 1);
2783
2784	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2785	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2786	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2787
2788	uint32_t cbRamSizeIgnored;
2789	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2790	if (RT_FAILURE(rc))
2791	return rc;
2792	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2793
2794	uint32_t u32 = 0;
2795	SSMR3GetUInt(pSSM, &u32);
2796	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2797	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2798	RTUINT uGuestMode;
2799	SSMR3GetUInt(pSSM, &uGuestMode);
2800	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2801
2802	/* check separator. */
2803	SSMR3GetU32(pSSM, &u32Sep);
2804	if (RT_FAILURE(rc))
2805	return rc;
2806	if (u32Sep != (uint32_t)~0)
2807	{
2808	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2809	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2810	}
2811	}
2812
2813	/*
2814	* The guest mappings.
2815	*/
2816	uint32_t i = 0;
2817	for (;; i++)
2818	{
2819	/* Check the seqence number / separator. */
2820	rc = SSMR3GetU32(pSSM, &u32Sep);
2821	if (RT_FAILURE(rc))
2822	return rc;
2823	if (u32Sep == ~0U)
2824	break;
2825	if (u32Sep != i)
2826	{
2827	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2828	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2829	}
2830
2831	/* get the mapping details. */
2832	char szDesc[256];
2833	szDesc[0] = '\0';
2834	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2835	if (RT_FAILURE(rc))
2836	return rc;
2837	RTGCPTR GCPtr;
2838	SSMR3GetGCPtr(pSSM, &GCPtr);
2839	RTGCPTR cPTs;
2840	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2841	if (RT_FAILURE(rc))
2842	return rc;
2843
2844	/* find matching range. */
2845	PPGMMAPPING pMapping;
2846	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2847	{
2848	if ( pMapping->cPTs == cPTs
2849	&& !strcmp(pMapping->pszDesc, szDesc))
2850	break;
2851	#ifdef DEBUG_sandervl
2852	if ( !strcmp(szDesc, "Hypervisor Memory Area")
2853	&& HWACCMIsEnabled(pVM))
2854	break;
2855	#endif
2856	}
2857	if (!pMapping)
2858	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)"),
2859	cPTs, szDesc, GCPtr);
2860
2861	/* relocate it. */
2862	if ( pMapping->GCPtr != GCPtr
2863	#ifdef DEBUG_sandervl
2864	&& !(!strcmp(szDesc, "Hypervisor Memory Area") && HWACCMIsEnabled(pVM))
2865	#endif
2866	)
2867	{
2868	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2869	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2870	}
2871	else
2872	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2873	}
2874
2875	/*
2876	* Load the RAM contents.
2877	*/
2878	if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
2879	{
2880	if (!pVM->pgm.s.LiveSave.fActive)
2881	{
2882	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2883	{
2884	rc = pgmR3LoadRamConfig(pVM, pSSM);
2885	if (RT_FAILURE(rc))
2886	return rc;
2887	}
2888	rc = pgmR3LoadRomRanges(pVM, pSSM);
2889	if (RT_FAILURE(rc))
2890	return rc;
2891	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2892	if (RT_FAILURE(rc))
2893	return rc;
2894	}
2895
2896	return pgmR3LoadMemory(pVM, pSSM, SSM_PASS_FINAL);
2897	}
2898	return pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
2899	}
2900
2901
2902	/**
2903	* Execute state load operation.
2904	*
2905	* @returns VBox status code.
2906	* @param pVM VM Handle.
2907	* @param pSSM SSM operation handle.
2908	* @param uVersion Data layout version.
2909	* @param uPass The data pass.
2910	*/
2911	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2912	{
2913	int rc;
2914	PPGM pPGM = &pVM->pgm.s;
2915
2916	/*
2917	* Validate version.
2918	*/
2919	if ( ( uPass != SSM_PASS_FINAL
2920	&& uVersion != PGM_SAVED_STATE_VERSION
2921	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2922	\|\| ( uVersion != PGM_SAVED_STATE_VERSION
2923	&& uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
2924	&& uVersion != PGM_SAVED_STATE_VERSION_3_0_0
2925	&& uVersion != PGM_SAVED_STATE_VERSION_2_2_2
2926	&& uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
2927	&& uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2928	)
2929	{
2930	AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
2931	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2932	}
2933
2934	/*
2935	* Do the loading while owning the lock because a bunch of the functions
2936	* we're using requires this.
2937	*/
2938	if (uPass != SSM_PASS_FINAL)
2939	{
2940	pgmLock(pVM);
2941	if (uPass != 0)
2942	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2943	else
2944	{
2945	pVM->pgm.s.LiveSave.fActive = true;
2946	if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
2947	rc = pgmR3LoadRamConfig(pVM, pSSM);
2948	else
2949	rc = VINF_SUCCESS;
2950	if (RT_SUCCESS(rc))
2951	rc = pgmR3LoadRomRanges(pVM, pSSM);
2952	if (RT_SUCCESS(rc))
2953	rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
2954	if (RT_SUCCESS(rc))
2955	rc = pgmR3LoadMemory(pVM, pSSM, uPass);
2956	}
2957	pgmUnlock(pVM);
2958	}
2959	else
2960	{
2961	pgmLock(pVM);
2962	rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
2963	pVM->pgm.s.LiveSave.fActive = false;
2964	pgmUnlock(pVM);
2965	if (RT_SUCCESS(rc))
2966	{
2967	/*
2968	* We require a full resync now.
2969	*/
2970	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2971	{
2972	PVMCPU pVCpu = &pVM->aCpus[i];
2973	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2974	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2975
2976	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2977	}
2978
2979	pgmR3HandlerPhysicalUpdateAll(pVM);
2980
2981	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2982	{
2983	PVMCPU pVCpu = &pVM->aCpus[i];
2984
2985	/*
2986	* Change the paging mode.
2987	*/
2988	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
2989
2990	/* Restore pVM->pgm.s.GCPhysCR3. */
2991	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2992	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
2993	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
2994	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2995	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
2996	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2997	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2998	else
2999	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3000	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3001	}
3002	}
3003	}
3004
3005	return rc;
3006	}
3007
3008
3009	/**
3010	* Registers the saved state callbacks with SSM.
3011	*
3012	* @returns VBox status code.
3013	* @param pVM Pointer to VM structure.
3014	* @param cbRam The RAM size.
3015	*/
3016	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3017	{
3018	return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3019	pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3020	NULL, pgmR3SaveExec, pgmR3SaveDone,
3021	pgmR3LoadPrep, pgmR3Load, NULL);
3022	}
3023

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

© 2023 Oracle
Contact – Privacy policy – Terms of Use