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source: vbox/trunk/src/VBox/VMM/PGMPhys.cpp@ 25414

Last change on this file since 25414 was 25230, checked in by vboxsync, 15 years ago

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1/* $Id: PGMPhys.cpp 25230 2009-12-08 11:11:45Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, Physical Memory Addressing.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PGM_PHYS
27#include <VBox/pgm.h>
28#include <VBox/iom.h>
29#include <VBox/mm.h>
30#include <VBox/stam.h>
31#include <VBox/rem.h>
32#include <VBox/pdmdev.h>
33#include "PGMInternal.h"
34#include <VBox/vm.h>
35#include <VBox/sup.h>
36#include <VBox/param.h>
37#include <VBox/err.h>
38#include <VBox/log.h>
39#include <iprt/assert.h>
40#include <iprt/alloc.h>
41#include <iprt/asm.h>
42#include <iprt/thread.h>
43#include <iprt/string.h>
44
45
46/*******************************************************************************
47* Defined Constants And Macros *
48*******************************************************************************/
49/** The number of pages to free in one batch. */
50#define PGMPHYS_FREE_PAGE_BATCH_SIZE 128
51
52
53/*******************************************************************************
54* Internal Functions *
55*******************************************************************************/
56static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser);
57static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
58
59
60/*
61 * PGMR3PhysReadU8-64
62 * PGMR3PhysWriteU8-64
63 */
64#define PGMPHYSFN_READNAME PGMR3PhysReadU8
65#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU8
66#define PGMPHYS_DATASIZE 1
67#define PGMPHYS_DATATYPE uint8_t
68#include "PGMPhysRWTmpl.h"
69
70#define PGMPHYSFN_READNAME PGMR3PhysReadU16
71#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU16
72#define PGMPHYS_DATASIZE 2
73#define PGMPHYS_DATATYPE uint16_t
74#include "PGMPhysRWTmpl.h"
75
76#define PGMPHYSFN_READNAME PGMR3PhysReadU32
77#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU32
78#define PGMPHYS_DATASIZE 4
79#define PGMPHYS_DATATYPE uint32_t
80#include "PGMPhysRWTmpl.h"
81
82#define PGMPHYSFN_READNAME PGMR3PhysReadU64
83#define PGMPHYSFN_WRITENAME PGMR3PhysWriteU64
84#define PGMPHYS_DATASIZE 8
85#define PGMPHYS_DATATYPE uint64_t
86#include "PGMPhysRWTmpl.h"
87
88
89/**
90 * EMT worker for PGMR3PhysReadExternal.
91 */
92static DECLCALLBACK(int) pgmR3PhysReadExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, void *pvBuf, size_t cbRead)
93{
94 PGMPhysRead(pVM, *pGCPhys, pvBuf, cbRead);
95 return VINF_SUCCESS;
96}
97
98
99/**
100 * Write to physical memory, external users.
101 *
102 * @returns VBox status code.
103 * @retval VINF_SUCCESS.
104 *
105 * @param pVM VM Handle.
106 * @param GCPhys Physical address to write to.
107 * @param pvBuf What to write.
108 * @param cbWrite How many bytes to write.
109 *
110 * @thread Any but EMTs.
111 */
112VMMR3DECL(int) PGMR3PhysReadExternal(PVM pVM, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
113{
114 VM_ASSERT_OTHER_THREAD(pVM);
115
116 AssertMsgReturn(cbRead > 0, ("don't even think about reading zero bytes!\n"), VINF_SUCCESS);
117 LogFlow(("PGMR3PhysReadExternal: %RGp %d\n", GCPhys, cbRead));
118
119 pgmLock(pVM);
120
121 /*
122 * Copy loop on ram ranges.
123 */
124 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
125 for (;;)
126 {
127 /* Find range. */
128 while (pRam && GCPhys > pRam->GCPhysLast)
129 pRam = pRam->CTX_SUFF(pNext);
130 /* Inside range or not? */
131 if (pRam && GCPhys >= pRam->GCPhys)
132 {
133 /*
134 * Must work our way thru this page by page.
135 */
136 RTGCPHYS off = GCPhys - pRam->GCPhys;
137 while (off < pRam->cb)
138 {
139 unsigned iPage = off >> PAGE_SHIFT;
140 PPGMPAGE pPage = &pRam->aPages[iPage];
141
142 /*
143 * If the page has an ALL access handler, we'll have to
144 * delegate the job to EMT.
145 */
146 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
147 {
148 pgmUnlock(pVM);
149
150 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysReadExternalEMT, 4,
151 pVM, &GCPhys, pvBuf, cbRead);
152 }
153 Assert(!PGM_PAGE_IS_MMIO(pPage));
154
155 /*
156 * Simple stuff, go ahead.
157 */
158 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
159 if (cb > cbRead)
160 cb = cbRead;
161 const void *pvSrc;
162 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, pRam->GCPhys + off, &pvSrc);
163 if (RT_SUCCESS(rc))
164 memcpy(pvBuf, pvSrc, cb);
165 else
166 {
167 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternalReadOnly failed on %RGp / %R[pgmpage] -> %Rrc\n",
168 pRam->GCPhys + off, pPage, rc));
169 memset(pvBuf, 0xff, cb);
170 }
171
172 /* next page */
173 if (cb >= cbRead)
174 {
175 pgmUnlock(pVM);
176 return VINF_SUCCESS;
177 }
178 cbRead -= cb;
179 off += cb;
180 GCPhys += cb;
181 pvBuf = (char *)pvBuf + cb;
182 } /* walk pages in ram range. */
183 }
184 else
185 {
186 LogFlow(("PGMPhysRead: Unassigned %RGp size=%u\n", GCPhys, cbRead));
187
188 /*
189 * Unassigned address space.
190 */
191 if (!pRam)
192 break;
193 size_t cb = pRam->GCPhys - GCPhys;
194 if (cb >= cbRead)
195 {
196 memset(pvBuf, 0xff, cbRead);
197 break;
198 }
199 memset(pvBuf, 0xff, cb);
200
201 cbRead -= cb;
202 pvBuf = (char *)pvBuf + cb;
203 GCPhys += cb;
204 }
205 } /* Ram range walk */
206
207 pgmUnlock(pVM);
208
209 return VINF_SUCCESS;
210}
211
212
213/**
214 * EMT worker for PGMR3PhysWriteExternal.
215 */
216static DECLCALLBACK(int) pgmR3PhysWriteExternalEMT(PVM pVM, PRTGCPHYS pGCPhys, const void *pvBuf, size_t cbWrite)
217{
218 /** @todo VERR_EM_NO_MEMORY */
219 PGMPhysWrite(pVM, *pGCPhys, pvBuf, cbWrite);
220 return VINF_SUCCESS;
221}
222
223
224/**
225 * Write to physical memory, external users.
226 *
227 * @returns VBox status code.
228 * @retval VINF_SUCCESS.
229 * @retval VERR_EM_NO_MEMORY.
230 *
231 * @param pVM VM Handle.
232 * @param GCPhys Physical address to write to.
233 * @param pvBuf What to write.
234 * @param cbWrite How many bytes to write.
235 * @param pszWho Who is writing. For tracking down who is writing
236 * after we've saved the state.
237 *
238 * @thread Any but EMTs.
239 */
240VMMDECL(int) PGMR3PhysWriteExternal(PVM pVM, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, const char *pszWho)
241{
242 VM_ASSERT_OTHER_THREAD(pVM);
243
244 AssertMsg(!pVM->pgm.s.fNoMorePhysWrites,
245 ("Calling PGMR3PhysWriteExternal after pgmR3Save()! GCPhys=%RGp cbWrite=%#x pszWho=%s\n",
246 GCPhys, cbWrite, pszWho));
247 AssertMsgReturn(cbWrite > 0, ("don't even think about writing zero bytes!\n"), VINF_SUCCESS);
248 LogFlow(("PGMR3PhysWriteExternal: %RGp %d\n", GCPhys, cbWrite));
249
250 pgmLock(pVM);
251
252 /*
253 * Copy loop on ram ranges, stop when we hit something difficult.
254 */
255 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
256 for (;;)
257 {
258 /* Find range. */
259 while (pRam && GCPhys > pRam->GCPhysLast)
260 pRam = pRam->CTX_SUFF(pNext);
261 /* Inside range or not? */
262 if (pRam && GCPhys >= pRam->GCPhys)
263 {
264 /*
265 * Must work our way thru this page by page.
266 */
267 RTGCPTR off = GCPhys - pRam->GCPhys;
268 while (off < pRam->cb)
269 {
270 RTGCPTR iPage = off >> PAGE_SHIFT;
271 PPGMPAGE pPage = &pRam->aPages[iPage];
272
273 /*
274 * Is the page problematic, we have to do the work on the EMT.
275 *
276 * Allocating writable pages and access handlers are
277 * problematic, write monitored pages are simple and can be
278 * dealth with here.
279 */
280 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
281 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
282 {
283 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
284 && !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
285 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
286 else
287 {
288 pgmUnlock(pVM);
289
290 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysWriteExternalEMT, 4,
291 pVM, &GCPhys, pvBuf, cbWrite);
292 }
293 }
294 Assert(!PGM_PAGE_IS_MMIO(pPage));
295
296 /*
297 * Simple stuff, go ahead.
298 */
299 size_t cb = PAGE_SIZE - (off & PAGE_OFFSET_MASK);
300 if (cb > cbWrite)
301 cb = cbWrite;
302 void *pvDst;
303 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, pRam->GCPhys + off, &pvDst);
304 if (RT_SUCCESS(rc))
305 memcpy(pvDst, pvBuf, cb);
306 else
307 AssertLogRelMsgFailed(("pgmPhysGCPhys2CCPtrInternal failed on %RGp / %R[pgmpage] -> %Rrc\n",
308 pRam->GCPhys + off, pPage, rc));
309
310 /* next page */
311 if (cb >= cbWrite)
312 {
313 pgmUnlock(pVM);
314 return VINF_SUCCESS;
315 }
316
317 cbWrite -= cb;
318 off += cb;
319 GCPhys += cb;
320 pvBuf = (const char *)pvBuf + cb;
321 } /* walk pages in ram range */
322 }
323 else
324 {
325 /*
326 * Unassigned address space, skip it.
327 */
328 if (!pRam)
329 break;
330 size_t cb = pRam->GCPhys - GCPhys;
331 if (cb >= cbWrite)
332 break;
333 cbWrite -= cb;
334 pvBuf = (const char *)pvBuf + cb;
335 GCPhys += cb;
336 }
337 } /* Ram range walk */
338
339 pgmUnlock(pVM);
340 return VINF_SUCCESS;
341}
342
343
344/**
345 * VMR3ReqCall worker for PGMR3PhysGCPhys2CCPtrExternal to make pages writable.
346 *
347 * @returns see PGMR3PhysGCPhys2CCPtrExternal
348 * @param pVM The VM handle.
349 * @param pGCPhys Pointer to the guest physical address.
350 * @param ppv Where to store the mapping address.
351 * @param pLock Where to store the lock.
352 */
353static DECLCALLBACK(int) pgmR3PhysGCPhys2CCPtrDelegated(PVM pVM, PRTGCPHYS pGCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
354{
355 /*
356 * Just hand it to PGMPhysGCPhys2CCPtr and check that it's not a page with
357 * an access handler after it succeeds.
358 */
359 int rc = pgmLock(pVM);
360 AssertRCReturn(rc, rc);
361
362 rc = PGMPhysGCPhys2CCPtr(pVM, *pGCPhys, ppv, pLock);
363 if (RT_SUCCESS(rc))
364 {
365 PPGMPAGEMAPTLBE pTlbe;
366 int rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, *pGCPhys, &pTlbe);
367 AssertFatalRC(rc2);
368 PPGMPAGE pPage = pTlbe->pPage;
369 if (PGM_PAGE_IS_MMIO(pPage))
370 {
371 PGMPhysReleasePageMappingLock(pVM, pLock);
372 rc = VERR_PGM_PHYS_PAGE_RESERVED;
373 }
374 else if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
375#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
376 || pgmPoolIsDirtyPage(pVM, *pGCPhys)
377#endif
378 )
379 {
380 /* We *must* flush any corresponding pgm pool page here, otherwise we'll
381 * not be informed about writes and keep bogus gst->shw mappings around.
382 */
383 pgmPoolFlushPageByGCPhys(pVM, *pGCPhys);
384 Assert(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage));
385 /** @todo r=bird: return VERR_PGM_PHYS_PAGE_RESERVED here if it still has
386 * active handlers, see the PGMR3PhysGCPhys2CCPtrExternal docs. */
387 }
388 }
389
390 pgmUnlock(pVM);
391 return rc;
392}
393
394
395/**
396 * Requests the mapping of a guest page into ring-3, external threads.
397 *
398 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
399 * release it.
400 *
401 * This API will assume your intention is to write to the page, and will
402 * therefore replace shared and zero pages. If you do not intend to modify the
403 * page, use the PGMR3PhysGCPhys2CCPtrReadOnlyExternal() API.
404 *
405 * @returns VBox status code.
406 * @retval VINF_SUCCESS on success.
407 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
408 * backing or if the page has any active access handlers. The caller
409 * must fall back on using PGMR3PhysWriteExternal.
410 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
411 *
412 * @param pVM The VM handle.
413 * @param GCPhys The guest physical address of the page that should be mapped.
414 * @param ppv Where to store the address corresponding to GCPhys.
415 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
416 *
417 * @remark Avoid calling this API from within critical sections (other than the
418 * PGM one) because of the deadlock risk when we have to delegating the
419 * task to an EMT.
420 * @thread Any.
421 */
422VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrExternal(PVM pVM, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock)
423{
424 AssertPtr(ppv);
425 AssertPtr(pLock);
426
427 Assert(VM_IS_EMT(pVM) || !PGMIsLockOwner(pVM));
428
429 int rc = pgmLock(pVM);
430 AssertRCReturn(rc, rc);
431
432 /*
433 * Query the Physical TLB entry for the page (may fail).
434 */
435 PPGMPAGEMAPTLBE pTlbe;
436 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
437 if (RT_SUCCESS(rc))
438 {
439 PPGMPAGE pPage = pTlbe->pPage;
440 if (PGM_PAGE_IS_MMIO(pPage))
441 rc = VERR_PGM_PHYS_PAGE_RESERVED;
442 else
443 {
444 /*
445 * If the page is shared, the zero page, or being write monitored
446 * it must be converted to an page that's writable if possible.
447 * We can only deal with write monitored pages here, the rest have
448 * to be on an EMT.
449 */
450 if ( PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
451 || PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
452#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
453 || pgmPoolIsDirtyPage(pVM, GCPhys)
454#endif
455 )
456 {
457 if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
458 && !PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage)
459#ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
460 && !pgmPoolIsDirtyPage(pVM, GCPhys)
461#endif
462 )
463 pgmPhysPageMakeWriteMonitoredWritable(pVM, pPage);
464 else
465 {
466 pgmUnlock(pVM);
467
468 return VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)pgmR3PhysGCPhys2CCPtrDelegated, 4,
469 pVM, &GCPhys, ppv, pLock);
470 }
471 }
472
473 /*
474 * Now, just perform the locking and calculate the return address.
475 */
476 PPGMPAGEMAP pMap = pTlbe->pMap;
477 if (pMap)
478 pMap->cRefs++;
479
480 unsigned cLocks = PGM_PAGE_GET_WRITE_LOCKS(pPage);
481 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
482 {
483 if (cLocks == 0)
484 pVM->pgm.s.cWriteLockedPages++;
485 PGM_PAGE_INC_WRITE_LOCKS(pPage);
486 }
487 else if (cLocks != PGM_PAGE_GET_WRITE_LOCKS(pPage))
488 {
489 PGM_PAGE_INC_WRITE_LOCKS(pPage);
490 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent write locked state!\n", GCPhys, pPage));
491 if (pMap)
492 pMap->cRefs++; /* Extra ref to prevent it from going away. */
493 }
494
495 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
496 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_WRITE;
497 pLock->pvMap = pMap;
498 }
499 }
500
501 pgmUnlock(pVM);
502 return rc;
503}
504
505
506/**
507 * Requests the mapping of a guest page into ring-3, external threads.
508 *
509 * When you're done with the page, call PGMPhysReleasePageMappingLock() ASAP to
510 * release it.
511 *
512 * @returns VBox status code.
513 * @retval VINF_SUCCESS on success.
514 * @retval VERR_PGM_PHYS_PAGE_RESERVED it it's a valid page but has no physical
515 * backing or if the page as an active ALL access handler. The caller
516 * must fall back on using PGMPhysRead.
517 * @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
518 *
519 * @param pVM The VM handle.
520 * @param GCPhys The guest physical address of the page that should be mapped.
521 * @param ppv Where to store the address corresponding to GCPhys.
522 * @param pLock Where to store the lock information that PGMPhysReleasePageMappingLock needs.
523 *
524 * @remark Avoid calling this API from within critical sections (other than
525 * the PGM one) because of the deadlock risk.
526 * @thread Any.
527 */
528VMMR3DECL(int) PGMR3PhysGCPhys2CCPtrReadOnlyExternal(PVM pVM, RTGCPHYS GCPhys, void const **ppv, PPGMPAGEMAPLOCK pLock)
529{
530 int rc = pgmLock(pVM);
531 AssertRCReturn(rc, rc);
532
533 /*
534 * Query the Physical TLB entry for the page (may fail).
535 */
536 PPGMPAGEMAPTLBE pTlbe;
537 rc = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
538 if (RT_SUCCESS(rc))
539 {
540 PPGMPAGE pPage = pTlbe->pPage;
541#if 1
542 /* MMIO pages doesn't have any readable backing. */
543 if (PGM_PAGE_IS_MMIO(pPage))
544 rc = VERR_PGM_PHYS_PAGE_RESERVED;
545#else
546 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
547 rc = VERR_PGM_PHYS_PAGE_RESERVED;
548#endif
549 else
550 {
551 /*
552 * Now, just perform the locking and calculate the return address.
553 */
554 PPGMPAGEMAP pMap = pTlbe->pMap;
555 if (pMap)
556 pMap->cRefs++;
557
558 unsigned cLocks = PGM_PAGE_GET_READ_LOCKS(pPage);
559 if (RT_LIKELY(cLocks < PGM_PAGE_MAX_LOCKS - 1))
560 {
561 if (cLocks == 0)
562 pVM->pgm.s.cReadLockedPages++;
563 PGM_PAGE_INC_READ_LOCKS(pPage);
564 }
565 else if (cLocks != PGM_PAGE_GET_READ_LOCKS(pPage))
566 {
567 PGM_PAGE_INC_READ_LOCKS(pPage);
568 AssertMsgFailed(("%RGp / %R[pgmpage] is entering permanent readonly locked state!\n", GCPhys, pPage));
569 if (pMap)
570 pMap->cRefs++; /* Extra ref to prevent it from going away. */
571 }
572
573 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
574 pLock->uPageAndType = (uintptr_t)pPage | PGMPAGEMAPLOCK_TYPE_READ;
575 pLock->pvMap = pMap;
576 }
577 }
578
579 pgmUnlock(pVM);
580 return rc;
581}
582
583
584/**
585 * Relinks the RAM ranges using the pSelfRC and pSelfR0 pointers.
586 *
587 * Called when anything was relocated.
588 *
589 * @param pVM Pointer to the shared VM structure.
590 */
591void pgmR3PhysRelinkRamRanges(PVM pVM)
592{
593 PPGMRAMRANGE pCur;
594
595#ifdef VBOX_STRICT
596 for (pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
597 {
598 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfR0 == MMHyperCCToR0(pVM, pCur));
599 Assert((pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pCur->pSelfRC == MMHyperCCToRC(pVM, pCur));
600 Assert((pCur->GCPhys & PAGE_OFFSET_MASK) == 0);
601 Assert((pCur->GCPhysLast & PAGE_OFFSET_MASK) == PAGE_OFFSET_MASK);
602 Assert((pCur->cb & PAGE_OFFSET_MASK) == 0);
603 Assert(pCur->cb == pCur->GCPhysLast - pCur->GCPhys + 1);
604 for (PPGMRAMRANGE pCur2 = pVM->pgm.s.pRamRangesR3; pCur2; pCur2 = pCur2->pNextR3)
605 Assert( pCur2 == pCur
606 || strcmp(pCur2->pszDesc, pCur->pszDesc)); /** @todo fix MMIO ranges!! */
607 }
608#endif
609
610 pCur = pVM->pgm.s.pRamRangesR3;
611 if (pCur)
612 {
613 pVM->pgm.s.pRamRangesR0 = pCur->pSelfR0;
614 pVM->pgm.s.pRamRangesRC = pCur->pSelfRC;
615
616 for (; pCur->pNextR3; pCur = pCur->pNextR3)
617 {
618 pCur->pNextR0 = pCur->pNextR3->pSelfR0;
619 pCur->pNextRC = pCur->pNextR3->pSelfRC;
620 }
621
622 Assert(pCur->pNextR0 == NIL_RTR0PTR);
623 Assert(pCur->pNextRC == NIL_RTRCPTR);
624 }
625 else
626 {
627 Assert(pVM->pgm.s.pRamRangesR0 == NIL_RTR0PTR);
628 Assert(pVM->pgm.s.pRamRangesRC == NIL_RTRCPTR);
629 }
630 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
631}
632
633
634/**
635 * Links a new RAM range into the list.
636 *
637 * @param pVM Pointer to the shared VM structure.
638 * @param pNew Pointer to the new list entry.
639 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
640 */
641static void pgmR3PhysLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, PPGMRAMRANGE pPrev)
642{
643 AssertMsg(pNew->pszDesc, ("%RGp-%RGp\n", pNew->GCPhys, pNew->GCPhysLast));
644 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfR0 == MMHyperCCToR0(pVM, pNew));
645 Assert((pNew->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pNew->pSelfRC == MMHyperCCToRC(pVM, pNew));
646
647 pgmLock(pVM);
648
649 PPGMRAMRANGE pRam = pPrev ? pPrev->pNextR3 : pVM->pgm.s.pRamRangesR3;
650 pNew->pNextR3 = pRam;
651 pNew->pNextR0 = pRam ? pRam->pSelfR0 : NIL_RTR0PTR;
652 pNew->pNextRC = pRam ? pRam->pSelfRC : NIL_RTRCPTR;
653
654 if (pPrev)
655 {
656 pPrev->pNextR3 = pNew;
657 pPrev->pNextR0 = pNew->pSelfR0;
658 pPrev->pNextRC = pNew->pSelfRC;
659 }
660 else
661 {
662 pVM->pgm.s.pRamRangesR3 = pNew;
663 pVM->pgm.s.pRamRangesR0 = pNew->pSelfR0;
664 pVM->pgm.s.pRamRangesRC = pNew->pSelfRC;
665 }
666 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
667 pgmUnlock(pVM);
668}
669
670
671/**
672 * Unlink an existing RAM range from the list.
673 *
674 * @param pVM Pointer to the shared VM structure.
675 * @param pRam Pointer to the new list entry.
676 * @param pPrev Pointer to the previous list entry. If NULL, insert as head.
677 */
678static void pgmR3PhysUnlinkRamRange2(PVM pVM, PPGMRAMRANGE pRam, PPGMRAMRANGE pPrev)
679{
680 Assert(pPrev ? pPrev->pNextR3 == pRam : pVM->pgm.s.pRamRangesR3 == pRam);
681 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfR0 == MMHyperCCToR0(pVM, pRam));
682 Assert((pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING) || pRam->pSelfRC == MMHyperCCToRC(pVM, pRam));
683
684 pgmLock(pVM);
685
686 PPGMRAMRANGE pNext = pRam->pNextR3;
687 if (pPrev)
688 {
689 pPrev->pNextR3 = pNext;
690 pPrev->pNextR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
691 pPrev->pNextRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
692 }
693 else
694 {
695 Assert(pVM->pgm.s.pRamRangesR3 == pRam);
696 pVM->pgm.s.pRamRangesR3 = pNext;
697 pVM->pgm.s.pRamRangesR0 = pNext ? pNext->pSelfR0 : NIL_RTR0PTR;
698 pVM->pgm.s.pRamRangesRC = pNext ? pNext->pSelfRC : NIL_RTRCPTR;
699 }
700 ASMAtomicIncU32(&pVM->pgm.s.idRamRangesGen);
701 pgmUnlock(pVM);
702}
703
704
705/**
706 * Unlink an existing RAM range from the list.
707 *
708 * @param pVM Pointer to the shared VM structure.
709 * @param pRam Pointer to the new list entry.
710 */
711static void pgmR3PhysUnlinkRamRange(PVM pVM, PPGMRAMRANGE pRam)
712{
713 pgmLock(pVM);
714
715 /* find prev. */
716 PPGMRAMRANGE pPrev = NULL;
717 PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3;
718 while (pCur != pRam)
719 {
720 pPrev = pCur;
721 pCur = pCur->pNextR3;
722 }
723 AssertFatal(pCur);
724
725 pgmR3PhysUnlinkRamRange2(pVM, pRam, pPrev);
726 pgmUnlock(pVM);
727}
728
729
730/**
731 * Frees a range of pages, replacing them with ZERO pages of the specified type.
732 *
733 * @returns VBox status code.
734 * @param pVM The VM handle.
735 * @param pRam The RAM range in which the pages resides.
736 * @param GCPhys The address of the first page.
737 * @param GCPhysLast The address of the last page.
738 * @param uType The page type to replace then with.
739 */
740static int pgmR3PhysFreePageRange(PVM pVM, PPGMRAMRANGE pRam, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast, uint8_t uType)
741{
742 uint32_t cPendingPages = 0;
743 PGMMFREEPAGESREQ pReq;
744 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
745 AssertLogRelRCReturn(rc, rc);
746
747 /* Itegerate the pages. */
748 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
749 uint32_t cPagesLeft = ((GCPhysLast - GCPhys) >> PAGE_SHIFT) + 1;
750 while (cPagesLeft-- > 0)
751 {
752 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
753 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
754
755 PGM_PAGE_SET_TYPE(pPageDst, uType);
756
757 GCPhys += PAGE_SIZE;
758 pPageDst++;
759 }
760
761 if (cPendingPages)
762 {
763 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
764 AssertLogRelRCReturn(rc, rc);
765 }
766 GMMR3FreePagesCleanup(pReq);
767
768 return rc;
769}
770
771
772/**
773 * PGMR3PhysRegisterRam worker that initializes and links a RAM range.
774 *
775 * @param pVM The VM handle.
776 * @param pNew The new RAM range.
777 * @param GCPhys The address of the RAM range.
778 * @param GCPhysLast The last address of the RAM range.
779 * @param RCPtrNew The RC address if the range is floating. NIL_RTRCPTR
780 * if in HMA.
781 * @param R0PtrNew Ditto for R0.
782 * @param pszDesc The description.
783 * @param pPrev The previous RAM range (for linking).
784 */
785static void pgmR3PhysInitAndLinkRamRange(PVM pVM, PPGMRAMRANGE pNew, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast,
786 RTRCPTR RCPtrNew, RTR0PTR R0PtrNew, const char *pszDesc, PPGMRAMRANGE pPrev)
787{
788 /*
789 * Initialize the range.
790 */
791 pNew->pSelfR0 = R0PtrNew != NIL_RTR0PTR ? R0PtrNew : MMHyperCCToR0(pVM, pNew);
792 pNew->pSelfRC = RCPtrNew != NIL_RTRCPTR ? RCPtrNew : MMHyperCCToRC(pVM, pNew);
793 pNew->GCPhys = GCPhys;
794 pNew->GCPhysLast = GCPhysLast;
795 pNew->cb = GCPhysLast - GCPhys + 1;
796 pNew->pszDesc = pszDesc;
797 pNew->fFlags = RCPtrNew != NIL_RTRCPTR ? PGM_RAM_RANGE_FLAGS_FLOATING : 0;
798 pNew->pvR3 = NULL;
799 pNew->paLSPages = NULL;
800
801 uint32_t const cPages = pNew->cb >> PAGE_SHIFT;
802 RTGCPHYS iPage = cPages;
803 while (iPage-- > 0)
804 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_RAM);
805
806 /* Update the page count stats. */
807 pVM->pgm.s.cZeroPages += cPages;
808 pVM->pgm.s.cAllPages += cPages;
809
810 /*
811 * Link it.
812 */
813 pgmR3PhysLinkRamRange(pVM, pNew, pPrev);
814}
815
816
817/**
818 * Relocate a floating RAM range.
819 *
820 * @copydoc FNPGMRELOCATE.
821 */
822static DECLCALLBACK(bool) pgmR3PhysRamRangeRelocate(PVM pVM, RTGCPTR GCPtrOld, RTGCPTR GCPtrNew, PGMRELOCATECALL enmMode, void *pvUser)
823{
824 PPGMRAMRANGE pRam = (PPGMRAMRANGE)pvUser;
825 Assert(pRam->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING);
826 Assert(pRam->pSelfRC == GCPtrOld + PAGE_SIZE);
827
828 switch (enmMode)
829 {
830 case PGMRELOCATECALL_SUGGEST:
831 return true;
832 case PGMRELOCATECALL_RELOCATE:
833 {
834 /* Update myself and then relink all the ranges. */
835 pgmLock(pVM);
836 pRam->pSelfRC = (RTRCPTR)(GCPtrNew + PAGE_SIZE);
837 pgmR3PhysRelinkRamRanges(pVM);
838 pgmUnlock(pVM);
839 return true;
840 }
841
842 default:
843 AssertFailedReturn(false);
844 }
845}
846
847
848/**
849 * PGMR3PhysRegisterRam worker that registers a high chunk.
850 *
851 * @returns VBox status code.
852 * @param pVM The VM handle.
853 * @param GCPhys The address of the RAM.
854 * @param cRamPages The number of RAM pages to register.
855 * @param cbChunk The size of the PGMRAMRANGE guest mapping.
856 * @param iChunk The chunk number.
857 * @param pszDesc The RAM range description.
858 * @param ppPrev Previous RAM range pointer. In/Out.
859 */
860static int pgmR3PhysRegisterHighRamChunk(PVM pVM, RTGCPHYS GCPhys, uint32_t cRamPages,
861 uint32_t cbChunk, uint32_t iChunk, const char *pszDesc,
862 PPGMRAMRANGE *ppPrev)
863{
864 const char *pszDescChunk = iChunk == 0
865 ? pszDesc
866 : MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s (#%u)", pszDesc, iChunk + 1);
867 AssertReturn(pszDescChunk, VERR_NO_MEMORY);
868
869 /*
870 * Allocate memory for the new chunk.
871 */
872 size_t const cChunkPages = RT_ALIGN_Z(RT_UOFFSETOF(PGMRAMRANGE, aPages[cRamPages]), PAGE_SIZE) >> PAGE_SHIFT;
873 PSUPPAGE paChunkPages = (PSUPPAGE)RTMemTmpAllocZ(sizeof(SUPPAGE) * cChunkPages);
874 AssertReturn(paChunkPages, VERR_NO_TMP_MEMORY);
875 RTR0PTR R0PtrChunk = NIL_RTR0PTR;
876 void *pvChunk = NULL;
877 int rc = SUPR3PageAllocEx(cChunkPages, 0 /*fFlags*/, &pvChunk,
878#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
879 VMMIsHwVirtExtForced(pVM) ? &R0PtrChunk : NULL,
880#else
881 NULL,
882#endif
883 paChunkPages);
884 if (RT_SUCCESS(rc))
885 {
886#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
887 if (!VMMIsHwVirtExtForced(pVM))
888 R0PtrChunk = NIL_RTR0PTR;
889#else
890 R0PtrChunk = (uintptr_t)pvChunk;
891#endif
892 memset(pvChunk, 0, cChunkPages << PAGE_SHIFT);
893
894 PPGMRAMRANGE pNew = (PPGMRAMRANGE)pvChunk;
895
896 /*
897 * Create a mapping and map the pages into it.
898 * We push these in below the HMA.
899 */
900 RTGCPTR GCPtrChunkMap = pVM->pgm.s.GCPtrPrevRamRangeMapping - cbChunk;
901 rc = PGMR3MapPT(pVM, GCPtrChunkMap, cbChunk, 0 /*fFlags*/, pgmR3PhysRamRangeRelocate, pNew, pszDescChunk);
902 if (RT_SUCCESS(rc))
903 {
904 pVM->pgm.s.GCPtrPrevRamRangeMapping = GCPtrChunkMap;
905
906 RTGCPTR const GCPtrChunk = GCPtrChunkMap + PAGE_SIZE;
907 RTGCPTR GCPtrPage = GCPtrChunk;
908 for (uint32_t iPage = 0; iPage < cChunkPages && RT_SUCCESS(rc); iPage++, GCPtrPage += PAGE_SIZE)
909 rc = PGMMap(pVM, GCPtrPage, paChunkPages[iPage].Phys, PAGE_SIZE, 0);
910 if (RT_SUCCESS(rc))
911 {
912 /*
913 * Ok, init and link the range.
914 */
915 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhys + ((RTGCPHYS)cRamPages << PAGE_SHIFT) - 1,
916 (RTRCPTR)GCPtrChunk, R0PtrChunk, pszDescChunk, *ppPrev);
917 *ppPrev = pNew;
918 }
919 }
920
921 if (RT_FAILURE(rc))
922 SUPR3PageFreeEx(pvChunk, cChunkPages);
923 }
924
925 RTMemTmpFree(paChunkPages);
926 return rc;
927}
928
929
930/**
931 * Sets up a range RAM.
932 *
933 * This will check for conflicting registrations, make a resource
934 * reservation for the memory (with GMM), and setup the per-page
935 * tracking structures (PGMPAGE).
936 *
937 * @returns VBox stutus code.
938 * @param pVM Pointer to the shared VM structure.
939 * @param GCPhys The physical address of the RAM.
940 * @param cb The size of the RAM.
941 * @param pszDesc The description - not copied, so, don't free or change it.
942 */
943VMMR3DECL(int) PGMR3PhysRegisterRam(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, const char *pszDesc)
944{
945 /*
946 * Validate input.
947 */
948 Log(("PGMR3PhysRegisterRam: GCPhys=%RGp cb=%RGp pszDesc=%s\n", GCPhys, cb, pszDesc));
949 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
950 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
951 AssertReturn(cb > 0, VERR_INVALID_PARAMETER);
952 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
953 AssertMsgReturn(GCPhysLast > GCPhys, ("The range wraps! GCPhys=%RGp cb=%RGp\n", GCPhys, cb), VERR_INVALID_PARAMETER);
954 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
955 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
956
957 pgmLock(pVM);
958
959 /*
960 * Find range location and check for conflicts.
961 * (We don't lock here because the locking by EMT is only required on update.)
962 */
963 PPGMRAMRANGE pPrev = NULL;
964 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
965 while (pRam && GCPhysLast >= pRam->GCPhys)
966 {
967 if ( GCPhysLast >= pRam->GCPhys
968 && GCPhys <= pRam->GCPhysLast)
969 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
970 GCPhys, GCPhysLast, pszDesc,
971 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
972 VERR_PGM_RAM_CONFLICT);
973
974 /* next */
975 pPrev = pRam;
976 pRam = pRam->pNextR3;
977 }
978
979 /*
980 * Register it with GMM (the API bitches).
981 */
982 const RTGCPHYS cPages = cb >> PAGE_SHIFT;
983 int rc = MMR3IncreaseBaseReservation(pVM, cPages);
984 if (RT_FAILURE(rc))
985 {
986 pgmUnlock(pVM);
987 return rc;
988 }
989
990 if ( GCPhys >= _4G
991 && cPages > 256)
992 {
993 /*
994 * The PGMRAMRANGE structures for the high memory can get very big.
995 * In order to avoid SUPR3PageAllocEx allocation failures due to the
996 * allocation size limit there and also to avoid being unable to find
997 * guest mapping space for them, we split this memory up into 4MB in
998 * (potential) raw-mode configs and 16MB chunks in forced AMD-V/VT-x
999 * mode.
1000 *
1001 * The first and last page of each mapping are guard pages and marked
1002 * not-present. So, we've got 4186112 and 16769024 bytes available for
1003 * the PGMRAMRANGE structure.
1004 *
1005 * Note! The sizes used here will influence the saved state.
1006 */
1007 uint32_t cbChunk;
1008 uint32_t cPagesPerChunk;
1009 if (VMMIsHwVirtExtForced(pVM))
1010 {
1011 cbChunk = 16U*_1M;
1012 cPagesPerChunk = 1048048; /* max ~1048059 */
1013 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 1048048 < 16U*_1M - PAGE_SIZE * 2);
1014 }
1015 else
1016 {
1017 cbChunk = 4U*_1M;
1018 cPagesPerChunk = 261616; /* max ~261627 */
1019 AssertCompile(sizeof(PGMRAMRANGE) + sizeof(PGMPAGE) * 261616 < 4U*_1M - PAGE_SIZE * 2);
1020 }
1021 AssertRelease(RT_UOFFSETOF(PGMRAMRANGE, aPages[cPagesPerChunk]) + PAGE_SIZE * 2 <= cbChunk);
1022
1023 RTGCPHYS cPagesLeft = cPages;
1024 RTGCPHYS GCPhysChunk = GCPhys;
1025 uint32_t iChunk = 0;
1026 while (cPagesLeft > 0)
1027 {
1028 uint32_t cPagesInChunk = cPagesLeft;
1029 if (cPagesInChunk > cPagesPerChunk)
1030 cPagesInChunk = cPagesPerChunk;
1031
1032 rc = pgmR3PhysRegisterHighRamChunk(pVM, GCPhysChunk, cPagesInChunk, cbChunk, iChunk, pszDesc, &pPrev);
1033 AssertRCReturn(rc, rc);
1034
1035 /* advance */
1036 GCPhysChunk += (RTGCPHYS)cPagesInChunk << PAGE_SHIFT;
1037 cPagesLeft -= cPagesInChunk;
1038 iChunk++;
1039 }
1040 }
1041 else
1042 {
1043 /*
1044 * Allocate, initialize and link the new RAM range.
1045 */
1046 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1047 PPGMRAMRANGE pNew;
1048 rc = MMR3HyperAllocOnceNoRel(pVM, cbRamRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1049 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1050
1051 pgmR3PhysInitAndLinkRamRange(pVM, pNew, GCPhys, GCPhysLast, NIL_RTRCPTR, NIL_RTR0PTR, pszDesc, pPrev);
1052 }
1053 PGMPhysInvalidatePageMapTLB(pVM);
1054 pgmUnlock(pVM);
1055
1056 /*
1057 * Notify REM.
1058 */
1059 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_RAM);
1060
1061 return VINF_SUCCESS;
1062}
1063
1064
1065/**
1066 * Worker called by PGMR3InitFinalize if we're configured to pre-allocate RAM.
1067 *
1068 * We do this late in the init process so that all the ROM and MMIO ranges have
1069 * been registered already and we don't go wasting memory on them.
1070 *
1071 * @returns VBox status code.
1072 *
1073 * @param pVM Pointer to the shared VM structure.
1074 */
1075int pgmR3PhysRamPreAllocate(PVM pVM)
1076{
1077 Assert(pVM->pgm.s.fRamPreAlloc);
1078 Log(("pgmR3PhysRamPreAllocate: enter\n"));
1079
1080 /*
1081 * Walk the RAM ranges and allocate all RAM pages, halt at
1082 * the first allocation error.
1083 */
1084 uint64_t cPages = 0;
1085 uint64_t NanoTS = RTTimeNanoTS();
1086 pgmLock(pVM);
1087 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1088 {
1089 PPGMPAGE pPage = &pRam->aPages[0];
1090 RTGCPHYS GCPhys = pRam->GCPhys;
1091 uint32_t cLeft = pRam->cb >> PAGE_SHIFT;
1092 while (cLeft-- > 0)
1093 {
1094 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1095 {
1096 switch (PGM_PAGE_GET_STATE(pPage))
1097 {
1098 case PGM_PAGE_STATE_ZERO:
1099 {
1100 int rc = pgmPhysAllocPage(pVM, pPage, GCPhys);
1101 if (RT_FAILURE(rc))
1102 {
1103 LogRel(("PGM: RAM Pre-allocation failed at %RGp (in %s) with rc=%Rrc\n", GCPhys, pRam->pszDesc, rc));
1104 pgmUnlock(pVM);
1105 return rc;
1106 }
1107 cPages++;
1108 break;
1109 }
1110
1111 case PGM_PAGE_STATE_ALLOCATED:
1112 case PGM_PAGE_STATE_WRITE_MONITORED:
1113 case PGM_PAGE_STATE_SHARED:
1114 /* nothing to do here. */
1115 break;
1116 }
1117 }
1118
1119 /* next */
1120 pPage++;
1121 GCPhys += PAGE_SIZE;
1122 }
1123 }
1124 pgmUnlock(pVM);
1125 NanoTS = RTTimeNanoTS() - NanoTS;
1126
1127 LogRel(("PGM: Pre-allocated %llu pages in %llu ms\n", cPages, NanoTS / 1000000));
1128 Log(("pgmR3PhysRamPreAllocate: returns VINF_SUCCESS\n"));
1129 return VINF_SUCCESS;
1130}
1131
1132
1133/**
1134 * Resets (zeros) the RAM.
1135 *
1136 * ASSUMES that the caller owns the PGM lock.
1137 *
1138 * @returns VBox status code.
1139 * @param pVM Pointer to the shared VM structure.
1140 */
1141int pgmR3PhysRamReset(PVM pVM)
1142{
1143 Assert(PGMIsLockOwner(pVM));
1144
1145 /*
1146 * We batch up pages that should be freed instead of calling GMM for
1147 * each and every one of them.
1148 */
1149 uint32_t cPendingPages = 0;
1150 PGMMFREEPAGESREQ pReq;
1151 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1152 AssertLogRelRCReturn(rc, rc);
1153
1154 /*
1155 * Walk the ram ranges.
1156 */
1157 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
1158 {
1159 uint32_t iPage = pRam->cb >> PAGE_SHIFT;
1160 AssertMsg(((RTGCPHYS)iPage << PAGE_SHIFT) == pRam->cb, ("%RGp %RGp\n", (RTGCPHYS)iPage << PAGE_SHIFT, pRam->cb));
1161
1162 if (!pVM->pgm.s.fRamPreAlloc)
1163 {
1164 /* Replace all RAM pages by ZERO pages. */
1165 while (iPage-- > 0)
1166 {
1167 PPGMPAGE pPage = &pRam->aPages[iPage];
1168 switch (PGM_PAGE_GET_TYPE(pPage))
1169 {
1170 case PGMPAGETYPE_RAM:
1171 if (!PGM_PAGE_IS_ZERO(pPage))
1172 {
1173 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1174 AssertLogRelRCReturn(rc, rc);
1175 }
1176 break;
1177
1178 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1179 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1180 break;
1181
1182 case PGMPAGETYPE_MMIO2:
1183 case PGMPAGETYPE_ROM_SHADOW: /* handled by pgmR3PhysRomReset. */
1184 case PGMPAGETYPE_ROM:
1185 case PGMPAGETYPE_MMIO:
1186 break;
1187 default:
1188 AssertFailed();
1189 }
1190 } /* for each page */
1191 }
1192 else
1193 {
1194 /* Zero the memory. */
1195 while (iPage-- > 0)
1196 {
1197 PPGMPAGE pPage = &pRam->aPages[iPage];
1198 switch (PGM_PAGE_GET_TYPE(pPage))
1199 {
1200 case PGMPAGETYPE_RAM:
1201 switch (PGM_PAGE_GET_STATE(pPage))
1202 {
1203 case PGM_PAGE_STATE_ZERO:
1204 break;
1205 case PGM_PAGE_STATE_SHARED:
1206 case PGM_PAGE_STATE_WRITE_MONITORED:
1207 rc = pgmPhysPageMakeWritable(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1208 AssertLogRelRCReturn(rc, rc);
1209 case PGM_PAGE_STATE_ALLOCATED:
1210 {
1211 void *pvPage;
1212 rc = pgmPhysPageMap(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pvPage);
1213 AssertLogRelRCReturn(rc, rc);
1214 ASMMemZeroPage(pvPage);
1215 break;
1216 }
1217 }
1218 break;
1219
1220 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1221 pgmHandlerPhysicalResetAliasedPage(pVM, pPage, pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1222 break;
1223
1224 case PGMPAGETYPE_MMIO2:
1225 case PGMPAGETYPE_ROM_SHADOW:
1226 case PGMPAGETYPE_ROM:
1227 case PGMPAGETYPE_MMIO:
1228 break;
1229 default:
1230 AssertFailed();
1231
1232 }
1233 } /* for each page */
1234 }
1235
1236 }
1237
1238 /*
1239 * Finish off any pages pending freeing.
1240 */
1241 if (cPendingPages)
1242 {
1243 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1244 AssertLogRelRCReturn(rc, rc);
1245 }
1246 GMMR3FreePagesCleanup(pReq);
1247
1248 return VINF_SUCCESS;
1249}
1250
1251
1252/**
1253 * This is the interface IOM is using to register an MMIO region.
1254 *
1255 * It will check for conflicts and ensure that a RAM range structure
1256 * is present before calling the PGMR3HandlerPhysicalRegister API to
1257 * register the callbacks.
1258 *
1259 * @returns VBox status code.
1260 *
1261 * @param pVM Pointer to the shared VM structure.
1262 * @param GCPhys The start of the MMIO region.
1263 * @param cb The size of the MMIO region.
1264 * @param pfnHandlerR3 The address of the ring-3 handler. (IOMR3MMIOHandler)
1265 * @param pvUserR3 The user argument for R3.
1266 * @param pfnHandlerR0 The address of the ring-0 handler. (IOMMMIOHandler)
1267 * @param pvUserR0 The user argument for R0.
1268 * @param pfnHandlerRC The address of the RC handler. (IOMMMIOHandler)
1269 * @param pvUserRC The user argument for RC.
1270 * @param pszDesc The description of the MMIO region.
1271 */
1272VMMR3DECL(int) PGMR3PhysMMIORegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb,
1273 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3, RTR3PTR pvUserR3,
1274 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0, RTR0PTR pvUserR0,
1275 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC, RTRCPTR pvUserRC,
1276 R3PTRTYPE(const char *) pszDesc)
1277{
1278 /*
1279 * Assert on some assumption.
1280 */
1281 VM_ASSERT_EMT(pVM);
1282 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1283 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1284 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1285 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1286
1287 /*
1288 * Make sure there's a RAM range structure for the region.
1289 */
1290 int rc;
1291 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1292 bool fRamExists = false;
1293 PPGMRAMRANGE pRamPrev = NULL;
1294 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1295 while (pRam && GCPhysLast >= pRam->GCPhys)
1296 {
1297 if ( GCPhysLast >= pRam->GCPhys
1298 && GCPhys <= pRam->GCPhysLast)
1299 {
1300 /* Simplification: all within the same range. */
1301 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1302 && GCPhysLast <= pRam->GCPhysLast,
1303 ("%RGp-%RGp (MMIO/%s) falls partly outside %RGp-%RGp (%s)\n",
1304 GCPhys, GCPhysLast, pszDesc,
1305 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1306 VERR_PGM_RAM_CONFLICT);
1307
1308 /* Check that it's all RAM or MMIO pages. */
1309 PCPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1310 uint32_t cLeft = cb >> PAGE_SHIFT;
1311 while (cLeft-- > 0)
1312 {
1313 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1314 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO,
1315 ("%RGp-%RGp (MMIO/%s): %RGp is not a RAM or MMIO page - type=%d desc=%s\n",
1316 GCPhys, GCPhysLast, pszDesc, PGM_PAGE_GET_TYPE(pPage), pRam->pszDesc),
1317 VERR_PGM_RAM_CONFLICT);
1318 pPage++;
1319 }
1320
1321 /* Looks good. */
1322 fRamExists = true;
1323 break;
1324 }
1325
1326 /* next */
1327 pRamPrev = pRam;
1328 pRam = pRam->pNextR3;
1329 }
1330 PPGMRAMRANGE pNew;
1331 if (fRamExists)
1332 {
1333 pNew = NULL;
1334
1335 /*
1336 * Make all the pages in the range MMIO/ZERO pages, freeing any
1337 * RAM pages currently mapped here. This might not be 100% correct
1338 * for PCI memory, but we're doing the same thing for MMIO2 pages.
1339 */
1340 rc = pgmLock(pVM);
1341 if (RT_SUCCESS(rc))
1342 {
1343 rc = pgmR3PhysFreePageRange(pVM, pRam, GCPhys, GCPhysLast, PGMPAGETYPE_MMIO);
1344 pgmUnlock(pVM);
1345 }
1346 AssertRCReturn(rc, rc);
1347 }
1348 else
1349 {
1350 pgmLock(pVM);
1351
1352 /*
1353 * No RAM range, insert an ad hoc one.
1354 *
1355 * Note that we don't have to tell REM about this range because
1356 * PGMHandlerPhysicalRegisterEx will do that for us.
1357 */
1358 Log(("PGMR3PhysMMIORegister: Adding ad hoc MMIO range for %RGp-%RGp %s\n", GCPhys, GCPhysLast, pszDesc));
1359
1360 const uint32_t cPages = cb >> PAGE_SHIFT;
1361 const size_t cbRamRange = RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]);
1362 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), 16, MM_TAG_PGM_PHYS, (void **)&pNew);
1363 AssertLogRelMsgRCReturn(rc, ("cbRamRange=%zu\n", cbRamRange), rc);
1364
1365 /* Initialize the range. */
1366 pNew->pSelfR0 = MMHyperCCToR0(pVM, pNew);
1367 pNew->pSelfRC = MMHyperCCToRC(pVM, pNew);
1368 pNew->GCPhys = GCPhys;
1369 pNew->GCPhysLast = GCPhysLast;
1370 pNew->cb = cb;
1371 pNew->pszDesc = pszDesc;
1372 pNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO;
1373 pNew->pvR3 = NULL;
1374 pNew->paLSPages = NULL;
1375
1376 uint32_t iPage = cPages;
1377 while (iPage-- > 0)
1378 PGM_PAGE_INIT_ZERO(&pNew->aPages[iPage], pVM, PGMPAGETYPE_MMIO);
1379 Assert(PGM_PAGE_GET_TYPE(&pNew->aPages[0]) == PGMPAGETYPE_MMIO);
1380
1381 /* update the page count stats. */
1382 pVM->pgm.s.cZeroPages += cPages;
1383 pVM->pgm.s.cAllPages += cPages;
1384
1385 /* link it */
1386 pgmR3PhysLinkRamRange(pVM, pNew, pRamPrev);
1387
1388 pgmUnlock(pVM);
1389 }
1390
1391 /*
1392 * Register the access handler.
1393 */
1394 rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_MMIO, GCPhys, GCPhysLast,
1395 pfnHandlerR3, pvUserR3,
1396 pfnHandlerR0, pvUserR0,
1397 pfnHandlerRC, pvUserRC, pszDesc);
1398 if ( RT_FAILURE(rc)
1399 && !fRamExists)
1400 {
1401 pVM->pgm.s.cZeroPages -= cb >> PAGE_SHIFT;
1402 pVM->pgm.s.cAllPages -= cb >> PAGE_SHIFT;
1403
1404 /* remove the ad hoc range. */
1405 pgmR3PhysUnlinkRamRange2(pVM, pNew, pRamPrev);
1406 pNew->cb = pNew->GCPhys = pNew->GCPhysLast = NIL_RTGCPHYS;
1407 MMHyperFree(pVM, pRam);
1408 }
1409 PGMPhysInvalidatePageMapTLB(pVM);
1410
1411 return rc;
1412}
1413
1414
1415/**
1416 * This is the interface IOM is using to register an MMIO region.
1417 *
1418 * It will take care of calling PGMHandlerPhysicalDeregister and clean up
1419 * any ad hoc PGMRAMRANGE left behind.
1420 *
1421 * @returns VBox status code.
1422 * @param pVM Pointer to the shared VM structure.
1423 * @param GCPhys The start of the MMIO region.
1424 * @param cb The size of the MMIO region.
1425 */
1426VMMR3DECL(int) PGMR3PhysMMIODeregister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
1427{
1428 VM_ASSERT_EMT(pVM);
1429
1430 /*
1431 * First deregister the handler, then check if we should remove the ram range.
1432 */
1433 int rc = PGMHandlerPhysicalDeregister(pVM, GCPhys);
1434 if (RT_SUCCESS(rc))
1435 {
1436 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
1437 PPGMRAMRANGE pRamPrev = NULL;
1438 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1439 while (pRam && GCPhysLast >= pRam->GCPhys)
1440 {
1441 /** @todo We're being a bit too careful here. rewrite. */
1442 if ( GCPhysLast == pRam->GCPhysLast
1443 && GCPhys == pRam->GCPhys)
1444 {
1445 Assert(pRam->cb == cb);
1446
1447 /*
1448 * See if all the pages are dead MMIO pages.
1449 */
1450 uint32_t const cPages = cb >> PAGE_SHIFT;
1451 bool fAllMMIO = true;
1452 uint32_t iPage = 0;
1453 uint32_t cLeft = cPages;
1454 while (cLeft-- > 0)
1455 {
1456 PPGMPAGE pPage = &pRam->aPages[iPage];
1457 if ( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO
1458 /*|| not-out-of-action later */)
1459 {
1460 fAllMMIO = false;
1461 Assert(PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_MMIO2_ALIAS_MMIO);
1462 AssertMsgFailed(("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1463 break;
1464 }
1465 Assert(PGM_PAGE_IS_ZERO(pPage));
1466 pPage++;
1467 }
1468 if (fAllMMIO)
1469 {
1470 /*
1471 * Ad-hoc range, unlink and free it.
1472 */
1473 Log(("PGMR3PhysMMIODeregister: Freeing ad hoc MMIO range for %RGp-%RGp %s\n",
1474 GCPhys, GCPhysLast, pRam->pszDesc));
1475
1476 pVM->pgm.s.cAllPages -= cPages;
1477 pVM->pgm.s.cZeroPages -= cPages;
1478
1479 pgmR3PhysUnlinkRamRange2(pVM, pRam, pRamPrev);
1480 pRam->cb = pRam->GCPhys = pRam->GCPhysLast = NIL_RTGCPHYS;
1481 MMHyperFree(pVM, pRam);
1482 break;
1483 }
1484 }
1485
1486 /*
1487 * Range match? It will all be within one range (see PGMAllHandler.cpp).
1488 */
1489 if ( GCPhysLast >= pRam->GCPhys
1490 && GCPhys <= pRam->GCPhysLast)
1491 {
1492 Assert(GCPhys >= pRam->GCPhys);
1493 Assert(GCPhysLast <= pRam->GCPhysLast);
1494
1495 /*
1496 * Turn the pages back into RAM pages.
1497 */
1498 uint32_t iPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1499 uint32_t cLeft = cb >> PAGE_SHIFT;
1500 while (cLeft--)
1501 {
1502 PPGMPAGE pPage = &pRam->aPages[iPage];
1503 AssertMsg(PGM_PAGE_IS_MMIO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1504 AssertMsg(PGM_PAGE_IS_ZERO(pPage), ("%RGp %R[pgmpage]\n", pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), pPage));
1505 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
1506 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_RAM);
1507 }
1508 break;
1509 }
1510
1511 /* next */
1512 pRamPrev = pRam;
1513 pRam = pRam->pNextR3;
1514 }
1515 }
1516
1517 PGMPhysInvalidatePageMapTLB(pVM);
1518 return rc;
1519}
1520
1521
1522/**
1523 * Locate a MMIO2 range.
1524 *
1525 * @returns Pointer to the MMIO2 range.
1526 * @param pVM Pointer to the shared VM structure.
1527 * @param pDevIns The device instance owning the region.
1528 * @param iRegion The region.
1529 */
1530DECLINLINE(PPGMMMIO2RANGE) pgmR3PhysMMIO2Find(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1531{
1532 /*
1533 * Search the list.
1534 */
1535 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
1536 if ( pCur->pDevInsR3 == pDevIns
1537 && pCur->iRegion == iRegion)
1538 return pCur;
1539 return NULL;
1540}
1541
1542
1543/**
1544 * Allocate and register an MMIO2 region.
1545 *
1546 * As mentioned elsewhere, MMIO2 is just RAM spelled differently. It's
1547 * RAM associated with a device. It is also non-shared memory with a
1548 * permanent ring-3 mapping and page backing (presently).
1549 *
1550 * A MMIO2 range may overlap with base memory if a lot of RAM
1551 * is configured for the VM, in which case we'll drop the base
1552 * memory pages. Presently we will make no attempt to preserve
1553 * anything that happens to be present in the base memory that
1554 * is replaced, this is of course incorrectly but it's too much
1555 * effort.
1556 *
1557 * @returns VBox status code.
1558 * @retval VINF_SUCCESS on success, *ppv pointing to the R3 mapping of the memory.
1559 * @retval VERR_ALREADY_EXISTS if the region already exists.
1560 *
1561 * @param pVM Pointer to the shared VM structure.
1562 * @param pDevIns The device instance owning the region.
1563 * @param iRegion The region number. If the MMIO2 memory is a PCI I/O region
1564 * this number has to be the number of that region. Otherwise
1565 * it can be any number safe UINT8_MAX.
1566 * @param cb The size of the region. Must be page aligned.
1567 * @param fFlags Reserved for future use, must be zero.
1568 * @param ppv Where to store the pointer to the ring-3 mapping of the memory.
1569 * @param pszDesc The description.
1570 */
1571VMMR3DECL(int) PGMR3PhysMMIO2Register(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc)
1572{
1573 /*
1574 * Validate input.
1575 */
1576 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1577 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1578 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1579 AssertPtrReturn(ppv, VERR_INVALID_POINTER);
1580 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
1581 AssertReturn(*pszDesc, VERR_INVALID_PARAMETER);
1582 AssertReturn(pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion) == NULL, VERR_ALREADY_EXISTS);
1583 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1584 AssertReturn(cb, VERR_INVALID_PARAMETER);
1585 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
1586
1587 const uint32_t cPages = cb >> PAGE_SHIFT;
1588 AssertLogRelReturn(((RTGCPHYS)cPages << PAGE_SHIFT) == cb, VERR_INVALID_PARAMETER);
1589 AssertLogRelReturn(cPages <= INT32_MAX / 2, VERR_NO_MEMORY);
1590
1591 /*
1592 * For the 2nd+ instance, mangle the description string so it's unique.
1593 */
1594 if (pDevIns->iInstance > 0) /** @todo Move to PDMDevHlp.cpp and use a real string cache. */
1595 {
1596 pszDesc = MMR3HeapAPrintf(pVM, MM_TAG_PGM_PHYS, "%s [%u]", pszDesc, pDevIns->iInstance);
1597 if (!pszDesc)
1598 return VERR_NO_MEMORY;
1599 }
1600
1601 /*
1602 * Try reserve and allocate the backing memory first as this is what is
1603 * most likely to fail.
1604 */
1605 int rc = MMR3AdjustFixedReservation(pVM, cPages, pszDesc);
1606 if (RT_SUCCESS(rc))
1607 {
1608 void *pvPages;
1609 PSUPPAGE paPages = (PSUPPAGE)RTMemTmpAlloc(cPages * sizeof(SUPPAGE));
1610 if (RT_SUCCESS(rc))
1611 rc = SUPR3PageAllocEx(cPages, 0 /*fFlags*/, &pvPages, NULL /*pR0Ptr*/, paPages);
1612 if (RT_SUCCESS(rc))
1613 {
1614 memset(pvPages, 0, cPages * PAGE_SIZE);
1615
1616 /*
1617 * Create the MMIO2 range record for it.
1618 */
1619 const size_t cbRange = RT_OFFSETOF(PGMMMIO2RANGE, RamRange.aPages[cPages]);
1620 PPGMMMIO2RANGE pNew;
1621 rc = MMR3HyperAllocOnceNoRel(pVM, cbRange, 0, MM_TAG_PGM_PHYS, (void **)&pNew);
1622 AssertLogRelMsgRC(rc, ("cbRamRange=%zu\n", cbRange));
1623 if (RT_SUCCESS(rc))
1624 {
1625 pNew->pDevInsR3 = pDevIns;
1626 pNew->pvR3 = pvPages;
1627 //pNew->pNext = NULL;
1628 //pNew->fMapped = false;
1629 //pNew->fOverlapping = false;
1630 pNew->iRegion = iRegion;
1631 pNew->idSavedState = UINT8_MAX;
1632 pNew->RamRange.pSelfR0 = MMHyperCCToR0(pVM, &pNew->RamRange);
1633 pNew->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pNew->RamRange);
1634 pNew->RamRange.GCPhys = NIL_RTGCPHYS;
1635 pNew->RamRange.GCPhysLast = NIL_RTGCPHYS;
1636 pNew->RamRange.pszDesc = pszDesc;
1637 pNew->RamRange.cb = cb;
1638 pNew->RamRange.fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2;
1639 pNew->RamRange.pvR3 = pvPages;
1640 //pNew->RamRange.paLSPages = NULL;
1641
1642 uint32_t iPage = cPages;
1643 while (iPage-- > 0)
1644 {
1645 PGM_PAGE_INIT(&pNew->RamRange.aPages[iPage],
1646 paPages[iPage].Phys, NIL_GMM_PAGEID,
1647 PGMPAGETYPE_MMIO2, PGM_PAGE_STATE_ALLOCATED);
1648 }
1649
1650 /* update page count stats */
1651 pVM->pgm.s.cAllPages += cPages;
1652 pVM->pgm.s.cPrivatePages += cPages;
1653
1654 /*
1655 * Link it into the list.
1656 * Since there is no particular order, just push it.
1657 */
1658 pgmLock(pVM);
1659 pNew->pNextR3 = pVM->pgm.s.pMmio2RangesR3;
1660 pVM->pgm.s.pMmio2RangesR3 = pNew;
1661 pgmUnlock(pVM);
1662
1663 *ppv = pvPages;
1664 RTMemTmpFree(paPages);
1665 PGMPhysInvalidatePageMapTLB(pVM);
1666 return VINF_SUCCESS;
1667 }
1668
1669 SUPR3PageFreeEx(pvPages, cPages);
1670 }
1671 RTMemTmpFree(paPages);
1672 MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pszDesc);
1673 }
1674 if (pDevIns->iInstance > 0)
1675 MMR3HeapFree((void *)pszDesc);
1676 return rc;
1677}
1678
1679
1680/**
1681 * Deregisters and frees an MMIO2 region.
1682 *
1683 * Any physical (and virtual) access handlers registered for the region must
1684 * be deregistered before calling this function.
1685 *
1686 * @returns VBox status code.
1687 * @param pVM Pointer to the shared VM structure.
1688 * @param pDevIns The device instance owning the region.
1689 * @param iRegion The region. If it's UINT32_MAX it'll be a wildcard match.
1690 */
1691VMMR3DECL(int) PGMR3PhysMMIO2Deregister(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion)
1692{
1693 /*
1694 * Validate input.
1695 */
1696 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1697 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1698 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
1699
1700 pgmLock(pVM);
1701 int rc = VINF_SUCCESS;
1702 unsigned cFound = 0;
1703 PPGMMMIO2RANGE pPrev = NULL;
1704 PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3;
1705 while (pCur)
1706 {
1707 if ( pCur->pDevInsR3 == pDevIns
1708 && ( iRegion == UINT32_MAX
1709 || pCur->iRegion == iRegion))
1710 {
1711 cFound++;
1712
1713 /*
1714 * Unmap it if it's mapped.
1715 */
1716 if (pCur->fMapped)
1717 {
1718 int rc2 = PGMR3PhysMMIO2Unmap(pVM, pCur->pDevInsR3, pCur->iRegion, pCur->RamRange.GCPhys);
1719 AssertRC(rc2);
1720 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1721 rc = rc2;
1722 }
1723
1724 /*
1725 * Unlink it
1726 */
1727 PPGMMMIO2RANGE pNext = pCur->pNextR3;
1728 if (pPrev)
1729 pPrev->pNextR3 = pNext;
1730 else
1731 pVM->pgm.s.pMmio2RangesR3 = pNext;
1732 pCur->pNextR3 = NULL;
1733
1734 /*
1735 * Free the memory.
1736 */
1737 int rc2 = SUPR3PageFreeEx(pCur->pvR3, pCur->RamRange.cb >> PAGE_SHIFT);
1738 AssertRC(rc2);
1739 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1740 rc = rc2;
1741
1742 uint32_t const cPages = pCur->RamRange.cb >> PAGE_SHIFT;
1743 rc2 = MMR3AdjustFixedReservation(pVM, -(int32_t)cPages, pCur->RamRange.pszDesc);
1744 AssertRC(rc2);
1745 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
1746 rc = rc2;
1747
1748 /* we're leaking hyper memory here if done at runtime. */
1749#ifdef VBOX_STRICT
1750 VMSTATE const enmState = VMR3GetState(pVM);
1751 AssertMsg( enmState == VMSTATE_POWERING_OFF
1752 || enmState == VMSTATE_POWERING_OFF_LS
1753 || enmState == VMSTATE_OFF
1754 || enmState == VMSTATE_OFF_LS
1755 || enmState == VMSTATE_DESTROYING
1756 || enmState == VMSTATE_TERMINATED
1757 || enmState == VMSTATE_CREATING
1758 , ("%s\n", VMR3GetStateName(enmState)));
1759#endif
1760 /*rc = MMHyperFree(pVM, pCur);
1761 AssertRCReturn(rc, rc); - not safe, see the alloc call. */
1762
1763
1764 /* update page count stats */
1765 pVM->pgm.s.cAllPages -= cPages;
1766 pVM->pgm.s.cPrivatePages -= cPages;
1767
1768 /* next */
1769 pCur = pNext;
1770 }
1771 else
1772 {
1773 pPrev = pCur;
1774 pCur = pCur->pNextR3;
1775 }
1776 }
1777 PGMPhysInvalidatePageMapTLB(pVM);
1778 pgmUnlock(pVM);
1779 return !cFound && iRegion != UINT32_MAX ? VERR_NOT_FOUND : rc;
1780}
1781
1782
1783/**
1784 * Maps a MMIO2 region.
1785 *
1786 * This is done when a guest / the bios / state loading changes the
1787 * PCI config. The replacing of base memory has the same restrictions
1788 * as during registration, of course.
1789 *
1790 * @returns VBox status code.
1791 *
1792 * @param pVM Pointer to the shared VM structure.
1793 * @param pDevIns The
1794 */
1795VMMR3DECL(int) PGMR3PhysMMIO2Map(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1796{
1797 /*
1798 * Validate input
1799 */
1800 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1801 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1802 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1803 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1804 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1805 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1806
1807 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1808 AssertReturn(pCur, VERR_NOT_FOUND);
1809 AssertReturn(!pCur->fMapped, VERR_WRONG_ORDER);
1810 Assert(pCur->RamRange.GCPhys == NIL_RTGCPHYS);
1811 Assert(pCur->RamRange.GCPhysLast == NIL_RTGCPHYS);
1812
1813 const RTGCPHYS GCPhysLast = GCPhys + pCur->RamRange.cb - 1;
1814 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
1815
1816 /*
1817 * Find our location in the ram range list, checking for
1818 * restriction we don't bother implementing yet (partially overlapping).
1819 */
1820 bool fRamExists = false;
1821 PPGMRAMRANGE pRamPrev = NULL;
1822 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1823 while (pRam && GCPhysLast >= pRam->GCPhys)
1824 {
1825 if ( GCPhys <= pRam->GCPhysLast
1826 && GCPhysLast >= pRam->GCPhys)
1827 {
1828 /* completely within? */
1829 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
1830 && GCPhysLast <= pRam->GCPhysLast,
1831 ("%RGp-%RGp (MMIO2/%s) falls partly outside %RGp-%RGp (%s)\n",
1832 GCPhys, GCPhysLast, pCur->RamRange.pszDesc,
1833 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
1834 VERR_PGM_RAM_CONFLICT);
1835 fRamExists = true;
1836 break;
1837 }
1838
1839 /* next */
1840 pRamPrev = pRam;
1841 pRam = pRam->pNextR3;
1842 }
1843 if (fRamExists)
1844 {
1845 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1846 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1847 while (cPagesLeft-- > 0)
1848 {
1849 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
1850 ("%RGp isn't a RAM page (%d) - mapping %RGp-%RGp (MMIO2/%s).\n",
1851 GCPhys, PGM_PAGE_GET_TYPE(pPage), GCPhys, GCPhysLast, pCur->RamRange.pszDesc),
1852 VERR_PGM_RAM_CONFLICT);
1853 pPage++;
1854 }
1855 }
1856 Log(("PGMR3PhysMMIO2Map: %RGp-%RGp fRamExists=%RTbool %s\n",
1857 GCPhys, GCPhysLast, fRamExists, pCur->RamRange.pszDesc));
1858
1859 /*
1860 * Make the changes.
1861 */
1862 pgmLock(pVM);
1863
1864 pCur->RamRange.GCPhys = GCPhys;
1865 pCur->RamRange.GCPhysLast = GCPhysLast;
1866 pCur->fMapped = true;
1867 pCur->fOverlapping = fRamExists;
1868
1869 if (fRamExists)
1870 {
1871/** @todo use pgmR3PhysFreePageRange here. */
1872 uint32_t cPendingPages = 0;
1873 PGMMFREEPAGESREQ pReq;
1874 int rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
1875 AssertLogRelRCReturn(rc, rc);
1876
1877 /* replace the pages, freeing all present RAM pages. */
1878 PPGMPAGE pPageSrc = &pCur->RamRange.aPages[0];
1879 PPGMPAGE pPageDst = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1880 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1881 while (cPagesLeft-- > 0)
1882 {
1883 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPageDst, GCPhys);
1884 AssertLogRelRCReturn(rc, rc); /* We're done for if this goes wrong. */
1885
1886 RTHCPHYS const HCPhys = PGM_PAGE_GET_HCPHYS(pPageSrc);
1887 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhys);
1888 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_MMIO2);
1889 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ALLOCATED);
1890
1891 pVM->pgm.s.cZeroPages--;
1892 GCPhys += PAGE_SIZE;
1893 pPageSrc++;
1894 pPageDst++;
1895 }
1896
1897 if (cPendingPages)
1898 {
1899 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
1900 AssertLogRelRCReturn(rc, rc);
1901 }
1902 GMMR3FreePagesCleanup(pReq);
1903 pgmUnlock(pVM);
1904 }
1905 else
1906 {
1907 RTGCPHYS cb = pCur->RamRange.cb;
1908
1909 /* link in the ram range */
1910 pgmR3PhysLinkRamRange(pVM, &pCur->RamRange, pRamPrev);
1911 pgmUnlock(pVM);
1912
1913 REMR3NotifyPhysRamRegister(pVM, GCPhys, cb, REM_NOTIFY_PHYS_RAM_FLAGS_MMIO2);
1914 }
1915
1916 PGMPhysInvalidatePageMapTLB(pVM);
1917 return VINF_SUCCESS;
1918}
1919
1920
1921/**
1922 * Unmaps a MMIO2 region.
1923 *
1924 * This is done when a guest / the bios / state loading changes the
1925 * PCI config. The replacing of base memory has the same restrictions
1926 * as during registration, of course.
1927 */
1928VMMR3DECL(int) PGMR3PhysMMIO2Unmap(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
1929{
1930 /*
1931 * Validate input
1932 */
1933 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
1934 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
1935 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
1936 AssertReturn(GCPhys != NIL_RTGCPHYS, VERR_INVALID_PARAMETER);
1937 AssertReturn(GCPhys != 0, VERR_INVALID_PARAMETER);
1938 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
1939
1940 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
1941 AssertReturn(pCur, VERR_NOT_FOUND);
1942 AssertReturn(pCur->fMapped, VERR_WRONG_ORDER);
1943 AssertReturn(pCur->RamRange.GCPhys == GCPhys, VERR_INVALID_PARAMETER);
1944 Assert(pCur->RamRange.GCPhysLast != NIL_RTGCPHYS);
1945
1946 Log(("PGMR3PhysMMIO2Unmap: %RGp-%RGp %s\n",
1947 pCur->RamRange.GCPhys, pCur->RamRange.GCPhysLast, pCur->RamRange.pszDesc));
1948
1949 /*
1950 * Unmap it.
1951 */
1952 pgmLock(pVM);
1953
1954 RTGCPHYS GCPhysRangeREM;
1955 RTGCPHYS cbRangeREM;
1956 bool fInformREM;
1957 if (pCur->fOverlapping)
1958 {
1959 /* Restore the RAM pages we've replaced. */
1960 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
1961 while (pRam->GCPhys > pCur->RamRange.GCPhysLast)
1962 pRam = pRam->pNextR3;
1963
1964 RTHCPHYS const HCPhysZeroPg = pVM->pgm.s.HCPhysZeroPg;
1965 Assert(HCPhysZeroPg != 0 && HCPhysZeroPg != NIL_RTHCPHYS);
1966 PPGMPAGE pPageDst = &pRam->aPages[(pCur->RamRange.GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
1967 uint32_t cPagesLeft = pCur->RamRange.cb >> PAGE_SHIFT;
1968 while (cPagesLeft-- > 0)
1969 {
1970 PGM_PAGE_SET_HCPHYS(pPageDst, HCPhysZeroPg);
1971 PGM_PAGE_SET_TYPE(pPageDst, PGMPAGETYPE_RAM);
1972 PGM_PAGE_SET_STATE(pPageDst, PGM_PAGE_STATE_ZERO);
1973 PGM_PAGE_SET_PAGEID(pPageDst, NIL_GMM_PAGEID);
1974
1975 pVM->pgm.s.cZeroPages++;
1976 pPageDst++;
1977 }
1978
1979 GCPhysRangeREM = NIL_RTGCPHYS; /* shuts up gcc */
1980 cbRangeREM = RTGCPHYS_MAX; /* ditto */
1981 fInformREM = false;
1982 }
1983 else
1984 {
1985 GCPhysRangeREM = pCur->RamRange.GCPhys;
1986 cbRangeREM = pCur->RamRange.cb;
1987 fInformREM = true;
1988
1989 pgmR3PhysUnlinkRamRange(pVM, &pCur->RamRange);
1990 }
1991
1992 pCur->RamRange.GCPhys = NIL_RTGCPHYS;
1993 pCur->RamRange.GCPhysLast = NIL_RTGCPHYS;
1994 pCur->fOverlapping = false;
1995 pCur->fMapped = false;
1996
1997 PGMPhysInvalidatePageMapTLB(pVM);
1998 pgmUnlock(pVM);
1999
2000 if (fInformREM)
2001 REMR3NotifyPhysRamDeregister(pVM, GCPhysRangeREM, cbRangeREM);
2002
2003 return VINF_SUCCESS;
2004}
2005
2006
2007/**
2008 * Checks if the given address is an MMIO2 base address or not.
2009 *
2010 * @returns true/false accordingly.
2011 * @param pVM Pointer to the shared VM structure.
2012 * @param pDevIns The owner of the memory, optional.
2013 * @param GCPhys The address to check.
2014 */
2015VMMR3DECL(bool) PGMR3PhysMMIO2IsBase(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2016{
2017 /*
2018 * Validate input
2019 */
2020 VM_ASSERT_EMT_RETURN(pVM, false);
2021 AssertPtrReturn(pDevIns, false);
2022 AssertReturn(GCPhys != NIL_RTGCPHYS, false);
2023 AssertReturn(GCPhys != 0, false);
2024 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), false);
2025
2026 /*
2027 * Search the list.
2028 */
2029 pgmLock(pVM);
2030 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2031 if (pCur->RamRange.GCPhys == GCPhys)
2032 {
2033 Assert(pCur->fMapped);
2034 pgmUnlock(pVM);
2035 return true;
2036 }
2037 pgmUnlock(pVM);
2038 return false;
2039}
2040
2041
2042/**
2043 * Gets the HC physical address of a page in the MMIO2 region.
2044 *
2045 * This is API is intended for MMHyper and shouldn't be called
2046 * by anyone else...
2047 *
2048 * @returns VBox status code.
2049 * @param pVM Pointer to the shared VM structure.
2050 * @param pDevIns The owner of the memory, optional.
2051 * @param iRegion The region.
2052 * @param off The page expressed an offset into the MMIO2 region.
2053 * @param pHCPhys Where to store the result.
2054 */
2055VMMR3DECL(int) PGMR3PhysMMIO2GetHCPhys(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, PRTHCPHYS pHCPhys)
2056{
2057 /*
2058 * Validate input
2059 */
2060 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2061 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2062 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2063
2064 pgmLock(pVM);
2065 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2066 AssertReturn(pCur, VERR_NOT_FOUND);
2067 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2068
2069 PCPGMPAGE pPage = &pCur->RamRange.aPages[off >> PAGE_SHIFT];
2070 *pHCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2071 pgmUnlock(pVM);
2072 return VINF_SUCCESS;
2073}
2074
2075
2076/**
2077 * Maps a portion of an MMIO2 region into kernel space (host).
2078 *
2079 * The kernel mapping will become invalid when the MMIO2 memory is deregistered
2080 * or the VM is terminated.
2081 *
2082 * @return VBox status code.
2083 *
2084 * @param pVM Pointer to the shared VM structure.
2085 * @param pDevIns The device owning the MMIO2 memory.
2086 * @param iRegion The region.
2087 * @param off The offset into the region. Must be page aligned.
2088 * @param cb The number of bytes to map. Must be page aligned.
2089 * @param pszDesc Mapping description.
2090 * @param pR0Ptr Where to store the R0 address.
2091 */
2092VMMR3DECL(int) PGMR3PhysMMIO2MapKernel(PVM pVM, PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2093 const char *pszDesc, PRTR0PTR pR0Ptr)
2094{
2095 /*
2096 * Validate input.
2097 */
2098 VM_ASSERT_EMT_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
2099 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2100 AssertReturn(iRegion <= UINT8_MAX, VERR_INVALID_PARAMETER);
2101
2102 PPGMMMIO2RANGE pCur = pgmR3PhysMMIO2Find(pVM, pDevIns, iRegion);
2103 AssertReturn(pCur, VERR_NOT_FOUND);
2104 AssertReturn(off < pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2105 AssertReturn(cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2106 AssertReturn(off + cb <= pCur->RamRange.cb, VERR_INVALID_PARAMETER);
2107
2108 /*
2109 * Pass the request on to the support library/driver.
2110 */
2111 int rc = SUPR3PageMapKernel(pCur->pvR3, off, cb, 0, pR0Ptr);
2112
2113 return rc;
2114}
2115
2116
2117/**
2118 * Registers a ROM image.
2119 *
2120 * Shadowed ROM images requires double the amount of backing memory, so,
2121 * don't use that unless you have to. Shadowing of ROM images is process
2122 * where we can select where the reads go and where the writes go. On real
2123 * hardware the chipset provides means to configure this. We provide
2124 * PGMR3PhysProtectROM() for this purpose.
2125 *
2126 * A read-only copy of the ROM image will always be kept around while we
2127 * will allocate RAM pages for the changes on demand (unless all memory
2128 * is configured to be preallocated).
2129 *
2130 * @returns VBox status.
2131 * @param pVM VM Handle.
2132 * @param pDevIns The device instance owning the ROM.
2133 * @param GCPhys First physical address in the range.
2134 * Must be page aligned!
2135 * @param cbRange The size of the range (in bytes).
2136 * Must be page aligned!
2137 * @param pvBinary Pointer to the binary data backing the ROM image.
2138 * This must be exactly \a cbRange in size.
2139 * @param fFlags Mask of flags. PGMPHYS_ROM_FLAGS_SHADOWED
2140 * and/or PGMPHYS_ROM_FLAGS_PERMANENT_BINARY.
2141 * @param pszDesc Pointer to description string. This must not be freed.
2142 *
2143 * @remark There is no way to remove the rom, automatically on device cleanup or
2144 * manually from the device yet. This isn't difficult in any way, it's
2145 * just not something we expect to be necessary for a while.
2146 */
2147VMMR3DECL(int) PGMR3PhysRomRegister(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS cb,
2148 const void *pvBinary, uint32_t fFlags, const char *pszDesc)
2149{
2150 Log(("PGMR3PhysRomRegister: pDevIns=%p GCPhys=%RGp(-%RGp) cb=%RGp pvBinary=%p fFlags=%#x pszDesc=%s\n",
2151 pDevIns, GCPhys, GCPhys + cb, cb, pvBinary, fFlags, pszDesc));
2152
2153 /*
2154 * Validate input.
2155 */
2156 AssertPtrReturn(pDevIns, VERR_INVALID_PARAMETER);
2157 AssertReturn(RT_ALIGN_T(GCPhys, PAGE_SIZE, RTGCPHYS) == GCPhys, VERR_INVALID_PARAMETER);
2158 AssertReturn(RT_ALIGN_T(cb, PAGE_SIZE, RTGCPHYS) == cb, VERR_INVALID_PARAMETER);
2159 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2160 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2161 AssertPtrReturn(pvBinary, VERR_INVALID_PARAMETER);
2162 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
2163 AssertReturn(!(fFlags & ~(PGMPHYS_ROM_FLAGS_SHADOWED | PGMPHYS_ROM_FLAGS_PERMANENT_BINARY)), VERR_INVALID_PARAMETER);
2164 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
2165
2166 const uint32_t cPages = cb >> PAGE_SHIFT;
2167
2168 /*
2169 * Find the ROM location in the ROM list first.
2170 */
2171 PPGMROMRANGE pRomPrev = NULL;
2172 PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3;
2173 while (pRom && GCPhysLast >= pRom->GCPhys)
2174 {
2175 if ( GCPhys <= pRom->GCPhysLast
2176 && GCPhysLast >= pRom->GCPhys)
2177 AssertLogRelMsgFailedReturn(("%RGp-%RGp (%s) conflicts with existing %RGp-%RGp (%s)\n",
2178 GCPhys, GCPhysLast, pszDesc,
2179 pRom->GCPhys, pRom->GCPhysLast, pRom->pszDesc),
2180 VERR_PGM_RAM_CONFLICT);
2181 /* next */
2182 pRomPrev = pRom;
2183 pRom = pRom->pNextR3;
2184 }
2185
2186 /*
2187 * Find the RAM location and check for conflicts.
2188 *
2189 * Conflict detection is a bit different than for RAM
2190 * registration since a ROM can be located within a RAM
2191 * range. So, what we have to check for is other memory
2192 * types (other than RAM that is) and that we don't span
2193 * more than one RAM range (layz).
2194 */
2195 bool fRamExists = false;
2196 PPGMRAMRANGE pRamPrev = NULL;
2197 PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
2198 while (pRam && GCPhysLast >= pRam->GCPhys)
2199 {
2200 if ( GCPhys <= pRam->GCPhysLast
2201 && GCPhysLast >= pRam->GCPhys)
2202 {
2203 /* completely within? */
2204 AssertLogRelMsgReturn( GCPhys >= pRam->GCPhys
2205 && GCPhysLast <= pRam->GCPhysLast,
2206 ("%RGp-%RGp (%s) falls partly outside %RGp-%RGp (%s)\n",
2207 GCPhys, GCPhysLast, pszDesc,
2208 pRam->GCPhys, pRam->GCPhysLast, pRam->pszDesc),
2209 VERR_PGM_RAM_CONFLICT);
2210 fRamExists = true;
2211 break;
2212 }
2213
2214 /* next */
2215 pRamPrev = pRam;
2216 pRam = pRam->pNextR3;
2217 }
2218 if (fRamExists)
2219 {
2220 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2221 uint32_t cPagesLeft = cPages;
2222 while (cPagesLeft-- > 0)
2223 {
2224 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM,
2225 ("%RGp (%R[pgmpage]) isn't a RAM page - registering %RGp-%RGp (%s).\n",
2226 pRam->GCPhys + ((RTGCPHYS)(uintptr_t)(pPage - &pRam->aPages[0]) << PAGE_SHIFT),
2227 pPage, GCPhys, GCPhysLast, pszDesc), VERR_PGM_RAM_CONFLICT);
2228 Assert(PGM_PAGE_IS_ZERO(pPage));
2229 pPage++;
2230 }
2231 }
2232
2233 /*
2234 * Update the base memory reservation if necessary.
2235 */
2236 uint32_t cExtraBaseCost = fRamExists ? cPages : 0;
2237 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2238 cExtraBaseCost += cPages;
2239 if (cExtraBaseCost)
2240 {
2241 int rc = MMR3IncreaseBaseReservation(pVM, cExtraBaseCost);
2242 if (RT_FAILURE(rc))
2243 return rc;
2244 }
2245
2246 /*
2247 * Allocate memory for the virgin copy of the RAM.
2248 */
2249 PGMMALLOCATEPAGESREQ pReq;
2250 int rc = GMMR3AllocatePagesPrepare(pVM, &pReq, cPages, GMMACCOUNT_BASE);
2251 AssertRCReturn(rc, rc);
2252
2253 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2254 {
2255 pReq->aPages[iPage].HCPhysGCPhys = GCPhys + (iPage << PAGE_SHIFT);
2256 pReq->aPages[iPage].idPage = NIL_GMM_PAGEID;
2257 pReq->aPages[iPage].idSharedPage = NIL_GMM_PAGEID;
2258 }
2259
2260 pgmLock(pVM);
2261 rc = GMMR3AllocatePagesPerform(pVM, pReq);
2262 pgmUnlock(pVM);
2263 if (RT_FAILURE(rc))
2264 {
2265 GMMR3AllocatePagesCleanup(pReq);
2266 return rc;
2267 }
2268
2269 /*
2270 * Allocate the new ROM range and RAM range (if necessary).
2271 */
2272 PPGMROMRANGE pRomNew;
2273 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMROMRANGE, aPages[cPages]), 0, MM_TAG_PGM_PHYS, (void **)&pRomNew);
2274 if (RT_SUCCESS(rc))
2275 {
2276 PPGMRAMRANGE pRamNew = NULL;
2277 if (!fRamExists)
2278 rc = MMHyperAlloc(pVM, RT_OFFSETOF(PGMRAMRANGE, aPages[cPages]), sizeof(PGMPAGE), MM_TAG_PGM_PHYS, (void **)&pRamNew);
2279 if (RT_SUCCESS(rc))
2280 {
2281 pgmLock(pVM);
2282
2283 /*
2284 * Initialize and insert the RAM range (if required).
2285 */
2286 PPGMROMPAGE pRomPage = &pRomNew->aPages[0];
2287 if (!fRamExists)
2288 {
2289 pRamNew->pSelfR0 = MMHyperCCToR0(pVM, pRamNew);
2290 pRamNew->pSelfRC = MMHyperCCToRC(pVM, pRamNew);
2291 pRamNew->GCPhys = GCPhys;
2292 pRamNew->GCPhysLast = GCPhysLast;
2293 pRamNew->cb = cb;
2294 pRamNew->pszDesc = pszDesc;
2295 pRamNew->fFlags = PGM_RAM_RANGE_FLAGS_AD_HOC_ROM;
2296 pRamNew->pvR3 = NULL;
2297 pRamNew->paLSPages = NULL;
2298
2299 PPGMPAGE pPage = &pRamNew->aPages[0];
2300 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2301 {
2302 PGM_PAGE_INIT(pPage,
2303 pReq->aPages[iPage].HCPhysGCPhys,
2304 pReq->aPages[iPage].idPage,
2305 PGMPAGETYPE_ROM,
2306 PGM_PAGE_STATE_ALLOCATED);
2307
2308 pRomPage->Virgin = *pPage;
2309 }
2310
2311 pVM->pgm.s.cAllPages += cPages;
2312 pgmR3PhysLinkRamRange(pVM, pRamNew, pRamPrev);
2313 }
2314 else
2315 {
2316 PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2317 for (uint32_t iPage = 0; iPage < cPages; iPage++, pPage++, pRomPage++)
2318 {
2319 PGM_PAGE_SET_TYPE(pPage, PGMPAGETYPE_ROM);
2320 PGM_PAGE_SET_HCPHYS(pPage, pReq->aPages[iPage].HCPhysGCPhys);
2321 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ALLOCATED);
2322 PGM_PAGE_SET_PAGEID(pPage, pReq->aPages[iPage].idPage);
2323
2324 pRomPage->Virgin = *pPage;
2325 }
2326
2327 pRamNew = pRam;
2328
2329 pVM->pgm.s.cZeroPages -= cPages;
2330 }
2331 pVM->pgm.s.cPrivatePages += cPages;
2332
2333 pgmUnlock(pVM);
2334
2335
2336 /*
2337 * !HACK ALERT! REM + (Shadowed) ROM ==> mess.
2338 *
2339 * If it's shadowed we'll register the handler after the ROM notification
2340 * so we get the access handler callbacks that we should. If it isn't
2341 * shadowed we'll do it the other way around to make REM use the built-in
2342 * ROM behavior and not the handler behavior (which is to route all access
2343 * to PGM atm).
2344 */
2345 if (fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2346 {
2347 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, true /* fShadowed */);
2348 rc = PGMR3HandlerPhysicalRegister(pVM,
2349 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2350 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2351 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2352 GCPhys, GCPhysLast,
2353 pgmR3PhysRomWriteHandler, pRomNew,
2354 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2355 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2356 }
2357 else
2358 {
2359 rc = PGMR3HandlerPhysicalRegister(pVM,
2360 fFlags & PGMPHYS_ROM_FLAGS_SHADOWED
2361 ? PGMPHYSHANDLERTYPE_PHYSICAL_ALL
2362 : PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
2363 GCPhys, GCPhysLast,
2364 pgmR3PhysRomWriteHandler, pRomNew,
2365 NULL, "pgmPhysRomWriteHandler", MMHyperCCToR0(pVM, pRomNew),
2366 NULL, "pgmPhysRomWriteHandler", MMHyperCCToRC(pVM, pRomNew), pszDesc);
2367 REMR3NotifyPhysRomRegister(pVM, GCPhys, cb, NULL, false /* fShadowed */);
2368 }
2369 if (RT_SUCCESS(rc))
2370 {
2371 pgmLock(pVM);
2372
2373 /*
2374 * Copy the image over to the virgin pages.
2375 * This must be done after linking in the RAM range.
2376 */
2377 PPGMPAGE pRamPage = &pRamNew->aPages[(GCPhys - pRamNew->GCPhys) >> PAGE_SHIFT];
2378 for (uint32_t iPage = 0; iPage < cPages; iPage++, pRamPage++)
2379 {
2380 void *pvDstPage;
2381 rc = pgmPhysPageMap(pVM, pRamPage, GCPhys + (iPage << PAGE_SHIFT), &pvDstPage);
2382 if (RT_FAILURE(rc))
2383 {
2384 VMSetError(pVM, rc, RT_SRC_POS, "Failed to map virgin ROM page at %RGp", GCPhys);
2385 break;
2386 }
2387 memcpy(pvDstPage, (const uint8_t *)pvBinary + (iPage << PAGE_SHIFT), PAGE_SIZE);
2388 }
2389 if (RT_SUCCESS(rc))
2390 {
2391 /*
2392 * Initialize the ROM range.
2393 * Note that the Virgin member of the pages has already been initialized above.
2394 */
2395 pRomNew->GCPhys = GCPhys;
2396 pRomNew->GCPhysLast = GCPhysLast;
2397 pRomNew->cb = cb;
2398 pRomNew->fFlags = fFlags;
2399 pRomNew->idSavedState = UINT8_MAX;
2400 pRomNew->pvOriginal = fFlags & PGMPHYS_ROM_FLAGS_PERMANENT_BINARY ? pvBinary : NULL;
2401 pRomNew->pszDesc = pszDesc;
2402
2403 for (unsigned iPage = 0; iPage < cPages; iPage++)
2404 {
2405 PPGMROMPAGE pPage = &pRomNew->aPages[iPage];
2406 pPage->enmProt = PGMROMPROT_READ_ROM_WRITE_IGNORE;
2407 PGM_PAGE_INIT_ZERO(&pPage->Shadow, pVM, PGMPAGETYPE_ROM_SHADOW);
2408 }
2409
2410 /* update the page count stats */
2411 pVM->pgm.s.cZeroPages += cPages;
2412 pVM->pgm.s.cAllPages += cPages;
2413
2414 /*
2415 * Insert the ROM range, tell REM and return successfully.
2416 */
2417 pRomNew->pNextR3 = pRom;
2418 pRomNew->pNextR0 = pRom ? MMHyperCCToR0(pVM, pRom) : NIL_RTR0PTR;
2419 pRomNew->pNextRC = pRom ? MMHyperCCToRC(pVM, pRom) : NIL_RTRCPTR;
2420
2421 if (pRomPrev)
2422 {
2423 pRomPrev->pNextR3 = pRomNew;
2424 pRomPrev->pNextR0 = MMHyperCCToR0(pVM, pRomNew);
2425 pRomPrev->pNextRC = MMHyperCCToRC(pVM, pRomNew);
2426 }
2427 else
2428 {
2429 pVM->pgm.s.pRomRangesR3 = pRomNew;
2430 pVM->pgm.s.pRomRangesR0 = MMHyperCCToR0(pVM, pRomNew);
2431 pVM->pgm.s.pRomRangesRC = MMHyperCCToRC(pVM, pRomNew);
2432 }
2433
2434 PGMPhysInvalidatePageMapTLB(pVM);
2435 GMMR3AllocatePagesCleanup(pReq);
2436 pgmUnlock(pVM);
2437 return VINF_SUCCESS;
2438 }
2439
2440 /* bail out */
2441
2442 pgmUnlock(pVM);
2443 int rc2 = PGMHandlerPhysicalDeregister(pVM, GCPhys);
2444 AssertRC(rc2);
2445 pgmLock(pVM);
2446 }
2447
2448 if (!fRamExists)
2449 {
2450 pgmR3PhysUnlinkRamRange2(pVM, pRamNew, pRamPrev);
2451 MMHyperFree(pVM, pRamNew);
2452 }
2453 }
2454 MMHyperFree(pVM, pRomNew);
2455 }
2456
2457 /** @todo Purge the mapping cache or something... */
2458 GMMR3FreeAllocatedPages(pVM, pReq);
2459 GMMR3AllocatePagesCleanup(pReq);
2460 pgmUnlock(pVM);
2461 return rc;
2462}
2463
2464
2465/**
2466 * \#PF Handler callback for ROM write accesses.
2467 *
2468 * @returns VINF_SUCCESS if the handler have carried out the operation.
2469 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2470 * @param pVM VM Handle.
2471 * @param GCPhys The physical address the guest is writing to.
2472 * @param pvPhys The HC mapping of that address.
2473 * @param pvBuf What the guest is reading/writing.
2474 * @param cbBuf How much it's reading/writing.
2475 * @param enmAccessType The access type.
2476 * @param pvUser User argument.
2477 */
2478static DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
2479{
2480 PPGMROMRANGE pRom = (PPGMROMRANGE)pvUser;
2481 const uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2482 Assert(iPage < (pRom->cb >> PAGE_SHIFT));
2483 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2484 Log5(("pgmR3PhysRomWriteHandler: %d %c %#08RGp %#04zx\n", pRomPage->enmProt, enmAccessType == PGMACCESSTYPE_READ ? 'R' : 'W', GCPhys, cbBuf));
2485
2486 if (enmAccessType == PGMACCESSTYPE_READ)
2487 {
2488 switch (pRomPage->enmProt)
2489 {
2490 /*
2491 * Take the default action.
2492 */
2493 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2494 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2495 case PGMROMPROT_READ_ROM_WRITE_RAM:
2496 case PGMROMPROT_READ_RAM_WRITE_RAM:
2497 return VINF_PGM_HANDLER_DO_DEFAULT;
2498
2499 default:
2500 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2501 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2502 VERR_INTERNAL_ERROR);
2503 }
2504 }
2505 else
2506 {
2507 Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2508 switch (pRomPage->enmProt)
2509 {
2510 /*
2511 * Ignore writes.
2512 */
2513 case PGMROMPROT_READ_ROM_WRITE_IGNORE:
2514 case PGMROMPROT_READ_RAM_WRITE_IGNORE:
2515 return VINF_SUCCESS;
2516
2517 /*
2518 * Write to the ram page.
2519 */
2520 case PGMROMPROT_READ_ROM_WRITE_RAM:
2521 case PGMROMPROT_READ_RAM_WRITE_RAM: /* yes this will get here too, it's *way* simpler that way. */
2522 {
2523 /* This should be impossible now, pvPhys doesn't work cross page anylonger. */
2524 Assert(((GCPhys - pRom->GCPhys + cbBuf - 1) >> PAGE_SHIFT) == iPage);
2525
2526 /*
2527 * Take the lock, do lazy allocation, map the page and copy the data.
2528 *
2529 * Note that we have to bypass the mapping TLB since it works on
2530 * guest physical addresses and entering the shadow page would
2531 * kind of screw things up...
2532 */
2533 int rc = pgmLock(pVM);
2534 AssertRC(rc);
2535
2536 PPGMPAGE pShadowPage = &pRomPage->Shadow;
2537 if (!PGMROMPROT_IS_ROM(pRomPage->enmProt))
2538 {
2539 pShadowPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
2540 AssertLogRelReturn(pShadowPage, VERR_INTERNAL_ERROR);
2541 }
2542
2543 void *pvDstPage;
2544 rc = pgmPhysPageMakeWritableAndMap(pVM, pShadowPage, GCPhys & X86_PTE_PG_MASK, &pvDstPage);
2545 if (RT_SUCCESS(rc))
2546 {
2547 memcpy((uint8_t *)pvDstPage + (GCPhys & PAGE_OFFSET_MASK), pvBuf, cbBuf);
2548 pRomPage->LiveSave.fWrittenTo = true;
2549 }
2550
2551 pgmUnlock(pVM);
2552 return rc;
2553 }
2554
2555 default:
2556 AssertMsgFailedReturn(("enmProt=%d iPage=%d GCPhys=%RGp\n",
2557 pRom->aPages[iPage].enmProt, iPage, GCPhys),
2558 VERR_INTERNAL_ERROR);
2559 }
2560 }
2561}
2562
2563
2564/**
2565 * Called by PGMR3Reset to reset the shadow, switch to the virgin,
2566 * and verify that the virgin part is untouched.
2567 *
2568 * This is done after the normal memory has been cleared.
2569 *
2570 * ASSUMES that the caller owns the PGM lock.
2571 *
2572 * @param pVM The VM handle.
2573 */
2574int pgmR3PhysRomReset(PVM pVM)
2575{
2576 Assert(PGMIsLockOwner(pVM));
2577 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2578 {
2579 const uint32_t cPages = pRom->cb >> PAGE_SHIFT;
2580
2581 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
2582 {
2583 /*
2584 * Reset the physical handler.
2585 */
2586 int rc = PGMR3PhysRomProtect(pVM, pRom->GCPhys, pRom->cb, PGMROMPROT_READ_ROM_WRITE_IGNORE);
2587 AssertRCReturn(rc, rc);
2588
2589 /*
2590 * What we do with the shadow pages depends on the memory
2591 * preallocation option. If not enabled, we'll just throw
2592 * out all the dirty pages and replace them by the zero page.
2593 */
2594 if (!pVM->pgm.s.fRamPreAlloc)
2595 {
2596 /* Free the dirty pages. */
2597 uint32_t cPendingPages = 0;
2598 PGMMFREEPAGESREQ pReq;
2599 rc = GMMR3FreePagesPrepare(pVM, &pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
2600 AssertRCReturn(rc, rc);
2601
2602 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2603 if (PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO)
2604 {
2605 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) == PGM_PAGE_STATE_ALLOCATED);
2606 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, &pRom->aPages[iPage].Shadow, pRom->GCPhys + (iPage << PAGE_SHIFT));
2607 AssertLogRelRCReturn(rc, rc);
2608 }
2609
2610 if (cPendingPages)
2611 {
2612 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2613 AssertLogRelRCReturn(rc, rc);
2614 }
2615 GMMR3FreePagesCleanup(pReq);
2616 }
2617 else
2618 {
2619 /* clear all the shadow pages. */
2620 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2621 {
2622 Assert(PGM_PAGE_GET_STATE(&pRom->aPages[iPage].Shadow) != PGM_PAGE_STATE_ZERO);
2623 void *pvDstPage;
2624 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2625 rc = pgmPhysPageMakeWritableAndMap(pVM, &pRom->aPages[iPage].Shadow, GCPhys, &pvDstPage);
2626 if (RT_FAILURE(rc))
2627 break;
2628 ASMMemZeroPage(pvDstPage);
2629 }
2630 AssertRCReturn(rc, rc);
2631 }
2632 }
2633
2634#ifdef VBOX_STRICT
2635 /*
2636 * Verify that the virgin page is unchanged if possible.
2637 */
2638 if (pRom->pvOriginal)
2639 {
2640 uint8_t const *pbSrcPage = (uint8_t const *)pRom->pvOriginal;
2641 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbSrcPage += PAGE_SIZE)
2642 {
2643 const RTGCPHYS GCPhys = pRom->GCPhys + (iPage << PAGE_SHIFT);
2644 void const *pvDstPage;
2645 int rc = pgmPhysPageMapReadOnly(pVM, &pRom->aPages[iPage].Virgin, GCPhys, &pvDstPage);
2646 if (RT_FAILURE(rc))
2647 break;
2648 if (memcmp(pvDstPage, pbSrcPage, PAGE_SIZE))
2649 LogRel(("pgmR3PhysRomReset: %RGp rom page changed (%s) - loaded saved state?\n",
2650 GCPhys, pRom->pszDesc));
2651 }
2652 }
2653#endif
2654 }
2655
2656 return VINF_SUCCESS;
2657}
2658
2659
2660/**
2661 * Change the shadowing of a range of ROM pages.
2662 *
2663 * This is intended for implementing chipset specific memory registers
2664 * and will not be very strict about the input. It will silently ignore
2665 * any pages that are not the part of a shadowed ROM.
2666 *
2667 * @returns VBox status code.
2668 * @retval VINF_PGM_SYNC_CR3
2669 *
2670 * @param pVM Pointer to the shared VM structure.
2671 * @param GCPhys Where to start. Page aligned.
2672 * @param cb How much to change. Page aligned.
2673 * @param enmProt The new ROM protection.
2674 */
2675VMMR3DECL(int) PGMR3PhysRomProtect(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, PGMROMPROT enmProt)
2676{
2677 /*
2678 * Check input
2679 */
2680 if (!cb)
2681 return VINF_SUCCESS;
2682 AssertReturn(!(GCPhys & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2683 AssertReturn(!(cb & PAGE_OFFSET_MASK), VERR_INVALID_PARAMETER);
2684 RTGCPHYS GCPhysLast = GCPhys + (cb - 1);
2685 AssertReturn(GCPhysLast > GCPhys, VERR_INVALID_PARAMETER);
2686 AssertReturn(enmProt >= PGMROMPROT_INVALID && enmProt <= PGMROMPROT_END, VERR_INVALID_PARAMETER);
2687
2688 /*
2689 * Process the request.
2690 */
2691 pgmLock(pVM);
2692 int rc = VINF_SUCCESS;
2693 bool fFlushTLB = false;
2694 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2695 {
2696 if ( GCPhys <= pRom->GCPhysLast
2697 && GCPhysLast >= pRom->GCPhys
2698 && (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
2699 {
2700 /*
2701 * Iterate the relevant pages and make necessary the changes.
2702 */
2703 bool fChanges = false;
2704 uint32_t const cPages = pRom->GCPhysLast <= GCPhysLast
2705 ? pRom->cb >> PAGE_SHIFT
2706 : (GCPhysLast - pRom->GCPhys + 1) >> PAGE_SHIFT;
2707 for (uint32_t iPage = (GCPhys - pRom->GCPhys) >> PAGE_SHIFT;
2708 iPage < cPages;
2709 iPage++)
2710 {
2711 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2712 if (PGMROMPROT_IS_ROM(pRomPage->enmProt) != PGMROMPROT_IS_ROM(enmProt))
2713 {
2714 fChanges = true;
2715
2716 /* flush references to the page. */
2717 PPGMPAGE pRamPage = pgmPhysGetPage(&pVM->pgm.s, pRom->GCPhys + (iPage << PAGE_SHIFT));
2718 int rc2 = pgmPoolTrackFlushGCPhys(pVM, pRamPage, &fFlushTLB);
2719 if (rc2 != VINF_SUCCESS && (rc == VINF_SUCCESS || RT_FAILURE(rc2)))
2720 rc = rc2;
2721
2722 PPGMPAGE pOld = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2723 PPGMPAGE pNew = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2724
2725 *pOld = *pRamPage;
2726 *pRamPage = *pNew;
2727 /** @todo preserve the volatile flags (handlers) when these have been moved out of HCPhys! */
2728 }
2729 pRomPage->enmProt = enmProt;
2730 }
2731
2732 /*
2733 * Reset the access handler if we made changes, no need
2734 * to optimize this.
2735 */
2736 if (fChanges)
2737 {
2738 int rc2 = PGMHandlerPhysicalReset(pVM, pRom->GCPhys);
2739 if (RT_FAILURE(rc2))
2740 {
2741 pgmUnlock(pVM);
2742 AssertRC(rc);
2743 return rc2;
2744 }
2745 }
2746
2747 /* Advance - cb isn't updated. */
2748 GCPhys = pRom->GCPhys + (cPages << PAGE_SHIFT);
2749 }
2750 }
2751 pgmUnlock(pVM);
2752 if (fFlushTLB)
2753 PGM_INVL_ALL_VCPU_TLBS(pVM);
2754
2755 return rc;
2756}
2757
2758
2759/**
2760 * Sets the Address Gate 20 state.
2761 *
2762 * @param pVCpu The VCPU to operate on.
2763 * @param fEnable True if the gate should be enabled.
2764 * False if the gate should be disabled.
2765 */
2766VMMDECL(void) PGMR3PhysSetA20(PVMCPU pVCpu, bool fEnable)
2767{
2768 LogFlow(("PGMR3PhysSetA20 %d (was %d)\n", fEnable, pVCpu->pgm.s.fA20Enabled));
2769 if (pVCpu->pgm.s.fA20Enabled != fEnable)
2770 {
2771 pVCpu->pgm.s.fA20Enabled = fEnable;
2772 pVCpu->pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!fEnable << 20);
2773 REMR3A20Set(pVCpu->pVMR3, pVCpu, fEnable);
2774 /** @todo we're not handling this correctly for VT-x / AMD-V. See #2911 */
2775 }
2776}
2777
2778
2779/**
2780 * Tree enumeration callback for dealing with age rollover.
2781 * It will perform a simple compression of the current age.
2782 */
2783static DECLCALLBACK(int) pgmR3PhysChunkAgeingRolloverCallback(PAVLU32NODECORE pNode, void *pvUser)
2784{
2785 Assert(PGMIsLockOwner((PVM)pvUser));
2786 /* Age compression - ASSUMES iNow == 4. */
2787 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2788 if (pChunk->iAge >= UINT32_C(0xffffff00))
2789 pChunk->iAge = 3;
2790 else if (pChunk->iAge >= UINT32_C(0xfffff000))
2791 pChunk->iAge = 2;
2792 else if (pChunk->iAge)
2793 pChunk->iAge = 1;
2794 else /* iAge = 0 */
2795 pChunk->iAge = 4;
2796
2797 /* reinsert */
2798 PVM pVM = (PVM)pvUser;
2799 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2800 pChunk->AgeCore.Key = pChunk->iAge;
2801 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2802 return 0;
2803}
2804
2805
2806/**
2807 * Tree enumeration callback that updates the chunks that have
2808 * been used since the last
2809 */
2810static DECLCALLBACK(int) pgmR3PhysChunkAgeingCallback(PAVLU32NODECORE pNode, void *pvUser)
2811{
2812 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)pNode;
2813 if (!pChunk->iAge)
2814 {
2815 PVM pVM = (PVM)pvUser;
2816 RTAvllU32Remove(&pVM->pgm.s.ChunkR3Map.pAgeTree, pChunk->AgeCore.Key);
2817 pChunk->AgeCore.Key = pChunk->iAge = pVM->pgm.s.ChunkR3Map.iNow;
2818 RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2819 }
2820
2821 return 0;
2822}
2823
2824
2825/**
2826 * Performs ageing of the ring-3 chunk mappings.
2827 *
2828 * @param pVM The VM handle.
2829 */
2830VMMR3DECL(void) PGMR3PhysChunkAgeing(PVM pVM)
2831{
2832 pgmLock(pVM);
2833 pVM->pgm.s.ChunkR3Map.AgeingCountdown = RT_MIN(pVM->pgm.s.ChunkR3Map.cMax / 4, 1024);
2834 pVM->pgm.s.ChunkR3Map.iNow++;
2835 if (pVM->pgm.s.ChunkR3Map.iNow == 0)
2836 {
2837 pVM->pgm.s.ChunkR3Map.iNow = 4;
2838 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingRolloverCallback, pVM);
2839 }
2840 else
2841 RTAvlU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pTree, true /*fFromLeft*/, pgmR3PhysChunkAgeingCallback, pVM);
2842 pgmUnlock(pVM);
2843}
2844
2845
2846/**
2847 * The structure passed in the pvUser argument of pgmR3PhysChunkUnmapCandidateCallback().
2848 */
2849typedef struct PGMR3PHYSCHUNKUNMAPCB
2850{
2851 PVM pVM; /**< The VM handle. */
2852 PPGMCHUNKR3MAP pChunk; /**< The chunk to unmap. */
2853} PGMR3PHYSCHUNKUNMAPCB, *PPGMR3PHYSCHUNKUNMAPCB;
2854
2855
2856/**
2857 * Callback used to find the mapping that's been unused for
2858 * the longest time.
2859 */
2860static DECLCALLBACK(int) pgmR3PhysChunkUnmapCandidateCallback(PAVLLU32NODECORE pNode, void *pvUser)
2861{
2862 do
2863 {
2864 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)((uint8_t *)pNode - RT_OFFSETOF(PGMCHUNKR3MAP, AgeCore));
2865 if ( pChunk->iAge
2866 && !pChunk->cRefs)
2867 {
2868 /*
2869 * Check that it's not in any of the TLBs.
2870 */
2871 PVM pVM = ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pVM;
2872 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
2873 if (pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk == pChunk)
2874 {
2875 pChunk = NULL;
2876 break;
2877 }
2878 if (pChunk)
2879 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.PhysTlbHC.aEntries); i++)
2880 if (pVM->pgm.s.PhysTlbHC.aEntries[i].pMap == pChunk)
2881 {
2882 pChunk = NULL;
2883 break;
2884 }
2885 if (pChunk)
2886 {
2887 ((PPGMR3PHYSCHUNKUNMAPCB)pvUser)->pChunk = pChunk;
2888 return 1; /* done */
2889 }
2890 }
2891
2892 /* next with the same age - this version of the AVL API doesn't enumerate the list, so we have to do it. */
2893 pNode = pNode->pList;
2894 } while (pNode);
2895 return 0;
2896}
2897
2898
2899/**
2900 * Finds a good candidate for unmapping when the ring-3 mapping cache is full.
2901 *
2902 * The candidate will not be part of any TLBs, so no need to flush
2903 * anything afterwards.
2904 *
2905 * @returns Chunk id.
2906 * @param pVM The VM handle.
2907 */
2908static int32_t pgmR3PhysChunkFindUnmapCandidate(PVM pVM)
2909{
2910 Assert(PGMIsLockOwner(pVM));
2911
2912 /*
2913 * Do tree ageing first?
2914 */
2915 if (pVM->pgm.s.ChunkR3Map.AgeingCountdown-- == 0)
2916 PGMR3PhysChunkAgeing(pVM);
2917
2918 /*
2919 * Enumerate the age tree starting with the left most node.
2920 */
2921 PGMR3PHYSCHUNKUNMAPCB Args;
2922 Args.pVM = pVM;
2923 Args.pChunk = NULL;
2924 if (RTAvllU32DoWithAll(&pVM->pgm.s.ChunkR3Map.pAgeTree, true /*fFromLeft*/, pgmR3PhysChunkUnmapCandidateCallback, pVM))
2925 return Args.pChunk->Core.Key;
2926 return INT32_MAX;
2927}
2928
2929
2930/**
2931 * Maps the given chunk into the ring-3 mapping cache.
2932 *
2933 * This will call ring-0.
2934 *
2935 * @returns VBox status code.
2936 * @param pVM The VM handle.
2937 * @param idChunk The chunk in question.
2938 * @param ppChunk Where to store the chunk tracking structure.
2939 *
2940 * @remarks Called from within the PGM critical section.
2941 */
2942int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk)
2943{
2944 int rc;
2945
2946 Assert(PGMIsLockOwner(pVM));
2947 /*
2948 * Allocate a new tracking structure first.
2949 */
2950#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2951 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3HeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk));
2952#else
2953 PPGMCHUNKR3MAP pChunk = (PPGMCHUNKR3MAP)MMR3UkHeapAlloc(pVM, MM_TAG_PGM_CHUNK_MAPPING, sizeof(*pChunk), NULL);
2954#endif
2955 AssertReturn(pChunk, VERR_NO_MEMORY);
2956 pChunk->Core.Key = idChunk;
2957 pChunk->AgeCore.Key = pVM->pgm.s.ChunkR3Map.iNow;
2958 pChunk->iAge = 0;
2959 pChunk->cRefs = 0;
2960 pChunk->cPermRefs = 0;
2961 pChunk->pv = NULL;
2962
2963 /*
2964 * Request the ring-0 part to map the chunk in question and if
2965 * necessary unmap another one to make space in the mapping cache.
2966 */
2967 GMMMAPUNMAPCHUNKREQ Req;
2968 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2969 Req.Hdr.cbReq = sizeof(Req);
2970 Req.pvR3 = NULL;
2971 Req.idChunkMap = idChunk;
2972 Req.idChunkUnmap = NIL_GMM_CHUNKID;
2973 if (pVM->pgm.s.ChunkR3Map.c >= pVM->pgm.s.ChunkR3Map.cMax)
2974 Req.idChunkUnmap = pgmR3PhysChunkFindUnmapCandidate(pVM);
2975/** @todo This is wrong. Any thread in the VM process should be able to do this,
2976 * there are depenenecies on this. What currently saves the day is that
2977 * we don't unmap anything and that all non-zero memory will therefore
2978 * be present when non-EMTs tries to access it. */
2979 rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_MAP_UNMAP_CHUNK, 0, &Req.Hdr);
2980 if (RT_SUCCESS(rc))
2981 {
2982 /*
2983 * Update the tree.
2984 */
2985 /* insert the new one. */
2986 AssertPtr(Req.pvR3);
2987 pChunk->pv = Req.pvR3;
2988 bool fRc = RTAvlU32Insert(&pVM->pgm.s.ChunkR3Map.pTree, &pChunk->Core);
2989 AssertRelease(fRc);
2990 pVM->pgm.s.ChunkR3Map.c++;
2991
2992 fRc = RTAvllU32Insert(&pVM->pgm.s.ChunkR3Map.pAgeTree, &pChunk->AgeCore);
2993 AssertRelease(fRc);
2994
2995 /* remove the unmapped one. */
2996 if (Req.idChunkUnmap != NIL_GMM_CHUNKID)
2997 {
2998 PPGMCHUNKR3MAP pUnmappedChunk = (PPGMCHUNKR3MAP)RTAvlU32Remove(&pVM->pgm.s.ChunkR3Map.pTree, Req.idChunkUnmap);
2999 AssertRelease(pUnmappedChunk);
3000 pUnmappedChunk->pv = NULL;
3001 pUnmappedChunk->Core.Key = UINT32_MAX;
3002#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3003 MMR3HeapFree(pUnmappedChunk);
3004#else
3005 MMR3UkHeapFree(pVM, pUnmappedChunk, MM_TAG_PGM_CHUNK_MAPPING);
3006#endif
3007 pVM->pgm.s.ChunkR3Map.c--;
3008 }
3009 }
3010 else
3011 {
3012 AssertRC(rc);
3013#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3014 MMR3HeapFree(pChunk);
3015#else
3016 MMR3UkHeapFree(pVM, pChunk, MM_TAG_PGM_CHUNK_MAPPING);
3017#endif
3018 pChunk = NULL;
3019 }
3020
3021 *ppChunk = pChunk;
3022 return rc;
3023}
3024
3025
3026/**
3027 * For VMMCALLRING3_PGM_MAP_CHUNK, considered internal.
3028 *
3029 * @returns see pgmR3PhysChunkMap.
3030 * @param pVM The VM handle.
3031 * @param idChunk The chunk to map.
3032 */
3033VMMR3DECL(int) PGMR3PhysChunkMap(PVM pVM, uint32_t idChunk)
3034{
3035 PPGMCHUNKR3MAP pChunk;
3036 int rc;
3037
3038 pgmLock(pVM);
3039 rc = pgmR3PhysChunkMap(pVM, idChunk, &pChunk);
3040 pgmUnlock(pVM);
3041 return rc;
3042}
3043
3044
3045/**
3046 * Invalidates the TLB for the ring-3 mapping cache.
3047 *
3048 * @param pVM The VM handle.
3049 */
3050VMMR3DECL(void) PGMR3PhysChunkInvalidateTLB(PVM pVM)
3051{
3052 pgmLock(pVM);
3053 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
3054 {
3055 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
3056 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].pChunk = NULL;
3057 }
3058 pgmUnlock(pVM);
3059}
3060
3061
3062/**
3063 * Response to VM_FF_PGM_NEED_HANDY_PAGES and VMMCALLRING3_PGM_ALLOCATE_HANDY_PAGES.
3064 *
3065 * This function will also work the VM_FF_PGM_NO_MEMORY force action flag, to
3066 * signal and clear the out of memory condition. When contracted, this API is
3067 * used to try clear the condition when the user wants to resume.
3068 *
3069 * @returns The following VBox status codes.
3070 * @retval VINF_SUCCESS on success. FFs cleared.
3071 * @retval VINF_EM_NO_MEMORY if we're out of memory. The FF is not cleared in
3072 * this case and it gets accompanied by VM_FF_PGM_NO_MEMORY.
3073 *
3074 * @param pVM The VM handle.
3075 *
3076 * @remarks The VINF_EM_NO_MEMORY status is for the benefit of the FF processing
3077 * in EM.cpp and shouldn't be propagated outside TRPM, HWACCM, EM and
3078 * pgmPhysEnsureHandyPage. There is one exception to this in the \#PF
3079 * handler.
3080 */
3081VMMR3DECL(int) PGMR3PhysAllocateHandyPages(PVM pVM)
3082{
3083 pgmLock(pVM);
3084
3085 /*
3086 * Allocate more pages, noting down the index of the first new page.
3087 */
3088 uint32_t iClear = pVM->pgm.s.cHandyPages;
3089 AssertMsgReturn(iClear <= RT_ELEMENTS(pVM->pgm.s.aHandyPages), ("%d", iClear), VERR_INTERNAL_ERROR);
3090 Log(("PGMR3PhysAllocateHandyPages: %d -> %d\n", iClear, RT_ELEMENTS(pVM->pgm.s.aHandyPages)));
3091 int rcAlloc = VINF_SUCCESS;
3092 int rcSeed = VINF_SUCCESS;
3093 int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3094 while (rc == VERR_GMM_SEED_ME)
3095 {
3096 void *pvChunk;
3097 rcAlloc = rc = SUPR3PageAlloc(GMM_CHUNK_SIZE >> PAGE_SHIFT, &pvChunk);
3098 if (RT_SUCCESS(rc))
3099 {
3100 rcSeed = rc = VMMR3CallR0(pVM, VMMR0_DO_GMM_SEED_CHUNK, (uintptr_t)pvChunk, NULL);
3101 if (RT_FAILURE(rc))
3102 SUPR3PageFree(pvChunk, GMM_CHUNK_SIZE >> PAGE_SHIFT);
3103 }
3104 if (RT_SUCCESS(rc))
3105 rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_ALLOCATE_HANDY_PAGES, 0, NULL);
3106 }
3107
3108 if (RT_SUCCESS(rc))
3109 {
3110 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc));
3111 Assert(pVM->pgm.s.cHandyPages > 0);
3112 VM_FF_CLEAR(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3113 VM_FF_CLEAR(pVM, VM_FF_PGM_NO_MEMORY);
3114
3115 /*
3116 * Clear the pages.
3117 */
3118 while (iClear < pVM->pgm.s.cHandyPages)
3119 {
3120 PGMMPAGEDESC pPage = &pVM->pgm.s.aHandyPages[iClear];
3121 void *pv;
3122 rc = pgmPhysPageMapByPageID(pVM, pPage->idPage, pPage->HCPhysGCPhys, &pv);
3123 AssertLogRelMsgBreak(RT_SUCCESS(rc), ("idPage=%#x HCPhysGCPhys=%RHp rc=%Rrc", pPage->idPage, pPage->HCPhysGCPhys, rc));
3124 ASMMemZeroPage(pv);
3125 iClear++;
3126 Log3(("PGMR3PhysAllocateHandyPages: idPage=%#x HCPhys=%RGp\n", pPage->idPage, pPage->HCPhysGCPhys));
3127 }
3128 }
3129 else
3130 {
3131 /*
3132 * We should never get here unless there is a genuine shortage of
3133 * memory (or some internal error). Flag the error so the VM can be
3134 * suspended ASAP and the user informed. If we're totally out of
3135 * handy pages we will return failure.
3136 */
3137 /* Report the failure. */
3138 LogRel(("PGM: Failed to procure handy pages; rc=%Rrc rcAlloc=%Rrc rcSeed=%Rrc cHandyPages=%#x\n"
3139 " cAllPages=%#x cPrivatePages=%#x cSharedPages=%#x cZeroPages=%#x\n",
3140 rc, rcAlloc, rcSeed,
3141 pVM->pgm.s.cHandyPages,
3142 pVM->pgm.s.cAllPages,
3143 pVM->pgm.s.cPrivatePages,
3144 pVM->pgm.s.cSharedPages,
3145 pVM->pgm.s.cZeroPages));
3146 if ( rc != VERR_NO_MEMORY
3147 && rc != VERR_LOCK_FAILED)
3148 {
3149 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3150 {
3151 LogRel(("PGM: aHandyPages[#%#04x] = {.HCPhysGCPhys=%RHp, .idPage=%#08x, .idSharedPage=%#08x}\n",
3152 i, pVM->pgm.s.aHandyPages[i].HCPhysGCPhys, pVM->pgm.s.aHandyPages[i].idPage,
3153 pVM->pgm.s.aHandyPages[i].idSharedPage));
3154 uint32_t const idPage = pVM->pgm.s.aHandyPages[i].idPage;
3155 if (idPage != NIL_GMM_PAGEID)
3156 {
3157 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
3158 pRam;
3159 pRam = pRam->pNextR3)
3160 {
3161 uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
3162 for (uint32_t iPage = 0; iPage < cPages; iPage++)
3163 if (PGM_PAGE_GET_PAGEID(&pRam->aPages[iPage]) == idPage)
3164 LogRel(("PGM: Used by %RGp %R[pgmpage] (%s)\n",
3165 pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pRam->aPages[iPage], pRam->pszDesc));
3166 }
3167 }
3168 }
3169 }
3170
3171 /* Set the FFs and adjust rc. */
3172 VM_FF_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES);
3173 VM_FF_SET(pVM, VM_FF_PGM_NO_MEMORY);
3174 if ( rc == VERR_NO_MEMORY
3175 || rc == VERR_LOCK_FAILED)
3176 rc = VINF_EM_NO_MEMORY;
3177 }
3178
3179 pgmUnlock(pVM);
3180 return rc;
3181}
3182
3183
3184/**
3185 * Frees the specified RAM page and replaces it with the ZERO page.
3186 *
3187 * This is used by ballooning, remapping MMIO2 and RAM reset.
3188 *
3189 * @param pVM Pointer to the shared VM structure.
3190 * @param pReq Pointer to the request.
3191 * @param pPage Pointer to the page structure.
3192 * @param GCPhys The guest physical address of the page, if applicable.
3193 *
3194 * @remarks The caller must own the PGM lock.
3195 */
3196static int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys)
3197{
3198 /*
3199 * Assert sanity.
3200 */
3201 Assert(PGMIsLockOwner(pVM));
3202 if (RT_UNLIKELY( PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_RAM
3203 && PGM_PAGE_GET_TYPE(pPage) != PGMPAGETYPE_ROM_SHADOW))
3204 {
3205 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3206 return VMSetError(pVM, VERR_PGM_PHYS_NOT_RAM, RT_SRC_POS, "GCPhys=%RGp type=%d", GCPhys, PGM_PAGE_GET_TYPE(pPage));
3207 }
3208
3209 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO)
3210 return VINF_SUCCESS;
3211
3212 const uint32_t idPage = PGM_PAGE_GET_PAGEID(pPage);
3213 Log3(("pgmPhysFreePage: idPage=%#x HCPhys=%RGp pPage=%R[pgmpage]\n", idPage, pPage));
3214 if (RT_UNLIKELY( idPage == NIL_GMM_PAGEID
3215 || idPage > GMM_PAGEID_LAST
3216 || PGM_PAGE_GET_CHUNKID(pPage) == NIL_GMM_CHUNKID))
3217 {
3218 AssertMsgFailed(("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, pPage));
3219 return VMSetError(pVM, VERR_PGM_PHYS_INVALID_PAGE_ID, RT_SRC_POS, "GCPhys=%RGp idPage=%#x", GCPhys, pPage);
3220 }
3221
3222 /* update page count stats. */
3223 if (PGM_PAGE_IS_SHARED(pPage))
3224 pVM->pgm.s.cSharedPages--;
3225 else
3226 pVM->pgm.s.cPrivatePages--;
3227 pVM->pgm.s.cZeroPages++;
3228
3229 /* Deal with write monitored pages. */
3230 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
3231 {
3232 PGM_PAGE_SET_WRITTEN_TO(pPage);
3233 pVM->pgm.s.cWrittenToPages++;
3234 }
3235
3236 /*
3237 * pPage = ZERO page.
3238 */
3239 PGM_PAGE_SET_HCPHYS(pPage, pVM->pgm.s.HCPhysZeroPg);
3240 PGM_PAGE_SET_STATE(pPage, PGM_PAGE_STATE_ZERO);
3241 PGM_PAGE_SET_PAGEID(pPage, NIL_GMM_PAGEID);
3242
3243 /*
3244 * Make sure it's not in the handy page array.
3245 */
3246 for (uint32_t i = pVM->pgm.s.cHandyPages; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
3247 {
3248 if (pVM->pgm.s.aHandyPages[i].idPage == idPage)
3249 {
3250 pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
3251 break;
3252 }
3253 if (pVM->pgm.s.aHandyPages[i].idSharedPage == idPage)
3254 {
3255 pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
3256 break;
3257 }
3258 }
3259
3260 /*
3261 * Push it onto the page array.
3262 */
3263 uint32_t iPage = *pcPendingPages;
3264 Assert(iPage < PGMPHYS_FREE_PAGE_BATCH_SIZE);
3265 *pcPendingPages += 1;
3266
3267 pReq->aPages[iPage].idPage = idPage;
3268
3269 if (iPage + 1 < PGMPHYS_FREE_PAGE_BATCH_SIZE)
3270 return VINF_SUCCESS;
3271
3272 /*
3273 * Flush the pages.
3274 */
3275 int rc = GMMR3FreePagesPerform(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE);
3276 if (RT_SUCCESS(rc))
3277 {
3278 GMMR3FreePagesRePrep(pVM, pReq, PGMPHYS_FREE_PAGE_BATCH_SIZE, GMMACCOUNT_BASE);
3279 *pcPendingPages = 0;
3280 }
3281 return rc;
3282}
3283
3284
3285/**
3286 * Converts a GC physical address to a HC ring-3 pointer, with some
3287 * additional checks.
3288 *
3289 * @returns VBox status code.
3290 * @retval VINF_SUCCESS on success.
3291 * @retval VINF_PGM_PHYS_TLB_CATCH_WRITE and *ppv set if the page has a write
3292 * access handler of some kind.
3293 * @retval VERR_PGM_PHYS_TLB_CATCH_ALL if the page has a handler catching all
3294 * accesses or is odd in any way.
3295 * @retval VERR_PGM_PHYS_TLB_UNASSIGNED if the page doesn't exist.
3296 *
3297 * @param pVM The VM handle.
3298 * @param GCPhys The GC physical address to convert.
3299 * @param fWritable Whether write access is required.
3300 * @param ppv Where to store the pointer corresponding to GCPhys on
3301 * success.
3302 */
3303VMMR3DECL(int) PGMR3PhysTlbGCPhys2Ptr(PVM pVM, RTGCPHYS GCPhys, bool fWritable, void **ppv)
3304{
3305 pgmLock(pVM);
3306
3307 PPGMRAMRANGE pRam;
3308 PPGMPAGE pPage;
3309 int rc = pgmPhysGetPageAndRangeEx(&pVM->pgm.s, GCPhys, &pPage, &pRam);
3310 if (RT_SUCCESS(rc))
3311 {
3312 if (!PGM_PAGE_HAS_ANY_HANDLERS(pPage))
3313 rc = VINF_SUCCESS;
3314 else
3315 {
3316 if (PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)) /* catches MMIO */
3317 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3318 else if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3319 {
3320 /** @todo Handle TLB loads of virtual handlers so ./test.sh can be made to work
3321 * in -norawr0 mode. */
3322 if (fWritable)
3323 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3324 }
3325 else
3326 {
3327 /* Temporarily disabled physical handler(s), since the recompiler
3328 doesn't get notified when it's reset we'll have to pretend it's
3329 operating normally. */
3330 if (pgmHandlerPhysicalIsAll(pVM, GCPhys))
3331 rc = VERR_PGM_PHYS_TLB_CATCH_ALL;
3332 else
3333 rc = VINF_PGM_PHYS_TLB_CATCH_WRITE;
3334 }
3335 }
3336 if (RT_SUCCESS(rc))
3337 {
3338 int rc2;
3339
3340 /* Make sure what we return is writable. */
3341 if (fWritable && rc != VINF_PGM_PHYS_TLB_CATCH_WRITE)
3342 switch (PGM_PAGE_GET_STATE(pPage))
3343 {
3344 case PGM_PAGE_STATE_ALLOCATED:
3345 break;
3346 case PGM_PAGE_STATE_ZERO:
3347 case PGM_PAGE_STATE_SHARED:
3348 case PGM_PAGE_STATE_WRITE_MONITORED:
3349 rc2 = pgmPhysPageMakeWritable(pVM, pPage, GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK);
3350 AssertLogRelRCReturn(rc2, rc2);
3351 break;
3352 }
3353
3354 /* Get a ring-3 mapping of the address. */
3355 PPGMPAGER3MAPTLBE pTlbe;
3356 rc2 = pgmPhysPageQueryTlbe(&pVM->pgm.s, GCPhys, &pTlbe);
3357 AssertLogRelRCReturn(rc2, rc2);
3358 *ppv = (void *)((uintptr_t)pTlbe->pv | (GCPhys & PAGE_OFFSET_MASK));
3359 /** @todo mapping/locking hell; this isn't horribly efficient since
3360 * pgmPhysPageLoadIntoTlb will repeat the lookup we've done here. */
3361
3362 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage] *ppv=%p\n", GCPhys, rc, pPage, *ppv));
3363 }
3364 else
3365 Log6(("PGMR3PhysTlbGCPhys2Ptr: GCPhys=%RGp rc=%Rrc pPage=%R[pgmpage]\n", GCPhys, rc, pPage));
3366
3367 /* else: handler catching all access, no pointer returned. */
3368 }
3369 else
3370 rc = VERR_PGM_PHYS_TLB_UNASSIGNED;
3371
3372 pgmUnlock(pVM);
3373 return rc;
3374}
3375
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