PGMInternal.h@ 15414

Last change on this file since 15414 was 15411, checked in by vboxsync, 16 years ago
VMM: Working around set overflows caused by the page pool.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 190.4 KB

Line
1	/* $Id: PGMInternal.h 15411 2008-12-13 03:30:58Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___PGMInternal_h
23	#define ___PGMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/err.h>
28	#include <VBox/stam.h>
29	#include <VBox/param.h>
30	#include <VBox/vmm.h>
31	#include <VBox/mm.h>
32	#include <VBox/pdmcritsect.h>
33	#include <VBox/pdmapi.h>
34	#include <VBox/dis.h>
35	#include <VBox/dbgf.h>
36	#include <VBox/log.h>
37	#include <VBox/gmm.h>
38	#include <VBox/hwaccm.h>
39	#include <iprt/avl.h>
40	#include <iprt/assert.h>
41	#include <iprt/critsect.h>
42
43
44
45	/** @defgroup grp_pgm_int Internals
46	* @ingroup grp_pgm
47	* @internal
48	* @{
49	*/
50
51
52	/** @name PGM Compile Time Config
53	* @{
54	*/
55
56	/**
57	* Solve page is out of sync issues inside Guest Context (in PGMGC.cpp).
58	* Comment it if it will break something.
59	*/
60	#define PGM_OUT_OF_SYNC_IN_GC
61
62	/**
63	* Check and skip global PDEs for non-global flushes
64	*/
65	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
66
67	/**
68	* Sync N pages instead of a whole page table
69	*/
70	#define PGM_SYNC_N_PAGES
71
72	/**
73	* Number of pages to sync during a page fault
74	*
75	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
76	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
77	*/
78	#define PGM_SYNC_NR_PAGES 8
79
80	/**
81	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
82	*/
83	#define PGM_MAX_PHYSCACHE_ENTRIES 64
84	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
85
86	/**
87	* Enable caching of PGMR3PhysRead/WriteByte/Word/Dword
88	*/
89	#define PGM_PHYSMEMACCESS_CACHING
90
91	/** @def PGMPOOL_WITH_CACHE
92	* Enable agressive caching using the page pool.
93	*
94	* This requires PGMPOOL_WITH_USER_TRACKING and PGMPOOL_WITH_MONITORING.
95	*/
96	#define PGMPOOL_WITH_CACHE
97
98	/** @def PGMPOOL_WITH_MIXED_PT_CR3
99	* When defined, we'll deal with 'uncachable' pages.
100	*/
101	#ifdef PGMPOOL_WITH_CACHE
102	# define PGMPOOL_WITH_MIXED_PT_CR3
103	#endif
104
105	/** @def PGMPOOL_WITH_MONITORING
106	* Monitor the guest pages which are shadowed.
107	* When this is enabled, PGMPOOL_WITH_CACHE or PGMPOOL_WITH_GCPHYS_TRACKING must
108	* be enabled as well.
109	* @remark doesn't really work without caching now. (Mixed PT/CR3 change.)
110	*/
111	#ifdef PGMPOOL_WITH_CACHE
112	# define PGMPOOL_WITH_MONITORING
113	#endif
114
115	/** @def PGMPOOL_WITH_GCPHYS_TRACKING
116	* Tracking the of shadow pages mapping guest physical pages.
117	*
118	* This is very expensive, the current cache prototype is trying to figure out
119	* whether it will be acceptable with an agressive caching policy.
120	*/
121	#if defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
122	# define PGMPOOL_WITH_GCPHYS_TRACKING
123	#endif
124
125	/** @def PGMPOOL_WITH_USER_TRACKING
126	* Tracking users of shadow pages. This is required for the linking of shadow page
127	* tables and physical guest addresses.
128	*/
129	#if defined(PGMPOOL_WITH_GCPHYS_TRACKING) \|\| defined(PGMPOOL_WITH_CACHE) \|\| defined(PGMPOOL_WITH_MONITORING)
130	# define PGMPOOL_WITH_USER_TRACKING
131	#endif
132
133	/** @def PGMPOOL_CFG_MAX_GROW
134	* The maximum number of pages to add to the pool in one go.
135	*/
136	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
137
138	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
139	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
140	*/
141	#ifdef VBOX_STRICT
142	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
143	#endif
144	/** @} */
145
146
147	/** @name PDPT and PML4 flags.
148	* These are placed in the three bits available for system programs in
149	* the PDPT and PML4 entries.
150	* @{ */
151	/** The entry is a permanent one and it's must always be present.
152	* Never free such an entry. */
153	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
154	/** Mapping (hypervisor allocated pagetable). */
155	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
156	/** @} */
157
158	/** @name Page directory flags.
159	* These are placed in the three bits available for system programs in
160	* the page directory entries.
161	* @{ */
162	/** Mapping (hypervisor allocated pagetable). */
163	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
164	/** Made read-only to facilitate dirty bit tracking. */
165	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
166	/** @} */
167
168	/** @name Page flags.
169	* These are placed in the three bits available for system programs in
170	* the page entries.
171	* @{ */
172	/** Made read-only to facilitate dirty bit tracking. */
173	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
174
175	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
176	/** Scanned and approved by CSAM (tm).
177	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
178	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/pgm.h. */
179	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
180	#endif
181	/** @} */
182
183	/** @name Defines used to indicate the shadow and guest paging in the templates.
184	* @{ */
185	#define PGM_TYPE_REAL 1
186	#define PGM_TYPE_PROT 2
187	#define PGM_TYPE_32BIT 3
188	#define PGM_TYPE_PAE 4
189	#define PGM_TYPE_AMD64 5
190	#define PGM_TYPE_NESTED 6
191	#define PGM_TYPE_EPT 7
192	#define PGM_TYPE_MAX PGM_TYPE_EPT
193	/** @} */
194
195	/** Macro for checking if the guest is using paging.
196	* @param uGstType PGM_TYPE_*
197	* @param uShwType PGM_TYPE_*
198	* @remark ASSUMES certain order of the PGM_TYPE_* values.
199	*/
200	#define PGM_WITH_PAGING(uGstType, uShwType) \
201	( (uGstType) >= PGM_TYPE_32BIT \
202	&& (uShwType) != PGM_TYPE_NESTED \
203	&& (uShwType) != PGM_TYPE_EPT)
204
205	/** Macro for checking if the guest supports the NX bit.
206	* @param uGstType PGM_TYPE_*
207	* @param uShwType PGM_TYPE_*
208	* @remark ASSUMES certain order of the PGM_TYPE_* values.
209	*/
210	#define PGM_WITH_NX(uGstType, uShwType) \
211	( (uGstType) >= PGM_TYPE_PAE \
212	&& (uShwType) != PGM_TYPE_NESTED \
213	&& (uShwType) != PGM_TYPE_EPT)
214
215
216	/** @def PGM_HCPHYS_2_PTR
217	* Maps a HC physical page pool address to a virtual address.
218	*
219	* @returns VBox status code.
220	* @param pVM The VM handle.
221	* @param HCPhys The HC physical address to map to a virtual one.
222	* @param ppv Where to store the virtual address. No need to cast this.
223	*
224	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
225	* small page window employeed by that function. Be careful.
226	* @remark There is no need to assert on the result.
227	*/
228	#ifdef IN_RC
229	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
230	PGMDynMapHCPage(pVM, HCPhys, (void **)(ppv))
231	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
232	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
233	pgmR0DynMapHCPageInlined(&(pVM)->pgm.s, HCPhys, (void **)(ppv))
234	#else
235	# define PGM_HCPHYS_2_PTR(pVM, HCPhys, ppv) \
236	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
237	#endif
238
239	/** @def PGM_HCPHYS_2_PTR_BY_PGM
240	* Maps a HC physical page pool address to a virtual address.
241	*
242	* @returns VBox status code.
243	* @param pPGM The PGM instance data.
244	* @param HCPhys The HC physical address to map to a virtual one.
245	* @param ppv Where to store the virtual address. No need to cast this.
246	*
247	* @remark In GC this uses PGMGCDynMapHCPage(), so it will consume of the
248	* small page window employeed by that function. Be careful.
249	* @remark There is no need to assert on the result.
250	*/
251	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
252	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
253	pgmR0DynMapHCPageInlined(pPGM, HCPhys, (void **)(ppv))
254	#else
255	# define PGM_HCPHYS_2_PTR_BY_PGM(pPGM, HCPhys, ppv) \
256	PGM_HCPHYS_2_PTR(PGM2VM(pPGM), HCPhys, (void **)(ppv))
257	#endif
258
259	/** @def PGM_GCPHYS_2_PTR
260	* Maps a GC physical page address to a virtual address.
261	*
262	* @returns VBox status code.
263	* @param pVM The VM handle.
264	* @param GCPhys The GC physical address to map to a virtual one.
265	* @param ppv Where to store the virtual address. No need to cast this.
266	*
267	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
268	* small page window employeed by that function. Be careful.
269	* @remark There is no need to assert on the result.
270	*/
271	#ifdef IN_RC
272	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
273	PGMDynMapGCPage(pVM, GCPhys, (void **)(ppv))
274	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
275	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
276	pgmR0DynMapGCPageInlined(&(pVM)->pgm.s, GCPhys, (void **)(ppv))
277	#else
278	# define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) \
279	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
280	#endif
281
282	/** @def PGM_GCPHYS_2_PTR_BY_PGM
283	* Maps a GC physical page address to a virtual address.
284	*
285	* @returns VBox status code.
286	* @param pPGM Pointer to the PGM instance data.
287	* @param GCPhys The GC physical address to map to a virtual one.
288	* @param ppv Where to store the virtual address. No need to cast this.
289	*
290	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
291	* small page window employeed by that function. Be careful.
292	* @remark There is no need to assert on the result.
293	*/
294	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
295	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
296	pgmR0DynMapGCPageInlined(pPGM, GCPhys, (void **)(ppv))
297	#else
298	# define PGM_GCPHYS_2_PTR_BY_PGM(pPGM, GCPhys, ppv) \
299	PGM_GCPHYS_2_PTR(PGM2VM(pPGM), GCPhys, ppv)
300	#endif
301
302	/** @def PGM_GCPHYS_2_PTR_EX
303	* Maps a unaligned GC physical page address to a virtual address.
304	*
305	* @returns VBox status code.
306	* @param pVM The VM handle.
307	* @param GCPhys The GC physical address to map to a virtual one.
308	* @param ppv Where to store the virtual address. No need to cast this.
309	*
310	* @remark In GC this uses PGMGCDynMapGCPage(), so it will consume of the
311	* small page window employeed by that function. Be careful.
312	* @remark There is no need to assert on the result.
313	*/
314	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
315	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
316	PGMDynMapGCPageOff(pVM, GCPhys, (void **)(ppv))
317	#else
318	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
319	PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only /, (PRTR3PTR)(ppv)) /* @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
320	#endif
321
322	/** @def PGM_INVL_PG
323	* Invalidates a page when in GC does nothing in HC.
324	*
325	* @param GCVirt The virtual address of the page to invalidate.
326	*/
327	#ifdef IN_RC
328	# define PGM_INVL_PG(GCVirt) ASMInvalidatePage((void *)(GCVirt))
329	#elif defined(IN_RING0)
330	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
331	#else
332	# define PGM_INVL_PG(GCVirt) HWACCMInvalidatePage(pVM, (RTGCPTR)(GCVirt))
333	#endif
334
335	/** @def PGM_INVL_BIG_PG
336	* Invalidates a 4MB page directory entry when in GC does nothing in HC.
337	*
338	* @param GCVirt The virtual address within the page directory to invalidate.
339	*/
340	#ifdef IN_RC
341	# define PGM_INVL_BIG_PG(GCVirt) ASMReloadCR3()
342	#elif defined(IN_RING0)
343	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
344	#else
345	# define PGM_INVL_BIG_PG(GCVirt) HWACCMFlushTLB(pVM)
346	#endif
347
348	/** @def PGM_INVL_GUEST_TLBS()
349	* Invalidates all guest TLBs.
350	*/
351	#ifdef IN_RC
352	# define PGM_INVL_GUEST_TLBS() ASMReloadCR3()
353	#elif defined(IN_RING0)
354	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
355	#else
356	# define PGM_INVL_GUEST_TLBS() HWACCMFlushTLB(pVM)
357	#endif
358
359
360	/**
361	* Structure for tracking GC Mappings.
362	*
363	* This structure is used by linked list in both GC and HC.
364	*/
365	typedef struct PGMMAPPING
366	{
367	/** Pointer to next entry. */
368	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
369	/** Pointer to next entry. */
370	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
371	/** Pointer to next entry. */
372	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
373	#if GC_ARCH_BITS == 64
374	RTRCPTR padding0;
375	#endif
376	/** Start Virtual address. */
377	RTGCPTR GCPtr;
378	/** Last Virtual address (inclusive). */
379	RTGCPTR GCPtrLast;
380	/** Range size (bytes). */
381	RTGCPTR cb;
382	/** Pointer to relocation callback function. */
383	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
384	/** User argument to the callback. */
385	R3PTRTYPE(void *) pvUser;
386	/** Mapping description / name. For easing debugging. */
387	R3PTRTYPE(const char *) pszDesc;
388	/** Number of page tables. */
389	RTUINT cPTs;
390	#if HC_ARCH_BITS != GC_ARCH_BITS \|\| GC_ARCH_BITS == 64
391	RTUINT uPadding1; /*< Alignment padding. /
392	#endif
393	/** Array of page table mapping data. Each entry
394	* describes one page table. The array can be longer
395	* than the declared length.
396	*/
397	struct
398	{
399	/** The HC physical address of the page table. */
400	RTHCPHYS HCPhysPT;
401	/** The HC physical address of the first PAE page table. */
402	RTHCPHYS HCPhysPaePT0;
403	/** The HC physical address of the second PAE page table. */
404	RTHCPHYS HCPhysPaePT1;
405	/** The HC virtual address of the 32-bit page table. */
406	R3PTRTYPE(PX86PT) pPTR3;
407	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
408	R3PTRTYPE(PX86PTPAE) paPaePTsR3;
409	/** The GC virtual address of the 32-bit page table. */
410	RCPTRTYPE(PX86PT) pPTRC;
411	/** The GC virtual address of the two PAE page table. */
412	RCPTRTYPE(PX86PTPAE) paPaePTsRC;
413	/** The GC virtual address of the 32-bit page table. */
414	R0PTRTYPE(PX86PT) pPTR0;
415	/** The GC virtual address of the two PAE page table. */
416	R0PTRTYPE(PX86PTPAE) paPaePTsR0;
417	} aPTs[1];
418	} PGMMAPPING;
419	/** Pointer to structure for tracking GC Mappings. */
420	typedef struct PGMMAPPING *PPGMMAPPING;
421
422
423	/**
424	* Physical page access handler structure.
425	*
426	* This is used to keep track of physical address ranges
427	* which are being monitored in some kind of way.
428	*/
429	typedef struct PGMPHYSHANDLER
430	{
431	AVLROGCPHYSNODECORE Core;
432	/** Access type. */
433	PGMPHYSHANDLERTYPE enmType;
434	/** Number of pages to update. */
435	uint32_t cPages;
436	/** Pointer to R3 callback function. */
437	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
438	/** User argument for R3 handlers. */
439	R3PTRTYPE(void *) pvUserR3;
440	/** Pointer to R0 callback function. */
441	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
442	/** User argument for R0 handlers. */
443	R0PTRTYPE(void *) pvUserR0;
444	/** Pointer to GC callback function. */
445	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
446	/** User argument for RC handlers. */
447	RCPTRTYPE(void *) pvUserRC;
448	/** Description / Name. For easing debugging. */
449	R3PTRTYPE(const char *) pszDesc;
450	#ifdef VBOX_WITH_STATISTICS
451	/** Profiling of this handler. */
452	STAMPROFILE Stat;
453	#endif
454	} PGMPHYSHANDLER;
455	/** Pointer to a physical page access handler structure. */
456	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
457
458
459	/**
460	* Cache node for the physical addresses covered by a virtual handler.
461	*/
462	typedef struct PGMPHYS2VIRTHANDLER
463	{
464	/** Core node for the tree based on physical ranges. */
465	AVLROGCPHYSNODECORE Core;
466	/** Offset from this struct to the PGMVIRTHANDLER structure. */
467	int32_t offVirtHandler;
468	/** Offset of the next alias relative to this one.
469	* Bit 0 is used for indicating whether we're in the tree.
470	* Bit 1 is used for indicating that we're the head node.
471	*/
472	int32_t offNextAlias;
473	} PGMPHYS2VIRTHANDLER;
474	/** Pointer to a phys to virtual handler structure. */
475	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
476
477	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
478	* node is in the tree. */
479	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
480	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
481	* node is in the head of an alias chain.
482	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
483	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
484	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
485	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
486
487
488	/**
489	* Virtual page access handler structure.
490	*
491	* This is used to keep track of virtual address ranges
492	* which are being monitored in some kind of way.
493	*/
494	typedef struct PGMVIRTHANDLER
495	{
496	/** Core node for the tree based on virtual ranges. */
497	AVLROGCPTRNODECORE Core;
498	/** Size of the range (in bytes). */
499	RTGCPTR cb;
500	/** Number of cache pages. */
501	uint32_t cPages;
502	/** Access type. */
503	PGMVIRTHANDLERTYPE enmType;
504	/** Pointer to the RC callback function. */
505	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
506	#if HC_ARCH_BITS == 64
507	RTRCPTR padding;
508	#endif
509	/** Pointer to the R3 callback function for invalidation. */
510	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
511	/** Pointer to the R3 callback function. */
512	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
513	/** Description / Name. For easing debugging. */
514	R3PTRTYPE(const char *) pszDesc;
515	#ifdef VBOX_WITH_STATISTICS
516	/** Profiling of this handler. */
517	STAMPROFILE Stat;
518	#endif
519	/** Array of cached physical addresses for the monitored ranged. */
520	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
521	} PGMVIRTHANDLER;
522	/** Pointer to a virtual page access handler structure. */
523	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
524
525
526	/**
527	* Page type.
528	* @remarks This enum has to fit in a 3-bit field (see PGMPAGE::u3Type).
529	* @todo convert to \#defines.
530	*/
531	typedef enum PGMPAGETYPE
532	{
533	/** The usual invalid zero entry. */
534	PGMPAGETYPE_INVALID = 0,
535	/** RAM page. (RWX) */
536	PGMPAGETYPE_RAM,
537	/** MMIO2 page. (RWX) */
538	PGMPAGETYPE_MMIO2,
539	/** Shadowed ROM. (RWX) */
540	PGMPAGETYPE_ROM_SHADOW,
541	/** ROM page. (R-X) */
542	PGMPAGETYPE_ROM,
543	/** MMIO page. (---) */
544	PGMPAGETYPE_MMIO,
545	/** End of valid entries. */
546	PGMPAGETYPE_END
547	} PGMPAGETYPE;
548	AssertCompile(PGMPAGETYPE_END < 7);
549
550	/** @name Page type predicates.
551	* @{ */
552	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
553	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
554	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
555	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
556	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
557	/** @} */
558
559
560	/**
561	* A Physical Guest Page tracking structure.
562	*
563	* The format of this structure is complicated because we have to fit a lot
564	* of information into as few bits as possible. The format is also subject
565	* to change (there is one comming up soon). Which means that for we'll be
566	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
567	* accessess to the structure.
568	*/
569	typedef struct PGMPAGE
570	{
571	/** The physical address and a whole lot of other stuff. All bits are used! */
572	RTHCPHYS HCPhys;
573	/** The page state. */
574	uint32_t u2StateX : 2;
575	/** Flag indicating that a write monitored page was written to when set. */
576	uint32_t fWrittenToX : 1;
577	/** For later. */
578	uint32_t fSomethingElse : 1;
579	/** The Page ID.
580	* @todo Merge with HCPhys once we've liberated HCPhys of its stuff.
581	* The HCPhys will be 100% static. */
582	uint32_t idPageX : 28;
583	/** The page type (PGMPAGETYPE). */
584	uint32_t u3Type : 3;
585	/** The physical handler state (PGM_PAGE_HNDL_PHYS_STATE) /
586	uint32_t u2HandlerPhysStateX : 2;
587	/** The virtual handler state (PGM_PAGE_HNDL_VIRT_STATE) /
588	uint32_t u2HandlerVirtStateX : 2;
589	uint32_t u29B : 25;
590	} PGMPAGE;
591	AssertCompileSize(PGMPAGE, 16);
592	/** Pointer to a physical guest page. */
593	typedef PGMPAGE *PPGMPAGE;
594	/** Pointer to a const physical guest page. */
595	typedef const PGMPAGE *PCPGMPAGE;
596	/** Pointer to a physical guest page pointer. */
597	typedef PPGMPAGE *PPPGMPAGE;
598
599
600	/**
601	* Clears the page structure.
602	* @param pPage Pointer to the physical guest page tracking structure.
603	*/
604	#define PGM_PAGE_CLEAR(pPage) \
605	do { \
606	(pPage)->HCPhys = 0; \
607	(pPage)->u2StateX = 0; \
608	(pPage)->fWrittenToX = 0; \
609	(pPage)->fSomethingElse = 0; \
610	(pPage)->idPageX = 0; \
611	(pPage)->u3Type = 0; \
612	(pPage)->u29B = 0; \
613	} while (0)
614
615	/**
616	* Initializes the page structure.
617	* @param pPage Pointer to the physical guest page tracking structure.
618	*/
619	#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
620	do { \
621	(pPage)->HCPhys = (_HCPhys); \
622	(pPage)->u2StateX = (_uState); \
623	(pPage)->fWrittenToX = 0; \
624	(pPage)->fSomethingElse = 0; \
625	(pPage)->idPageX = (_idPage); \
626	/(pPage)->u3Type = (_uType); - later / \
627	PGM_PAGE_SET_TYPE(pPage, _uType); \
628	(pPage)->u29B = 0; \
629	} while (0)
630
631	/**
632	* Initializes the page structure of a ZERO page.
633	* @param pPage Pointer to the physical guest page tracking structure.
634	*/
635	#ifdef VBOX_WITH_NEW_PHYS_CODE
636	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
637	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
638	#else
639	# define PGM_PAGE_INIT_ZERO(pPage, pVM, _uType) \
640	PGM_PAGE_INIT(pPage, 0, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
641	#endif
642	/** Temporary hack. Replaced by PGM_PAGE_INIT_ZERO once the old code is kicked out. */
643	# define PGM_PAGE_INIT_ZERO_REAL(pPage, pVM, _uType) \
644	PGM_PAGE_INIT(pPage, (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (_uType), PGM_PAGE_STATE_ZERO)
645
646
647	/** @name The Page state, PGMPAGE::u2StateX.
648	* @{ */
649	/** The zero page.
650	* This is a per-VM page that's never ever mapped writable. */
651	#define PGM_PAGE_STATE_ZERO 0
652	/** A allocated page.
653	* This is a per-VM page allocated from the page pool (or wherever
654	* we get MMIO2 pages from if the type is MMIO2).
655	*/
656	#define PGM_PAGE_STATE_ALLOCATED 1
657	/** A allocated page that's being monitored for writes.
658	* The shadow page table mappings are read-only. When a write occurs, the
659	* fWrittenTo member is set, the page remapped as read-write and the state
660	* moved back to allocated. */
661	#define PGM_PAGE_STATE_WRITE_MONITORED 2
662	/** The page is shared, aka. copy-on-write.
663	* This is a page that's shared with other VMs. */
664	#define PGM_PAGE_STATE_SHARED 3
665	/** @} */
666
667
668	/**
669	* Gets the page state.
670	* @returns page state (PGM_PAGE_STATE_*).
671	* @param pPage Pointer to the physical guest page tracking structure.
672	*/
673	#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->u2StateX )
674
675	/**
676	* Sets the page state.
677	* @param pPage Pointer to the physical guest page tracking structure.
678	* @param _uState The new page state.
679	*/
680	#define PGM_PAGE_SET_STATE(pPage, _uState) \
681	do { (pPage)->u2StateX = (_uState); } while (0)
682
683
684	/**
685	* Gets the host physical address of the guest page.
686	* @returns host physical address (RTHCPHYS).
687	* @param pPage Pointer to the physical guest page tracking structure.
688	*/
689	#define PGM_PAGE_GET_HCPHYS(pPage) ( (pPage)->HCPhys & UINT64_C(0x0000fffffffff000) )
690
691	/**
692	* Sets the host physical address of the guest page.
693	* @param pPage Pointer to the physical guest page tracking structure.
694	* @param _HCPhys The new host physical address.
695	*/
696	#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
697	do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0xffff000000000fff)) \
698	\| ((_HCPhys) & UINT64_C(0x0000fffffffff000)); } while (0)
699
700	/**
701	* Get the Page ID.
702	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
703	* @param pPage Pointer to the physical guest page tracking structure.
704	*/
705	#define PGM_PAGE_GET_PAGEID(pPage) ( (pPage)->idPageX )
706	/* later:
707	#define PGM_PAGE_GET_PAGEID(pPage) ( ((uint32_t)(pPage)->HCPhys >> (48 - 12))
708	\| ((uint32_t)(pPage)->HCPhys & 0xfff) )
709	*/
710	/**
711	* Sets the Page ID.
712	* @param pPage Pointer to the physical guest page tracking structure.
713	*/
714	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->idPageX = (_idPage); } while (0)
715	/* later:
716	#define PGM_PAGE_SET_PAGEID(pPage, _idPage) do { (pPage)->HCPhys = (((pPage)->HCPhys) & UINT64_C(0x0000fffffffff000)) \
717	\| ((_idPage) & 0xfff) \
718	\| (((_idPage) & 0x0ffff000) << (48-12)); } while (0)
719	*/
720
721	/**
722	* Get the Chunk ID.
723	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
724	* @param pPage Pointer to the physical guest page tracking structure.
725	*/
726	#define PGM_PAGE_GET_CHUNKID(pPage) ( (pPage)->idPageX >> GMM_CHUNKID_SHIFT )
727	/* later:
728	#if GMM_CHUNKID_SHIFT == 12
729	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> 48) )
730	#elif GMM_CHUNKID_SHIFT > 12
731	# define PGM_PAGE_GET_CHUNKID(pPage) ( (uint32_t)((pPage)->HCPhys >> (48 + (GMM_CHUNKID_SHIFT - 12)) )
732	#elif GMM_CHUNKID_SHIFT < 12
733	# define PGM_PAGE_GET_CHUNKID(pPage) ( ( (uint32_t)((pPage)->HCPhys >> 48) << (12 - GMM_CHUNKID_SHIFT) ) \
734	\| ( (uint32_t)((pPage)->HCPhys & 0xfff) >> GMM_CHUNKID_SHIFT ) )
735	#else
736	# error "GMM_CHUNKID_SHIFT isn't defined or something."
737	#endif
738	*/
739
740	/**
741	* Get the index of the page within the allocaiton chunk.
742	* @returns The page index.
743	* @param pPage Pointer to the physical guest page tracking structure.
744	*/
745	#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (pPage)->idPageX & GMM_PAGEID_IDX_MASK )
746	/* later:
747	#if GMM_CHUNKID_SHIFT <= 12
748	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & GMM_PAGEID_IDX_MASK) )
749	#else
750	# define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhys & 0xfff) \
751	\| ( (uint32_t)((pPage)->HCPhys >> 48) & (RT_BIT_32(GMM_CHUNKID_SHIFT - 12) - 1) ) )
752	#endif
753	*/
754
755
756	/**
757	* Gets the page type.
758	* @returns The page type.
759	* @param pPage Pointer to the physical guest page tracking structure.
760	*/
761	#define PGM_PAGE_GET_TYPE(pPage) (pPage)->u3Type
762
763	/**
764	* Sets the page type.
765	* @param pPage Pointer to the physical guest page tracking structure.
766	* @param _enmType The new page type (PGMPAGETYPE).
767	*/
768	#ifdef VBOX_WITH_NEW_PHYS_CODE
769	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
770	do { (pPage)->u3Type = (_enmType); } while (0)
771	#else
772	#define PGM_PAGE_SET_TYPE(pPage, _enmType) \
773	do { \
774	(pPage)->u3Type = (_enmType); \
775	if ((_enmType) == PGMPAGETYPE_ROM) \
776	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM; \
777	else if ((_enmType) == PGMPAGETYPE_ROM_SHADOW) \
778	(pPage)->HCPhys \|= MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO2; \
779	else if ((_enmType) == PGMPAGETYPE_MMIO2) \
780	(pPage)->HCPhys \|= MM_RAM_FLAGS_MMIO2; \
781	} while (0)
782	#endif
783
784
785	/**
786	* Checks if the page is 'reserved'.
787	* @returns true/false.
788	* @param pPage Pointer to the physical guest page tracking structure.
789	*/
790	#define PGM_PAGE_IS_RESERVED(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_RESERVED) )
791
792	/**
793	* Checks if the page is marked for MMIO.
794	* @returns true/false.
795	* @param pPage Pointer to the physical guest page tracking structure.
796	*/
797	#define PGM_PAGE_IS_MMIO(pPage) ( !!((pPage)->HCPhys & MM_RAM_FLAGS_MMIO) )
798
799	/**
800	* Checks if the page is backed by the ZERO page.
801	* @returns true/false.
802	* @param pPage Pointer to the physical guest page tracking structure.
803	*/
804	#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_ZERO )
805
806	/**
807	* Checks if the page is backed by a SHARED page.
808	* @returns true/false.
809	* @param pPage Pointer to the physical guest page tracking structure.
810	*/
811	#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->u2StateX == PGM_PAGE_STATE_SHARED )
812
813
814	/**
815	* Marks the paget as written to (for GMM change monitoring).
816	* @param pPage Pointer to the physical guest page tracking structure.
817	*/
818	#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 1; } while (0)
819
820	/**
821	* Clears the written-to indicator.
822	* @param pPage Pointer to the physical guest page tracking structure.
823	*/
824	#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->fWrittenToX = 0; } while (0)
825
826	/**
827	* Checks if the page was marked as written-to.
828	* @returns true/false.
829	* @param pPage Pointer to the physical guest page tracking structure.
830	*/
831	#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( (pPage)->fWrittenToX )
832
833
834	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateX).
835	*
836	* @remarks The values are assigned in order of priority, so we can calculate
837	* the correct state for a page with different handlers installed.
838	* @{ */
839	/** No handler installed. */
840	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
841	/** Monitoring is temporarily disabled. */
842	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
843	/** Write access is monitored. */
844	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
845	/** All access is monitored. */
846	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
847	/** @} */
848
849	/**
850	* Gets the physical access handler state of a page.
851	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
852	* @param pPage Pointer to the physical guest page tracking structure.
853	*/
854	#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) ( (pPage)->u2HandlerPhysStateX )
855
856	/**
857	* Sets the physical access handler state of a page.
858	* @param pPage Pointer to the physical guest page tracking structure.
859	* @param _uState The new state value.
860	*/
861	#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
862	do { (pPage)->u2HandlerPhysStateX = (_uState); } while (0)
863
864	/**
865	* Checks if the page has any physical access handlers, including temporariliy disabled ones.
866	* @returns true/false
867	* @param pPage Pointer to the physical guest page tracking structure.
868	*/
869	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE )
870
871	/**
872	* Checks if the page has any active physical access handlers.
873	* @returns true/false
874	* @param pPage Pointer to the physical guest page tracking structure.
875	*/
876	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) ( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
877
878
879	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateX).
880	*
881	* @remarks The values are assigned in order of priority, so we can calculate
882	* the correct state for a page with different handlers installed.
883	* @{ */
884	/** No handler installed. */
885	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
886	/* 1 is reserved so the lineup is identical with the physical ones. */
887	/** Write access is monitored. */
888	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
889	/** All access is monitored. */
890	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
891	/** @} */
892
893	/**
894	* Gets the virtual access handler state of a page.
895	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
896	* @param pPage Pointer to the physical guest page tracking structure.
897	*/
898	#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ( (pPage)->u2HandlerVirtStateX )
899
900	/**
901	* Sets the virtual access handler state of a page.
902	* @param pPage Pointer to the physical guest page tracking structure.
903	* @param _uState The new state value.
904	*/
905	#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
906	do { (pPage)->u2HandlerVirtStateX = (_uState); } while (0)
907
908	/**
909	* Checks if the page has any virtual access handlers.
910	* @returns true/false
911	* @param pPage Pointer to the physical guest page tracking structure.
912	*/
913	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ( (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
914
915	/**
916	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
917	* virtual handlers.
918	* @returns true/false
919	* @param pPage Pointer to the physical guest page tracking structure.
920	*/
921	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
922
923
924
925	/**
926	* Checks if the page has any access handlers, including temporarily disabled ones.
927	* @returns true/false
928	* @param pPage Pointer to the physical guest page tracking structure.
929	*/
930	#define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
931	( (pPage)->u2HandlerPhysStateX != PGM_PAGE_HNDL_PHYS_STATE_NONE \
932	\|\| (pPage)->u2HandlerVirtStateX != PGM_PAGE_HNDL_VIRT_STATE_NONE )
933
934	/**
935	* Checks if the page has any active access handlers.
936	* @returns true/false
937	* @param pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
940	( (pPage)->u2HandlerPhysStateX >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
941	\|\| (pPage)->u2HandlerVirtStateX >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
942
943	/**
944	* Checks if the page has any active access handlers catching all accesses.
945	* @returns true/false
946	* @param pPage Pointer to the physical guest page tracking structure.
947	*/
948	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
949	( (pPage)->u2HandlerPhysStateX == PGM_PAGE_HNDL_PHYS_STATE_ALL \
950	\|\| (pPage)->u2HandlerVirtStateX == PGM_PAGE_HNDL_VIRT_STATE_ALL )
951
952
953	/**
954	* Ram range for GC Phys to HC Phys conversion.
955	*
956	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
957	* conversions too, but we'll let MM handle that for now.
958	*
959	* This structure is used by linked lists in both GC and HC.
960	*/
961	typedef struct PGMRAMRANGE
962	{
963	/** Pointer to the next RAM range - for R3. */
964	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
965	/** Pointer to the next RAM range - for R0. */
966	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
967	/** Pointer to the next RAM range - for RC. */
968	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
969	/** Pointer alignment. */
970	RTRCPTR RCPtrAlignment;
971	/** Start of the range. Page aligned. */
972	RTGCPHYS GCPhys;
973	/** Last address in the range (inclusive). Page aligned (-1). */
974	RTGCPHYS GCPhysLast;
975	/** Size of the range. (Page aligned of course). */
976	RTGCPHYS cb;
977	/** MM_RAM_* flags */
978	uint32_t fFlags;
979	uint32_t u32Alignment; /*< alignment. /
980	#ifndef VBOX_WITH_NEW_PHYS_CODE
981	/** R3 virtual lookup ranges for chunks.
982	* Currently only used with MM_RAM_FLAGS_DYNAMIC_ALLOC ranges.
983	* @remarks This is occationally accessed from ring-0!! (not darwin) */
984	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	R3PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
986	# else
987	R3R0PTRTYPE(PRTR3UINTPTR) paChunkR3Ptrs;
988	# endif
989	#endif
990	/** Start of the HC mapping of the range. This is only used for MMIO2. */
991	R3PTRTYPE(void *) pvR3;
992	/** The range description. */
993	R3PTRTYPE(const char *) pszDesc;
994
995	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
996	#ifdef VBOX_WITH_NEW_PHYS_CODE
997	uint32_t au32Reserved[2];
998	#elif HC_ARCH_BITS == 32
999	uint32_t au32Reserved[1];
1000	#endif
1001
1002	/** Array of physical guest page tracking structures. */
1003	PGMPAGE aPages[1];
1004	} PGMRAMRANGE;
1005	/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1006	typedef PGMRAMRANGE *PPGMRAMRANGE;
1007
1008	/** Return hc ptr corresponding to the ram range and physical offset */
1009	#define PGMRAMRANGE_GETHCPTR(pRam, off) \
1010	(pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) ? (RTHCPTR)((pRam)->paChunkR3Ptrs[(off) >> PGM_DYNAMIC_CHUNK_SHIFT] + ((off) & PGM_DYNAMIC_CHUNK_OFFSET_MASK)) \
1011	: (RTHCPTR)((RTR3UINTPTR)(pRam)->pvR3 + (off));
1012
1013	/**
1014	* Per page tracking structure for ROM image.
1015	*
1016	* A ROM image may have a shadow page, in which case we may have
1017	* two pages backing it. This structure contains the PGMPAGE for
1018	* both while PGMRAMRANGE have a copy of the active one. It is
1019	* important that these aren't out of sync in any regard other
1020	* than page pool tracking data.
1021	*/
1022	typedef struct PGMROMPAGE
1023	{
1024	/** The page structure for the virgin ROM page. */
1025	PGMPAGE Virgin;
1026	/** The page structure for the shadow RAM page. */
1027	PGMPAGE Shadow;
1028	/** The current protection setting. */
1029	PGMROMPROT enmProt;
1030	/** Pad the structure size to a multiple of 8. */
1031	uint32_t u32Padding;
1032	} PGMROMPAGE;
1033	/** Pointer to a ROM page tracking structure. */
1034	typedef PGMROMPAGE *PPGMROMPAGE;
1035
1036
1037	/**
1038	* A registered ROM image.
1039	*
1040	* This is needed to keep track of ROM image since they generally
1041	* intrude into a PGMRAMRANGE. It also keeps track of additional
1042	* info like the two page sets (read-only virgin and read-write shadow),
1043	* the current state of each page.
1044	*
1045	* Because access handlers cannot easily be executed in a different
1046	* context, the ROM ranges needs to be accessible and in all contexts.
1047	*/
1048	typedef struct PGMROMRANGE
1049	{
1050	/** Pointer to the next range - R3. */
1051	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1052	/** Pointer to the next range - R0. */
1053	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1054	/** Pointer to the next range - RC. */
1055	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1056	/** Pointer alignment */
1057	RTRCPTR GCPtrAlignment;
1058	/** Address of the range. */
1059	RTGCPHYS GCPhys;
1060	/** Address of the last byte in the range. */
1061	RTGCPHYS GCPhysLast;
1062	/** Size of the range. */
1063	RTGCPHYS cb;
1064	/** The flags (PGMPHYS_ROM_FLAG_). /
1065	uint32_t fFlags;
1066	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1067	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 7 : 3];
1068	/** Pointer to the original bits when PGMPHYS_ROM_FLAG_PERMANENT_BINARY was specified.
1069	* This is used for strictness checks. */
1070	R3PTRTYPE(const void *) pvOriginal;
1071	/** The ROM description. */
1072	R3PTRTYPE(const char *) pszDesc;
1073	/** The per page tracking structures. */
1074	PGMROMPAGE aPages[1];
1075	} PGMROMRANGE;
1076	/** Pointer to a ROM range. */
1077	typedef PGMROMRANGE *PPGMROMRANGE;
1078
1079
1080	/**
1081	* A registered MMIO2 (= Device RAM) range.
1082	*
1083	* There are a few reason why we need to keep track of these
1084	* registrations. One of them is the deregistration & cleanup
1085	* stuff, while another is that the PGMRAMRANGE associated with
1086	* such a region may have to be removed from the ram range list.
1087	*
1088	* Overlapping with a RAM range has to be 100% or none at all. The
1089	* pages in the existing RAM range must not be ROM nor MMIO. A guru
1090	* meditation will be raised if a partial overlap or an overlap of
1091	* ROM pages is encountered. On an overlap we will free all the
1092	* existing RAM pages and put in the ram range pages instead.
1093	*/
1094	typedef struct PGMMMIO2RANGE
1095	{
1096	/** The owner of the range. (a device) */
1097	PPDMDEVINSR3 pDevInsR3;
1098	/** Pointer to the ring-3 mapping of the allocation. */
1099	RTR3PTR pvR3;
1100	/** Pointer to the next range - R3. */
1101	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1102	/** Whether it's mapped or not. */
1103	bool fMapped;
1104	/** Whether it's overlapping or not. */
1105	bool fOverlapping;
1106	/** The PCI region number.
1107	* @remarks This ASSUMES that nobody will ever really need to have multiple
1108	* PCI devices with matching MMIO region numbers on a single device. */
1109	uint8_t iRegion;
1110	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundrary. */
1111	uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 1 : 5];
1112	/** The associated RAM range. */
1113	PGMRAMRANGE RamRange;
1114	} PGMMMIO2RANGE;
1115	/** Pointer to a MMIO2 range. */
1116	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1117
1118
1119
1120
1121	/**
1122	* PGMPhysRead/Write cache entry
1123	*/
1124	typedef struct PGMPHYSCACHEENTRY
1125	{
1126	/** R3 pointer to physical page. */
1127	R3PTRTYPE(uint8_t *) pbR3;
1128	/** GC Physical address for cache entry */
1129	RTGCPHYS GCPhys;
1130	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1131	RTGCPHYS u32Padding0; /*< alignment padding. /
1132	#endif
1133	} PGMPHYSCACHEENTRY;
1134
1135	/**
1136	* PGMPhysRead/Write cache to reduce REM memory access overhead
1137	*/
1138	typedef struct PGMPHYSCACHE
1139	{
1140	/** Bitmap of valid cache entries */
1141	uint64_t aEntries;
1142	/** Cache entries */
1143	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1144	} PGMPHYSCACHE;
1145
1146
1147	/** Pointer to an allocation chunk ring-3 mapping. */
1148	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1149	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1150	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1151
1152	/**
1153	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1154	*
1155	* The primary tree (Core) uses the chunk id as key.
1156	* The secondary tree (AgeCore) is used for ageing and uses ageing sequence number as key.
1157	*/
1158	typedef struct PGMCHUNKR3MAP
1159	{
1160	/** The key is the chunk id. */
1161	AVLU32NODECORE Core;
1162	/** The key is the ageing sequence number. */
1163	AVLLU32NODECORE AgeCore;
1164	/** The current age thingy. */
1165	uint32_t iAge;
1166	/** The current reference count. */
1167	uint32_t volatile cRefs;
1168	/** The current permanent reference count. */
1169	uint32_t volatile cPermRefs;
1170	/** The mapping address. */
1171	void *pv;
1172	} PGMCHUNKR3MAP;
1173
1174	/**
1175	* Allocation chunk ring-3 mapping TLB entry.
1176	*/
1177	typedef struct PGMCHUNKR3MAPTLBE
1178	{
1179	/** The chunk id. */
1180	uint32_t volatile idChunk;
1181	#if HC_ARCH_BITS == 64
1182	uint32_t u32Padding; /*< alignment padding. /
1183	#endif
1184	/** The chunk map. */
1185	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1186	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1187	#else
1188	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1189	#endif
1190	} PGMCHUNKR3MAPTLBE;
1191	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1192	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1193
1194	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1195	* @remark Must be a power of two value. */
1196	#define PGM_CHUNKR3MAPTLB_ENTRIES 32
1197
1198	/**
1199	* Allocation chunk ring-3 mapping TLB.
1200	*
1201	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1202	* At first glance this might look kinda odd since AVL trees are
1203	* supposed to give the most optimial lookup times of all trees
1204	* due to their balancing. However, take a tree with 1023 nodes
1205	* in it, that's 10 levels, meaning that most searches has to go
1206	* down 9 levels before they find what they want. This isn't fast
1207	* compared to a TLB hit. There is the factor of cache misses,
1208	* and of course the problem with trees and branch prediction.
1209	* This is why we use TLBs in front of most of the trees.
1210	*
1211	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1212	* difficult when we switch to the new inlined AVL trees (from kStuff).
1213	*/
1214	typedef struct PGMCHUNKR3MAPTLB
1215	{
1216	/** The TLB entries. */
1217	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1218	} PGMCHUNKR3MAPTLB;
1219
1220	/**
1221	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1222	* @returns Chunk TLB index.
1223	* @param idChunk The Chunk ID.
1224	*/
1225	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1226
1227
1228	/**
1229	* Ring-3 guest page mapping TLB entry.
1230	* @remarks used in ring-0 as well at the moment.
1231	*/
1232	typedef struct PGMPAGER3MAPTLBE
1233	{
1234	/** Address of the page. */
1235	RTGCPHYS volatile GCPhys;
1236	/** The guest page. */
1237	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1238	R3PTRTYPE(PPGMPAGE) volatile pPage;
1239	#else
1240	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1241	#endif
1242	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1243	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1244	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1245	#else
1246	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1247	#endif
1248	/** The address */
1249	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1250	R3PTRTYPE(void *) volatile pv;
1251	#else
1252	R3R0PTRTYPE(void *) volatile pv;
1253	#endif
1254	#if HC_ARCH_BITS == 32
1255	uint32_t u32Padding; /*< alignment padding. /
1256	#endif
1257	} PGMPAGER3MAPTLBE;
1258	/** Pointer to an entry in the HC physical TLB. */
1259	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1260
1261
1262	/** The number of entries in the ring-3 guest page mapping TLB.
1263	* @remarks The value must be a power of two. */
1264	#define PGM_PAGER3MAPTLB_ENTRIES 64
1265
1266	/**
1267	* Ring-3 guest page mapping TLB.
1268	* @remarks used in ring-0 as well at the moment.
1269	*/
1270	typedef struct PGMPAGER3MAPTLB
1271	{
1272	/** The TLB entries. */
1273	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1274	} PGMPAGER3MAPTLB;
1275	/** Pointer to the ring-3 guest page mapping TLB. */
1276	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1277
1278	/**
1279	* Calculates the index of the TLB entry for the specified guest page.
1280	* @returns Physical TLB index.
1281	* @param GCPhys The guest physical address.
1282	*/
1283	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1284
1285
1286	/**
1287	* Mapping cache usage set entry.
1288	*
1289	* @remarks 16-bit ints was choosen as the set is not expected to be used beyond
1290	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1291	* cache. If it's extended to include ring-3, well, then something will
1292	* have be changed here...
1293	*/
1294	typedef struct PGMMAPSETENTRY
1295	{
1296	/** The mapping cache index. */
1297	uint16_t iPage;
1298	/** The number of references.
1299	* The max is UINT16_MAX - 1. */
1300	uint16_t cRefs;
1301	/** Pointer to the page. */
1302	RTR0PTR pvPage;
1303	/** The physical address for this entry. */
1304	RTHCPHYS HCPhys;
1305	} PGMMAPSETENTRY;
1306	/** Pointer to a mapping cache usage set entry. */
1307	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1308
1309	/**
1310	* Mapping cache usage set.
1311	*
1312	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1313	* done during exits / traps. The set is
1314	*/
1315	typedef struct PGMMAPSET
1316	{
1317	/** The number of occupied entries.
1318	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1319	* dynamic mappings. */
1320	uint32_t cEntries;
1321	/** The start of the current subset.
1322	* This is UINT32_MAX if no subset is currently open. */
1323	uint32_t iSubset;
1324	/** The index of the current CPU, only valid if the set is open. */
1325	int32_t iCpu;
1326	/** The entries. */
1327	PGMMAPSETENTRY aEntries[32];
1328	/** HCPhys -> iEntry fast lookup table.
1329	* Use PGMMAPSET_HASH for hashing.
1330	* The entries may or may not be valid, check against cEntries. */
1331	uint8_t aiHashTable[64];
1332	} PGMMAPSET;
1333	/** Pointer to the mapping cache set. */
1334	typedef PGMMAPSET *PPGMMAPSET;
1335
1336	/** PGMMAPSET::cEntries value for a closed set. */
1337	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1338
1339	/** Hash function for aiHashTable. */
1340	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 63)
1341
1342
1343	/** @name Context neutrual page mapper TLB.
1344	*
1345	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1346	* code is writting in a kind of context neutrual way. Time will show whether
1347	* this actually makes sense or not...
1348	*
1349	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1350	* context ends up using a global mapping cache on some platforms
1351	* (darwin).
1352	*
1353	* @{ */
1354	/** @typedef PPGMPAGEMAPTLB
1355	* The page mapper TLB pointer type for the current context. */
1356	/** @typedef PPGMPAGEMAPTLB
1357	* The page mapper TLB entry pointer type for the current context. */
1358	/** @typedef PPGMPAGEMAPTLB
1359	* The page mapper TLB entry pointer pointer type for the current context. */
1360	/** @def PGM_PAGEMAPTLB_ENTRIES
1361	* The number of TLB entries in the page mapper TLB for the current context. */
1362	/** @def PGM_PAGEMAPTLB_IDX
1363	* Calculate the TLB index for a guest physical address.
1364	* @returns The TLB index.
1365	* @param GCPhys The guest physical address. */
1366	/** @typedef PPGMPAGEMAP
1367	* Pointer to a page mapper unit for current context. */
1368	/** @typedef PPPGMPAGEMAP
1369	* Pointer to a page mapper unit pointer for current context. */
1370	#ifdef IN_RC
1371	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1372	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1373	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1374	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1375	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1376	typedef void * PPGMPAGEMAP;
1377	typedef void ** PPPGMPAGEMAP;
1378	//#elif IN_RING0
1379	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1380	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1381	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1382	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1383	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1384	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1385	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1386	#else
1387	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1388	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1389	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1390	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1391	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1392	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1393	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1394	#endif
1395	/** @} */
1396
1397
1398	/** @name PGM Pool Indexes.
1399	* Aka. the unique shadow page identifier.
1400	* @{ */
1401	/** NIL page pool IDX. */
1402	#define NIL_PGMPOOL_IDX 0
1403	/** The first normal index. */
1404	#define PGMPOOL_IDX_FIRST_SPECIAL 1
1405	/** Page directory (32-bit root). */
1406	#define PGMPOOL_IDX_PD 1
1407	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1408	/** Page directory (32-bit root). */
1409	#define PGMPOOL_IDX_PD 1
1410	/** Page Directory Pointer Table (PAE root). */
1411	#define PGMPOOL_IDX_PDPT 2
1412	/** AMD64 CR3 level index.*/
1413	#define PGMPOOL_IDX_AMD64_CR3 3
1414	/** Nested paging root.*/
1415	#define PGMPOOL_IDX_NESTED_ROOT 4
1416	/** The first normal index. */
1417	#define PGMPOOL_IDX_FIRST 5
1418	#else
1419	/** The extended PAE page directory (2048 entries, works as root currently). */
1420	#define PGMPOOL_IDX_PAE_PD 2
1421	/** PAE Page Directory Table 0. */
1422	#define PGMPOOL_IDX_PAE_PD_0 3
1423	/** PAE Page Directory Table 1. */
1424	#define PGMPOOL_IDX_PAE_PD_1 4
1425	/** PAE Page Directory Table 2. */
1426	#define PGMPOOL_IDX_PAE_PD_2 5
1427	/** PAE Page Directory Table 3. */
1428	#define PGMPOOL_IDX_PAE_PD_3 6
1429	/** Page Directory Pointer Table (PAE root, not currently used). */
1430	#define PGMPOOL_IDX_PDPT 7
1431	/** AMD64 CR3 level index.*/
1432	#define PGMPOOL_IDX_AMD64_CR3 8
1433	/** Nested paging root.*/
1434	#define PGMPOOL_IDX_NESTED_ROOT 9
1435	/** The first normal index. */
1436	#define PGMPOOL_IDX_FIRST 10
1437	#endif
1438	/** The last valid index. (inclusive, 14 bits) */
1439	#define PGMPOOL_IDX_LAST 0x3fff
1440	/** @} */
1441
1442	/** The NIL index for the parent chain. */
1443	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1444
1445	/**
1446	* Node in the chain linking a shadowed page to it's parent (user).
1447	*/
1448	#pragma pack(1)
1449	typedef struct PGMPOOLUSER
1450	{
1451	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1452	uint16_t iNext;
1453	/** The user page index. */
1454	uint16_t iUser;
1455	/** Index into the user table. */
1456	uint32_t iUserTable;
1457	} PGMPOOLUSER, *PPGMPOOLUSER;
1458	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1459	#pragma pack()
1460
1461
1462	/** The NIL index for the phys ext chain. */
1463	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1464
1465	/**
1466	* Node in the chain of physical cross reference extents.
1467	*/
1468	#pragma pack(1)
1469	typedef struct PGMPOOLPHYSEXT
1470	{
1471	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1472	uint16_t iNext;
1473	/** The user page index. */
1474	uint16_t aidx[3];
1475	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1476	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1477	#pragma pack()
1478
1479
1480	/**
1481	* The kind of page that's being shadowed.
1482	*/
1483	typedef enum PGMPOOLKIND
1484	{
1485	/** The virtual invalid 0 entry. */
1486	PGMPOOLKIND_INVALID = 0,
1487	/** The entry is free (=unused). */
1488	PGMPOOLKIND_FREE,
1489
1490	/** Shw: 32-bit page table; Gst: no paging */
1491	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1492	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1493	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1494	/** Shw: 32-bit page table; Gst: 4MB page. */
1495	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1496	/** Shw: PAE page table; Gst: no paging */
1497	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1498	/** Shw: PAE page table; Gst: 32-bit page table. */
1499	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1500	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1501	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1502	/** Shw: PAE page table; Gst: PAE page table. */
1503	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1504	/** Shw: PAE page table; Gst: 2MB page. */
1505	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1506
1507	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1508	PGMPOOLKIND_32BIT_PD,
1509	/** Shw: 32-bit page directory. Gst: real mode. */
1510	PGMPOOLKIND_32BIT_PD_PHYS_REAL,
1511	/** Shw: 32-bit page directory. Gst: protected mode without paging. */
1512	PGMPOOLKIND_32BIT_PD_PHYS_PROT,
1513	/** Shw: PAE page directory; Gst: 32-bit page directory. */
1514	PGMPOOLKIND_PAE_PD_FOR_32BIT_PD,
1515	/** Shw: PAE page directory; Gst: PAE page directory. */
1516	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1517	/** Shw: PAE page directory; Gst: real mode. */
1518	PGMPOOLKIND_PAE_PD_PHYS_REAL,
1519	/** Shw: PAE page directory; Gst: protected mode without paging. */
1520	PGMPOOLKIND_PAE_PD_PHYS_PROT,
1521
1522	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1523	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1524	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1525	PGMPOOLKIND_PAE_PDPT,
1526
1527	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1528	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1529	/** Shw: 64-bit page directory pointer table; Gst: no paging */
1530	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1531	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1532	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1533	/** Shw: 64-bit page directory table; Gst: no paging */
1534	PGMPOOLKIND_64BIT_PD_FOR_PHYS,
1535
1536	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1537	PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
1538
1539	/** Shw: EPT page directory pointer table; Gst: no paging */
1540	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1541	/** Shw: EPT page directory table; Gst: no paging */
1542	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1543	/** Shw: EPT page table; Gst: no paging */
1544	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1545
1546	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1547	/** Shw: Root 32-bit page directory. */
1548	PGMPOOLKIND_ROOT_32BIT_PD,
1549	/** Shw: Root PAE page directory */
1550	PGMPOOLKIND_ROOT_PAE_PD,
1551	/** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
1552	PGMPOOLKIND_ROOT_PDPT,
1553	#endif
1554	/** Shw: Root Nested paging table. */
1555	PGMPOOLKIND_ROOT_NESTED,
1556
1557	/** The last valid entry. */
1558	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
1559	} PGMPOOLKIND;
1560
1561
1562	/**
1563	* The tracking data for a page in the pool.
1564	*/
1565	typedef struct PGMPOOLPAGE
1566	{
1567	/** AVL node code with the (R3) physical address of this page. */
1568	AVLOHCPHYSNODECORE Core;
1569	/** Pointer to the R3 mapping of the page. */
1570	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1571	R3PTRTYPE(void *) pvPageR3;
1572	#else
1573	R3R0PTRTYPE(void *) pvPageR3;
1574	#endif
1575	/** The guest physical address. */
1576	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
1577	uint32_t Alignment0;
1578	#endif
1579	RTGCPHYS GCPhys;
1580	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
1581	uint8_t enmKind;
1582	uint8_t bPadding;
1583	/** The index of this page. */
1584	uint16_t idx;
1585	/** The next entry in the list this page currently resides in.
1586	* It's either in the free list or in the GCPhys hash. */
1587	uint16_t iNext;
1588	#ifdef PGMPOOL_WITH_USER_TRACKING
1589	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
1590	uint16_t iUserHead;
1591	/** The number of present entries. */
1592	uint16_t cPresent;
1593	/** The first entry in the table which is present. */
1594	uint16_t iFirstPresent;
1595	#endif
1596	#ifdef PGMPOOL_WITH_MONITORING
1597	/** The number of modifications to the monitored page. */
1598	uint16_t cModifications;
1599	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
1600	uint16_t iModifiedNext;
1601	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
1602	uint16_t iModifiedPrev;
1603	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
1604	uint16_t iMonitoredNext;
1605	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
1606	uint16_t iMonitoredPrev;
1607	#endif
1608	#ifdef PGMPOOL_WITH_CACHE
1609	/** The next page in the age list. */
1610	uint16_t iAgeNext;
1611	/** The previous page in the age list. */
1612	uint16_t iAgePrev;
1613	#endif /* PGMPOOL_WITH_CACHE */
1614	/** Used to indicate that the page is zeroed. */
1615	bool fZeroed;
1616	/** Used to indicate that a PT has non-global entries. */
1617	bool fSeenNonGlobal;
1618	/** Used to indicate that we're monitoring writes to the guest page. */
1619	bool fMonitored;
1620	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
1621	* (All pages are in the age list.) */
1622	bool fCached;
1623	/** This is used by the R3 access handlers when invoked by an async thread.
1624	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
1625	bool volatile fReusedFlushPending;
1626	/** Used to indicate that the guest is mapping the page is also used as a CR3.
1627	* In these cases the access handler acts differently and will check
1628	* for mapping conflicts like the normal CR3 handler.
1629	* @todo When we change the CR3 shadowing to use pool pages, this flag can be
1630	* replaced by a list of pages which share access handler.
1631	*/
1632	bool fCR3Mix;
1633	} PGMPOOLPAGE, PPGMPOOLPAGE, *PPPGMPOOLPAGE;
1634
1635
1636	#ifdef PGMPOOL_WITH_CACHE
1637	/** The hash table size. */
1638	# define PGMPOOL_HASH_SIZE 0x40
1639	/** The hash function. */
1640	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
1641	#endif
1642
1643
1644	/**
1645	* The shadow page pool instance data.
1646	*
1647	* It's all one big allocation made at init time, except for the
1648	* pages that is. The user nodes follows immediatly after the
1649	* page structures.
1650	*/
1651	typedef struct PGMPOOL
1652	{
1653	/** The VM handle - R3 Ptr. */
1654	PVMR3 pVMR3;
1655	/** The VM handle - R0 Ptr. */
1656	PVMR0 pVMR0;
1657	/** The VM handle - RC Ptr. */
1658	PVMRC pVMRC;
1659	/** The max pool size. This includes the special IDs. */
1660	uint16_t cMaxPages;
1661	/** The current pool size. */
1662	uint16_t cCurPages;
1663	/** The head of the free page list. */
1664	uint16_t iFreeHead;
1665	/* Padding. */
1666	uint16_t u16Padding;
1667	#ifdef PGMPOOL_WITH_USER_TRACKING
1668	/** Head of the chain of free user nodes. */
1669	uint16_t iUserFreeHead;
1670	/** The number of user nodes we've allocated. */
1671	uint16_t cMaxUsers;
1672	/** The number of present page table entries in the entire pool. */
1673	uint32_t cPresent;
1674	/** Pointer to the array of user nodes - RC pointer. */
1675	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
1676	/** Pointer to the array of user nodes - R3 pointer. */
1677	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
1678	/** Pointer to the array of user nodes - R0 pointer. */
1679	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
1680	#endif /* PGMPOOL_WITH_USER_TRACKING */
1681	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1682	/** Head of the chain of free phys ext nodes. */
1683	uint16_t iPhysExtFreeHead;
1684	/** The number of user nodes we've allocated. */
1685	uint16_t cMaxPhysExts;
1686	/** Pointer to the array of physical xref extent - RC pointer. */
1687	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
1688	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
1689	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
1690	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
1691	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
1692	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1693	#ifdef PGMPOOL_WITH_CACHE
1694	/** Hash table for GCPhys addresses. */
1695	uint16_t aiHash[PGMPOOL_HASH_SIZE];
1696	/** The head of the age list. */
1697	uint16_t iAgeHead;
1698	/** The tail of the age list. */
1699	uint16_t iAgeTail;
1700	/** Set if the cache is enabled. */
1701	bool fCacheEnabled;
1702	#endif /* PGMPOOL_WITH_CACHE */
1703	#ifdef PGMPOOL_WITH_MONITORING
1704	/** Head of the list of modified pages. */
1705	uint16_t iModifiedHead;
1706	/** The current number of modified pages. */
1707	uint16_t cModifiedPages;
1708	/** Access handler, RC. */
1709	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
1710	/** Access handler, R0. */
1711	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
1712	/** Access handler, R3. */
1713	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
1714	/** The access handler description (HC ptr). */
1715	R3PTRTYPE(const char *) pszAccessHandler;
1716	#endif /* PGMPOOL_WITH_MONITORING */
1717	/** The number of pages currently in use. */
1718	uint16_t cUsedPages;
1719	#ifdef VBOX_WITH_STATISTICS
1720	/** The high wather mark for cUsedPages. */
1721	uint16_t cUsedPagesHigh;
1722	uint32_t Alignment1; /*< Align the next member on a 64-bit boundrary. /
1723	/** Profiling pgmPoolAlloc(). */
1724	STAMPROFILEADV StatAlloc;
1725	/** Profiling pgmPoolClearAll(). */
1726	STAMPROFILE StatClearAll;
1727	/** Profiling pgmPoolFlushAllInt(). */
1728	STAMPROFILE StatFlushAllInt;
1729	/** Profiling pgmPoolFlushPage(). */
1730	STAMPROFILE StatFlushPage;
1731	/** Profiling pgmPoolFree(). */
1732	STAMPROFILE StatFree;
1733	/** Profiling time spent zeroing pages. */
1734	STAMPROFILE StatZeroPage;
1735	# ifdef PGMPOOL_WITH_USER_TRACKING
1736	/** Profiling of pgmPoolTrackDeref. */
1737	STAMPROFILE StatTrackDeref;
1738	/** Profiling pgmTrackFlushGCPhysPT. */
1739	STAMPROFILE StatTrackFlushGCPhysPT;
1740	/** Profiling pgmTrackFlushGCPhysPTs. */
1741	STAMPROFILE StatTrackFlushGCPhysPTs;
1742	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
1743	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
1744	/** Number of times we've been out of user records. */
1745	STAMCOUNTER StatTrackFreeUpOneUser;
1746	# endif
1747	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1748	/** Profiling deref activity related tracking GC physical pages. */
1749	STAMPROFILE StatTrackDerefGCPhys;
1750	/** Number of linear searches for a HCPhys in the ram ranges. */
1751	STAMCOUNTER StatTrackLinearRamSearches;
1752	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
1753	STAMCOUNTER StamTrackPhysExtAllocFailures;
1754	# endif
1755	# ifdef PGMPOOL_WITH_MONITORING
1756	/** Profiling the RC/R0 access handler. */
1757	STAMPROFILE StatMonitorRZ;
1758	/** Times we've failed interpreting the instruction. */
1759	STAMCOUNTER StatMonitorRZEmulateInstr;
1760	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
1761	STAMPROFILE StatMonitorRZFlushPage;
1762	/** Times we've detected fork(). */
1763	STAMCOUNTER StatMonitorRZFork;
1764	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
1765	STAMPROFILE StatMonitorRZHandled;
1766	/** Times we've failed interpreting a patch code instruction. */
1767	STAMCOUNTER StatMonitorRZIntrFailPatch1;
1768	/** Times we've failed interpreting a patch code instruction during flushing. */
1769	STAMCOUNTER StatMonitorRZIntrFailPatch2;
1770	/** The number of times we've seen rep prefixes we can't handle. */
1771	STAMCOUNTER StatMonitorRZRepPrefix;
1772	/** Profiling the REP STOSD cases we've handled. */
1773	STAMPROFILE StatMonitorRZRepStosd;
1774
1775	/** Profiling the R3 access handler. */
1776	STAMPROFILE StatMonitorR3;
1777	/** Times we've failed interpreting the instruction. */
1778	STAMCOUNTER StatMonitorR3EmulateInstr;
1779	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
1780	STAMPROFILE StatMonitorR3FlushPage;
1781	/** Times we've detected fork(). */
1782	STAMCOUNTER StatMonitorR3Fork;
1783	/** Profiling the R3 access we've handled (except REP STOSD). */
1784	STAMPROFILE StatMonitorR3Handled;
1785	/** The number of times we've seen rep prefixes we can't handle. */
1786	STAMCOUNTER StatMonitorR3RepPrefix;
1787	/** Profiling the REP STOSD cases we've handled. */
1788	STAMPROFILE StatMonitorR3RepStosd;
1789	/** The number of times we're called in an async thread an need to flush. */
1790	STAMCOUNTER StatMonitorR3Async;
1791	/** The high wather mark for cModifiedPages. */
1792	uint16_t cModifiedPagesHigh;
1793	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundrary. /
1794	# endif
1795	# ifdef PGMPOOL_WITH_CACHE
1796	/** The number of cache hits. */
1797	STAMCOUNTER StatCacheHits;
1798	/** The number of cache misses. */
1799	STAMCOUNTER StatCacheMisses;
1800	/** The number of times we've got a conflict of 'kind' in the cache. */
1801	STAMCOUNTER StatCacheKindMismatches;
1802	/** Number of times we've been out of pages. */
1803	STAMCOUNTER StatCacheFreeUpOne;
1804	/** The number of cacheable allocations. */
1805	STAMCOUNTER StatCacheCacheable;
1806	/** The number of uncacheable allocations. */
1807	STAMCOUNTER StatCacheUncacheable;
1808	# endif
1809	#elif HC_ARCH_BITS == 64
1810	uint32_t Alignment3; /*< Align the next member on a 64-bit boundrary. /
1811	#endif
1812	/** The AVL tree for looking up a page by its HC physical address. */
1813	AVLOHCPHYSTREE HCPhysTree;
1814	uint32_t Alignment4; /*< Align the next member on a 64-bit boundrary. /
1815	/** Array of pages. (cMaxPages in length)
1816	* The Id is the index into thist array.
1817	*/
1818	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
1819	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
1820
1821
1822	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1823	DECLINLINE(void ) pgmPoolMapPageInlined(PVM pVM, PPGMPOOLPAGE pPage, int iLine, const char pszFile);
1824	#endif
1825
1826	/** @def PGMPOOL_PAGE_2_PTR
1827	* Maps a pool page pool into the current context.
1828	*
1829	* @returns VBox status code.
1830	* @param pVM The VM handle.
1831	* @param pPage The pool page.
1832	*
1833	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1834	* small page window employeed by that function. Be careful.
1835	* @remark There is no need to assert on the result.
1836	*/
1837	#if defined(IN_RC)
1838	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage), __LINE__, 0)
1839	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1840	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined(&(pVM)->pgm.s, (pPage), __LINE__, __PRETTY_FUNCTION__)
1841	#elif defined(VBOX_STRICT)
1842	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
1843	DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
1844	{
1845	Assert(pPage->pvPageR3);
1846	return pPage->pvPageR3;
1847	}
1848	#else
1849	# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
1850	#endif
1851
1852	/** @def PGMPOOL_PAGE_2_PTR_BY_PGM
1853	* Maps a pool page pool into the current context.
1854	*
1855	* @returns VBox status code.
1856	* @param pPGM Pointer to the PGM instance data.
1857	* @param pPage The pool page.
1858	*
1859	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
1860	* small page window employeed by that function. Be careful.
1861	* @remark There is no need to assert on the result.
1862	*/
1863	#if defined(IN_RC)
1864	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage), __LINE__, 0)
1865	#elif defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
1866	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) pgmPoolMapPageInlined((pPGM), (pPage), __LINE__, __PRETTY_FUNCTION__)
1867	#else
1868	# define PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPage) PGMPOOL_PAGE_2_PTR(PGM2VM(pPGM), pPage)
1869	#endif
1870
1871
1872
1873	/**
1874	* Trees are using self relative offsets as pointers.
1875	* So, all its data, including the root pointer, must be in the heap for HC and GC
1876	* to have the same layout.
1877	*/
1878	typedef struct PGMTREES
1879	{
1880	/** Physical access handlers (AVL range+offsetptr tree). */
1881	AVLROGCPHYSTREE PhysHandlers;
1882	/** Virtual access handlers (AVL range + GC ptr tree). */
1883	AVLROGCPTRTREE VirtHandlers;
1884	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
1885	AVLROGCPHYSTREE PhysToVirtHandlers;
1886	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
1887	AVLROGCPTRTREE HyperVirtHandlers;
1888	} PGMTREES;
1889	/** Pointer to PGM trees. */
1890	typedef PGMTREES *PPGMTREES;
1891
1892
1893	/** @name Paging mode macros
1894	* @{ */
1895	#ifdef IN_RC
1896	# define PGM_CTX(a,b) a##RC##b
1897	# define PGM_CTX_STR(a,b) a "GC" b
1898	# define PGM_CTX_DECL(type) VMMRCDECL(type)
1899	#else
1900	# ifdef IN_RING3
1901	# define PGM_CTX(a,b) a##R3##b
1902	# define PGM_CTX_STR(a,b) a "R3" b
1903	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
1904	# else
1905	# define PGM_CTX(a,b) a##R0##b
1906	# define PGM_CTX_STR(a,b) a "R0" b
1907	# define PGM_CTX_DECL(type) VMMDECL(type)
1908	# endif
1909	#endif
1910
1911	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
1912	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
1913	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
1914	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
1915	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
1916	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
1917	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
1918	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
1919	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
1920	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
1921	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
1922	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
1923	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
1924	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
1925	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
1926	#define PGM_GST_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Gst##name))
1927	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
1928
1929	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
1930	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
1931	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
1932	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
1933	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
1934	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
1935	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
1936	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
1937	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
1938	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
1939	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
1940	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
1941	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
1942	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
1943	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
1944	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
1945	#define PGM_SHW_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Shw##name))
1946
1947	/* Shw_Gst */
1948	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
1949	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
1950	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
1951	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
1952	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
1953	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
1954	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
1955	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
1956	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
1957	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
1958	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
1959	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
1960	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
1961	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
1962	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
1963	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
1964	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
1965	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
1966	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
1967
1968	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
1969	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
1970	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
1971	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
1972	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
1973	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
1974	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
1975	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
1976	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
1977	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
1978	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
1979	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
1980	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
1981	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
1982	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
1983	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
1984	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
1985	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
1986	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
1987	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
1988	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
1989	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
1990	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
1991	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
1992	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
1993	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
1994	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
1995	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
1996	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
1997	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
1998	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
1999	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2000	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2001	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2002	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2003	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2004	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2005
2006	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2007	#define PGM_BTH_PFN(name, pVM) ((pVM)->pgm.s.PGM_CTX(pfn,Bth##name))
2008	/** @} */
2009
2010	/**
2011	* Data for each paging mode.
2012	*/
2013	typedef struct PGMMODEDATA
2014	{
2015	/** The guest mode type. */
2016	uint32_t uGstType;
2017	/** The shadow mode type. */
2018	uint32_t uShwType;
2019
2020	/** @name Function pointers for Shadow paging.
2021	* @{
2022	*/
2023	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2024	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2025	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2026	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2027
2028	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2029	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2030
2031	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2032	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2033	/** @} */
2034
2035	/** @name Function pointers for Guest paging.
2036	* @{
2037	*/
2038	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2039	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2040	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2041	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2042	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2043	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2044	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2045	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2046	#endif
2047	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2048	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2049	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2050	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2051	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2052	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2053	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2054	#endif
2055	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2056	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2057	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2058	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2059	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2060	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2061	#endif
2062	DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2063	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2064	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2065	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2066	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2067	#endif
2068	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2069	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2070	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2071	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2072	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2073	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2074	#endif
2075	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2076	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2077	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2078	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2079	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2080	#endif
2081	/** @} */
2082
2083	/** @name Function pointers for Both Shadow and Guest paging.
2084	* @{
2085	*/
2086	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2087	/* no pfnR3BthTrap0eHandler */
2088	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2089	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2090	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2091	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2092	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2093	#ifdef VBOX_STRICT
2094	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2095	#endif
2096
2097	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2098	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2099	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2100	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2101	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2102	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2103	#ifdef VBOX_STRICT
2104	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2105	#endif
2106
2107	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2108	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2109	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2110	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2111	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2112	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2113	#ifdef VBOX_STRICT
2114	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2115	#endif
2116	/** @} */
2117	} PGMMODEDATA, *PPGMMODEDATA;
2118
2119
2120
2121	/**
2122	* Converts a PGM pointer into a VM pointer.
2123	* @returns Pointer to the VM structure the PGM is part of.
2124	* @param pPGM Pointer to PGM instance data.
2125	*/
2126	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2127
2128	/**
2129	* PGM Data (part of VM)
2130	*/
2131	typedef struct PGM
2132	{
2133	/** Offset to the VM structure. */
2134	RTINT offVM;
2135	/** Offset of the PGMCPU structure relative to VMCPU. */
2136	int32_t offVCpu;
2137	/** Alignment padding. */
2138	int32_t i32Alignment;
2139
2140	/*
2141	* This will be redefined at least two more times before we're done, I'm sure.
2142	* The current code is only to get on with the coding.
2143	* - 2004-06-10: initial version, bird.
2144	* - 2004-07-02: 1st time, bird.
2145	* - 2004-10-18: 2nd time, bird.
2146	* - 2005-07-xx: 3rd time, bird.
2147	*/
2148
2149	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2150	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
2151	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
2152	RCPTRTYPE(PX86PTEPAE) paDynPageMapPaePTEsGC;
2153
2154	/** The host paging mode. (This is what SUPLib reports.) */
2155	SUPPAGINGMODE enmHostMode;
2156	/** The shadow paging mode. */
2157	PGMMODE enmShadowMode;
2158	/** The guest paging mode. */
2159	PGMMODE enmGuestMode;
2160
2161	/** The current physical address representing in the guest CR3 register. */
2162	RTGCPHYS GCPhysCR3;
2163	/** Pointer to the 5 page CR3 content mapping.
2164	* The first page is always the CR3 (in some form) while the 4 other pages
2165	* are used of the PDs in PAE mode. */
2166	RTGCPTR GCPtrCR3Mapping;
2167	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2168	uint32_t u32Alignment;
2169	#endif
2170	/** The physical address of the currently monitored guest CR3 page.
2171	* When this value is NIL_RTGCPHYS no page is being monitored. */
2172	RTGCPHYS GCPhysGstCR3Monitored;
2173
2174	/** @name 32-bit Guest Paging.
2175	* @{ */
2176	/** The guest's page directory, R3 pointer. */
2177	R3PTRTYPE(PX86PD) pGst32BitPdR3;
2178	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2179	/** The guest's page directory, R0 pointer. */
2180	R0PTRTYPE(PX86PD) pGst32BitPdR0;
2181	#endif
2182	/** The guest's page directory, static RC mapping. */
2183	RCPTRTYPE(PX86PD) pGst32BitPdRC;
2184	/** @} */
2185
2186	/** @name PAE Guest Paging.
2187	* @{ */
2188	/** The guest's page directory pointer table, static RC mapping. */
2189	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
2190	/** The guest's page directory pointer table, R3 pointer. */
2191	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
2192	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2193	/** The guest's page directory pointer table, R0 pointer. */
2194	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
2195	#endif
2196
2197	/** The guest's page directories, R3 pointers.
2198	* These are individual pointers and don't have to be adjecent.
2199	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2200	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
2201	/** The guest's page directories, R0 pointers.
2202	* Same restrictions as apGstPaePDsR3. */
2203	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2204	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
2205	#endif
2206	/** The guest's page directories, static GC mapping.
2207	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
2208	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
2209	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
2210	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
2211	RTGCPHYS aGCPhysGstPaePDs[4];
2212	/** The physical addresses of the monitored guest page directories (PAE). */
2213	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
2214	/** @} */
2215
2216	/** @name AMD64 Guest Paging.
2217	* @{ */
2218	/** The guest's page directory pointer table, R3 pointer. */
2219	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
2220	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2221	/** The guest's page directory pointer table, R0 pointer. */
2222	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
2223	#endif
2224	/** @} */
2225
2226	/** @name 32-bit Shadow Paging
2227	* @{ */
2228	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2229	/** The Physical Address (HC) of the current active shadow CR3. */
2230	RTHCPHYS HCPhysShwCR3;
2231	/** Pointer to the page of the current active CR3 - R3 Ptr. */
2232	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
2233	/** Pointer to the page of the current active CR3 - R0 Ptr. */
2234	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
2235	/** Pointer to the page of the current active CR3 - RC Ptr. */
2236	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
2237	# if HC_ARCH_BITS == 64
2238	RTRCPTR alignment6; /*< structure size alignment. /
2239	# endif
2240	#else
2241	/** The 32-Bit PD - R3 Ptr. */
2242	R3PTRTYPE(PX86PD) pShw32BitPdR3;
2243	/** The 32-Bit PD - R0 Ptr. */
2244	R0PTRTYPE(PX86PD) pShw32BitPdR0;
2245	/** The 32-Bit PD - RC Ptr. */
2246	RCPTRTYPE(PX86PD) pShw32BitPdRC;
2247	# if HC_ARCH_BITS == 64
2248	uint32_t u32Padding1; /*< alignment padding. /
2249	# endif
2250	/** The Physical Address (HC) of the 32-Bit PD. */
2251	RTHCPHYS HCPhysShw32BitPD;
2252	/** @} */
2253
2254	/** @name PAE Shadow Paging
2255	* @{ */
2256	/** The four PDs for the low 4GB - R3 Ptr.
2257	* Even though these are 4 pointers, what they point at is a single table.
2258	* Thus, it's possible to walk the 2048 entries starting where apHCPaePDs[0] points. */
2259	R3PTRTYPE(PX86PDPAE) apShwPaePDsR3[4];
2260	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2261	/** The four PDs for the low 4GB - R0 Ptr.
2262	* Same kind of mapping as apHCPaePDs. */
2263	R0PTRTYPE(PX86PDPAE) apShwPaePDsR0[4];
2264	# endif
2265	/** The four PDs for the low 4GB - RC Ptr.
2266	* Same kind of mapping as apHCPaePDs. */
2267	RCPTRTYPE(PX86PDPAE) apShwPaePDsRC[4];
2268	/** The Physical Address (HC) of the four PDs for the low 4GB.
2269	* These are NOT 4 contiguous pages. */
2270	RTHCPHYS aHCPhysPaePDs[4];
2271	/** The Physical Address (HC) of the PAE PDPT. */
2272	RTHCPHYS HCPhysShwPaePdpt;
2273	/** The PAE PDPT - R3 Ptr. */
2274	R3PTRTYPE(PX86PDPT) pShwPaePdptR3;
2275	/** The PAE PDPT - R0 Ptr. */
2276	R0PTRTYPE(PX86PDPT) pShwPaePdptR0;
2277	/** The PAE PDPT - RC Ptr. */
2278	RCPTRTYPE(PX86PDPT) pShwPaePdptRC;
2279	/** @} */
2280	# if HC_ARCH_BITS == 64
2281	RTRCPTR alignment5; /*< structure size alignment. /
2282	# endif
2283
2284	/** @name AMD64 Shadow Paging
2285	* Extends PAE Paging.
2286	* @{ */
2287	/** The Page Map Level 4 table - R3 Ptr. */
2288	R3PTRTYPE(PX86PML4) pShwPaePml4R3;
2289	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2290	/** The Page Map Level 4 table - R0 Ptr. */
2291	R0PTRTYPE(PX86PML4) pShwPaePml4R0;
2292	# endif
2293	/** The Physical Address (HC) of the Page Map Level 4 table. */
2294	RTHCPHYS HCPhysShwPaePml4;
2295	/** The pgm pool page descriptor for the current active CR3 - R3 Ptr. */
2296	R3PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R3;
2297	/** The pgm pool page descriptor for the current active CR3 - R0 Ptr. */
2298	R0PTRTYPE(PPGMPOOLPAGE) pShwAmd64CR3R0;
2299	/** @}*/
2300
2301	/** @name Nested Shadow Paging
2302	* @{ */
2303	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R3 pointer. */
2304	RTR3PTR pShwNestedRootR3;
2305	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
2306	/** Root table; format depends on the host paging mode (AMD-V) or EPT - R0 pointer. */
2307	RTR0PTR pShwNestedRootR0;
2308	# endif
2309	/** The Physical Address (HC) of the nested paging root. */
2310	RTHCPHYS HCPhysShwNestedRoot;
2311	#endif
2312	/** @} */
2313
2314	/** @name Function pointers for Shadow paging.
2315	* @{
2316	*/
2317	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVM pVM, RTGCPTR offDelta));
2318	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVM pVM));
2319	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2320	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2321
2322	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2323	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2324
2325	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2326	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2327
2328	/** @} */
2329
2330	/** @name Function pointers for Guest paging.
2331	* @{
2332	*/
2333	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVM pVM, RTGCPTR offDelta));
2334	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVM pVM));
2335	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2336	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2337	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2338	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2339	DECLR3CALLBACKMEMBER(int, pfnR3GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2340	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmonitorCR3,(PVM pVM));
2341	#endif
2342	DECLR3CALLBACKMEMBER(int, pfnR3GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2343	DECLR3CALLBACKMEMBER(int, pfnR3GstUnmapCR3,(PVM pVM));
2344	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2345	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstWriteHandlerCR3;
2346	R3PTRTYPE(const char *) pszR3GstWriteHandlerCR3;
2347	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnR3GstPAEWriteHandlerCR3;
2348	R3PTRTYPE(const char *) pszR3GstPAEWriteHandlerCR3;
2349	#endif
2350	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2351	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2352	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2353	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2354	DECLRCCALLBACKMEMBER(int, pfnRCGstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2355	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmonitorCR3,(PVM pVM));
2356	#endif
2357	DECLRCCALLBACKMEMBER(int, pfnRCGstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2358	DECLRCCALLBACKMEMBER(int, pfnRCGstUnmapCR3,(PVM pVM));
2359	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2360	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstWriteHandlerCR3;
2361	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnRCGstPAEWriteHandlerCR3;
2362	#endif
2363	#if HC_ARCH_BITS == 64
2364	RTRCPTR alignment3; /*< structure size alignment. /
2365	#endif
2366
2367	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2368	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVM pVM, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2369	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVM pVM, RTGCPTR GCPtr, PX86PDEPAE pPde));
2370	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2371	DECLR0CALLBACKMEMBER(int, pfnR0GstMonitorCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2372	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmonitorCR3,(PVM pVM));
2373	#endif
2374	DECLR0CALLBACKMEMBER(int, pfnR0GstMapCR3,(PVM pVM, RTGCPHYS GCPhysCR3));
2375	DECLR0CALLBACKMEMBER(int, pfnR0GstUnmapCR3,(PVM pVM));
2376	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2377	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstWriteHandlerCR3;
2378	R0PTRTYPE(PFNPGMRCPHYSHANDLER) pfnR0GstPAEWriteHandlerCR3;
2379	#endif
2380	/** @} */
2381
2382	/** @name Function pointers for Both Shadow and Guest paging.
2383	* @{
2384	*/
2385	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVM pVM, RTGCPTR offDelta));
2386	/* no pfnR3BthTrap0eHandler */
2387	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2388	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2389	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2390	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2391	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2392	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2393
2394	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2395	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2396	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2397	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2398	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2399	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2400	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2401
2402	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault));
2403	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVM pVM, RTGCPTR GCPtrPage));
2404	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2405	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncPage,(PVM pVM, X86PDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uError));
2406	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVM pVM, RTGCPTR GCPtrPage));
2407	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVM pVM, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2408	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2409	#if HC_ARCH_BITS == 64
2410	RTRCPTR alignment2; /*< structure size alignment. /
2411	#endif
2412	/** @} */
2413
2414	/** Pointer to SHW+GST mode data (function pointers).
2415	* The index into this table is made up from */
2416	R3PTRTYPE(PPGMMODEDATA) paModeData;
2417
2418	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2419	* This is sorted by physical address and contains no overlapping ranges. */
2420	R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2421	/** R0 pointer corresponding to PGM::pRamRangesR3. */
2422	R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2423	/** RC pointer corresponding to PGM::pRamRangesR3. */
2424	RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2425	/** The configured RAM size. */
2426	RTUINT cbRamSize;
2427
2428	/** Pointer to the list of ROM ranges - for R3.
2429	* This is sorted by physical address and contains no overlapping ranges. */
2430	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2431	/** R0 pointer corresponding to PGM::pRomRangesR3. */
2432	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2433	/** RC pointer corresponding to PGM::pRomRangesR3. */
2434	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
2435	/** Alignment padding. */
2436	RTRCPTR GCPtrPadding2;
2437
2438	/** Pointer to the list of MMIO2 ranges - for R3.
2439	* Registration order. */
2440	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2441
2442	/** PGM offset based trees - R3 Ptr. */
2443	R3PTRTYPE(PPGMTREES) pTreesR3;
2444	/** PGM offset based trees - R0 Ptr. */
2445	R0PTRTYPE(PPGMTREES) pTreesR0;
2446	/** PGM offset based trees - RC Ptr. */
2447	RCPTRTYPE(PPGMTREES) pTreesRC;
2448
2449	/** Linked list of GC mappings - for RC.
2450	* The list is sorted ascending on address.
2451	*/
2452	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
2453	/** Linked list of GC mappings - for HC.
2454	* The list is sorted ascending on address.
2455	*/
2456	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2457	/** Linked list of GC mappings - for R0.
2458	* The list is sorted ascending on address.
2459	*/
2460	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2461
2462	/** If set no conflict checks are required. (boolean) */
2463	bool fMappingsFixed;
2464	/** If set, then no mappings are put into the shadow page table. (boolean) */
2465	bool fDisableMappings;
2466	/** Size of fixed mapping */
2467	uint32_t cbMappingFixed;
2468	/** Base address (GC) of fixed mapping */
2469	RTGCPTR GCPtrMappingFixed;
2470	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
2471	uint32_t u32Padding0; /*< alignment padding. /
2472	#endif
2473
2474
2475	/** @name Intermediate Context
2476	* @{ */
2477	/** Pointer to the intermediate page directory - Normal. */
2478	R3PTRTYPE(PX86PD) pInterPD;
2479	/** Pointer to the intermedate page tables - Normal.
2480	* There are two page tables, one for the identity mapping and one for
2481	* the host context mapping (of the core code). */
2482	R3PTRTYPE(PX86PT) apInterPTs[2];
2483	/** Pointer to the intermedate page tables - PAE. */
2484	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
2485	/** Pointer to the intermedate page directory - PAE. */
2486	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
2487	/** Pointer to the intermedate page directory - PAE. */
2488	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
2489	/** Pointer to the intermedate page-map level 4 - AMD64. */
2490	R3PTRTYPE(PX86PML4) pInterPaePML4;
2491	/** Pointer to the intermedate page directory - AMD64. */
2492	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
2493	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
2494	RTHCPHYS HCPhysInterPD;
2495	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
2496	RTHCPHYS HCPhysInterPaePDPT;
2497	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
2498	RTHCPHYS HCPhysInterPaePML4;
2499	/** @} */
2500
2501	/** Base address of the dynamic page mapping area.
2502	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
2503	*/
2504	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
2505	/** The index of the last entry used in the dynamic page mapping area. */
2506	RTUINT iDynPageMapLast;
2507	/** Cache containing the last entries in the dynamic page mapping area.
2508	* The cache size is covering half of the mapping area. */
2509	RTHCPHYS aHCPhysDynPageMapCache[MM_HYPER_DYNAMIC_SIZE >> (PAGE_SHIFT + 1)];
2510
2511	/** The address of the ring-0 mapping cache if we're making use of it. */
2512	RTR0PTR pvR0DynMapUsed;
2513	#if HC_ARCH_BITS == 32
2514	RTR0PTR R0PtrPadding0; /*< Alignment. /
2515	#endif
2516
2517
2518	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 */
2519	RTGCPHYS GCPhys4MBPSEMask;
2520
2521	/** A20 gate mask.
2522	* Our current approach to A20 emulation is to let REM do it and don't bother
2523	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2524	* But whould need arrise, we'll subject physical addresses to this mask. */
2525	RTGCPHYS GCPhysA20Mask;
2526	/** A20 gate state - boolean! */
2527	RTUINT fA20Enabled;
2528
2529	/** What needs syncing (PGM_SYNC_*).
2530	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
2531	* PGMFlushTLB, and PGMR3Load. */
2532	RTUINT fSyncFlags;
2533
2534	/** PGM critical section.
2535	* This protects the physical & virtual access handlers, ram ranges,
2536	* and the page flag updating (some of it anyway).
2537	*/
2538	PDMCRITSECT CritSect;
2539
2540	/** Shadow Page Pool - R3 Ptr. */
2541	R3PTRTYPE(PPGMPOOL) pPoolR3;
2542	/** Shadow Page Pool - R0 Ptr. */
2543	R0PTRTYPE(PPGMPOOL) pPoolR0;
2544	/** Shadow Page Pool - RC Ptr. */
2545	RCPTRTYPE(PPGMPOOL) pPoolRC;
2546
2547	/** We're not in a state which permits writes to guest memory.
2548	* (Only used in strict builds.) */
2549	bool fNoMorePhysWrites;
2550
2551	/** Flush the cache on the next access. */
2552	bool fPhysCacheFlushPending;
2553	/** @todo r=bird: Fix member names!*/
2554	/** PGMPhysRead cache */
2555	PGMPHYSCACHE pgmphysreadcache;
2556	/** PGMPhysWrite cache */
2557	PGMPHYSCACHE pgmphyswritecache;
2558
2559	/**
2560	* Data associated with managing the ring-3 mappings of the allocation chunks.
2561	*/
2562	struct
2563	{
2564	/** The chunk tree, ordered by chunk id. */
2565	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2566	R3PTRTYPE(PAVLU32NODECORE) pTree;
2567	#else
2568	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
2569	#endif
2570	/** The chunk mapping TLB. */
2571	PGMCHUNKR3MAPTLB Tlb;
2572	/** The number of mapped chunks. */
2573	uint32_t c;
2574	/** The maximum number of mapped chunks.
2575	* @cfgm PGM/MaxRing3Chunks */
2576	uint32_t cMax;
2577	/** The chunk age tree, ordered by ageing sequence number. */
2578	R3PTRTYPE(PAVLLU32NODECORE) pAgeTree;
2579	/** The current time. */
2580	uint32_t iNow;
2581	/** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
2582	uint32_t AgeingCountdown;
2583	} ChunkR3Map;
2584
2585	/**
2586	* The page mapping TLB for ring-3 and (for the time being) ring-0.
2587	*/
2588	PGMPAGER3MAPTLB PhysTlbHC;
2589
2590	/** @name The zero page.
2591	* @{ */
2592	/** The host physical address of the zero page. */
2593	RTHCPHYS HCPhysZeroPg;
2594	/** The ring-3 mapping of the zero page. */
2595	RTR3PTR pvZeroPgR3;
2596	/** The ring-0 mapping of the zero page. */
2597	RTR0PTR pvZeroPgR0;
2598	/** The GC mapping of the zero page. */
2599	RTGCPTR pvZeroPgGC;
2600	#if GC_ARCH_BITS != 32
2601	uint32_t u32ZeroAlignment; /*< Alignment padding. /
2602	#endif
2603	/** @}*/
2604
2605	/** The number of handy pages. */
2606	uint32_t cHandyPages;
2607	/**
2608	* Array of handy pages.
2609	*
2610	* This array is used in a two way communication between pgmPhysAllocPage
2611	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
2612	* an intermediary.
2613	*
2614	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
2615	* (The current size of 32 pages, means 128 KB of handy memory.)
2616	*/
2617	GMMPAGEDESC aHandyPages[32];
2618
2619	/** @name Release Statistics
2620	* @{ */
2621	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero.) /
2622	uint32_t cPrivatePages; /*< The number of private pages. /
2623	uint32_t cSharedPages; /*< The number of shared pages. /
2624	uint32_t cZeroPages; /*< The number of zero backed pages. /
2625	/** The number of times the guest has switched mode since last reset or statistics reset. */
2626	STAMCOUNTER cGuestModeChanges;
2627	/** @} */
2628
2629	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
2630	/** RC: Which statistic this \#PF should be attributed to. */
2631	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
2632	RTRCPTR padding0;
2633	/** R0: Which statistic this \#PF should be attributed to. */
2634	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
2635	RTR0PTR padding1;
2636
2637	/* Common */
2638	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2639	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2640	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2641	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2642	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2643	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2644	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2645	# endif
2646	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
2647	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
2648
2649	/* R3 only: */
2650	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2651	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2652	STAMCOUNTER StatR3GuestPDWrite; /*< R3: The total number of times pgmHCGuestPDWriteHandler() was called. /
2653	STAMCOUNTER StatR3GuestPDWriteConflict; /*< R3: The number of times GuestPDWriteContlict() detected a conflict. /
2654	STAMCOUNTER StatR3DynRamTotal; /*< R3: Allocated MBs of guest ram /
2655	STAMCOUNTER StatR3DynRamGrow; /*< R3: Nr of pgmr3PhysGrowRange calls. /
2656
2657	/* R0 only: */
2658	STAMCOUNTER StatR0DynMapMigrateInvlPg; /*< R0: invlpg in PGMDynMapMigrateAutoSet. /
2659	STAMPROFILE StatR0DynMapGCPageInl; /*< R0: Calls to pgmR0DynMapGCPageInlined. /
2660	STAMCOUNTER StatR0DynMapGCPageInlHits; /*< R0: Hash table lookup hits. /
2661	STAMCOUNTER StatR0DynMapGCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2662	STAMCOUNTER StatR0DynMapGCPageInlRamHits; /*< R0: 1st ram range hits. /
2663	STAMCOUNTER StatR0DynMapGCPageInlRamMisses; /*< R0: 1st ram range misses, takes slow path. /
2664	STAMPROFILE StatR0DynMapHCPageInl; /*< R0: Calls to pgmR0DynMapHCPageInlined. /
2665	STAMCOUNTER StatR0DynMapHCPageInlHits; /*< R0: Hash table lookup hits. /
2666	STAMCOUNTER StatR0DynMapHCPageInlMisses; /*< R0: Misses that falls back to code common with PGMDynMapHCPage. /
2667	STAMPROFILE StatR0DynMapHCPage; /*< R0: Calls to PGMDynMapHCPage. /
2668	STAMCOUNTER StatR0DynMapSetOptimize; /*< R0: Calls to pgmDynMapOptimizeAutoSet. /
2669	STAMCOUNTER StatR0DynMapSetSearchFlushes; /*< R0: Set search restorting to subset flushes. /
2670	STAMCOUNTER StatR0DynMapSetSearchHits; /*< R0: Set search hits. /
2671	STAMCOUNTER StatR0DynMapSetSearchMisses; /*< R0: Set search misses. /
2672	STAMCOUNTER StatR0DynMapPage; /*< R0: Calls to pgmR0DynMapPage. /
2673	STAMCOUNTER StatR0DynMapPageHits0; /*< R0: Hits at iPage+0. /
2674	STAMCOUNTER StatR0DynMapPageHits1; /*< R0: Hits at iPage+1. /
2675	STAMCOUNTER StatR0DynMapPageHits2; /*< R0: Hits at iPage+2. /
2676	STAMCOUNTER StatR0DynMapPageInvlPg; /*< R0: invlpg. /
2677	STAMCOUNTER StatR0DynMapPageSlow; /*< R0: Calls to pgmR0DynMapPageSlow. /
2678	STAMCOUNTER StatR0DynMapPageSlowLoopHits; /*< R0: Hits in the pgmR0DynMapPageSlow search loop. /
2679	STAMCOUNTER StatR0DynMapPageSlowLoopMisses; /*< R0: Misses in the pgmR0DynMapPageSlow search loop. /
2680	//STAMCOUNTER StatR0DynMapPageSlowLostHits; /*< R0: Lost hits. /
2681	STAMCOUNTER StatR0DynMapSubsets; /*< R0: Times PGMDynMapPushAutoSubset was called. /
2682	STAMCOUNTER StatR0DynMapPopFlushes; /*< R0: Times PGMDynMapPopAutoSubset flushes the subset. /
2683
2684	/* RC only: */
2685	STAMCOUNTER StatRCDynMapCacheMisses; /*< RC: The number of dynamic page mapping cache hits /
2686	STAMCOUNTER StatRCDynMapCacheHits; /*< RC: The number of dynamic page mapping cache misses /
2687	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2688	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2689
2690	/* RZ only: */
2691	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
2692	STAMPROFILE StatRZTrap0eTimeCheckPageFault;
2693	STAMPROFILE StatRZTrap0eTimeSyncPT;
2694	STAMPROFILE StatRZTrap0eTimeMapping;
2695	STAMPROFILE StatRZTrap0eTimeOutOfSync;
2696	STAMPROFILE StatRZTrap0eTimeHandlers;
2697	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
2698	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
2699	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
2700	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
2701	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
2702	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
2703	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
2704	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
2705	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
2706	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
2707	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
2708	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
2709	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
2710	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
2711	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
2712	STAMCOUNTER StatRZTrap0eHandlersPhysical; /*< RC/R0: Number of traps due to physical access handlers. /
2713	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
2714	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
2715	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
2716	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
2717	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
2718	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: #PF err kind /
2719	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: #PF err kind /
2720	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: #PF err kind /
2721	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: #PF err kind /
2722	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: #PF err kind /
2723	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: #PF err kind /
2724	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: #PF err kind /
2725	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: #PF err kind /
2726	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: #PF err kind /
2727	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: #PF err kind /
2728	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: #PF err kind /
2729	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest #PFs. /
2730	STAMCOUNTER StatRZTrap0eGuestPFUnh; /*< RC/R0: Real guest #PF ending up at the end of the #PF code. /
2731	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest #PF to HMA or other mapping. /
2732	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
2733	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
2734	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the #PFs. /
2735	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
2736	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
2737	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
2738	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
2739	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
2740
2741	/* HC - R3 and (maybe) R0: */
2742
2743	/* RZ & R3: */
2744	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
2745	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
2746	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
2747	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
2748	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
2749	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
2750	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
2751	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
2752	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
2753	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
2754	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
2755	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
2756	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
2757	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
2758	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
2759	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
2760	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2761	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
2762	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
2763	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
2764	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2765	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
2766	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
2767	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
2768	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
2769	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
2770	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
2771	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
2772	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
2773	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
2774	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
2775	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2776	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2777	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
2778	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2779	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2780	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2781	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2782	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2783	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2784	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
2785	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2786	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2787	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2788	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2789	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2790	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2791	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2792	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
2793	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2794	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2795	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2796	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2797	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
2798
2799	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
2800	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
2801	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
2802	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
2803	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
2804	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
2805	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
2806	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
2807	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
2808	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
2809	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
2810	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
2811	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
2812	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
2813	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
2814	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
2815	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
2816	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
2817	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
2818	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
2819	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2820	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
2821	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
2822	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
2823	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
2824	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
2825	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
2826	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
2827	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
2828	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
2829	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
2830	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
2831	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
2832	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
2833	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
2834	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
2835	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
2836	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2837	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in #PF or VerifyAccessSyncPage. /
2838	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in #PF or VerifyAccessSyncPage. /
2839	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
2840	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2841	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2842	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2843	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2844	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2845	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2846	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2847	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
2848	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
2849	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
2850	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
2851	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
2852	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
2853	#endif /* VBOX_WITH_STATISTICS */
2854	} PGM;
2855	/** Pointer to the PGM instance data. */
2856	typedef PGM *PPGM;
2857
2858
2859	/**
2860	* PGMCPU Data (part of VMCPU).
2861	*/
2862	typedef struct PGMCPU
2863	{
2864	/** Offset to the VMCPU structure. */
2865	RTINT offVMCPU;
2866	/** Automatically tracked physical memory mapping set.
2867	* Ring-0 and strict raw-mode builds. */
2868	PGMMAPSET AutoSet;
2869	} PGMCPU;
2870	/** Pointer to the per-cpu PGM data. */
2871	typedef PGMCPU *PPGMCPU;
2872
2873
2874	/** @name PGM::fSyncFlags Flags
2875	* @{
2876	*/
2877	/** Updates the virtual access handler state bit in PGMPAGE. */
2878	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
2879	/** Always sync CR3. */
2880	#define PGM_SYNC_ALWAYS RT_BIT(1)
2881	/** Check monitoring on next CR3 (re)load and invalidate page. */
2882	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
2883	/** Check guest mapping in SyncCR3. */
2884	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
2885	/** Clear the page pool (a light weight flush). */
2886	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(8)
2887	/** @} */
2888
2889
2890	__BEGIN_DECLS
2891
2892	int pgmLock(PVM pVM);
2893	void pgmUnlock(PVM pVM);
2894
2895	VMMRCDECL(int) pgmGCGuestPDWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2896	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, void pvFault, RTGCPHYS GCPhysFault, void pvUser);
2897
2898	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
2899	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
2900	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
2901	void pgmR3MapRelocate(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping, RTGCPTR GCPtrNewMapping);
2902	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2903
2904	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
2905	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
2906	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
2907	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
2908	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
2909	#else
2910	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
2911	#endif
2912	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
2913
2914
2915	void pgmPhysFreePage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2916	int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
2917	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
2918	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPPGMPAGEMAP ppMap, void **ppv);
2919	#ifdef IN_RING3
2920	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
2921	int pgmR3PhysRamReset(PVM pVM);
2922	int pgmR3PhysRomReset(PVM pVM);
2923	# ifndef VBOX_WITH_NEW_PHYS_CODE
2924	int pgmr3PhysGrowRange(PVM pVM, RTGCPHYS GCPhys);
2925	# endif
2926
2927	int pgmR3PoolInit(PVM pVM);
2928	void pgmR3PoolRelocate(PVM pVM);
2929	void pgmR3PoolReset(PVM pVM);
2930
2931	#endif /* IN_RING3 */
2932	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2933	int pgmR0DynMapHCPageCommon(PVM pVM, PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv);
2934	#endif
2935	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2936	void *pgmPoolMapPageFallback(PPGM pPGM, PPGMPOOLPAGE pPage);
2937	#endif
2938	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage);
2939	PPGMPOOLPAGE pgmPoolGetPageByHCPhys(PVM pVM, RTHCPHYS HCPhys);
2940	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
2941	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
2942	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2943	void pgmPoolFlushAll(PVM pVM);
2944	void pgmPoolClearAll(PVM pVM);
2945	int pgmPoolSyncCR3(PVM pVM);
2946	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
2947	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
2948	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
2949	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
2950	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
2951	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
2952	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT);
2953	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage);
2954	#ifdef PGMPOOL_WITH_MONITORING
2955	# ifdef IN_RING3
2956	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTHCPTR pvAddress, PDISCPUSTATE pCpu);
2957	# else
2958	void pgmPoolMonitorChainChanging(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, RTGCPTR pvAddress, PDISCPUSTATE pCpu);
2959	# endif
2960	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2961	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
2962	void pgmPoolMonitorModifiedClearAll(PVM pVM);
2963	int pgmPoolMonitorMonitorCR3(PPGMPOOL pPool, uint16_t idxRoot, RTGCPHYS GCPhysCR3);
2964	int pgmPoolMonitorUnmonitorCR3(PPGMPOOL pPool, uint16_t idxRoot);
2965	#endif
2966
2967	__END_DECLS
2968
2969
2970	/**
2971	* Gets the PGMRAMRANGE structure for a guest page.
2972	*
2973	* @returns Pointer to the RAM range on success.
2974	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
2975	*
2976	* @param pPGM PGM handle.
2977	* @param GCPhys The GC physical address.
2978	*/
2979	DECLINLINE(PPGMRAMRANGE) pgmPhysGetRange(PPGM pPGM, RTGCPHYS GCPhys)
2980	{
2981	/*
2982	* Optimize for the first range.
2983	*/
2984	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
2985	RTGCPHYS off = GCPhys - pRam->GCPhys;
2986	if (RT_UNLIKELY(off >= pRam->cb))
2987	{
2988	do
2989	{
2990	pRam = pRam->CTX_SUFF(pNext);
2991	if (RT_UNLIKELY(!pRam))
2992	break;
2993	off = GCPhys - pRam->GCPhys;
2994	} while (off >= pRam->cb);
2995	}
2996	return pRam;
2997	}
2998
2999
3000	/**
3001	* Gets the PGMPAGE structure for a guest page.
3002	*
3003	* @returns Pointer to the page on success.
3004	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3005	*
3006	* @param pPGM PGM handle.
3007	* @param GCPhys The GC physical address.
3008	*/
3009	DECLINLINE(PPGMPAGE) pgmPhysGetPage(PPGM pPGM, RTGCPHYS GCPhys)
3010	{
3011	/*
3012	* Optimize for the first range.
3013	*/
3014	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3015	RTGCPHYS off = GCPhys - pRam->GCPhys;
3016	if (RT_UNLIKELY(off >= pRam->cb))
3017	{
3018	do
3019	{
3020	pRam = pRam->CTX_SUFF(pNext);
3021	if (RT_UNLIKELY(!pRam))
3022	return NULL;
3023	off = GCPhys - pRam->GCPhys;
3024	} while (off >= pRam->cb);
3025	}
3026	return &pRam->aPages[off >> PAGE_SHIFT];
3027	}
3028
3029
3030	/**
3031	* Gets the PGMPAGE structure for a guest page.
3032	*
3033	* Old Phys code: Will make sure the page is present.
3034	*
3035	* @returns VBox status code.
3036	* @retval VINF_SUCCESS and a valid *ppPage on success.
3037	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3038	*
3039	* @param pPGM PGM handle.
3040	* @param GCPhys The GC physical address.
3041	* @param ppPage Where to store the page poitner on success.
3042	*/
3043	DECLINLINE(int) pgmPhysGetPageEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage)
3044	{
3045	/*
3046	* Optimize for the first range.
3047	*/
3048	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3049	RTGCPHYS off = GCPhys - pRam->GCPhys;
3050	if (RT_UNLIKELY(off >= pRam->cb))
3051	{
3052	do
3053	{
3054	pRam = pRam->CTX_SUFF(pNext);
3055	if (RT_UNLIKELY(!pRam))
3056	{
3057	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3058	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3059	}
3060	off = GCPhys - pRam->GCPhys;
3061	} while (off >= pRam->cb);
3062	}
3063	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3064	#ifndef VBOX_WITH_NEW_PHYS_CODE
3065
3066	/*
3067	* Make sure it's present.
3068	*/
3069	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3070	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3071	{
3072	#ifdef IN_RING3
3073	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3074	#else
3075	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3076	#endif
3077	if (RT_FAILURE(rc))
3078	{
3079	ppPage = NULL; / avoid incorrect and very annoying GCC warnings */
3080	return rc;
3081	}
3082	Assert(rc == VINF_SUCCESS);
3083	}
3084	#endif
3085	return VINF_SUCCESS;
3086	}
3087
3088
3089
3090
3091	/**
3092	* Gets the PGMPAGE structure for a guest page.
3093	*
3094	* Old Phys code: Will make sure the page is present.
3095	*
3096	* @returns VBox status code.
3097	* @retval VINF_SUCCESS and a valid *ppPage on success.
3098	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if the address isn't valid.
3099	*
3100	* @param pPGM PGM handle.
3101	* @param GCPhys The GC physical address.
3102	* @param ppPage Where to store the page poitner on success.
3103	* @param ppRamHint Where to read and store the ram list hint.
3104	* The caller initializes this to NULL before the call.
3105	*/
3106	DECLINLINE(int) pgmPhysGetPageWithHintEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRamHint)
3107	{
3108	RTGCPHYS off;
3109	PPGMRAMRANGE pRam = *ppRamHint;
3110	if ( !pRam
3111	\|\| RT_UNLIKELY((off = GCPhys - pRam->GCPhys) >= pRam->cb))
3112	{
3113	pRam = pPGM->CTX_SUFF(pRamRanges);
3114	off = GCPhys - pRam->GCPhys;
3115	if (RT_UNLIKELY(off >= pRam->cb))
3116	{
3117	do
3118	{
3119	pRam = pRam->CTX_SUFF(pNext);
3120	if (RT_UNLIKELY(!pRam))
3121	{
3122	ppPage = NULL; / Kill the incorrect and extremely annoying GCC warnings. */
3123	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3124	}
3125	off = GCPhys - pRam->GCPhys;
3126	} while (off >= pRam->cb);
3127	}
3128	*ppRamHint = pRam;
3129	}
3130	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3131	#ifndef VBOX_WITH_NEW_PHYS_CODE
3132
3133	/*
3134	* Make sure it's present.
3135	*/
3136	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3137	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3138	{
3139	#ifdef IN_RING3
3140	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3141	#else
3142	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3143	#endif
3144	if (RT_FAILURE(rc))
3145	{
3146	ppPage = NULL; / Shut up annoying smart ass. */
3147	return rc;
3148	}
3149	Assert(rc == VINF_SUCCESS);
3150	}
3151	#endif
3152	return VINF_SUCCESS;
3153	}
3154
3155
3156	/**
3157	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3158	*
3159	* @returns Pointer to the page on success.
3160	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3161	*
3162	* @param pPGM PGM handle.
3163	* @param GCPhys The GC physical address.
3164	* @param ppRam Where to store the pointer to the PGMRAMRANGE.
3165	*/
3166	DECLINLINE(PPGMPAGE) pgmPhysGetPageAndRange(PPGM pPGM, RTGCPHYS GCPhys, PPGMRAMRANGE *ppRam)
3167	{
3168	/*
3169	* Optimize for the first range.
3170	*/
3171	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3172	RTGCPHYS off = GCPhys - pRam->GCPhys;
3173	if (RT_UNLIKELY(off >= pRam->cb))
3174	{
3175	do
3176	{
3177	pRam = pRam->CTX_SUFF(pNext);
3178	if (RT_UNLIKELY(!pRam))
3179	return NULL;
3180	off = GCPhys - pRam->GCPhys;
3181	} while (off >= pRam->cb);
3182	}
3183	*ppRam = pRam;
3184	return &pRam->aPages[off >> PAGE_SHIFT];
3185	}
3186
3187
3188	/**
3189	* Gets the PGMPAGE structure for a guest page together with the PGMRAMRANGE.
3190	*
3191	* @returns Pointer to the page on success.
3192	* @returns NULL on a VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS condition.
3193	*
3194	* @param pPGM PGM handle.
3195	* @param GCPhys The GC physical address.
3196	* @param ppPage Where to store the pointer to the PGMPAGE structure.
3197	* @param ppRam Where to store the pointer to the PGMRAMRANGE structure.
3198	*/
3199	DECLINLINE(int) pgmPhysGetPageAndRangeEx(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam)
3200	{
3201	/*
3202	* Optimize for the first range.
3203	*/
3204	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3205	RTGCPHYS off = GCPhys - pRam->GCPhys;
3206	if (RT_UNLIKELY(off >= pRam->cb))
3207	{
3208	do
3209	{
3210	pRam = pRam->CTX_SUFF(pNext);
3211	if (RT_UNLIKELY(!pRam))
3212	{
3213	ppRam = NULL; / Shut up silly GCC warnings. */
3214	ppPage = NULL; / ditto */
3215	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3216	}
3217	off = GCPhys - pRam->GCPhys;
3218	} while (off >= pRam->cb);
3219	}
3220	*ppRam = pRam;
3221	*ppPage = &pRam->aPages[off >> PAGE_SHIFT];
3222	#ifndef VBOX_WITH_NEW_PHYS_CODE
3223
3224	/*
3225	* Make sure it's present.
3226	*/
3227	if (RT_UNLIKELY( !PGM_PAGE_GET_HCPHYS(*ppPage)
3228	&& (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)))
3229	{
3230	#ifdef IN_RING3
3231	int rc = pgmr3PhysGrowRange(PGM2VM(pPGM), GCPhys);
3232	#else
3233	int rc = CTXALLMID(VMM, CallHost)(PGM2VM(pPGM), VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
3234	#endif
3235	if (RT_FAILURE(rc))
3236	{
3237	ppPage = NULL; / Shut up silly GCC warnings. */
3238	ppPage = NULL; / ditto */
3239	return rc;
3240	}
3241	Assert(rc == VINF_SUCCESS);
3242
3243	}
3244	#endif
3245	return VINF_SUCCESS;
3246	}
3247
3248
3249	/**
3250	* Convert GC Phys to HC Phys.
3251	*
3252	* @returns VBox status.
3253	* @param pPGM PGM handle.
3254	* @param GCPhys The GC physical address.
3255	* @param pHCPhys Where to store the corresponding HC physical address.
3256	*
3257	* @deprecated Doesn't deal with zero, shared or write monitored pages.
3258	* Avoid when writing new code!
3259	*/
3260	DECLINLINE(int) pgmRamGCPhys2HCPhys(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPHYS pHCPhys)
3261	{
3262	PPGMPAGE pPage;
3263	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3264	if (RT_FAILURE(rc))
3265	return rc;
3266	*pHCPhys = PGM_PAGE_GET_HCPHYS(pPage) \| (GCPhys & PAGE_OFFSET_MASK);
3267	return VINF_SUCCESS;
3268	}
3269
3270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3271
3272	/**
3273	* Inlined version of the ring-0 version of PGMDynMapHCPage that
3274	* optimizes access to pages already in the set.
3275	*
3276	* @returns See pgmR0DynMapHCPageCommon.
3277	* @param pPGM Pointer to the PVM instance data.
3278	* @param HCPhys The physical address of the page.
3279	* @param ppv Where to store the mapping address.
3280	*/
3281	DECLINLINE(int) pgmR0DynMapHCPageInlined(PPGM pPGM, RTHCPHYS HCPhys, void **ppv)
3282	{
3283	STAM_PROFILE_START(&pPGM->StatR0DynMapHCPageInl, a);
3284	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3285	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3286	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3287	int rc;
3288
3289	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3290	unsigned iEntry = pSet->aiHashTable[iHash];
3291	if ( iEntry < pSet->cEntries
3292	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3293	{
3294	*ppv = pSet->aEntries[iEntry].pvPage;
3295	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlHits);
3296	rc = VINF_SUCCESS;
3297	}
3298	else
3299	{
3300	STAM_COUNTER_INC(&pPGM->StatR0DynMapHCPageInlMisses);
3301	rc = pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3302	}
3303
3304	STAM_PROFILE_STOP(&pPGM->StatR0DynMapHCPageInl, a);
3305	return rc;
3306	}
3307
3308
3309	/**
3310	* Inlined version of the ring-0 version of PGMDynMapGCPage that optimizes
3311	* access to pages already in the set.
3312	*
3313	* @returns See pgmR0DynMapHCPageCommon.
3314	* @param pPGM Pointer to the PVM instance data.
3315	* @param HCPhys The physical address of the page.
3316	* @param ppv Where to store the mapping address.
3317	*/
3318	DECLINLINE(int) pgmR0DynMapGCPageInlined(PPGM pPGM, RTGCPHYS GCPhys, void **ppv)
3319	{
3320	STAM_PROFILE_START(&pPGM->StatR0DynMapGCPageInl, a);
3321	Assert(!(GCPhys & PAGE_OFFSET_MASK));
3322
3323	/*
3324	* Get the ram range.
3325	*/
3326	PPGMRAMRANGE pRam = pPGM->CTX_SUFF(pRamRanges);
3327	RTGCPHYS off = GCPhys - pRam->GCPhys;
3328	if (RT_UNLIKELY(off >= pRam->cb
3329	/** @todo \|\| page state stuff */))
3330	{
3331	/* This case is not counted into StatR0DynMapGCPageInl. */
3332	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamMisses);
3333	return PGMDynMapGCPage(PGM2VM(pPGM), GCPhys, ppv);
3334	}
3335
3336	RTHCPHYS HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[off >> PAGE_SHIFT]);
3337	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlRamHits);
3338
3339	/*
3340	* pgmR0DynMapHCPageInlined with out stats.
3341	*/
3342	PPGMMAPSET pSet = &((PPGMCPU)((uint8_t )VMMGetCpu(PGM2VM(pPGM)) + pPGM->offVCpu))->AutoSet; / very pretty ;-) */
3343	Assert(!(HCPhys & PAGE_OFFSET_MASK));
3344	Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
3345	int rc;
3346
3347	unsigned iHash = PGMMAPSET_HASH(HCPhys);
3348	unsigned iEntry = pSet->aiHashTable[iHash];
3349	if ( iEntry < pSet->cEntries
3350	&& pSet->aEntries[iEntry].HCPhys == HCPhys)
3351	{
3352	*ppv = pSet->aEntries[iEntry].pvPage;
3353	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlHits);
3354	rc = VINF_SUCCESS;
3355	}
3356	else
3357	{
3358	STAM_COUNTER_INC(&pPGM->StatR0DynMapGCPageInlMisses);
3359	rc = pgmR0DynMapHCPageCommon(PGM2VM(pPGM), pSet, HCPhys, ppv);
3360	}
3361
3362	STAM_PROFILE_STOP(&pPGM->StatR0DynMapGCPageInl, a);
3363	return rc;
3364	}
3365
3366	#endif /* VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
3367
3368	#ifndef IN_RC
3369	/**
3370	* Queries the Physical TLB entry for a physical guest page,
3371	* attemting to load the TLB entry if necessary.
3372	*
3373	* @returns VBox status code.
3374	* @retval VINF_SUCCESS on success
3375	* @retval VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS if it's not a valid physical address.
3376	* @param pPGM The PGM instance handle.
3377	* @param GCPhys The address of the guest page.
3378	* @param ppTlbe Where to store the pointer to the TLB entry.
3379	*/
3380
3381	DECLINLINE(int) pgmPhysPageQueryTlbe(PPGM pPGM, RTGCPHYS GCPhys, PPPGMPAGEMAPTLBE ppTlbe)
3382	{
3383	int rc;
3384	PPGMPAGEMAPTLBE pTlbe = &pPGM->CTXSUFF(PhysTlb).aEntries[PGM_PAGEMAPTLB_IDX(GCPhys)];
3385	if (pTlbe->GCPhys == (GCPhys & X86_PTE_PAE_PG_MASK))
3386	{
3387	STAM_COUNTER_INC(&pPGM->CTX_MID_Z(Stat,PageMapTlbHits));
3388	rc = VINF_SUCCESS;
3389	}
3390	else
3391	rc = pgmPhysPageLoadIntoTlb(pPGM, GCPhys);
3392	*ppTlbe = pTlbe;
3393	return rc;
3394	}
3395	#endif /* !IN_RC */
3396
3397	#if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3398
3399	# ifndef VBOX_WITH_NEW_PHYS_CODE
3400	/**
3401	* Convert GC Phys to HC Virt.
3402	*
3403	* @returns VBox status.
3404	* @param pPGM PGM handle.
3405	* @param GCPhys The GC physical address.
3406	* @param pHCPtr Where to store the corresponding HC virtual address.
3407	*
3408	* @deprecated This will be eliminated by PGMPhysGCPhys2CCPtr. Only user is
3409	* pgmPoolMonitorGCPtr2CCPtr.
3410	*/
3411	DECLINLINE(int) pgmRamGCPhys2HCPtr(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr)
3412	{
3413	PPGMRAMRANGE pRam;
3414	PPGMPAGE pPage;
3415	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3416	if (RT_FAILURE(rc))
3417	{
3418	pHCPtr = 0; / Shut up silly GCC warnings. */
3419	return rc;
3420	}
3421	RTGCPHYS off = GCPhys - pRam->GCPhys;
3422
3423	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3424	{
3425	unsigned iChunk = off >> PGM_DYNAMIC_CHUNK_SHIFT;
3426	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[iChunk] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3427	return VINF_SUCCESS;
3428	}
3429	if (pRam->pvR3)
3430	{
3431	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3432	return VINF_SUCCESS;
3433	}
3434	pHCPtr = 0; / Shut up silly GCC warnings. */
3435	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3436	}
3437	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
3438	#endif /* !IN_RC && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) */
3439
3440	/**
3441	* Convert GC Phys to HC Virt and HC Phys.
3442	*
3443	* @returns VBox status.
3444	* @param pPGM PGM handle.
3445	* @param GCPhys The GC physical address.
3446	* @param pHCPtr Where to store the corresponding HC virtual address.
3447	* @param pHCPhys Where to store the HC Physical address and its flags.
3448	*
3449	* @deprecated Will go away or be changed. Only user is MapCR3. MapCR3 will have to do ring-3
3450	* and ring-0 locking of the CR3 in a lazy fashion I'm fear... or perhaps not. we'll see.
3451	*/
3452	DECLINLINE(int) pgmRamGCPhys2HCPtrAndHCPhysWithFlags(PPGM pPGM, RTGCPHYS GCPhys, PRTHCPTR pHCPtr, PRTHCPHYS pHCPhys)
3453	{
3454	PPGMRAMRANGE pRam;
3455	PPGMPAGE pPage;
3456	int rc = pgmPhysGetPageAndRangeEx(pPGM, GCPhys, &pPage, &pRam);
3457	if (RT_FAILURE(rc))
3458	{
3459	pHCPtr = 0; / Shut up crappy GCC warnings */
3460	pHCPhys = 0; / ditto */
3461	return rc;
3462	}
3463	RTGCPHYS off = GCPhys - pRam->GCPhys;
3464
3465	pHCPhys = pPage->HCPhys; /* @todo PAGE FLAGS */
3466	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
3467	{
3468	unsigned idx = (off >> PGM_DYNAMIC_CHUNK_SHIFT);
3469	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* ASSUMES only MapCR3 usage. */
3470	PRTR3UINTPTR paChunkR3Ptrs = (PRTR3UINTPTR)MMHyperR3ToCC(PGM2VM(pPGM), pRam->paChunkR3Ptrs);
3471	*pHCPtr = (RTHCPTR)(paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3472	#else
3473	*pHCPtr = (RTHCPTR)(pRam->paChunkR3Ptrs[idx] + (off & PGM_DYNAMIC_CHUNK_OFFSET_MASK));
3474	#endif
3475	return VINF_SUCCESS;
3476	}
3477	if (pRam->pvR3)
3478	{
3479	*pHCPtr = (RTHCPTR)((RTHCUINTPTR)pRam->pvR3 + off);
3480	return VINF_SUCCESS;
3481	}
3482	*pHCPtr = 0;
3483	return VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
3484	}
3485
3486
3487	/**
3488	* Clears flags associated with a RAM address.
3489	*
3490	* @returns VBox status code.
3491	* @param pPGM PGM handle.
3492	* @param GCPhys Guest context physical address.
3493	* @param fFlags fFlags to clear. (Bits 0-11.)
3494	*/
3495	DECLINLINE(int) pgmRamFlagsClearByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3496	{
3497	PPGMPAGE pPage;
3498	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3499	if (RT_FAILURE(rc))
3500	return rc;
3501
3502	fFlags &= ~X86_PTE_PAE_PG_MASK;
3503	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3504	return VINF_SUCCESS;
3505	}
3506
3507
3508	/**
3509	* Clears flags associated with a RAM address.
3510	*
3511	* @returns VBox status code.
3512	* @param pPGM PGM handle.
3513	* @param GCPhys Guest context physical address.
3514	* @param fFlags fFlags to clear. (Bits 0-11.)
3515	* @param ppRamHint Where to read and store the ram list hint.
3516	* The caller initializes this to NULL before the call.
3517	*/
3518	DECLINLINE(int) pgmRamFlagsClearByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3519	{
3520	PPGMPAGE pPage;
3521	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3522	if (RT_FAILURE(rc))
3523	return rc;
3524
3525	fFlags &= ~X86_PTE_PAE_PG_MASK;
3526	pPage->HCPhys &= ~(RTHCPHYS)fFlags; /** @todo PAGE FLAGS */
3527	return VINF_SUCCESS;
3528	}
3529
3530
3531	/**
3532	* Sets (bitwise OR) flags associated with a RAM address.
3533	*
3534	* @returns VBox status code.
3535	* @param pPGM PGM handle.
3536	* @param GCPhys Guest context physical address.
3537	* @param fFlags fFlags to set clear. (Bits 0-11.)
3538	*/
3539	DECLINLINE(int) pgmRamFlagsSetByGCPhys(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags)
3540	{
3541	PPGMPAGE pPage;
3542	int rc = pgmPhysGetPageEx(pPGM, GCPhys, &pPage);
3543	if (RT_FAILURE(rc))
3544	return rc;
3545
3546	fFlags &= ~X86_PTE_PAE_PG_MASK;
3547	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3548	return VINF_SUCCESS;
3549	}
3550
3551
3552	/**
3553	* Sets (bitwise OR) flags associated with a RAM address.
3554	*
3555	* @returns VBox status code.
3556	* @param pPGM PGM handle.
3557	* @param GCPhys Guest context physical address.
3558	* @param fFlags fFlags to set clear. (Bits 0-11.)
3559	* @param ppRamHint Where to read and store the ram list hint.
3560	* The caller initializes this to NULL before the call.
3561	*/
3562	DECLINLINE(int) pgmRamFlagsSetByGCPhysWithHint(PPGM pPGM, RTGCPHYS GCPhys, unsigned fFlags, PPGMRAMRANGE *ppRamHint)
3563	{
3564	PPGMPAGE pPage;
3565	int rc = pgmPhysGetPageWithHintEx(pPGM, GCPhys, &pPage, ppRamHint);
3566	if (RT_FAILURE(rc))
3567	return rc;
3568
3569	fFlags &= ~X86_PTE_PAE_PG_MASK;
3570	pPage->HCPhys \|= fFlags; /** @todo PAGE FLAGS */
3571	return VINF_SUCCESS;
3572	}
3573
3574
3575	/**
3576	* Calculated the guest physical address of the large (4 MB) page in 32 bits paging mode.
3577	* Takes PSE-36 into account.
3578	*
3579	* @returns guest physical address
3580	* @param pPGM Pointer to the PGM instance data.
3581	* @param Pde Guest Pde
3582	*/
3583	DECLINLINE(RTGCPHYS) pgmGstGet4MBPhysPage(PPGM pPGM, X86PDE Pde)
3584	{
3585	RTGCPHYS GCPhys = Pde.u & X86_PDE4M_PG_MASK;
3586	GCPhys \|= (RTGCPHYS)Pde.b.u8PageNoHigh << 32;
3587
3588	return GCPhys & pPGM->GCPhys4MBPSEMask;
3589	}
3590
3591
3592	/**
3593	* Gets the page directory entry for the specified address (32-bit paging).
3594	*
3595	* @returns The page directory entry in question.
3596	* @param pPGM Pointer to the PGM instance data.
3597	* @param GCPtr The address.
3598	*/
3599	DECLINLINE(X86PDE) pgmGstGet32bitPDE(PPGM pPGM, RTGCPTR GCPtr)
3600	{
3601	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3602	PCX86PD pGuestPD = 0;
3603	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3604	if (RT_FAILURE(rc))
3605	{
3606	X86PDE ZeroPde = {0};
3607	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPde);
3608	}
3609	return pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3610	#else
3611	return pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3612	#endif
3613	}
3614
3615
3616	/**
3617	* Gets the address of a specific page directory entry (32-bit paging).
3618	*
3619	* @returns Pointer the page directory entry in question.
3620	* @param pPGM Pointer to the PGM instance data.
3621	* @param GCPtr The address.
3622	*/
3623	DECLINLINE(PX86PDE) pgmGstGet32bitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3624	{
3625	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3626	PX86PD pGuestPD = 0;
3627	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3628	AssertRCReturn(rc, 0);
3629	return &pGuestPD->a[GCPtr >> X86_PD_SHIFT];
3630	#else
3631	return &pPGM->CTX_SUFF(pGst32BitPd)->a[GCPtr >> X86_PD_SHIFT];
3632	#endif
3633	}
3634
3635
3636	/**
3637	* Gets the address the guest page directory (32-bit paging).
3638	*
3639	* @returns Pointer the page directory entry in question.
3640	* @param pPGM Pointer to the PGM instance data.
3641	*/
3642	DECLINLINE(PX86PD) pgmGstGet32bitPDPtr(PPGM pPGM)
3643	{
3644	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3645	PX86PD pGuestPD = 0;
3646	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPD);
3647	AssertRCReturn(rc, 0);
3648	return pGuestPD;
3649	#else
3650	return pPGM->CTX_SUFF(pGst32BitPd);
3651	#endif
3652	}
3653
3654
3655	/**
3656	* Gets the guest page directory pointer table.
3657	*
3658	* @returns Pointer to the page directory in question.
3659	* @returns NULL if the page directory is not present or on an invalid page.
3660	* @param pPGM Pointer to the PGM instance data.
3661	*/
3662	DECLINLINE(PX86PDPT) pgmGstGetPaePDPTPtr(PPGM pPGM)
3663	{
3664	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3665	PX86PDPT pGuestPDPT = 0;
3666	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3667	AssertRCReturn(rc, 0);
3668	return pGuestPDPT;
3669	#else
3670	return pPGM->CTX_SUFF(pGstPaePdpt);
3671	#endif
3672	}
3673
3674
3675	/**
3676	* Gets the guest page directory pointer table entry for the specified address.
3677	*
3678	* @returns Pointer to the page directory in question.
3679	* @returns NULL if the page directory is not present or on an invalid page.
3680	* @param pPGM Pointer to the PGM instance data.
3681	* @param GCPtr The address.
3682	*/
3683	DECLINLINE(PX86PDPE) pgmGstGetPaePDPEPtr(PPGM pPGM, RTGCPTR GCPtr)
3684	{
3685	AssertGCPtr32(GCPtr);
3686
3687	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3688	PX86PDPT pGuestPDPT = 0;
3689	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPDPT);
3690	AssertRCReturn(rc, 0);
3691	return &pGuestPDPT->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3692	#else
3693	return &pPGM->CTX_SUFF(pGstPaePdpt)->a[(GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE];
3694	#endif
3695	}
3696
3697
3698	/**
3699	* Gets the page directory for the specified address.
3700	*
3701	* @returns Pointer to the page directory in question.
3702	* @returns NULL if the page directory is not present or on an invalid page.
3703	* @param pPGM Pointer to the PGM instance data.
3704	* @param GCPtr The address.
3705	*/
3706	DECLINLINE(PX86PDPAE) pgmGstGetPaePD(PPGM pPGM, RTGCPTR GCPtr)
3707	{
3708	AssertGCPtr32(GCPtr);
3709
3710	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3711	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3712	AssertReturn(pGuestPDPT, 0);
3713	#else
3714	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3715	#endif
3716	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3717	if (pGuestPDPT->a[iPdPt].n.u1Present)
3718	{
3719	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3720	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3721	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3722	#endif
3723
3724	/* cache is out-of-sync. */
3725	PX86PDPAE pPD;
3726	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3727	if (RT_SUCCESS(rc))
3728	return pPD;
3729	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3730	/* returning NULL is ok if we assume it's just an invalid page of some kind emulated as all 0s. (not quite true) */
3731	}
3732	return NULL;
3733	}
3734
3735
3736	/**
3737	* Gets the page directory entry for the specified address.
3738	*
3739	* @returns Pointer to the page directory entry in question.
3740	* @returns NULL if the page directory is not present or on an invalid page.
3741	* @param pPGM Pointer to the PGM instance data.
3742	* @param GCPtr The address.
3743	*/
3744	DECLINLINE(PX86PDEPAE) pgmGstGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
3745	{
3746	AssertGCPtr32(GCPtr);
3747
3748	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3749	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3750	AssertReturn(pGuestPDPT, 0);
3751	#else
3752	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3753	#endif
3754	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3755	if (pGuestPDPT->a[iPdPt].n.u1Present)
3756	{
3757	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3758	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3759	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3760	return &pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3761	#endif
3762
3763	/* The cache is out-of-sync. */
3764	PX86PDPAE pPD;
3765	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3766	if (RT_SUCCESS(rc))
3767	return &pPD->a[iPD];
3768	AssertMsgFailed(("Impossible! rc=%Rrc PDPE=%RX64\n", rc, pGuestPDPT->a[iPdPt].u));
3769	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page or something which we'll emulate as all 0s. (not quite true) */
3770	}
3771	return NULL;
3772	}
3773
3774
3775	/**
3776	* Gets the page directory entry for the specified address.
3777	*
3778	* @returns The page directory entry in question.
3779	* @returns A non-present entry if the page directory is not present or on an invalid page.
3780	* @param pPGM Pointer to the PGM instance data.
3781	* @param GCPtr The address.
3782	*/
3783	DECLINLINE(X86PDEPAE) pgmGstGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
3784	{
3785	AssertGCPtr32(GCPtr);
3786
3787	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3788	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3789	if (RT_LIKELY(pGuestPDPT))
3790	#else
3791	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3792	#endif
3793	{
3794	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3795	if (pGuestPDPT->a[iPdPt].n.u1Present)
3796	{
3797	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3798	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3799	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3800	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt]->a[iPD];
3801	#endif
3802
3803	/* cache is out-of-sync. */
3804	PX86PDPAE pPD;
3805	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3806	if (RT_SUCCESS(rc))
3807	return pPD->a[iPD];
3808	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt]));
3809	}
3810	}
3811	X86PDEPAE ZeroPde = {0};
3812	return ZeroPde;
3813	}
3814
3815
3816	/**
3817	* Gets the page directory pointer table entry for the specified address
3818	* and returns the index into the page directory
3819	*
3820	* @returns Pointer to the page directory in question.
3821	* @returns NULL if the page directory is not present or on an invalid page.
3822	* @param pPGM Pointer to the PGM instance data.
3823	* @param GCPtr The address.
3824	* @param piPD Receives the index into the returned page directory
3825	* @param pPdpe Receives the page directory pointer entry. Optional.
3826	*/
3827	DECLINLINE(PX86PDPAE) pgmGstGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr, unsigned *piPD, PX86PDPE pPdpe)
3828	{
3829	AssertGCPtr32(GCPtr);
3830
3831	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3832	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pPGM);
3833	AssertReturn(pGuestPDPT, 0);
3834	#else
3835	PX86PDPT pGuestPDPT = pPGM->CTX_SUFF(pGstPaePdpt);
3836	#endif
3837	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
3838	if (pPdpe)
3839	*pPdpe = pGuestPDPT->a[iPdPt];
3840	if (pGuestPDPT->a[iPdPt].n.u1Present)
3841	{
3842	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3843	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3844	if ((pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK) == pPGM->aGCPhysGstPaePDs[iPdPt])
3845	{
3846	*piPD = iPD;
3847	return pPGM->CTX_SUFF(apGstPaePDs)[iPdPt];
3848	}
3849	#endif
3850
3851	/* cache is out-of-sync. */
3852	PX86PDPAE pPD;
3853	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPDPT->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3854	if (RT_SUCCESS(rc))
3855	{
3856	*piPD = iPD;
3857	return pPD;
3858	}
3859	AssertMsgFailed(("Impossible! rc=%d PDPE=%#llx\n", rc, pGuestPDPT->a[iPdPt].u));
3860	/* returning NIL_RTGCPHYS is ok if we assume it's just an invalid page of some kind emulated as all 0s. */
3861	}
3862	return NULL;
3863	}
3864
3865	#ifndef IN_RC
3866
3867	/**
3868	* Gets the page map level-4 pointer for the guest.
3869	*
3870	* @returns Pointer to the PML4 page.
3871	* @param pPGM Pointer to the PGM instance data.
3872	*/
3873	DECLINLINE(PX86PML4) pgmGstGetLongModePML4Ptr(PPGM pPGM)
3874	{
3875	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3876	PX86PML4 pGuestPml4;
3877	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3878	AssertRCReturn(rc, NULL);
3879	return pGuestPml4;
3880	#else
3881	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3882	return pPGM->CTX_SUFF(pGstAmd64Pml4);
3883	#endif
3884	}
3885
3886
3887	/**
3888	* Gets the pointer to a page map level-4 entry.
3889	*
3890	* @returns Pointer to the PML4 entry.
3891	* @param pPGM Pointer to the PGM instance data.
3892	* @param iPml4 The index.
3893	*/
3894	DECLINLINE(PX86PML4E) pgmGstGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
3895	{
3896	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3897	PX86PML4 pGuestPml4;
3898	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3899	AssertRCReturn(rc, NULL);
3900	return &pGuestPml4->a[iPml4];
3901	#else
3902	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3903	return &pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3904	#endif
3905	}
3906
3907
3908	/**
3909	* Gets a page map level-4 entry.
3910	*
3911	* @returns The PML4 entry.
3912	* @param pPGM Pointer to the PGM instance data.
3913	* @param iPml4 The index.
3914	*/
3915	DECLINLINE(X86PML4E) pgmGstGetLongModePML4E(PPGM pPGM, unsigned int iPml4)
3916	{
3917	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3918	PX86PML4 pGuestPml4;
3919	int rc = pgmR0DynMapGCPageInlined(pPGM, pPGM->GCPhysCR3, (void **)&pGuestPml4);
3920	if (RT_FAILURE(rc))
3921	{
3922	X86PML4E ZeroPml4e = {0};
3923	AssertMsgFailedReturn(("%Rrc\n", rc), ZeroPml4e);
3924	}
3925	return pGuestPml4->a[iPml4];
3926	#else
3927	Assert(pPGM->CTX_SUFF(pGstAmd64Pml4));
3928	return pPGM->CTX_SUFF(pGstAmd64Pml4)->a[iPml4];
3929	#endif
3930	}
3931
3932
3933	/**
3934	* Gets the page directory pointer entry for the specified address.
3935	*
3936	* @returns Pointer to the page directory pointer entry in question.
3937	* @returns NULL if the page directory is not present or on an invalid page.
3938	* @param pPGM Pointer to the PGM instance data.
3939	* @param GCPtr The address.
3940	* @param ppPml4e Page Map Level-4 Entry (out)
3941	*/
3942	DECLINLINE(PX86PDPE) pgmGstGetLongModePDPTPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e)
3943	{
3944	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3945	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3946	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3947	if (pPml4e->n.u1Present)
3948	{
3949	PX86PDPT pPdpt;
3950	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdpt);
3951	AssertRCReturn(rc, NULL);
3952
3953	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3954	return &pPdpt->a[iPdPt];
3955	}
3956	return NULL;
3957	}
3958
3959
3960	/**
3961	* Gets the page directory entry for the specified address.
3962	*
3963	* @returns The page directory entry in question.
3964	* @returns A non-present entry if the page directory is not present or on an invalid page.
3965	* @param pPGM Pointer to the PGM instance data.
3966	* @param GCPtr The address.
3967	* @param ppPml4e Page Map Level-4 Entry (out)
3968	* @param pPdpe Page directory pointer table entry (out)
3969	*/
3970	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDEEx(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E *ppPml4e, PX86PDPE pPdpe)
3971	{
3972	X86PDEPAE ZeroPde = {0};
3973	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
3974	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3975	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
3976	if (pPml4e->n.u1Present)
3977	{
3978	PCX86PDPT pPdptTemp;
3979	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
3980	AssertRCReturn(rc, ZeroPde);
3981
3982	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3983	*pPdpe = pPdptTemp->a[iPdPt];
3984	if (pPdptTemp->a[iPdPt].n.u1Present)
3985	{
3986	PCX86PDPAE pPD;
3987	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
3988	AssertRCReturn(rc, ZeroPde);
3989
3990	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
3991	return pPD->a[iPD];
3992	}
3993	}
3994
3995	return ZeroPde;
3996	}
3997
3998
3999	/**
4000	* Gets the page directory entry for the specified address.
4001	*
4002	* @returns The page directory entry in question.
4003	* @returns A non-present entry if the page directory is not present or on an invalid page.
4004	* @param pPGM Pointer to the PGM instance data.
4005	* @param GCPtr The address.
4006	*/
4007	DECLINLINE(X86PDEPAE) pgmGstGetLongModePDE(PPGM pPGM, RTGCPTR64 GCPtr)
4008	{
4009	X86PDEPAE ZeroPde = {0};
4010	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4011	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4012	if (pGuestPml4->a[iPml4].n.u1Present)
4013	{
4014	PCX86PDPT pPdptTemp;
4015	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4016	AssertRCReturn(rc, ZeroPde);
4017
4018	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4019	if (pPdptTemp->a[iPdPt].n.u1Present)
4020	{
4021	PCX86PDPAE pPD;
4022	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4023	AssertRCReturn(rc, ZeroPde);
4024
4025	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4026	return pPD->a[iPD];
4027	}
4028	}
4029	return ZeroPde;
4030	}
4031
4032
4033	/**
4034	* Gets the page directory entry for the specified address.
4035	*
4036	* @returns Pointer to the page directory entry in question.
4037	* @returns NULL if the page directory is not present or on an invalid page.
4038	* @param pPGM Pointer to the PGM instance data.
4039	* @param GCPtr The address.
4040	*/
4041	DECLINLINE(PX86PDEPAE) pgmGstGetLongModePDEPtr(PPGM pPGM, RTGCPTR64 GCPtr)
4042	{
4043	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4044	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4045	if (pGuestPml4->a[iPml4].n.u1Present)
4046	{
4047	PCX86PDPT pPdptTemp;
4048	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4049	AssertRCReturn(rc, NULL);
4050
4051	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4052	if (pPdptTemp->a[iPdPt].n.u1Present)
4053	{
4054	PX86PDPAE pPD;
4055	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4056	AssertRCReturn(rc, NULL);
4057
4058	const unsigned iPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4059	return &pPD->a[iPD];
4060	}
4061	}
4062	return NULL;
4063	}
4064
4065
4066	/**
4067	* Gets the GUEST page directory pointer for the specified address.
4068	*
4069	* @returns The page directory in question.
4070	* @returns NULL if the page directory is not present or on an invalid page.
4071	* @param pPGM Pointer to the PGM instance data.
4072	* @param GCPtr The address.
4073	* @param ppPml4e Page Map Level-4 Entry (out)
4074	* @param pPdpe Page directory pointer table entry (out)
4075	* @param piPD Receives the index into the returned page directory
4076	*/
4077	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, PX86PML4E ppPml4e, PX86PDPE pPdpe, unsigned piPD)
4078	{
4079	PX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4080	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4081	PCX86PML4E pPml4e = *ppPml4e = &pGuestPml4->a[iPml4];
4082	if (pPml4e->n.u1Present)
4083	{
4084	PCX86PDPT pPdptTemp;
4085	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPml4e->u & X86_PML4E_PG_MASK, &pPdptTemp);
4086	AssertRCReturn(rc, NULL);
4087
4088	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4089	*pPdpe = pPdptTemp->a[iPdPt];
4090	if (pPdptTemp->a[iPdPt].n.u1Present)
4091	{
4092	PX86PDPAE pPD;
4093	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4094	AssertRCReturn(rc, NULL);
4095
4096	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4097	return pPD;
4098	}
4099	}
4100	return 0;
4101	}
4102
4103	#endif /* !IN_RC */
4104
4105
4106	/**
4107	* Gets the shadow page directory, 32-bit.
4108	*
4109	* @returns Pointer to the shadow 32-bit PD.
4110	* @param pPGM Pointer to the PGM instance data.
4111	*/
4112	DECLINLINE(PX86PD) pgmShwGet32BitPDPtr(PPGM pPGM)
4113	{
4114	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4115	return (PX86PD)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4116	#else
4117	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4118	PX86PD pShwPd;
4119	Assert(pPGM->HCPhysShw32BitPD != 0 && pPGM->HCPhysShw32BitPD != NIL_RTHCPHYS);
4120	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShw32BitPD, &pShwPd);
4121	AssertRCReturn(rc, NULL);
4122	return pShwPd;
4123	# else
4124	return pPGM->CTX_SUFF(pShw32BitPd);
4125	# endif
4126	#endif
4127	}
4128
4129
4130	/**
4131	* Gets the shadow page directory entry for the specified address, 32-bit.
4132	*
4133	* @returns Shadow 32-bit PDE.
4134	* @param pPGM Pointer to the PGM instance data.
4135	* @param GCPtr The address.
4136	*/
4137	DECLINLINE(X86PDE) pgmShwGet32BitPDE(PPGM pPGM, RTGCPTR GCPtr)
4138	{
4139	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4140
4141	PX86PD pShwPde = pgmShwGet32BitPDPtr(pPGM);
4142	if (!pShwPde)
4143	{
4144	X86PDE ZeroPde = {0};
4145	return ZeroPde;
4146	}
4147	return pShwPde->a[iPd];
4148	}
4149
4150
4151	/**
4152	* Gets the pointer to the shadow page directory entry for the specified
4153	* address, 32-bit.
4154	*
4155	* @returns Pointer to the shadow 32-bit PDE.
4156	* @param pPGM Pointer to the PGM instance data.
4157	* @param GCPtr The address.
4158	*/
4159	DECLINLINE(PX86PDE) pgmShwGet32BitPDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4160	{
4161	const unsigned iPd = (GCPtr >> X86_PD_SHIFT) & X86_PD_MASK;
4162
4163	PX86PD pPde = pgmShwGet32BitPDPtr(pPGM);
4164	AssertReturn(pPde, NULL);
4165	return &pPde->a[iPd];
4166	}
4167
4168
4169	/**
4170	* Gets the shadow page pointer table, PAE.
4171	*
4172	* @returns Pointer to the shadow PAE PDPT.
4173	* @param pPGM Pointer to the PGM instance data.
4174	*/
4175	DECLINLINE(PX86PDPT) pgmShwGetPaePDPTPtr(PPGM pPGM)
4176	{
4177	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4178	return (PX86PDPT)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4179	#else
4180	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4181	PX86PDPT pShwPdpt;
4182	Assert(pPGM->HCPhysShwPaePdpt != 0 && pPGM->HCPhysShwPaePdpt != NIL_RTHCPHYS);
4183	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePdpt, &pShwPdpt);
4184	AssertRCReturn(rc, 0);
4185	return pShwPdpt;
4186	# else
4187	return pPGM->CTX_SUFF(pShwPaePdpt);
4188	# endif
4189	#endif
4190	}
4191
4192
4193	/**
4194	* Gets the shadow page directory for the specified address, PAE.
4195	*
4196	* @returns Pointer to the shadow PD.
4197	* @param pPGM Pointer to the PGM instance data.
4198	* @param GCPtr The address.
4199	*/
4200	DECLINLINE(PX86PDPAE) pgmShwGetPaePDPtr(PPGM pPGM, RTGCPTR GCPtr)
4201	{
4202	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4203	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4204	PX86PDPT pPdpt = pgmShwGetPaePDPTPtr(pPGM);
4205
4206	/* Fetch the pgm pool shadow descriptor. */
4207	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(PGM2VM(pPGM), pPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
4208	AssertReturn(pShwPde, NULL);
4209
4210	return (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pShwPde);
4211	#else
4212	const unsigned iPdpt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_PAE;
4213	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4214	PX86PDPAE pPD;
4215	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->aHCPhysPaePDs[iPdpt], &pPD);
4216	AssertRCReturn(rc, 0);
4217	return pPD;
4218	# else
4219	PX86PDPAE pPD = pPGM->CTX_SUFF(apShwPaePDs)[iPdpt];
4220	Assert(pPD);
4221	return pPD;
4222	# endif
4223	#endif
4224	}
4225
4226
4227	/**
4228	* Gets the shadow page directory entry, PAE.
4229	*
4230	* @returns PDE.
4231	* @param pPGM Pointer to the PGM instance data.
4232	* @param GCPtr The address.
4233	*/
4234	DECLINLINE(X86PDEPAE) pgmShwGetPaePDE(PPGM pPGM, RTGCPTR GCPtr)
4235	{
4236	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4237
4238	PX86PDPAE pShwPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4239	if (!pShwPde)
4240	{
4241	X86PDEPAE ZeroPde = {0};
4242	return ZeroPde;
4243	}
4244	return pShwPde->a[iPd];
4245	}
4246
4247
4248	/**
4249	* Gets the pointer to the shadow page directory entry for an address, PAE.
4250	*
4251	* @returns Pointer to the PDE.
4252	* @param pPGM Pointer to the PGM instance data.
4253	* @param GCPtr The address.
4254	*/
4255	DECLINLINE(PX86PDEPAE) pgmShwGetPaePDEPtr(PPGM pPGM, RTGCPTR GCPtr)
4256	{
4257	const unsigned iPd = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4258
4259	PX86PDPAE pPde = pgmShwGetPaePDPtr(pPGM, GCPtr);
4260	AssertReturn(pPde, NULL);
4261	return &pPde->a[iPd];
4262	}
4263
4264	#ifndef IN_RC
4265
4266	/**
4267	* Gets the shadow page map level-4 pointer.
4268	*
4269	* @returns Pointer to the shadow PML4.
4270	* @param pPGM Pointer to the PGM instance data.
4271	*/
4272	DECLINLINE(PX86PML4) pgmShwGetLongModePML4Ptr(PPGM pPGM)
4273	{
4274	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4275	return (PX86PML4)PGMPOOL_PAGE_2_PTR_BY_PGM(pPGM, pPGM->CTX_SUFF(pShwPageCR3));
4276	#else
4277	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4278	PX86PML4 pShwPml4;
4279	Assert(pPGM->HCPhysShwPaePml4 != 0 && pPGM->HCPhysShwPaePml4 != NIL_RTHCPHYS);
4280	int rc = PGM_HCPHYS_2_PTR_BY_PGM(pPGM, pPGM->HCPhysShwPaePml4, &pShwPml4);
4281	AssertRCReturn(rc, 0);
4282	return pShwPml4;
4283	# else
4284	Assert(pPGM->CTX_SUFF(pShwPaePml4));
4285	return pPGM->CTX_SUFF(pShwPaePml4);
4286	# endif
4287	#endif
4288	}
4289
4290
4291	/**
4292	* Gets the shadow page map level-4 entry for the specified address.
4293	*
4294	* @returns The entry.
4295	* @param pPGM Pointer to the PGM instance data.
4296	* @param GCPtr The address.
4297	*/
4298	DECLINLINE(X86PML4E) pgmShwGetLongModePML4E(PPGM pPGM, RTGCPTR GCPtr)
4299	{
4300	const unsigned iPml4 = ((RTGCUINTPTR64)GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4301	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4302
4303	if (!pShwPml4)
4304	{
4305	X86PML4E ZeroPml4e = {0};
4306	return ZeroPml4e;
4307	}
4308	return pShwPml4->a[iPml4];
4309	}
4310
4311
4312	/**
4313	* Gets the pointer to the specified shadow page map level-4 entry.
4314	*
4315	* @returns The entry.
4316	* @param pPGM Pointer to the PGM instance data.
4317	* @param iPml4 The PML4 index.
4318	*/
4319	DECLINLINE(PX86PML4E) pgmShwGetLongModePML4EPtr(PPGM pPGM, unsigned int iPml4)
4320	{
4321	PX86PML4 pShwPml4 = pgmShwGetLongModePML4Ptr(pPGM);
4322	if (!pShwPml4)
4323	return NULL;
4324	return &pShwPml4->a[iPml4];
4325	}
4326
4327
4328	/**
4329	* Gets the GUEST page directory pointer for the specified address.
4330	*
4331	* @returns The page directory in question.
4332	* @returns NULL if the page directory is not present or on an invalid page.
4333	* @param pPGM Pointer to the PGM instance data.
4334	* @param GCPtr The address.
4335	* @param piPD Receives the index into the returned page directory
4336	*/
4337	DECLINLINE(PX86PDPAE) pgmGstGetLongModePDPtr(PPGM pPGM, RTGCPTR64 GCPtr, unsigned *piPD)
4338	{
4339	PCX86PML4 pGuestPml4 = pgmGstGetLongModePML4Ptr(pPGM);
4340	const unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4341	if (pGuestPml4->a[iPml4].n.u1Present)
4342	{
4343	PCX86PDPT pPdptTemp;
4344	int rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pGuestPml4->a[iPml4].u & X86_PML4E_PG_MASK, &pPdptTemp);
4345	AssertRCReturn(rc, NULL);
4346
4347	const unsigned iPdPt = (GCPtr >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
4348	if (pPdptTemp->a[iPdPt].n.u1Present)
4349	{
4350	PX86PDPAE pPD;
4351	rc = PGM_GCPHYS_2_PTR_BY_PGM(pPGM, pPdptTemp->a[iPdPt].u & X86_PDPE_PG_MASK, &pPD);
4352	AssertRCReturn(rc, NULL);
4353
4354	*piPD = (GCPtr >> X86_PD_PAE_SHIFT) & X86_PD_PAE_MASK;
4355	return pPD;
4356	}
4357	}
4358	return NULL;
4359	}
4360
4361	#endif /* !IN_RC */
4362
4363	/**
4364	* Checks if any of the specified page flags are set for the given page.
4365	*
4366	* @returns true if any of the flags are set.
4367	* @returns false if all the flags are clear.
4368	* @param pPGM PGM handle.
4369	* @param GCPhys The GC physical address.
4370	* @param fFlags The flags to check for.
4371	*/
4372	DECLINLINE(bool) pgmRamTestFlags(PPGM pPGM, RTGCPHYS GCPhys, uint64_t fFlags)
4373	{
4374	PPGMPAGE pPage = pgmPhysGetPage(pPGM, GCPhys);
4375	return pPage
4376	&& (pPage->HCPhys & fFlags) != 0; /** @todo PAGE FLAGS */
4377	}
4378
4379
4380	/**
4381	* Gets the page state for a physical handler.
4382	*
4383	* @returns The physical handler page state.
4384	* @param pCur The physical handler in question.
4385	*/
4386	DECLINLINE(unsigned) pgmHandlerPhysicalCalcState(PPGMPHYSHANDLER pCur)
4387	{
4388	switch (pCur->enmType)
4389	{
4390	case PGMPHYSHANDLERTYPE_PHYSICAL_WRITE:
4391	return PGM_PAGE_HNDL_PHYS_STATE_WRITE;
4392
4393	case PGMPHYSHANDLERTYPE_MMIO:
4394	case PGMPHYSHANDLERTYPE_PHYSICAL_ALL:
4395	return PGM_PAGE_HNDL_PHYS_STATE_ALL;
4396
4397	default:
4398	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4399	}
4400	}
4401
4402
4403	/**
4404	* Gets the page state for a virtual handler.
4405	*
4406	* @returns The virtual handler page state.
4407	* @param pCur The virtual handler in question.
4408	* @remarks This should never be used on a hypervisor access handler.
4409	*/
4410	DECLINLINE(unsigned) pgmHandlerVirtualCalcState(PPGMVIRTHANDLER pCur)
4411	{
4412	switch (pCur->enmType)
4413	{
4414	case PGMVIRTHANDLERTYPE_WRITE:
4415	return PGM_PAGE_HNDL_VIRT_STATE_WRITE;
4416	case PGMVIRTHANDLERTYPE_ALL:
4417	return PGM_PAGE_HNDL_VIRT_STATE_ALL;
4418	default:
4419	AssertFatalMsgFailed(("Invalid type %d\n", pCur->enmType));
4420	}
4421	}
4422
4423
4424	/**
4425	* Clears one physical page of a virtual handler
4426	*
4427	* @param pPGM Pointer to the PGM instance.
4428	* @param pCur Virtual handler structure
4429	* @param iPage Physical page index
4430	*
4431	* @remark Only used when PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL is being set, so no
4432	* need to care about other handlers in the same page.
4433	*/
4434	DECLINLINE(void) pgmHandlerVirtualClearPage(PPGM pPGM, PPGMVIRTHANDLER pCur, unsigned iPage)
4435	{
4436	const PPGMPHYS2VIRTHANDLER pPhys2Virt = &pCur->aPhysToVirt[iPage];
4437
4438	/*
4439	* Remove the node from the tree (it's supposed to be in the tree if we get here!).
4440	*/
4441	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4442	AssertReleaseMsg(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4443	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4444	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4445	#endif
4446	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_IS_HEAD)
4447	{
4448	/* We're the head of the alias chain. */
4449	PPGMPHYS2VIRTHANDLER pRemove = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysRemove(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key); NOREF(pRemove);
4450	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4451	AssertReleaseMsg(pRemove != NULL,
4452	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4453	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias));
4454	AssertReleaseMsg(pRemove == pPhys2Virt,
4455	("wanted: pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4456	" got: pRemove=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4457	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias,
4458	pRemove, pRemove->Core.Key, pRemove->Core.KeyLast, pRemove->offVirtHandler, pRemove->offNextAlias));
4459	#endif
4460	if (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4461	{
4462	/* Insert the next list in the alias chain into the tree. */
4463	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4464	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4465	AssertReleaseMsg(pNext->offNextAlias & PGMPHYS2VIRTHANDLER_IN_TREE,
4466	("pNext=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4467	pNext, pNext->Core.Key, pNext->Core.KeyLast, pNext->offVirtHandler, pNext->offNextAlias));
4468	#endif
4469	pNext->offNextAlias \|= PGMPHYS2VIRTHANDLER_IS_HEAD;
4470	bool fRc = RTAvlroGCPhysInsert(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, &pNext->Core);
4471	AssertRelease(fRc);
4472	}
4473	}
4474	else
4475	{
4476	/* Locate the previous node in the alias chain. */
4477	PPGMPHYS2VIRTHANDLER pPrev = (PPGMPHYS2VIRTHANDLER)RTAvlroGCPhysGet(&pPGM->CTX_SUFF(pTrees)->PhysToVirtHandlers, pPhys2Virt->Core.Key);
4478	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4479	AssertReleaseMsg(pPrev != pPhys2Virt,
4480	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4481	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4482	#endif
4483	for (;;)
4484	{
4485	PPGMPHYS2VIRTHANDLER pNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPrev + (pPrev->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4486	if (pNext == pPhys2Virt)
4487	{
4488	/* unlink. */
4489	LogFlow(("pgmHandlerVirtualClearPage: removed %p:{.offNextAlias=%#RX32} from alias chain. prev %p:{.offNextAlias=%#RX32} [%RGp-%RGp]\n",
4490	pPhys2Virt, pPhys2Virt->offNextAlias, pPrev, pPrev->offNextAlias, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast));
4491	if (!(pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4492	pPrev->offNextAlias &= ~PGMPHYS2VIRTHANDLER_OFF_MASK;
4493	else
4494	{
4495	PPGMPHYS2VIRTHANDLER pNewNext = (PPGMPHYS2VIRTHANDLER)((intptr_t)pPhys2Virt + (pPhys2Virt->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4496	pPrev->offNextAlias = ((intptr_t)pNewNext - (intptr_t)pPrev)
4497	\| (pPrev->offNextAlias & ~PGMPHYS2VIRTHANDLER_OFF_MASK);
4498	}
4499	break;
4500	}
4501
4502	/* next */
4503	if (pNext == pPrev)
4504	{
4505	#ifdef VBOX_STRICT_PGM_HANDLER_VIRTUAL
4506	AssertReleaseMsg(pNext != pPrev,
4507	("pPhys2Virt=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32} pPrev=%p\n",
4508	pPhys2Virt, pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offVirtHandler, pPhys2Virt->offNextAlias, pPrev));
4509	#endif
4510	break;
4511	}
4512	pPrev = pNext;
4513	}
4514	}
4515	Log2(("PHYS2VIRT: Removing %RGp-%RGp %#RX32 %s\n",
4516	pPhys2Virt->Core.Key, pPhys2Virt->Core.KeyLast, pPhys2Virt->offNextAlias, R3STRING(pCur->pszDesc)));
4517	pPhys2Virt->offNextAlias = 0;
4518	pPhys2Virt->Core.KeyLast = NIL_RTGCPHYS; /* require reinsert */
4519
4520	/*
4521	* Clear the ram flags for this page.
4522	*/
4523	PPGMPAGE pPage = pgmPhysGetPage(pPGM, pPhys2Virt->Core.Key);
4524	AssertReturnVoid(pPage);
4525	PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, PGM_PAGE_HNDL_VIRT_STATE_NONE);
4526	}
4527
4528
4529	/**
4530	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4531	*
4532	* @returns Pointer to the shadow page structure.
4533	* @param pPool The pool.
4534	* @param HCPhys The HC physical address of the shadow page.
4535	*/
4536	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4537	{
4538	/*
4539	* Look up the page.
4540	*/
4541	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4542	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4543	return pPage;
4544	}
4545
4546
4547	/**
4548	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4549	*
4550	* @returns Pointer to the shadow page structure.
4551	* @param pPool The pool.
4552	* @param idx The pool page index.
4553	*/
4554	DECLINLINE(PPGMPOOLPAGE) pgmPoolGetPageByIdx(PPGMPOOL pPool, unsigned idx)
4555	{
4556	AssertFatalMsg(idx >= PGMPOOL_IDX_FIRST && idx < pPool->cCurPages, ("idx=%d\n", idx));
4557	return &pPool->aPages[idx];
4558	}
4559
4560
4561	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4562	/**
4563	* Clear references to guest physical memory.
4564	*
4565	* @param pPool The pool.
4566	* @param pPoolPage The pool page.
4567	* @param pPhysPage The physical guest page tracking structure.
4568	*/
4569	DECLINLINE(void) pgmTrackDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage)
4570	{
4571	/*
4572	* Just deal with the simple case here.
4573	*/
4574	# ifdef LOG_ENABLED
4575	const RTHCPHYS HCPhysOrg = pPhysPage->HCPhys; /** @todo PAGE FLAGS */
4576	# endif
4577	const unsigned cRefs = pPhysPage->HCPhys >> MM_RAM_FLAGS_CREFS_SHIFT; /** @todo PAGE FLAGS */
4578	if (cRefs == 1)
4579	{
4580	Assert(pPoolPage->idx == ((pPhysPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT) & MM_RAM_FLAGS_IDX_MASK));
4581	pPhysPage->HCPhys = pPhysPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK;
4582	}
4583	else
4584	pgmPoolTrackPhysExtDerefGCPhys(pPool, pPoolPage, pPhysPage);
4585	LogFlow(("pgmTrackDerefGCPhys: HCPhys=%RHp -> %RHp\n", HCPhysOrg, pPhysPage->HCPhys));
4586	}
4587	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
4588
4589
4590	#ifdef PGMPOOL_WITH_CACHE
4591	/**
4592	* Moves the page to the head of the age list.
4593	*
4594	* This is done when the cached page is used in one way or another.
4595	*
4596	* @param pPool The pool.
4597	* @param pPage The cached page.
4598	* @todo inline in PGMInternal.h!
4599	*/
4600	DECLINLINE(void) pgmPoolCacheUsed(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
4601	{
4602	/*
4603	* Move to the head of the age list.
4604	*/
4605	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
4606	{
4607	/* unlink */
4608	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
4609	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
4610	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
4611	else
4612	pPool->iAgeTail = pPage->iAgePrev;
4613
4614	/* insert at head */
4615	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4616	pPage->iAgeNext = pPool->iAgeHead;
4617	Assert(pPage->iAgeNext != NIL_PGMPOOL_IDX); /* we would've already been head then */
4618	pPool->iAgeHead = pPage->idx;
4619	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->idx;
4620	}
4621	}
4622	#endif /* PGMPOOL_WITH_CACHE */
4623
4624
4625	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4626	/**
4627	* Maps the page into current context (RC and maybe R0).
4628	*
4629	* @returns pointer to the mapping.
4630	* @param pVM Pointer to the PGM instance data.
4631	* @param pPage The page.
4632	*/
4633	DECLINLINE(void ) pgmPoolMapPageInlined(PPGM pPGM, PPGMPOOLPAGE pPage, int iLine, const char pszFile)
4634	{
4635	if (pPage->idx >= PGMPOOL_IDX_FIRST)
4636	{
4637	Assert(pPage->idx < pPGM->CTX_SUFF(pPool)->cCurPages);
4638	void *pv;
4639	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
4640	int rc = pgmR0DynMapHCPageInlined(pPGM, pPage->Core.Key, &pv);
4641	# else
4642	int rc = PGMDynMapHCPage(PGM2VM(pPGM), pPage->Core.Key, &pv);
4643	# endif
4644	if (RT_SUCCESS(rc))
4645	return pv;
4646	AssertMsgFailed(("%Rrc: %s(%d)\n", rc, pszFile, iLine));
4647	}
4648	return pgmPoolMapPageFallback(pPGM, pPage);
4649	}
4650	#endif
4651
4652
4653	/**
4654	* Tells if mappings are to be put into the shadow page table or not
4655	*
4656	* @returns boolean result
4657	* @param pVM VM handle.
4658	*/
4659
4660	DECLINLINE(bool) pgmMapAreMappingsEnabled(PPGM pPGM)
4661	{
4662	#ifdef IN_RING0
4663	/* There are no mappings in VT-x and AMD-V mode. */
4664	Assert(pPGM->fDisableMappings);
4665	return false;
4666	#else
4667	return !pPGM->fDisableMappings;
4668	#endif
4669	}
4670
4671	/** @} */
4672
4673	#endif
4674

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/PGMInternal.h@ 15414

Download in other formats: