VirtualBox

source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 30037

Last change on this file since 30037 was 29646, checked in by vboxsync, 14 years ago

Proper shared page cleanup when terminating the VM
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1/* $Id: PGM.cpp 29646 2010-05-18 15:44:08Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @page pg_pgm PGM - The Page Manager and Monitor
20 *
21 * @see grp_pgm,
22 * @ref pg_pgm_pool,
23 * @ref pg_pgm_phys.
24 *
25 *
26 * @section sec_pgm_modes Paging Modes
27 *
28 * There are three memory contexts: Host Context (HC), Guest Context (GC)
29 * and intermediate context. When talking about paging HC can also be refered to
30 * as "host paging", and GC refered to as "shadow paging".
31 *
32 * We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33 * is defined by the host operating system. The mode used in the shadow paging mode
34 * depends on the host paging mode and what the mode the guest is currently in. The
35 * following relation between the two is defined:
36 *
37 * @verbatim
38 Host > 32-bit | PAE | AMD64 |
39 Guest | | | |
40 ==v================================
41 32-bit 32-bit PAE PAE
42 -------|--------|--------|--------|
43 PAE PAE PAE PAE
44 -------|--------|--------|--------|
45 AMD64 AMD64 AMD64 AMD64
46 -------|--------|--------|--------| @endverbatim
47 *
48 * All configuration except those in the diagonal (upper left) are expected to
49 * require special effort from the switcher (i.e. a bit slower).
50 *
51 *
52 *
53 *
54 * @section sec_pgm_shw The Shadow Memory Context
55 *
56 *
57 * [..]
58 *
59 * Because of guest context mappings requires PDPT and PML4 entries to allow
60 * writing on AMD64, the two upper levels will have fixed flags whatever the
61 * guest is thinking of using there. So, when shadowing the PD level we will
62 * calculate the effective flags of PD and all the higher levels. In legacy
63 * PAE mode this only applies to the PWT and PCD bits (the rest are
64 * ignored/reserved/MBZ). We will ignore those bits for the present.
65 *
66 *
67 *
68 * @section sec_pgm_int The Intermediate Memory Context
69 *
70 * The world switch goes thru an intermediate memory context which purpose it is
71 * to provide different mappings of the switcher code. All guest mappings are also
72 * present in this context.
73 *
74 * The switcher code is mapped at the same location as on the host, at an
75 * identity mapped location (physical equals virtual address), and at the
76 * hypervisor location. The identity mapped location is for when the world
77 * switches that involves disabling paging.
78 *
79 * PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80 * simplifies switching guest CPU mode and consistency at the cost of more
81 * code to do the work. All memory use for those page tables is located below
82 * 4GB (this includes page tables for guest context mappings).
83 *
84 *
85 * @subsection subsec_pgm_int_gc Guest Context Mappings
86 *
87 * During assignment and relocation of a guest context mapping the intermediate
88 * memory context is used to verify the new location.
89 *
90 * Guest context mappings are currently restricted to below 4GB, for reasons
91 * of simplicity. This may change when we implement AMD64 support.
92 *
93 *
94 *
95 *
96 * @section sec_pgm_misc Misc
97 *
98 * @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99 *
100 * The differences between legacy PAE and long mode PAE are:
101 * -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102 * all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103 * usual meanings while 6 is ignored (AMD). This means that upon switching to
104 * legacy PAE mode we'll have to clear these bits and when going to long mode
105 * they must be set. This applies to both intermediate and shadow contexts,
106 * however we don't need to do it for the intermediate one since we're
107 * executing with CR0.WP at that time.
108 * -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109 * a page aligned one is required.
110 *
111 *
112 * @section sec_pgm_handlers Access Handlers
113 *
114 * Placeholder.
115 *
116 *
117 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
118 *
119 * Placeholder.
120 *
121 *
122 * @subsection sec_pgm_handlers_virt Virtual Access Handlers
123 *
124 * We currently implement three types of virtual access handlers: ALL, WRITE
125 * and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126 *
127 * The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128 * to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129 * a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130 * rest of this section is going to be about these handlers.
131 *
132 * We'll go thru the life cycle of a handler and try make sense of it all, don't know
133 * how successfull this is gonna be...
134 *
135 * 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136 * PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137 * and create a new node that is inserted into the AVL tree (range key). Then
138 * a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139 *
140 * 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141 *
142 * 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143 * via the current guest CR3 and update the physical page -> virtual handler
144 * translation. Needless to say, this doesn't exactly scale very well. If any changes
145 * are detected, it will flag a virtual bit update just like we did on registration.
146 * PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147 *
148 * 2b. The virtual bit update process will iterate all the pages covered by all the
149 * virtual handlers and update the PGMPAGE virtual handler state to the max of all
150 * virtual handlers on that page.
151 *
152 * 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153 * we don't miss any alias mappings of the monitored pages.
154 *
155 * 2d. SyncCR3 will then proceed with syncing the CR3 table.
156 *
157 * 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158 * read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159 * will call the handlers like in the next step. If the physical mapping has
160 * changed we will - some time in the future - perform a handler callback
161 * (optional) and update the physical -> virtual handler cache.
162 *
163 * 4. \#PF(,write) on a page in the range. This will cause the handler to
164 * be invoked.
165 *
166 * 5. The guest invalidates the page and changes the physical backing or
167 * unmaps it. This should cause the invalidation callback to be invoked
168 * (it might not yet be 100% perfect). Exactly what happens next... is
169 * this where we mess up and end up out of sync for a while?
170 *
171 * 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172 * We will then set all PGMPAGEs in the physical -> virtual handler cache for
173 * this handler to NONE and trigger a full PGM resync (basically the same
174 * as int step 1). Which means 2 is executed again.
175 *
176 *
177 * @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178 *
179 * There is a bunch of things that needs to be done to make the virtual handlers
180 * work 100% correctly and work more efficiently.
181 *
182 * The first bit hasn't been implemented yet because it's going to slow the
183 * whole mess down even more, and besides it seems to be working reliably for
184 * our current uses. OTOH, some of the optimizations might end up more or less
185 * implementing the missing bits, so we'll see.
186 *
187 * On the optimization side, the first thing to do is to try avoid unnecessary
188 * cache flushing. Then try team up with the shadowing code to track changes
189 * in mappings by means of access to them (shadow in), updates to shadows pages,
190 * invlpg, and shadow PT discarding (perhaps).
191 *
192 * Some idea that have popped up for optimization for current and new features:
193 * - bitmap indicating where there are virtual handlers installed.
194 * (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
195 * - Further optimize this by min/max (needs min/max avl getters).
196 * - Shadow page table entry bit (if any left)?
197 *
198 */
199
200
201/** @page pg_pgm_phys PGM Physical Guest Memory Management
202 *
203 *
204 * Objectives:
205 * - Guest RAM over-commitment using memory ballooning,
206 * zero pages and general page sharing.
207 * - Moving or mirroring a VM onto a different physical machine.
208 *
209 *
210 * @subsection subsec_pgmPhys_Definitions Definitions
211 *
212 * Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213 * machinery assoicated with it.
214 *
215 *
216 *
217 *
218 * @subsection subsec_pgmPhys_AllocPage Allocating a page.
219 *
220 * Initially we map *all* guest memory to the (per VM) zero page, which
221 * means that none of the read functions will cause pages to be allocated.
222 *
223 * Exception, access bit in page tables that have been shared. This must
224 * be handled, but we must also make sure PGMGst*Modify doesn't make
225 * unnecessary modifications.
226 *
227 * Allocation points:
228 * - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229 * - Replacing a zero page mapping at \#PF.
230 * - Replacing a shared page mapping at \#PF.
231 * - ROM registration (currently MMR3RomRegister).
232 * - VM restore (pgmR3Load).
233 *
234 * For the first three it would make sense to keep a few pages handy
235 * until we've reached the max memory commitment for the VM.
236 *
237 * For the ROM registration, we know exactly how many pages we need
238 * and will request these from ring-0. For restore, we will save
239 * the number of non-zero pages in the saved state and allocate
240 * them up front. This would allow the ring-0 component to refuse
241 * the request if the isn't sufficient memory available for VM use.
242 *
243 * Btw. for both ROM and restore allocations we won't be requiring
244 * zeroed pages as they are going to be filled instantly.
245 *
246 *
247 * @subsection subsec_pgmPhys_FreePage Freeing a page
248 *
249 * There are a few points where a page can be freed:
250 * - After being replaced by the zero page.
251 * - After being replaced by a shared page.
252 * - After being ballooned by the guest additions.
253 * - At reset.
254 * - At restore.
255 *
256 * When freeing one or more pages they will be returned to the ring-0
257 * component and replaced by the zero page.
258 *
259 * The reasoning for clearing out all the pages on reset is that it will
260 * return us to the exact same state as on power on, and may thereby help
261 * us reduce the memory load on the system. Further it might have a
262 * (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263 *
264 * On restore, as mention under the allocation topic, pages should be
265 * freed / allocated depending on how many is actually required by the
266 * new VM state. The simplest approach is to do like on reset, and free
267 * all non-ROM pages and then allocate what we need.
268 *
269 * A measure to prevent some fragmentation, would be to let each allocation
270 * chunk have some affinity towards the VM having allocated the most pages
271 * from it. Also, try make sure to allocate from allocation chunks that
272 * are almost full. Admittedly, both these measures might work counter to
273 * our intentions and its probably not worth putting a lot of effort,
274 * cpu time or memory into this.
275 *
276 *
277 * @subsection subsec_pgmPhys_SharePage Sharing a page
278 *
279 * The basic idea is that there there will be a idle priority kernel
280 * thread walking the non-shared VM pages hashing them and looking for
281 * pages with the same checksum. If such pages are found, it will compare
282 * them byte-by-byte to see if they actually are identical. If found to be
283 * identical it will allocate a shared page, copy the content, check that
284 * the page didn't change while doing this, and finally request both the
285 * VMs to use the shared page instead. If the page is all zeros (special
286 * checksum and byte-by-byte check) it will request the VM that owns it
287 * to replace it with the zero page.
288 *
289 * To make this efficient, we will have to make sure not to try share a page
290 * that will change its contents soon. This part requires the most work.
291 * A simple idea would be to request the VM to write monitor the page for
292 * a while to make sure it isn't modified any time soon. Also, it may
293 * make sense to skip pages that are being write monitored since this
294 * information is readily available to the thread if it works on the
295 * per-VM guest memory structures (presently called PGMRAMRANGE).
296 *
297 *
298 * @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299 *
300 * The pages are organized in allocation chunks in ring-0, this is a necessity
301 * if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302 * could easily work on a page-by-page basis if we liked. Whether this is possible
303 * or efficient on NT I don't quite know.) Fragmentation within these chunks may
304 * become a problem as part of the idea here is that we wish to return memory to
305 * the host system.
306 *
307 * For instance, starting two VMs at the same time, they will both allocate the
308 * guest memory on-demand and if permitted their page allocations will be
309 * intermixed. Shut down one of the two VMs and it will be difficult to return
310 * any memory to the host system because the page allocation for the two VMs are
311 * mixed up in the same allocation chunks.
312 *
313 * To further complicate matters, when pages are freed because they have been
314 * ballooned or become shared/zero the whole idea is that the page is supposed
315 * to be reused by another VM or returned to the host system. This will cause
316 * allocation chunks to contain pages belonging to different VMs and prevent
317 * returning memory to the host when one of those VM shuts down.
318 *
319 * The only way to really deal with this problem is to move pages. This can
320 * either be done at VM shutdown and or by the idle priority worker thread
321 * that will be responsible for finding sharable/zero pages. The mechanisms
322 * involved for coercing a VM to move a page (or to do it for it) will be
323 * the same as when telling it to share/zero a page.
324 *
325 *
326 * @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327 *
328 * There's a difficult balance between keeping the per-page tracking structures
329 * (global and guest page) easy to use and keeping them from eating too much
330 * memory. We have limited virtual memory resources available when operating in
331 * 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332 * tracking structures will be attemted designed such that we can deal with up
333 * to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334 *
335 *
336 * @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337 *
338 * @see pg_GMM
339 *
340 * @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341 *
342 * Fixed info is the physical address of the page (HCPhys) and the page id
343 * (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344 * Today we've restricting ourselves to 40(-12) bits because this is the current
345 * restrictions of all AMD64 implementations (I think Barcelona will up this
346 * to 48(-12) bits, not that it really matters) and I needed the bits for
347 * tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348 * decent range for the page id: 2^(28+12) = 1024TB.
349 *
350 * In additions to these, we'll have to keep maintaining the page flags as we
351 * currently do. Although it wouldn't harm to optimize these quite a bit, like
352 * for instance the ROM shouldn't depend on having a write handler installed
353 * in order for it to become read-only. A RO/RW bit should be considered so
354 * that the page syncing code doesn't have to mess about checking multiple
355 * flag combinations (ROM || RW handler || write monitored) in order to
356 * figure out how to setup a shadow PTE. But this of course, is second
357 * priority at present. Current this requires 12 bits, but could probably
358 * be optimized to ~8.
359 *
360 * Then there's the 24 bits used to track which shadow page tables are
361 * currently mapping a page for the purpose of speeding up physical
362 * access handlers, and thereby the page pool cache. More bit for this
363 * purpose wouldn't hurt IIRC.
364 *
365 * Then there is a new bit in which we need to record what kind of page
366 * this is, shared, zero, normal or write-monitored-normal. This'll
367 * require 2 bits. One bit might be needed for indicating whether a
368 * write monitored page has been written to. And yet another one or
369 * two for tracking migration status. 3-4 bits total then.
370 *
371 * Whatever is left will can be used to record the sharabilitiy of a
372 * page. The page checksum will not be stored in the per-VM table as
373 * the idle thread will not be permitted to do modifications to it.
374 * It will instead have to keep its own working set of potentially
375 * shareable pages and their check sums and stuff.
376 *
377 * For the present we'll keep the current packing of the
378 * PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379 * we'll have to change it to a struct with a total of 128-bits at
380 * our disposal.
381 *
382 * The initial layout will be like this:
383 * @verbatim
384 RTHCPHYS HCPhys; The current stuff.
385 63:40 Current shadow PT tracking stuff.
386 39:12 The physical page frame number.
387 11:0 The current flags.
388 uint32_t u28PageId : 28; The page id.
389 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391 uint32_t u1Reserved : 1; Reserved for later.
392 uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393 @endverbatim
394 *
395 * The final layout will be something like this:
396 * @verbatim
397 RTHCPHYS HCPhys; The current stuff.
398 63:48 High page id (12+).
399 47:12 The physical page frame number.
400 11:0 Low page id.
401 uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402 uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403 uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404 uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405 uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406 uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407 uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408 uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409 @endverbatim
410 *
411 * Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412 * around that I'm afraid. It means that the cost of dealing out 32GB of memory
413 * to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414 * example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415 *
416 * A couple of cost examples for the total cost per-VM + kernel.
417 * 32-bit Windows and 32-bit linux:
418 * 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419 * 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420 * 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421 * 64-bit Windows and 64-bit linux:
422 * 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423 * 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424 * 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425 *
426 * UPDATE - 2007-09-27:
427 * Will need a ballooned flag/state too because we cannot
428 * trust the guest 100% and reporting the same page as ballooned more
429 * than once will put the GMM off balance.
430 *
431 *
432 * @subsection subsec_pgmPhys_Serializing Serializing Access
433 *
434 * Initially, we'll try a simple scheme:
435 *
436 * - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437 * by the EMT thread of that VM while in the pgm critsect.
438 * - Other threads in the VM process that needs to make reliable use of
439 * the per-VM RAM tracking structures will enter the critsect.
440 * - No process external thread or kernel thread will ever try enter
441 * the pgm critical section, as that just won't work.
442 * - The idle thread (and similar threads) doesn't not need 100% reliable
443 * data when performing it tasks as the EMT thread will be the one to
444 * do the actual changes later anyway. So, as long as it only accesses
445 * the main ram range, it can do so by somehow preventing the VM from
446 * being destroyed while it works on it...
447 *
448 * - The over-commitment management, including the allocating/freeing
449 * chunks, is serialized by a ring-0 mutex lock (a fast one since the
450 * more mundane mutex implementation is broken on Linux).
451 * - A separeate mutex is protecting the set of allocation chunks so
452 * that pages can be shared or/and freed up while some other VM is
453 * allocating more chunks. This mutex can be take from under the other
454 * one, but not the otherway around.
455 *
456 *
457 * @subsection subsec_pgmPhys_Request VM Request interface
458 *
459 * When in ring-0 it will become necessary to send requests to a VM so it can
460 * for instance move a page while defragmenting during VM destroy. The idle
461 * thread will make use of this interface to request VMs to setup shared
462 * pages and to perform write monitoring of pages.
463 *
464 * I would propose an interface similar to the current VMReq interface, similar
465 * in that it doesn't require locking and that the one sending the request may
466 * wait for completion if it wishes to. This shouldn't be very difficult to
467 * realize.
468 *
469 * The requests themselves are also pretty simple. They are basically:
470 * -# Check that some precondition is still true.
471 * -# Do the update.
472 * -# Update all shadow page tables involved with the page.
473 *
474 * The 3rd step is identical to what we're already doing when updating a
475 * physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476 *
477 *
478 *
479 * @section sec_pgmPhys_MappingCaches Mapping Caches
480 *
481 * In order to be able to map in and out memory and to be able to support
482 * guest with more RAM than we've got virtual address space, we'll employing
483 * a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484 * and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485 * memory context for the HWACCM execution.
486 *
487 *
488 * @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489 *
490 * We've considered implementing the ring-3 mapping cache page based but found
491 * that this was bother some when one had to take into account TLBs+SMP and
492 * portability (missing the necessary APIs on several platforms). There were
493 * also some performance concerns with this approach which hadn't quite been
494 * worked out.
495 *
496 * Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497 * matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498 * only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499 * compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500 * costly than a single page, although how much more costly is uncertain. We'll
501 * try address this by using a very big cache, preferably bigger than the actual
502 * VM RAM size if possible. The current VM RAM sizes should give some idea for
503 * 32-bit boxes, while on 64-bit we can probably get away with employing an
504 * unlimited cache.
505 *
506 * The cache have to parts, as already indicated, the ring-3 side and the
507 * ring-0 side.
508 *
509 * The ring-0 will be tied to the page allocator since it will operate on the
510 * memory objects it contains. It will therefore require the first ring-0 mutex
511 * discussed in @ref subsec_pgmPhys_Serializing. We
512 * some double house keeping wrt to who has mapped what I think, since both
513 * VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514 *
515 * The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516 * require anyone that desires to do changes to the mapping cache to do that
517 * from within this critsect. Alternatively, we could employ a separate critsect
518 * for serializing changes to the mapping cache as this would reduce potential
519 * contention with other threads accessing mappings unrelated to the changes
520 * that are in process. We can see about this later, contention will show
521 * up in the statistics anyway, so it'll be simple to tell.
522 *
523 * The organization of the ring-3 part will be very much like how the allocation
524 * chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525 * having to walk the tree all the time, we'll have a couple of lookaside entries
526 * like in we do for I/O ports and MMIO in IOM.
527 *
528 * The simplified flow of a PGMPhysRead/Write function:
529 * -# Enter the PGM critsect.
530 * -# Lookup GCPhys in the ram ranges and get the Page ID.
531 * -# Calc the Allocation Chunk ID from the Page ID.
532 * -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533 * If not found in cache:
534 * -# Call ring-0 and request it to be mapped and supply
535 * a chunk to be unmapped if the cache is maxed out already.
536 * -# Insert the new mapping into the AVL tree (id + R3 address).
537 * -# Update the relevant lookaside entry and return the mapping address.
538 * -# Do the read/write according to monitoring flags and everything.
539 * -# Leave the critsect.
540 *
541 *
542 * @section sec_pgmPhys_Fallback Fallback
543 *
544 * Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545 * API and thus require a fallback.
546 *
547 * So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548 * will return to the ring-3 caller (and later ring-0) and asking it to seed
549 * the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550 * then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551 * "SeededAllocPages" call to ring-0.
552 *
553 * The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554 * all page sharing (zero page detection will continue). It will also force
555 * all allocations to come from the VM which seeded the page. Both these
556 * measures are taken to make sure that there will never be any need for
557 * mapping anything into ring-3 - everything will be mapped already.
558 *
559 * Whether we'll continue to use the current MM locked memory management
560 * for this I don't quite know (I'd prefer not to and just ditch that all
561 * togther), we'll see what's simplest to do.
562 *
563 *
564 *
565 * @section sec_pgmPhys_Changes Changes
566 *
567 * Breakdown of the changes involved?
568 */
569
570/*******************************************************************************
571* Header Files *
572*******************************************************************************/
573#define LOG_GROUP LOG_GROUP_PGM
574#include <VBox/dbgf.h>
575#include <VBox/pgm.h>
576#include <VBox/cpum.h>
577#include <VBox/iom.h>
578#include <VBox/sup.h>
579#include <VBox/mm.h>
580#include <VBox/em.h>
581#include <VBox/stam.h>
582#include <VBox/rem.h>
583#include <VBox/selm.h>
584#include <VBox/ssm.h>
585#include <VBox/hwaccm.h>
586#include "PGMInternal.h"
587#include <VBox/vm.h>
588#include "PGMInline.h"
589
590#include <VBox/dbg.h>
591#include <VBox/param.h>
592#include <VBox/err.h>
593
594#include <iprt/asm.h>
595#include <iprt/assert.h>
596#include <iprt/env.h>
597#include <iprt/mem.h>
598#include <iprt/file.h>
599#include <iprt/string.h>
600#include <iprt/thread.h>
601
602
603/*******************************************************************************
604* Defined Constants And Macros *
605*******************************************************************************/
606/** Saved state data unit version for 2.5.x and later. */
607#define PGM_SAVED_STATE_VERSION 9
608/** Saved state data unit version for 2.2.2 and later. */
609#define PGM_SAVED_STATE_VERSION_2_2_2 8
610/** Saved state data unit version for 2.2.0. */
611#define PGM_SAVED_STATE_VERSION_RR_DESC 7
612/** Saved state data unit version. */
613#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
614
615
616/*******************************************************************************
617* Internal Functions *
618*******************************************************************************/
619static int pgmR3InitPaging(PVM pVM);
620static void pgmR3InitStats(PVM pVM);
621static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
622static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
623static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
624static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
625static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
626static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
627#ifdef VBOX_STRICT
628static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
629#endif
630static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
631static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
632static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
633
634#ifdef VBOX_WITH_DEBUGGER
635/** @todo Convert the first two commands to 'info' items. */
636static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640# ifdef VBOX_STRICT
641static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642# endif
643static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644#endif
645
646
647/*******************************************************************************
648* Global Variables *
649*******************************************************************************/
650#ifdef VBOX_WITH_DEBUGGER
651/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
652static const DBGCVARDESC g_aPgmErrorArgs[] =
653{
654 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
655 { 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
656};
657
658static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
659{
660 /* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
661 { 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
662 { 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
663};
664
665/** Command descriptors. */
666static const DBGCCMD g_aCmds[] =
667{
668 /* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
669 { "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
670 { "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
671 { "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
672 { "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
673#ifdef VBOX_STRICT
674 { "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
675#endif
676 { "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
677 { "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
678};
679#endif
680
681
682
683
684/*
685 * Shadow - 32-bit mode
686 */
687#define PGM_SHW_TYPE PGM_TYPE_32BIT
688#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
689#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
690#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
691#include "PGMShw.h"
692
693/* Guest - real mode */
694#define PGM_GST_TYPE PGM_TYPE_REAL
695#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
696#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
697#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
698#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
699#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
700#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
701#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
702#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
703#include "PGMBth.h"
704#include "PGMGstDefs.h"
705#include "PGMGst.h"
706#undef BTH_PGMPOOLKIND_PT_FOR_PT
707#undef BTH_PGMPOOLKIND_ROOT
708#undef PGM_BTH_NAME
709#undef PGM_BTH_NAME_RC_STR
710#undef PGM_BTH_NAME_R0_STR
711#undef PGM_GST_TYPE
712#undef PGM_GST_NAME
713#undef PGM_GST_NAME_RC_STR
714#undef PGM_GST_NAME_R0_STR
715
716/* Guest - protected mode */
717#define PGM_GST_TYPE PGM_TYPE_PROT
718#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
719#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
720#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
721#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
722#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
723#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
724#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
725#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
726#include "PGMBth.h"
727#include "PGMGstDefs.h"
728#include "PGMGst.h"
729#undef BTH_PGMPOOLKIND_PT_FOR_PT
730#undef BTH_PGMPOOLKIND_ROOT
731#undef PGM_BTH_NAME
732#undef PGM_BTH_NAME_RC_STR
733#undef PGM_BTH_NAME_R0_STR
734#undef PGM_GST_TYPE
735#undef PGM_GST_NAME
736#undef PGM_GST_NAME_RC_STR
737#undef PGM_GST_NAME_R0_STR
738
739/* Guest - 32-bit mode */
740#define PGM_GST_TYPE PGM_TYPE_32BIT
741#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
742#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
743#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
744#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
745#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
746#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
747#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
748#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
749#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
750#include "PGMBth.h"
751#include "PGMGstDefs.h"
752#include "PGMGst.h"
753#undef BTH_PGMPOOLKIND_PT_FOR_BIG
754#undef BTH_PGMPOOLKIND_PT_FOR_PT
755#undef BTH_PGMPOOLKIND_ROOT
756#undef PGM_BTH_NAME
757#undef PGM_BTH_NAME_RC_STR
758#undef PGM_BTH_NAME_R0_STR
759#undef PGM_GST_TYPE
760#undef PGM_GST_NAME
761#undef PGM_GST_NAME_RC_STR
762#undef PGM_GST_NAME_R0_STR
763
764#undef PGM_SHW_TYPE
765#undef PGM_SHW_NAME
766#undef PGM_SHW_NAME_RC_STR
767#undef PGM_SHW_NAME_R0_STR
768
769
770/*
771 * Shadow - PAE mode
772 */
773#define PGM_SHW_TYPE PGM_TYPE_PAE
774#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
775#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
776#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
777#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
778#include "PGMShw.h"
779
780/* Guest - real mode */
781#define PGM_GST_TYPE PGM_TYPE_REAL
782#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
783#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
784#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
785#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
786#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
787#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
788#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
789#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
790#include "PGMGstDefs.h"
791#include "PGMBth.h"
792#undef BTH_PGMPOOLKIND_PT_FOR_PT
793#undef BTH_PGMPOOLKIND_ROOT
794#undef PGM_BTH_NAME
795#undef PGM_BTH_NAME_RC_STR
796#undef PGM_BTH_NAME_R0_STR
797#undef PGM_GST_TYPE
798#undef PGM_GST_NAME
799#undef PGM_GST_NAME_RC_STR
800#undef PGM_GST_NAME_R0_STR
801
802/* Guest - protected mode */
803#define PGM_GST_TYPE PGM_TYPE_PROT
804#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
805#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
806#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
807#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
808#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
809#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
810#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
811#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
812#include "PGMGstDefs.h"
813#include "PGMBth.h"
814#undef BTH_PGMPOOLKIND_PT_FOR_PT
815#undef BTH_PGMPOOLKIND_ROOT
816#undef PGM_BTH_NAME
817#undef PGM_BTH_NAME_RC_STR
818#undef PGM_BTH_NAME_R0_STR
819#undef PGM_GST_TYPE
820#undef PGM_GST_NAME
821#undef PGM_GST_NAME_RC_STR
822#undef PGM_GST_NAME_R0_STR
823
824/* Guest - 32-bit mode */
825#define PGM_GST_TYPE PGM_TYPE_32BIT
826#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
827#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
828#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
829#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
830#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
831#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
832#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
833#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
834#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
835#include "PGMGstDefs.h"
836#include "PGMBth.h"
837#undef BTH_PGMPOOLKIND_PT_FOR_BIG
838#undef BTH_PGMPOOLKIND_PT_FOR_PT
839#undef BTH_PGMPOOLKIND_ROOT
840#undef PGM_BTH_NAME
841#undef PGM_BTH_NAME_RC_STR
842#undef PGM_BTH_NAME_R0_STR
843#undef PGM_GST_TYPE
844#undef PGM_GST_NAME
845#undef PGM_GST_NAME_RC_STR
846#undef PGM_GST_NAME_R0_STR
847
848/* Guest - PAE mode */
849#define PGM_GST_TYPE PGM_TYPE_PAE
850#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
851#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
852#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
853#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
854#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
855#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
856#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
857#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
858#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
859#include "PGMBth.h"
860#include "PGMGstDefs.h"
861#include "PGMGst.h"
862#undef BTH_PGMPOOLKIND_PT_FOR_BIG
863#undef BTH_PGMPOOLKIND_PT_FOR_PT
864#undef BTH_PGMPOOLKIND_ROOT
865#undef PGM_BTH_NAME
866#undef PGM_BTH_NAME_RC_STR
867#undef PGM_BTH_NAME_R0_STR
868#undef PGM_GST_TYPE
869#undef PGM_GST_NAME
870#undef PGM_GST_NAME_RC_STR
871#undef PGM_GST_NAME_R0_STR
872
873#undef PGM_SHW_TYPE
874#undef PGM_SHW_NAME
875#undef PGM_SHW_NAME_RC_STR
876#undef PGM_SHW_NAME_R0_STR
877
878
879/*
880 * Shadow - AMD64 mode
881 */
882#define PGM_SHW_TYPE PGM_TYPE_AMD64
883#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
884#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
885#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
886#include "PGMShw.h"
887
888#ifdef VBOX_WITH_64_BITS_GUESTS
889/* Guest - AMD64 mode */
890# define PGM_GST_TYPE PGM_TYPE_AMD64
891# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
892# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
893# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
894# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
895# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
896# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
897# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
898# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
899# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
900# include "PGMBth.h"
901# include "PGMGstDefs.h"
902# include "PGMGst.h"
903# undef BTH_PGMPOOLKIND_PT_FOR_BIG
904# undef BTH_PGMPOOLKIND_PT_FOR_PT
905# undef BTH_PGMPOOLKIND_ROOT
906# undef PGM_BTH_NAME
907# undef PGM_BTH_NAME_RC_STR
908# undef PGM_BTH_NAME_R0_STR
909# undef PGM_GST_TYPE
910# undef PGM_GST_NAME
911# undef PGM_GST_NAME_RC_STR
912# undef PGM_GST_NAME_R0_STR
913#endif /* VBOX_WITH_64_BITS_GUESTS */
914
915#undef PGM_SHW_TYPE
916#undef PGM_SHW_NAME
917#undef PGM_SHW_NAME_RC_STR
918#undef PGM_SHW_NAME_R0_STR
919
920
921/*
922 * Shadow - Nested paging mode
923 */
924#define PGM_SHW_TYPE PGM_TYPE_NESTED
925#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
926#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
927#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
928#include "PGMShw.h"
929
930/* Guest - real mode */
931#define PGM_GST_TYPE PGM_TYPE_REAL
932#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
933#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
934#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
935#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
936#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
937#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
938#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
939#include "PGMGstDefs.h"
940#include "PGMBth.h"
941#undef BTH_PGMPOOLKIND_PT_FOR_PT
942#undef PGM_BTH_NAME
943#undef PGM_BTH_NAME_RC_STR
944#undef PGM_BTH_NAME_R0_STR
945#undef PGM_GST_TYPE
946#undef PGM_GST_NAME
947#undef PGM_GST_NAME_RC_STR
948#undef PGM_GST_NAME_R0_STR
949
950/* Guest - protected mode */
951#define PGM_GST_TYPE PGM_TYPE_PROT
952#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
953#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
954#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
955#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
956#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
957#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
958#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
959#include "PGMGstDefs.h"
960#include "PGMBth.h"
961#undef BTH_PGMPOOLKIND_PT_FOR_PT
962#undef PGM_BTH_NAME
963#undef PGM_BTH_NAME_RC_STR
964#undef PGM_BTH_NAME_R0_STR
965#undef PGM_GST_TYPE
966#undef PGM_GST_NAME
967#undef PGM_GST_NAME_RC_STR
968#undef PGM_GST_NAME_R0_STR
969
970/* Guest - 32-bit mode */
971#define PGM_GST_TYPE PGM_TYPE_32BIT
972#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
973#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
974#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
975#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
976#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
977#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
978#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
979#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
980#include "PGMGstDefs.h"
981#include "PGMBth.h"
982#undef BTH_PGMPOOLKIND_PT_FOR_BIG
983#undef BTH_PGMPOOLKIND_PT_FOR_PT
984#undef PGM_BTH_NAME
985#undef PGM_BTH_NAME_RC_STR
986#undef PGM_BTH_NAME_R0_STR
987#undef PGM_GST_TYPE
988#undef PGM_GST_NAME
989#undef PGM_GST_NAME_RC_STR
990#undef PGM_GST_NAME_R0_STR
991
992/* Guest - PAE mode */
993#define PGM_GST_TYPE PGM_TYPE_PAE
994#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
995#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
996#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
997#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
998#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
999#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1000#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1001#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1002#include "PGMGstDefs.h"
1003#include "PGMBth.h"
1004#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1005#undef BTH_PGMPOOLKIND_PT_FOR_PT
1006#undef PGM_BTH_NAME
1007#undef PGM_BTH_NAME_RC_STR
1008#undef PGM_BTH_NAME_R0_STR
1009#undef PGM_GST_TYPE
1010#undef PGM_GST_NAME
1011#undef PGM_GST_NAME_RC_STR
1012#undef PGM_GST_NAME_R0_STR
1013
1014#ifdef VBOX_WITH_64_BITS_GUESTS
1015/* Guest - AMD64 mode */
1016# define PGM_GST_TYPE PGM_TYPE_AMD64
1017# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1018# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1019# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1020# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1021# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1022# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1023# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1024# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1025# include "PGMGstDefs.h"
1026# include "PGMBth.h"
1027# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1028# undef BTH_PGMPOOLKIND_PT_FOR_PT
1029# undef PGM_BTH_NAME
1030# undef PGM_BTH_NAME_RC_STR
1031# undef PGM_BTH_NAME_R0_STR
1032# undef PGM_GST_TYPE
1033# undef PGM_GST_NAME
1034# undef PGM_GST_NAME_RC_STR
1035# undef PGM_GST_NAME_R0_STR
1036#endif /* VBOX_WITH_64_BITS_GUESTS */
1037
1038#undef PGM_SHW_TYPE
1039#undef PGM_SHW_NAME
1040#undef PGM_SHW_NAME_RC_STR
1041#undef PGM_SHW_NAME_R0_STR
1042
1043
1044/*
1045 * Shadow - EPT
1046 */
1047#define PGM_SHW_TYPE PGM_TYPE_EPT
1048#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1049#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1050#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1051#include "PGMShw.h"
1052
1053/* Guest - real mode */
1054#define PGM_GST_TYPE PGM_TYPE_REAL
1055#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1056#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1057#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1058#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1059#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1060#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1061#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1062#include "PGMGstDefs.h"
1063#include "PGMBth.h"
1064#undef BTH_PGMPOOLKIND_PT_FOR_PT
1065#undef PGM_BTH_NAME
1066#undef PGM_BTH_NAME_RC_STR
1067#undef PGM_BTH_NAME_R0_STR
1068#undef PGM_GST_TYPE
1069#undef PGM_GST_NAME
1070#undef PGM_GST_NAME_RC_STR
1071#undef PGM_GST_NAME_R0_STR
1072
1073/* Guest - protected mode */
1074#define PGM_GST_TYPE PGM_TYPE_PROT
1075#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1076#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1077#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1078#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1079#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1080#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1081#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1082#include "PGMGstDefs.h"
1083#include "PGMBth.h"
1084#undef BTH_PGMPOOLKIND_PT_FOR_PT
1085#undef PGM_BTH_NAME
1086#undef PGM_BTH_NAME_RC_STR
1087#undef PGM_BTH_NAME_R0_STR
1088#undef PGM_GST_TYPE
1089#undef PGM_GST_NAME
1090#undef PGM_GST_NAME_RC_STR
1091#undef PGM_GST_NAME_R0_STR
1092
1093/* Guest - 32-bit mode */
1094#define PGM_GST_TYPE PGM_TYPE_32BIT
1095#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1096#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1097#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1098#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1099#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1100#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1101#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1102#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1103#include "PGMGstDefs.h"
1104#include "PGMBth.h"
1105#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1106#undef BTH_PGMPOOLKIND_PT_FOR_PT
1107#undef PGM_BTH_NAME
1108#undef PGM_BTH_NAME_RC_STR
1109#undef PGM_BTH_NAME_R0_STR
1110#undef PGM_GST_TYPE
1111#undef PGM_GST_NAME
1112#undef PGM_GST_NAME_RC_STR
1113#undef PGM_GST_NAME_R0_STR
1114
1115/* Guest - PAE mode */
1116#define PGM_GST_TYPE PGM_TYPE_PAE
1117#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1118#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1119#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1120#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1121#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1122#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1123#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1124#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1125#include "PGMGstDefs.h"
1126#include "PGMBth.h"
1127#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1128#undef BTH_PGMPOOLKIND_PT_FOR_PT
1129#undef PGM_BTH_NAME
1130#undef PGM_BTH_NAME_RC_STR
1131#undef PGM_BTH_NAME_R0_STR
1132#undef PGM_GST_TYPE
1133#undef PGM_GST_NAME
1134#undef PGM_GST_NAME_RC_STR
1135#undef PGM_GST_NAME_R0_STR
1136
1137#ifdef VBOX_WITH_64_BITS_GUESTS
1138/* Guest - AMD64 mode */
1139# define PGM_GST_TYPE PGM_TYPE_AMD64
1140# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1141# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1142# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1143# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1144# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1145# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1146# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1147# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1148# include "PGMGstDefs.h"
1149# include "PGMBth.h"
1150# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1151# undef BTH_PGMPOOLKIND_PT_FOR_PT
1152# undef PGM_BTH_NAME
1153# undef PGM_BTH_NAME_RC_STR
1154# undef PGM_BTH_NAME_R0_STR
1155# undef PGM_GST_TYPE
1156# undef PGM_GST_NAME
1157# undef PGM_GST_NAME_RC_STR
1158# undef PGM_GST_NAME_R0_STR
1159#endif /* VBOX_WITH_64_BITS_GUESTS */
1160
1161#undef PGM_SHW_TYPE
1162#undef PGM_SHW_NAME
1163#undef PGM_SHW_NAME_RC_STR
1164#undef PGM_SHW_NAME_R0_STR
1165
1166
1167
1168/**
1169 * Initiates the paging of VM.
1170 *
1171 * @returns VBox status code.
1172 * @param pVM Pointer to VM structure.
1173 */
1174VMMR3DECL(int) PGMR3Init(PVM pVM)
1175{
1176 LogFlow(("PGMR3Init:\n"));
1177 PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1178 int rc;
1179
1180 /*
1181 * Assert alignment and sizes.
1182 */
1183 AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1184 AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1185 AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1186
1187 /*
1188 * Init the structure.
1189 */
1190#ifdef PGM_WITHOUT_MAPPINGS
1191 pVM->pgm.s.fMappingsDisabled = true;
1192#endif
1193 pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1194 pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1195
1196 /* Init the per-CPU part. */
1197 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1198 {
1199 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1200 PPGMCPU pPGM = &pVCpu->pgm.s;
1201
1202 pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1203 pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1204 pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1205
1206 pPGM->enmShadowMode = PGMMODE_INVALID;
1207 pPGM->enmGuestMode = PGMMODE_INVALID;
1208
1209 pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1210
1211 pPGM->pGstPaePdptR3 = NULL;
1212#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1213 pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1214#endif
1215 pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1216 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1217 {
1218 pPGM->apGstPaePDsR3[i] = NULL;
1219#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1220 pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1221#endif
1222 pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1223 pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1224 pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1225 }
1226
1227 pPGM->fA20Enabled = true;
1228 }
1229
1230 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1231 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1232 pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1233
1234 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1235#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1236 true
1237#else
1238 false
1239#endif
1240 );
1241 AssertLogRelRCReturn(rc, rc);
1242
1243#if HC_ARCH_BITS == 64 || 1 /** @todo 4GB/32-bit: remove || 1 later and adjust the limit. */
1244 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1245#else
1246 rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1247#endif
1248 AssertLogRelRCReturn(rc, rc);
1249 for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1250 pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1251
1252 /*
1253 * Get the configured RAM size - to estimate saved state size.
1254 */
1255 uint64_t cbRam;
1256 rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1257 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1258 cbRam = 0;
1259 else if (RT_SUCCESS(rc))
1260 {
1261 if (cbRam < PAGE_SIZE)
1262 cbRam = 0;
1263 cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1264 }
1265 else
1266 {
1267 AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1268 return rc;
1269 }
1270
1271 /*
1272 * Register callbacks, string formatters and the saved state data unit.
1273 */
1274#ifdef VBOX_STRICT
1275 VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1276#endif
1277 PGMRegisterStringFormatTypes();
1278
1279 rc = pgmR3InitSavedState(pVM, cbRam);
1280 if (RT_FAILURE(rc))
1281 return rc;
1282
1283 /*
1284 * Initialize the PGM critical section and flush the phys TLBs
1285 */
1286 rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1287 AssertRCReturn(rc, rc);
1288
1289 PGMR3PhysChunkInvalidateTLB(pVM);
1290 PGMPhysInvalidatePageMapTLB(pVM);
1291
1292 /*
1293 * For the time being we sport a full set of handy pages in addition to the base
1294 * memory to simplify things.
1295 */
1296 rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1297 AssertRCReturn(rc, rc);
1298
1299 /*
1300 * Trees
1301 */
1302 rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1303 if (RT_SUCCESS(rc))
1304 {
1305 pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1306 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1307
1308 /*
1309 * Alocate the zero page.
1310 */
1311 rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1312 }
1313 if (RT_SUCCESS(rc))
1314 {
1315 pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1316 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1317 pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1318 AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1319
1320 /*
1321 * Init the paging.
1322 */
1323 rc = pgmR3InitPaging(pVM);
1324 }
1325 if (RT_SUCCESS(rc))
1326 {
1327 /*
1328 * Init the page pool.
1329 */
1330 rc = pgmR3PoolInit(pVM);
1331 }
1332 if (RT_SUCCESS(rc))
1333 {
1334 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1335 {
1336 PVMCPU pVCpu = &pVM->aCpus[i];
1337 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1338 if (RT_FAILURE(rc))
1339 break;
1340 }
1341 }
1342
1343 if (RT_SUCCESS(rc))
1344 {
1345 /*
1346 * Info & statistics
1347 */
1348 DBGFR3InfoRegisterInternal(pVM, "mode",
1349 "Shows the current paging mode. "
1350 "Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1351 pgmR3InfoMode);
1352 DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1353 "Dumps all the entries in the top level paging table. No arguments.",
1354 pgmR3InfoCr3);
1355 DBGFR3InfoRegisterInternal(pVM, "phys",
1356 "Dumps all the physical address ranges. No arguments.",
1357 pgmR3PhysInfo);
1358 DBGFR3InfoRegisterInternal(pVM, "handlers",
1359 "Dumps physical, virtual and hyper virtual handlers. "
1360 "Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1361 "Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1362 pgmR3InfoHandlers);
1363 DBGFR3InfoRegisterInternal(pVM, "mappings",
1364 "Dumps guest mappings.",
1365 pgmR3MapInfo);
1366
1367 pgmR3InitStats(pVM);
1368
1369#ifdef VBOX_WITH_DEBUGGER
1370 /*
1371 * Debugger commands.
1372 */
1373 static bool s_fRegisteredCmds = false;
1374 if (!s_fRegisteredCmds)
1375 {
1376 int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1377 if (RT_SUCCESS(rc2))
1378 s_fRegisteredCmds = true;
1379 }
1380#endif
1381 return VINF_SUCCESS;
1382 }
1383
1384 /* Almost no cleanup necessary, MM frees all memory. */
1385 PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1386
1387 return rc;
1388}
1389
1390
1391/**
1392 * Initializes the per-VCPU PGM.
1393 *
1394 * @returns VBox status code.
1395 * @param pVM The VM to operate on.
1396 */
1397VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1398{
1399 LogFlow(("PGMR3InitCPU\n"));
1400 return VINF_SUCCESS;
1401}
1402
1403
1404/**
1405 * Init paging.
1406 *
1407 * Since we need to check what mode the host is operating in before we can choose
1408 * the right paging functions for the host we have to delay this until R0 has
1409 * been initialized.
1410 *
1411 * @returns VBox status code.
1412 * @param pVM VM handle.
1413 */
1414static int pgmR3InitPaging(PVM pVM)
1415{
1416 /*
1417 * Force a recalculation of modes and switcher so everyone gets notified.
1418 */
1419 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1420 {
1421 PVMCPU pVCpu = &pVM->aCpus[i];
1422
1423 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1424 pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1425 }
1426
1427 pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1428
1429 /*
1430 * Allocate static mapping space for whatever the cr3 register
1431 * points to and in the case of PAE mode to the 4 PDs.
1432 */
1433 int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1434 if (RT_FAILURE(rc))
1435 {
1436 AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1437 return rc;
1438 }
1439 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1440
1441 /*
1442 * Allocate pages for the three possible intermediate contexts
1443 * (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1444 * for the sake of simplicity. The AMD64 uses the PAE for the
1445 * lower levels, making the total number of pages 11 (3 + 7 + 1).
1446 *
1447 * We assume that two page tables will be enought for the core code
1448 * mappings (HC virtual and identity).
1449 */
1450 pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1451 pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1452 pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1453 pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1454 pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1455 pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1456 pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1457 pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1458 pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1459 pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1460 pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1461 pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1462
1463 pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1464 AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1465 pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1466 AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1467 pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1468 AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1469
1470 /*
1471 * Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1472 */
1473 ASMMemZeroPage(pVM->pgm.s.pInterPD);
1474 ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1475 ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1476
1477 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1478 ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1479
1480 ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1481 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1482 {
1483 ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1484 pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P | PGM_PLXFLAGS_PERMANENT
1485 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1486 }
1487
1488 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1489 {
1490 const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1491 pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
1492 | MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1493 }
1494
1495 RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1496 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1497 pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
1498 | HCPhysInterPaePDPT64;
1499
1500 /*
1501 * Initialize paging workers and mode from current host mode
1502 * and the guest running in real mode.
1503 */
1504 pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1505 switch (pVM->pgm.s.enmHostMode)
1506 {
1507 case SUPPAGINGMODE_32_BIT:
1508 case SUPPAGINGMODE_32_BIT_GLOBAL:
1509 case SUPPAGINGMODE_PAE:
1510 case SUPPAGINGMODE_PAE_GLOBAL:
1511 case SUPPAGINGMODE_PAE_NX:
1512 case SUPPAGINGMODE_PAE_GLOBAL_NX:
1513 break;
1514
1515 case SUPPAGINGMODE_AMD64:
1516 case SUPPAGINGMODE_AMD64_GLOBAL:
1517 case SUPPAGINGMODE_AMD64_NX:
1518 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1519#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1520 if (ARCH_BITS != 64)
1521 {
1522 AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1523 LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1524 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1525 }
1526#endif
1527 break;
1528 default:
1529 AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1530 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1531 }
1532 rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1533 if (RT_SUCCESS(rc))
1534 {
1535 LogFlow(("pgmR3InitPaging: returns successfully\n"));
1536#if HC_ARCH_BITS == 64
1537 LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1538 pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1539 LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1540 MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1541 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1542 MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1543 MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1544#endif
1545
1546 return VINF_SUCCESS;
1547 }
1548
1549 LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1550 return rc;
1551}
1552
1553
1554/**
1555 * Init statistics
1556 */
1557static void pgmR3InitStats(PVM pVM)
1558{
1559 PPGM pPGM = &pVM->pgm.s;
1560 int rc;
1561
1562 /* Common - misc variables */
1563 STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1564 STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1565 STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1566 STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1567 STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1568 STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1569 STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1570 STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1571 STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1572 STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1573 STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1574 STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1575 STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1576 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1577 STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1578
1579 STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1580 STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1581 STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1582 STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1583
1584 /* Live save */
1585 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1586 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1587 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1588 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1589 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1590 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1591 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1592 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1593 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1594 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1595 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1596 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1597 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1598 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1599 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1600 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1601 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1602 STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1603
1604#ifdef VBOX_WITH_STATISTICS
1605
1606# define PGM_REG_COUNTER(a, b, c) \
1607 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1608 AssertRC(rc);
1609
1610# define PGM_REG_COUNTER_BYTES(a, b, c) \
1611 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1612 AssertRC(rc);
1613
1614# define PGM_REG_PROFILE(a, b, c) \
1615 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1616 AssertRC(rc);
1617
1618 PGM_REG_PROFILE(&pPGM->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1619 PGM_REG_PROFILE(&pPGM->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1620 PGM_REG_PROFILE(&pPGM->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1621 PGM_REG_PROFILE(&pPGM->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1622
1623 PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1624 PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1625 PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1626 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1627 PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1628 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1629 PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1630 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1631 PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1632 PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1633
1634 PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1635 PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1636 PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1637 PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1638 PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1639 PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1640 PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1641 PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1642 PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1643 PGM_REG_COUNTER(&pPGM->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1644
1645 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1646 PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1647 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1648 PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1649
1650 PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1651 PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1652 PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1653 PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1654
1655 PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1656 PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1657/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1658 PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1659 PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1660/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1661
1662 PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1663 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1664 PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1665 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1666 PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1667 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1668 PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1669 PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1670
1671 /* GC only: */
1672 PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1673 PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1674 PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1675 PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1676
1677 PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1678 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1679 PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1680 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1681 PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1682 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1683 PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1684 PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1685
1686 PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1687 PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1688 PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1689 PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1690 PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1691 PGM_REG_COUNTER(&pPGM->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1692 PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1693
1694# undef PGM_REG_COUNTER
1695# undef PGM_REG_PROFILE
1696#endif
1697
1698 /*
1699 * Note! The layout below matches the member layout exactly!
1700 */
1701
1702 /*
1703 * Common - stats
1704 */
1705 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1706 {
1707 PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1708
1709#define PGM_REG_COUNTER(a, b, c) \
1710 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1711 AssertRC(rc);
1712#define PGM_REG_PROFILE(a, b, c) \
1713 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1714 AssertRC(rc);
1715
1716 PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1717
1718#ifdef VBOX_WITH_STATISTICS
1719
1720# if 0 /* rarely useful; leave for debugging. */
1721 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1722 STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1723 "The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1724 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPagePD); j++)
1725 STAMR3RegisterF(pVM, &pPgmCpu->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1726 "The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1727# endif
1728 /* R0 only: */
1729 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapMigrateInvlPg, "/PGM/CPU%u/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1730 PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapGCPageInl, "/PGM/CPU%u/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1731 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1732 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1733 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1734 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%u/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1735 PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPageInl, "/PGM/CPU%u/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1736 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlHits, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1737 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapHCPageInlMisses, "/PGM/CPU%u/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1738 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPage, "/PGM/CPU%u/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1739 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetOptimize, "/PGM/CPU%u/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1740 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchFlushes, "/PGM/CPU%u/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1741 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchHits, "/PGM/CPU%u/R0/DynMapPage/SetSearchHits", "Set search hits.");
1742 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSetSearchMisses, "/PGM/CPU%u/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1743 PGM_REG_PROFILE(&pPgmCpu->StatR0DynMapHCPage, "/PGM/CPU%u/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1744 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits0, "/PGM/CPU%u/R0/DynMapPage/Hits0", "Hits at iPage+0");
1745 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits1, "/PGM/CPU%u/R0/DynMapPage/Hits1", "Hits at iPage+1");
1746 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageHits2, "/PGM/CPU%u/R0/DynMapPage/Hits2", "Hits at iPage+2");
1747 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageInvlPg, "/PGM/CPU%u/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1748 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlow, "/PGM/CPU%u/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1749 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%u/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1750 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%u/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1751 //PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMapPage/SlowLostHits", "Lost hits.");
1752 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapSubsets, "/PGM/CPU%u/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1753 PGM_REG_COUNTER(&pPgmCpu->StatR0DynMapPopFlushes, "/PGM/CPU%u/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1754 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[0], "/PGM/CPU%u/R0/SetSize000..09", "00-09% filled");
1755 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[1], "/PGM/CPU%u/R0/SetSize010..19", "10-19% filled");
1756 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[2], "/PGM/CPU%u/R0/SetSize020..29", "20-29% filled");
1757 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[3], "/PGM/CPU%u/R0/SetSize030..39", "30-39% filled");
1758 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[4], "/PGM/CPU%u/R0/SetSize040..49", "40-49% filled");
1759 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[5], "/PGM/CPU%u/R0/SetSize050..59", "50-59% filled");
1760 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[6], "/PGM/CPU%u/R0/SetSize060..69", "60-69% filled");
1761 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[7], "/PGM/CPU%u/R0/SetSize070..79", "70-79% filled");
1762 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[8], "/PGM/CPU%u/R0/SetSize080..89", "80-89% filled");
1763 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[9], "/PGM/CPU%u/R0/SetSize090..99", "90-99% filled");
1764 PGM_REG_COUNTER(&pPgmCpu->aStatR0DynMapSetSize[10], "/PGM/CPU%u/R0/SetSize100", "100% filled");
1765
1766 /* RZ only: */
1767 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1768 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%u/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1769 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeSyncPT, "/PGM/CPU%u/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1770 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeMapping, "/PGM/CPU%u/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1771 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1772 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTimeHandlers, "/PGM/CPU%u/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1773 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1774 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1775 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1776 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1777 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1778 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1779 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1780 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1781 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1782 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1783 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1784 PGM_REG_PROFILE(&pPgmCpu->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1785 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1786 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1787 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1788 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersPhysical, "/PGM/CPU%u/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1789 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1790 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1791 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1792 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1793 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1794 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1795 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1796 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1797 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1798 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1799 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1800 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1801 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1802 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1803 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1804 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1805 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1806 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFUnh, "/PGM/CPU%u/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1807 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1808 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1809 PGM_REG_COUNTER(&pPgmCpu->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1810#if 0 /* rarely useful; leave for debugging. */
1811 for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatRZTrap0ePD); j++)
1812 STAMR3RegisterF(pVM, &pPgmCpu->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1813 "The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1814#endif
1815 PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1816 PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1817 PGM_REG_COUNTER(&pPgmCpu->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1818 PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1819 PGM_REG_COUNTER(&pPgmCpu->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1820
1821 /* HC only: */
1822
1823 /* RZ & R3: */
1824 PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1825 PGM_REG_PROFILE(&pPgmCpu->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1826 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1827 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1828 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1829 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1830 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1831 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1832 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1833 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1834 PGM_REG_PROFILE(&pPgmCpu->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1835 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1836 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1837 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1838 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1839 PGM_REG_COUNTER(&pPgmCpu->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1840 PGM_REG_COUNTER(&pPgmCpu->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1841 PGM_REG_PROFILE(&pPgmCpu->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1842 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1843 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1844 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1845 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1846 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1847 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1848 PGM_REG_COUNTER(&pPgmCpu->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1849 PGM_REG_COUNTER(&pPgmCpu->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1850 PGM_REG_PROFILE(&pPgmCpu->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1851 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1852 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1853 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1854 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1855 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1856 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1857 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1858 PGM_REG_COUNTER(&pPgmCpu->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1859 PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1860 PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1861 PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1862 PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1863 PGM_REG_COUNTER(&pPgmCpu->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1864 PGM_REG_PROFILE(&pPgmCpu->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1865 PGM_REG_PROFILE(&pPgmCpu->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1866 PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1867 PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1868 PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1869 PGM_REG_COUNTER(&pPgmCpu->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1870 PGM_REG_PROFILE(&pPgmCpu->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1871
1872 PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1873 PGM_REG_PROFILE(&pPgmCpu->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1874 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1875 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1876 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1877 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1878 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1879 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1880 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1881 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1882 PGM_REG_PROFILE(&pPgmCpu->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1883 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1884 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1885 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1886 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1887 PGM_REG_COUNTER(&pPgmCpu->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1888 PGM_REG_COUNTER(&pPgmCpu->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1889 PGM_REG_PROFILE(&pPgmCpu->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1890 PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1891 PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1892 PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1893 PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1894 PGM_REG_COUNTER(&pPgmCpu->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1895 PGM_REG_COUNTER(&pPgmCpu->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1896 PGM_REG_COUNTER(&pPgmCpu->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1897 PGM_REG_PROFILE(&pPgmCpu->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1898 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1899 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1900 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1901 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1902 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1903 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1904 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1905 PGM_REG_COUNTER(&pPgmCpu->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1906 PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1907 PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1908 PGM_REG_COUNTER(&pPgmCpu->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1909 PGM_REG_PROFILE(&pPgmCpu->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1910 PGM_REG_PROFILE(&pPgmCpu->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1911 PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1912 PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1913 PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1914 PGM_REG_COUNTER(&pPgmCpu->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1915 PGM_REG_PROFILE(&pPgmCpu->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1916#endif /* VBOX_WITH_STATISTICS */
1917
1918#undef PGM_REG_PROFILE
1919#undef PGM_REG_COUNTER
1920
1921 }
1922}
1923
1924
1925/**
1926 * Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1927 *
1928 * The dynamic mapping area will also be allocated and initialized at this
1929 * time. We could allocate it during PGMR3Init of course, but the mapping
1930 * wouldn't be allocated at that time preventing us from setting up the
1931 * page table entries with the dummy page.
1932 *
1933 * @returns VBox status code.
1934 * @param pVM VM handle.
1935 */
1936VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1937{
1938 RTGCPTR GCPtr;
1939 int rc;
1940
1941 /*
1942 * Reserve space for the dynamic mappings.
1943 */
1944 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1945 if (RT_SUCCESS(rc))
1946 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1947
1948 if ( RT_SUCCESS(rc)
1949 && (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1950 {
1951 rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1952 if (RT_SUCCESS(rc))
1953 pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1954 }
1955 if (RT_SUCCESS(rc))
1956 {
1957 AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1958 MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1959 }
1960 return rc;
1961}
1962
1963
1964/**
1965 * Ring-3 init finalizing.
1966 *
1967 * @returns VBox status code.
1968 * @param pVM The VM handle.
1969 */
1970VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1971{
1972 int rc;
1973
1974 /*
1975 * Reserve space for the dynamic mappings.
1976 * Initialize the dynamic mapping pages with dummy pages to simply the cache.
1977 */
1978 /* get the pointer to the page table entries. */
1979 PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1980 AssertRelease(pMapping);
1981 const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1982 const unsigned iPT = off >> X86_PD_SHIFT;
1983 const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1984 pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1985 pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1986
1987 /* init cache */
1988 RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1989 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1990 pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1991
1992 for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1993 {
1994 rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1995 AssertRCReturn(rc, rc);
1996 }
1997
1998 /*
1999 * Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2000 * Intel only goes up to 36 bits, so we stick to 36 as well.
2001 */
2002 /** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
2003 uint32_t u32Dummy, u32Features;
2004 CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2005
2006 if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2007 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
2008 else
2009 pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2010
2011 /*
2012 * Allocate memory if we're supposed to do that.
2013 */
2014 if (pVM->pgm.s.fRamPreAlloc)
2015 rc = pgmR3PhysRamPreAllocate(pVM);
2016
2017 LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2018 return rc;
2019}
2020
2021
2022/**
2023 * Applies relocations to data and code managed by this component.
2024 *
2025 * This function will be called at init and whenever the VMM need to relocate it
2026 * self inside the GC.
2027 *
2028 * @param pVM The VM.
2029 * @param offDelta Relocation delta relative to old location.
2030 */
2031VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2032{
2033 LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2034
2035 /*
2036 * Paging stuff.
2037 */
2038 pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2039
2040 pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2041
2042 /* Shadow, guest and both mode switch & relocation for each VCPU. */
2043 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2044 {
2045 PVMCPU pVCpu = &pVM->aCpus[i];
2046
2047 pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2048
2049 PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2050 PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2051 PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2052 }
2053
2054 /*
2055 * Trees.
2056 */
2057 pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2058
2059 /*
2060 * Ram ranges.
2061 */
2062 if (pVM->pgm.s.pRamRangesR3)
2063 {
2064 /* Update the pSelfRC pointers and relink them. */
2065 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2066 if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2067 pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2068 pgmR3PhysRelinkRamRanges(pVM);
2069 }
2070
2071 /*
2072 * Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2073 * be mapped and thus not included in the above exercise.
2074 */
2075 for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2076 if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2077 pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2078
2079 /*
2080 * Update the two page directories with all page table mappings.
2081 * (One or more of them have changed, that's why we're here.)
2082 */
2083 pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2084 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2085 pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2086
2087 /* Relocate GC addresses of Page Tables. */
2088 for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2089 {
2090 for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2091 {
2092 pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2093 pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2094 }
2095 }
2096
2097 /*
2098 * Dynamic page mapping area.
2099 */
2100 pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2101 pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2102 pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2103
2104 /*
2105 * The Zero page.
2106 */
2107 pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2108#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2109 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
2110#else
2111 AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2112#endif
2113
2114 /*
2115 * Physical and virtual handlers.
2116 */
2117 RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2118 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2119 RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2120
2121 /*
2122 * The page pool.
2123 */
2124 pgmR3PoolRelocate(pVM);
2125}
2126
2127
2128/**
2129 * Callback function for relocating a physical access handler.
2130 *
2131 * @returns 0 (continue enum)
2132 * @param pNode Pointer to a PGMPHYSHANDLER node.
2133 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2134 * not certain the delta will fit in a void pointer for all possible configs.
2135 */
2136static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2137{
2138 PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2139 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2140 if (pHandler->pfnHandlerRC)
2141 pHandler->pfnHandlerRC += offDelta;
2142 if (pHandler->pvUserRC >= 0x10000)
2143 pHandler->pvUserRC += offDelta;
2144 return 0;
2145}
2146
2147
2148/**
2149 * Callback function for relocating a virtual access handler.
2150 *
2151 * @returns 0 (continue enum)
2152 * @param pNode Pointer to a PGMVIRTHANDLER node.
2153 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2154 * not certain the delta will fit in a void pointer for all possible configs.
2155 */
2156static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2157{
2158 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2159 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2160 Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2161 || pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2162 Assert(pHandler->pfnHandlerRC);
2163 pHandler->pfnHandlerRC += offDelta;
2164 return 0;
2165}
2166
2167
2168/**
2169 * Callback function for relocating a virtual access handler for the hypervisor mapping.
2170 *
2171 * @returns 0 (continue enum)
2172 * @param pNode Pointer to a PGMVIRTHANDLER node.
2173 * @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2174 * not certain the delta will fit in a void pointer for all possible configs.
2175 */
2176static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2177{
2178 PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2179 RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2180 Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2181 Assert(pHandler->pfnHandlerRC);
2182 pHandler->pfnHandlerRC += offDelta;
2183 return 0;
2184}
2185
2186
2187/**
2188 * Resets a virtual CPU when unplugged.
2189 *
2190 * @param pVM The VM handle.
2191 * @param pVCpu The virtual CPU handle.
2192 */
2193VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2194{
2195 int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2196 AssertRC(rc);
2197
2198 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2199 AssertRC(rc);
2200
2201 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2202
2203 pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2204
2205 /*
2206 * Re-init other members.
2207 */
2208 pVCpu->pgm.s.fA20Enabled = true;
2209
2210 /*
2211 * Clear the FFs PGM owns.
2212 */
2213 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2214 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2215}
2216
2217
2218/**
2219 * The VM is being reset.
2220 *
2221 * For the PGM component this means that any PD write monitors
2222 * needs to be removed.
2223 *
2224 * @param pVM VM handle.
2225 */
2226VMMR3DECL(void) PGMR3Reset(PVM pVM)
2227{
2228 int rc;
2229
2230 LogFlow(("PGMR3Reset:\n"));
2231 VM_ASSERT_EMT(pVM);
2232
2233 pgmLock(pVM);
2234
2235 /*
2236 * Unfix any fixed mappings and disable CR3 monitoring.
2237 */
2238 pVM->pgm.s.fMappingsFixed = false;
2239 pVM->pgm.s.fMappingsFixedRestored = false;
2240 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2241 pVM->pgm.s.cbMappingFixed = 0;
2242
2243 /*
2244 * Exit the guest paging mode before the pgm pool gets reset.
2245 * Important to clean up the amd64 case.
2246 */
2247 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2248 {
2249 PVMCPU pVCpu = &pVM->aCpus[i];
2250 rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2251 AssertRC(rc);
2252 }
2253
2254#ifdef DEBUG
2255 DBGFR3InfoLog(pVM, "mappings", NULL);
2256 DBGFR3InfoLog(pVM, "handlers", "all nostat");
2257#endif
2258
2259 /*
2260 * Switch mode back to real mode. (before resetting the pgm pool!)
2261 */
2262 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2263 {
2264 PVMCPU pVCpu = &pVM->aCpus[i];
2265
2266 rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2267 AssertRC(rc);
2268
2269 STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2270 }
2271
2272 /*
2273 * Reset the shadow page pool.
2274 */
2275 pgmR3PoolReset(pVM);
2276
2277 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2278 {
2279 PVMCPU pVCpu = &pVM->aCpus[i];
2280
2281 /*
2282 * Re-init other members.
2283 */
2284 pVCpu->pgm.s.fA20Enabled = true;
2285
2286 /*
2287 * Clear the FFs PGM owns.
2288 */
2289 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2290 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2291 }
2292
2293 /*
2294 * Reset (zero) RAM pages.
2295 */
2296 rc = pgmR3PhysRamReset(pVM);
2297 if (RT_SUCCESS(rc))
2298 {
2299 /*
2300 * Reset (zero) shadow ROM pages.
2301 */
2302 rc = pgmR3PhysRomReset(pVM);
2303 }
2304
2305 pgmUnlock(pVM);
2306 AssertReleaseRC(rc);
2307}
2308
2309
2310#ifdef VBOX_STRICT
2311/**
2312 * VM state change callback for clearing fNoMorePhysWrites after
2313 * a snapshot has been created.
2314 */
2315static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2316{
2317 if ( enmState == VMSTATE_RUNNING
2318 || enmState == VMSTATE_RESUMING)
2319 pVM->pgm.s.fNoMorePhysWrites = false;
2320}
2321#endif
2322
2323
2324/**
2325 * Terminates the PGM.
2326 *
2327 * @returns VBox status code.
2328 * @param pVM Pointer to VM structure.
2329 */
2330VMMR3DECL(int) PGMR3Term(PVM pVM)
2331{
2332 /* Must free shared pages here. */
2333 pgmLock(pVM);
2334 pgmR3PhysRamTerm(pVM);
2335 pgmUnlock(pVM);
2336
2337 PGMDeregisterStringFormatTypes();
2338 return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2339}
2340
2341
2342/**
2343 * Terminates the per-VCPU PGM.
2344 *
2345 * Termination means cleaning up and freeing all resources,
2346 * the VM it self is at this point powered off or suspended.
2347 *
2348 * @returns VBox status code.
2349 * @param pVM The VM to operate on.
2350 */
2351VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2352{
2353 return 0;
2354}
2355
2356
2357/**
2358 * Show paging mode.
2359 *
2360 * @param pVM VM Handle.
2361 * @param pHlp The info helpers.
2362 * @param pszArgs "all" (default), "guest", "shadow" or "host".
2363 */
2364static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2365{
2366 /* digest argument. */
2367 bool fGuest, fShadow, fHost;
2368 if (pszArgs)
2369 pszArgs = RTStrStripL(pszArgs);
2370 if (!pszArgs || !*pszArgs || strstr(pszArgs, "all"))
2371 fShadow = fHost = fGuest = true;
2372 else
2373 {
2374 fShadow = fHost = fGuest = false;
2375 if (strstr(pszArgs, "guest"))
2376 fGuest = true;
2377 if (strstr(pszArgs, "shadow"))
2378 fShadow = true;
2379 if (strstr(pszArgs, "host"))
2380 fHost = true;
2381 }
2382
2383 /** @todo SMP support! */
2384 /* print info. */
2385 if (fGuest)
2386 pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2387 PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2388 pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2389 if (fShadow)
2390 pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2391 if (fHost)
2392 {
2393 const char *psz;
2394 switch (pVM->pgm.s.enmHostMode)
2395 {
2396 case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2397 case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2398 case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2399 case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2400 case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2401 case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2402 case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2403 case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2404 case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2405 case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2406 case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2407 default: psz = "unknown"; break;
2408 }
2409 pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2410 }
2411}
2412
2413
2414/**
2415 * Dump registered MMIO ranges to the log.
2416 *
2417 * @param pVM VM Handle.
2418 * @param pHlp The info helpers.
2419 * @param pszArgs Arguments, ignored.
2420 */
2421static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2422{
2423 NOREF(pszArgs);
2424 pHlp->pfnPrintf(pHlp,
2425 "RAM ranges (pVM=%p)\n"
2426 "%.*s %.*s\n",
2427 pVM,
2428 sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2429 sizeof(RTHCPTR) * 2, "pvHC ");
2430
2431 for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2432 pHlp->pfnPrintf(pHlp,
2433 "%RGp-%RGp %RHv %s\n",
2434 pCur->GCPhys,
2435 pCur->GCPhysLast,
2436 pCur->pvR3,
2437 pCur->pszDesc);
2438}
2439
2440/**
2441 * Dump the page directory to the log.
2442 *
2443 * @param pVM VM Handle.
2444 * @param pHlp The info helpers.
2445 * @param pszArgs Arguments, ignored.
2446 */
2447static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2448{
2449 /** @todo SMP support!! */
2450 PVMCPU pVCpu = &pVM->aCpus[0];
2451
2452/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2453 /* Big pages supported? */
2454 const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2455
2456 /* Global pages supported? */
2457 const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2458
2459 NOREF(pszArgs);
2460
2461 /*
2462 * Get page directory addresses.
2463 */
2464 PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2465 Assert(pPDSrc);
2466 Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2467
2468 /*
2469 * Iterate the page directory.
2470 */
2471 for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2472 {
2473 X86PDE PdeSrc = pPDSrc->a[iPD];
2474 if (PdeSrc.n.u1Present)
2475 {
2476 if (PdeSrc.b.u1Size && fPSE)
2477 pHlp->pfnPrintf(pHlp,
2478 "%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2479 iPD,
2480 pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2481 PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2482 else
2483 pHlp->pfnPrintf(pHlp,
2484 "%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2485 iPD,
2486 (RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2487 PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2488 }
2489 }
2490}
2491
2492
2493/**
2494 * Service a VMMCALLRING3_PGM_LOCK call.
2495 *
2496 * @returns VBox status code.
2497 * @param pVM The VM handle.
2498 */
2499VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2500{
2501 int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2502 AssertRC(rc);
2503 return rc;
2504}
2505
2506
2507/**
2508 * Converts a PGMMODE value to a PGM_TYPE_* \#define.
2509 *
2510 * @returns PGM_TYPE_*.
2511 * @param pgmMode The mode value to convert.
2512 */
2513DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2514{
2515 switch (pgmMode)
2516 {
2517 case PGMMODE_REAL: return PGM_TYPE_REAL;
2518 case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2519 case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2520 case PGMMODE_PAE:
2521 case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2522 case PGMMODE_AMD64:
2523 case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2524 case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2525 case PGMMODE_EPT: return PGM_TYPE_EPT;
2526 default:
2527 AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2528 }
2529}
2530
2531
2532/**
2533 * Gets the index into the paging mode data array of a SHW+GST mode.
2534 *
2535 * @returns PGM::paPagingData index.
2536 * @param uShwType The shadow paging mode type.
2537 * @param uGstType The guest paging mode type.
2538 */
2539DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2540{
2541 Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2542 Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2543 return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2544 + (uGstType - PGM_TYPE_REAL);
2545}
2546
2547
2548/**
2549 * Gets the index into the paging mode data array of a SHW+GST mode.
2550 *
2551 * @returns PGM::paPagingData index.
2552 * @param enmShw The shadow paging mode.
2553 * @param enmGst The guest paging mode.
2554 */
2555DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2556{
2557 Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2558 Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2559 return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2560}
2561
2562
2563/**
2564 * Calculates the max data index.
2565 * @returns The number of entries in the paging data array.
2566 */
2567DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2568{
2569 return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2570}
2571
2572
2573/**
2574 * Initializes the paging mode data kept in PGM::paModeData.
2575 *
2576 * @param pVM The VM handle.
2577 * @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2578 * This is used early in the init process to avoid trouble with PDM
2579 * not being initialized yet.
2580 */
2581static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2582{
2583 PPGMMODEDATA pModeData;
2584 int rc;
2585
2586 /*
2587 * Allocate the array on the first call.
2588 */
2589 if (!pVM->pgm.s.paModeData)
2590 {
2591 pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2592 AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2593 }
2594
2595 /*
2596 * Initialize the array entries.
2597 */
2598 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2599 pModeData->uShwType = PGM_TYPE_32BIT;
2600 pModeData->uGstType = PGM_TYPE_REAL;
2601 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2602 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2603 rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2604
2605 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2606 pModeData->uShwType = PGM_TYPE_32BIT;
2607 pModeData->uGstType = PGM_TYPE_PROT;
2608 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2609 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2610 rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2611
2612 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2613 pModeData->uShwType = PGM_TYPE_32BIT;
2614 pModeData->uGstType = PGM_TYPE_32BIT;
2615 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2616 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2617 rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2618
2619 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2620 pModeData->uShwType = PGM_TYPE_PAE;
2621 pModeData->uGstType = PGM_TYPE_REAL;
2622 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2623 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2624 rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2625
2626 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2627 pModeData->uShwType = PGM_TYPE_PAE;
2628 pModeData->uGstType = PGM_TYPE_PROT;
2629 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2630 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2631 rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2632
2633 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2634 pModeData->uShwType = PGM_TYPE_PAE;
2635 pModeData->uGstType = PGM_TYPE_32BIT;
2636 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2637 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2638 rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2639
2640 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2641 pModeData->uShwType = PGM_TYPE_PAE;
2642 pModeData->uGstType = PGM_TYPE_PAE;
2643 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2644 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2645 rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2646
2647#ifdef VBOX_WITH_64_BITS_GUESTS
2648 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2649 pModeData->uShwType = PGM_TYPE_AMD64;
2650 pModeData->uGstType = PGM_TYPE_AMD64;
2651 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2652 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2653 rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2654#endif
2655
2656 /* The nested paging mode. */
2657 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2658 pModeData->uShwType = PGM_TYPE_NESTED;
2659 pModeData->uGstType = PGM_TYPE_REAL;
2660 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2661 rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2662
2663 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2664 pModeData->uShwType = PGM_TYPE_NESTED;
2665 pModeData->uGstType = PGM_TYPE_PROT;
2666 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2667 rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2668
2669 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2670 pModeData->uShwType = PGM_TYPE_NESTED;
2671 pModeData->uGstType = PGM_TYPE_32BIT;
2672 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2673 rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2674
2675 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2676 pModeData->uShwType = PGM_TYPE_NESTED;
2677 pModeData->uGstType = PGM_TYPE_PAE;
2678 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2679 rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2680
2681#ifdef VBOX_WITH_64_BITS_GUESTS
2682 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2683 pModeData->uShwType = PGM_TYPE_NESTED;
2684 pModeData->uGstType = PGM_TYPE_AMD64;
2685 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2686 rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2687#endif
2688
2689 /* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2690 switch (pVM->pgm.s.enmHostMode)
2691 {
2692#if HC_ARCH_BITS == 32
2693 case SUPPAGINGMODE_32_BIT:
2694 case SUPPAGINGMODE_32_BIT_GLOBAL:
2695 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2696 {
2697 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2698 rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2699 }
2700# ifdef VBOX_WITH_64_BITS_GUESTS
2701 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2702 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703# endif
2704 break;
2705
2706 case SUPPAGINGMODE_PAE:
2707 case SUPPAGINGMODE_PAE_NX:
2708 case SUPPAGINGMODE_PAE_GLOBAL:
2709 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2710 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2711 {
2712 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2713 rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714 }
2715# ifdef VBOX_WITH_64_BITS_GUESTS
2716 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2717 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2718# endif
2719 break;
2720#endif /* HC_ARCH_BITS == 32 */
2721
2722#if HC_ARCH_BITS == 64 || defined(RT_OS_DARWIN)
2723 case SUPPAGINGMODE_AMD64:
2724 case SUPPAGINGMODE_AMD64_GLOBAL:
2725 case SUPPAGINGMODE_AMD64_NX:
2726 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2727# ifdef VBOX_WITH_64_BITS_GUESTS
2728 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2729# else
2730 for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2731# endif
2732 {
2733 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2734 rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735 }
2736 break;
2737#endif /* HC_ARCH_BITS == 64 || RT_OS_DARWIN */
2738
2739 default:
2740 AssertFailed();
2741 break;
2742 }
2743
2744 /* Extended paging (EPT) / Intel VT-x */
2745 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2746 pModeData->uShwType = PGM_TYPE_EPT;
2747 pModeData->uGstType = PGM_TYPE_REAL;
2748 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749 rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2750 rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751
2752 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2753 pModeData->uShwType = PGM_TYPE_EPT;
2754 pModeData->uGstType = PGM_TYPE_PROT;
2755 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756 rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757 rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758
2759 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2760 pModeData->uShwType = PGM_TYPE_EPT;
2761 pModeData->uGstType = PGM_TYPE_32BIT;
2762 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763 rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2764 rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765
2766 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2767 pModeData->uShwType = PGM_TYPE_EPT;
2768 pModeData->uGstType = PGM_TYPE_PAE;
2769 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2770 rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771 rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772
2773#ifdef VBOX_WITH_64_BITS_GUESTS
2774 pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2775 pModeData->uShwType = PGM_TYPE_EPT;
2776 pModeData->uGstType = PGM_TYPE_AMD64;
2777 rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2778 rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779 rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2780#endif
2781 return VINF_SUCCESS;
2782}
2783
2784
2785/**
2786 * Switch to different (or relocated in the relocate case) mode data.
2787 *
2788 * @param pVM The VM handle.
2789 * @param pVCpu The VMCPU to operate on.
2790 * @param enmShw The the shadow paging mode.
2791 * @param enmGst The the guest paging mode.
2792 */
2793static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2794{
2795 PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2796
2797 Assert(pModeData->uGstType == pgmModeToType(enmGst));
2798 Assert(pModeData->uShwType == pgmModeToType(enmShw));
2799
2800 /* shadow */
2801 pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2802 pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2803 pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2804 Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2805 pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2806
2807 pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2808 pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2809
2810 pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2811 pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2812
2813
2814 /* guest */
2815 pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2816 pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2817 pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2818 Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2819 pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2820 pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2821 pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2822 pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2823 pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2824 pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2825 pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2826 pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2827
2828 /* both */
2829 pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2830 pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2831 pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2832 Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2833 pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2834 pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2835 pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2836#ifdef VBOX_STRICT
2837 pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2838#endif
2839 pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2840 pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2841
2842 pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2843 pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2844 pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2845 pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2846 pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2847 pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2848#ifdef VBOX_STRICT
2849 pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2850#endif
2851 pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2852 pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2853
2854 pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2855 pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2856 pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2857 pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2858 pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2859 pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2860#ifdef VBOX_STRICT
2861 pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2862#endif
2863 pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2864 pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
2865}
2866
2867
2868/**
2869 * Calculates the shadow paging mode.
2870 *
2871 * @returns The shadow paging mode.
2872 * @param pVM VM handle.
2873 * @param enmGuestMode The guest mode.
2874 * @param enmHostMode The host mode.
2875 * @param enmShadowMode The current shadow mode.
2876 * @param penmSwitcher Where to store the switcher to use.
2877 * VMMSWITCHER_INVALID means no change.
2878 */
2879static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2880{
2881 VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2882 switch (enmGuestMode)
2883 {
2884 /*
2885 * When switching to real or protected mode we don't change
2886 * anything since it's likely that we'll switch back pretty soon.
2887 *
2888 * During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2889 * and is supposed to determine which shadow paging and switcher to
2890 * use during init.
2891 */
2892 case PGMMODE_REAL:
2893 case PGMMODE_PROTECTED:
2894 if ( enmShadowMode != PGMMODE_INVALID
2895 && !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2896 break; /* (no change) */
2897
2898 switch (enmHostMode)
2899 {
2900 case SUPPAGINGMODE_32_BIT:
2901 case SUPPAGINGMODE_32_BIT_GLOBAL:
2902 enmShadowMode = PGMMODE_32_BIT;
2903 enmSwitcher = VMMSWITCHER_32_TO_32;
2904 break;
2905
2906 case SUPPAGINGMODE_PAE:
2907 case SUPPAGINGMODE_PAE_NX:
2908 case SUPPAGINGMODE_PAE_GLOBAL:
2909 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2910 enmShadowMode = PGMMODE_PAE;
2911 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2912#ifdef DEBUG_bird
2913 if (RTEnvExist("VBOX_32BIT"))
2914 {
2915 enmShadowMode = PGMMODE_32_BIT;
2916 enmSwitcher = VMMSWITCHER_PAE_TO_32;
2917 }
2918#endif
2919 break;
2920
2921 case SUPPAGINGMODE_AMD64:
2922 case SUPPAGINGMODE_AMD64_GLOBAL:
2923 case SUPPAGINGMODE_AMD64_NX:
2924 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2925 enmShadowMode = PGMMODE_PAE;
2926 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2927#ifdef DEBUG_bird
2928 if (RTEnvExist("VBOX_32BIT"))
2929 {
2930 enmShadowMode = PGMMODE_32_BIT;
2931 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2932 }
2933#endif
2934 break;
2935
2936 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2937 }
2938 break;
2939
2940 case PGMMODE_32_BIT:
2941 switch (enmHostMode)
2942 {
2943 case SUPPAGINGMODE_32_BIT:
2944 case SUPPAGINGMODE_32_BIT_GLOBAL:
2945 enmShadowMode = PGMMODE_32_BIT;
2946 enmSwitcher = VMMSWITCHER_32_TO_32;
2947 break;
2948
2949 case SUPPAGINGMODE_PAE:
2950 case SUPPAGINGMODE_PAE_NX:
2951 case SUPPAGINGMODE_PAE_GLOBAL:
2952 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2953 enmShadowMode = PGMMODE_PAE;
2954 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2955#ifdef DEBUG_bird
2956 if (RTEnvExist("VBOX_32BIT"))
2957 {
2958 enmShadowMode = PGMMODE_32_BIT;
2959 enmSwitcher = VMMSWITCHER_PAE_TO_32;
2960 }
2961#endif
2962 break;
2963
2964 case SUPPAGINGMODE_AMD64:
2965 case SUPPAGINGMODE_AMD64_GLOBAL:
2966 case SUPPAGINGMODE_AMD64_NX:
2967 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2968 enmShadowMode = PGMMODE_PAE;
2969 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2970#ifdef DEBUG_bird
2971 if (RTEnvExist("VBOX_32BIT"))
2972 {
2973 enmShadowMode = PGMMODE_32_BIT;
2974 enmSwitcher = VMMSWITCHER_AMD64_TO_32;
2975 }
2976#endif
2977 break;
2978
2979 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2980 }
2981 break;
2982
2983 case PGMMODE_PAE:
2984 case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2985 switch (enmHostMode)
2986 {
2987 case SUPPAGINGMODE_32_BIT:
2988 case SUPPAGINGMODE_32_BIT_GLOBAL:
2989 enmShadowMode = PGMMODE_PAE;
2990 enmSwitcher = VMMSWITCHER_32_TO_PAE;
2991 break;
2992
2993 case SUPPAGINGMODE_PAE:
2994 case SUPPAGINGMODE_PAE_NX:
2995 case SUPPAGINGMODE_PAE_GLOBAL:
2996 case SUPPAGINGMODE_PAE_GLOBAL_NX:
2997 enmShadowMode = PGMMODE_PAE;
2998 enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2999 break;
3000
3001 case SUPPAGINGMODE_AMD64:
3002 case SUPPAGINGMODE_AMD64_GLOBAL:
3003 case SUPPAGINGMODE_AMD64_NX:
3004 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3005 enmShadowMode = PGMMODE_PAE;
3006 enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3007 break;
3008
3009 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3010 }
3011 break;
3012
3013 case PGMMODE_AMD64:
3014 case PGMMODE_AMD64_NX:
3015 switch (enmHostMode)
3016 {
3017 case SUPPAGINGMODE_32_BIT:
3018 case SUPPAGINGMODE_32_BIT_GLOBAL:
3019 enmShadowMode = PGMMODE_AMD64;
3020 enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3021 break;
3022
3023 case SUPPAGINGMODE_PAE:
3024 case SUPPAGINGMODE_PAE_NX:
3025 case SUPPAGINGMODE_PAE_GLOBAL:
3026 case SUPPAGINGMODE_PAE_GLOBAL_NX:
3027 enmShadowMode = PGMMODE_AMD64;
3028 enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3029 break;
3030
3031 case SUPPAGINGMODE_AMD64:
3032 case SUPPAGINGMODE_AMD64_GLOBAL:
3033 case SUPPAGINGMODE_AMD64_NX:
3034 case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3035 enmShadowMode = PGMMODE_AMD64;
3036 enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3037 break;
3038
3039 default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3040 }
3041 break;
3042
3043
3044 default:
3045 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3046 *penmSwitcher = VMMSWITCHER_INVALID;
3047 return PGMMODE_INVALID;
3048 }
3049 /* Override the shadow mode is nested paging is active. */
3050 if (HWACCMIsNestedPagingActive(pVM))
3051 enmShadowMode = HWACCMGetShwPagingMode(pVM);
3052
3053 *penmSwitcher = enmSwitcher;
3054 return enmShadowMode;
3055}
3056
3057
3058/**
3059 * Performs the actual mode change.
3060 * This is called by PGMChangeMode and pgmR3InitPaging().
3061 *
3062 * @returns VBox status code. May suspend or power off the VM on error, but this
3063 * will trigger using FFs and not status codes.
3064 *
3065 * @param pVM VM handle.
3066 * @param pVCpu The VMCPU to operate on.
3067 * @param enmGuestMode The new guest mode. This is assumed to be different from
3068 * the current mode.
3069 */
3070VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3071{
3072 bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3073 bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3074
3075 Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3076 STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3077
3078 /*
3079 * Calc the shadow mode and switcher.
3080 */
3081 VMMSWITCHER enmSwitcher;
3082 PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3083
3084#ifdef VBOX_WITH_RAW_MODE
3085 if (enmSwitcher != VMMSWITCHER_INVALID)
3086 {
3087 /*
3088 * Select new switcher.
3089 */
3090 int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3091 if (RT_FAILURE(rc))
3092 {
3093 AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3094 return rc;
3095 }
3096 }
3097#endif
3098
3099 /*
3100 * Exit old mode(s).
3101 */
3102#if HC_ARCH_BITS == 32
3103 /* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3104 const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3105 && enmShadowMode == PGMMODE_NESTED);
3106#else
3107 const bool fForceShwEnterExit = false;
3108#endif
3109 /* shadow */
3110 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3111 || fForceShwEnterExit)
3112 {
3113 LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3114 if (PGM_SHW_PFN(Exit, pVCpu))
3115 {
3116 int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3117 if (RT_FAILURE(rc))
3118 {
3119 AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3120 return rc;
3121 }
3122 }
3123
3124 }
3125 else
3126 LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3127
3128 /* guest */
3129 if (PGM_GST_PFN(Exit, pVCpu))
3130 {
3131 int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3132 if (RT_FAILURE(rc))
3133 {
3134 AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3135 return rc;
3136 }
3137 }
3138
3139 /*
3140 * Load new paging mode data.
3141 */
3142 pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3143
3144 /*
3145 * Enter new shadow mode (if changed).
3146 */
3147 if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3148 || fForceShwEnterExit)
3149 {
3150 int rc;
3151 pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3152 switch (enmShadowMode)
3153 {
3154 case PGMMODE_32_BIT:
3155 rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3156 break;
3157 case PGMMODE_PAE:
3158 case PGMMODE_PAE_NX:
3159 rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3160 break;
3161 case PGMMODE_AMD64:
3162 case PGMMODE_AMD64_NX:
3163 rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3164 break;
3165 case PGMMODE_NESTED:
3166 rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3167 break;
3168 case PGMMODE_EPT:
3169 rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3170 break;
3171 case PGMMODE_REAL:
3172 case PGMMODE_PROTECTED:
3173 default:
3174 AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3175 return VERR_INTERNAL_ERROR;
3176 }
3177 if (RT_FAILURE(rc))
3178 {
3179 AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3180 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3181 return rc;
3182 }
3183 }
3184
3185 /*
3186 * Always flag the necessary updates
3187 */
3188 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3189
3190 /*
3191 * Enter the new guest and shadow+guest modes.
3192 */
3193 int rc = -1;
3194 int rc2 = -1;
3195 RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3196 pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3197 switch (enmGuestMode)
3198 {
3199 case PGMMODE_REAL:
3200 rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3201 switch (pVCpu->pgm.s.enmShadowMode)
3202 {
3203 case PGMMODE_32_BIT:
3204 rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3205 break;
3206 case PGMMODE_PAE:
3207 case PGMMODE_PAE_NX:
3208 rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3209 break;
3210 case PGMMODE_NESTED:
3211 rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3212 break;
3213 case PGMMODE_EPT:
3214 rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3215 break;
3216 case PGMMODE_AMD64:
3217 case PGMMODE_AMD64_NX:
3218 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3219 default: AssertFailed(); break;
3220 }
3221 break;
3222
3223 case PGMMODE_PROTECTED:
3224 rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3225 switch (pVCpu->pgm.s.enmShadowMode)
3226 {
3227 case PGMMODE_32_BIT:
3228 rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3229 break;
3230 case PGMMODE_PAE:
3231 case PGMMODE_PAE_NX:
3232 rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3233 break;
3234 case PGMMODE_NESTED:
3235 rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3236 break;
3237 case PGMMODE_EPT:
3238 rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3239 break;
3240 case PGMMODE_AMD64:
3241 case PGMMODE_AMD64_NX:
3242 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3243 default: AssertFailed(); break;
3244 }
3245 break;
3246
3247 case PGMMODE_32_BIT:
3248 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3249 rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3250 switch (pVCpu->pgm.s.enmShadowMode)
3251 {
3252 case PGMMODE_32_BIT:
3253 rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3254 break;
3255 case PGMMODE_PAE:
3256 case PGMMODE_PAE_NX:
3257 rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3258 break;
3259 case PGMMODE_NESTED:
3260 rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3261 break;
3262 case PGMMODE_EPT:
3263 rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3264 break;
3265 case PGMMODE_AMD64:
3266 case PGMMODE_AMD64_NX:
3267 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3268 default: AssertFailed(); break;
3269 }
3270 break;
3271
3272 case PGMMODE_PAE_NX:
3273 case PGMMODE_PAE:
3274 {
3275 uint32_t u32Dummy, u32Features;
3276
3277 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3278 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3279 return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3280 N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3281
3282 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3283 rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3284 switch (pVCpu->pgm.s.enmShadowMode)
3285 {
3286 case PGMMODE_PAE:
3287 case PGMMODE_PAE_NX:
3288 rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3289 break;
3290 case PGMMODE_NESTED:
3291 rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3292 break;
3293 case PGMMODE_EPT:
3294 rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3295 break;
3296 case PGMMODE_32_BIT:
3297 case PGMMODE_AMD64:
3298 case PGMMODE_AMD64_NX:
3299 AssertMsgFailed(("Should use PAE shadow mode!\n"));
3300 default: AssertFailed(); break;
3301 }
3302 break;
3303 }
3304
3305#ifdef VBOX_WITH_64_BITS_GUESTS
3306 case PGMMODE_AMD64_NX:
3307 case PGMMODE_AMD64:
3308 GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3309 rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3310 switch (pVCpu->pgm.s.enmShadowMode)
3311 {
3312 case PGMMODE_AMD64:
3313 case PGMMODE_AMD64_NX:
3314 rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3315 break;
3316 case PGMMODE_NESTED:
3317 rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3318 break;
3319 case PGMMODE_EPT:
3320 rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3321 break;
3322 case PGMMODE_32_BIT:
3323 case PGMMODE_PAE:
3324 case PGMMODE_PAE_NX:
3325 AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3326 default: AssertFailed(); break;
3327 }
3328 break;
3329#endif
3330
3331 default:
3332 AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3333 rc = VERR_NOT_IMPLEMENTED;
3334 break;
3335 }
3336
3337 /* status codes. */
3338 AssertRC(rc);
3339 AssertRC(rc2);
3340 if (RT_SUCCESS(rc))
3341 {
3342 rc = rc2;
3343 if (RT_SUCCESS(rc)) /* no informational status codes. */
3344 rc = VINF_SUCCESS;
3345 }
3346
3347 /* Notify HWACCM as well. */
3348 HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3349 return rc;
3350}
3351
3352/**
3353 * Release the pgm lock if owned by the current VCPU
3354 *
3355 * @param pVM The VM to operate on.
3356 */
3357VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
3358{
3359 while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
3360 PDMCritSectLeave(&pVM->pgm.s.CritSect);
3361}
3362
3363/**
3364 * Called by pgmPoolFlushAllInt prior to flushing the pool.
3365 *
3366 * @returns VBox status code, fully asserted.
3367 * @param pVM The VM handle.
3368 * @param pVCpu The VMCPU to operate on.
3369 */
3370int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3371{
3372 /* Unmap the old CR3 value before flushing everything. */
3373 int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3374 AssertRC(rc);
3375
3376 /* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3377 rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3378 AssertRC(rc);
3379 Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3380 return rc;
3381}
3382
3383
3384/**
3385 * Called by pgmPoolFlushAllInt after flushing the pool.
3386 *
3387 * @returns VBox status code, fully asserted.
3388 * @param pVM The VM handle.
3389 * @param pVCpu The VMCPU to operate on.
3390 */
3391int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3392{
3393 pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3394 int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3395 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3396 AssertRCReturn(rc, rc);
3397 AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3398
3399 Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3400 AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3401 || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3402 ("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3403 return rc;
3404}
3405
3406
3407/**
3408 * Dumps a PAE shadow page table.
3409 *
3410 * @returns VBox status code (VINF_SUCCESS).
3411 * @param pVM The VM handle.
3412 * @param pPT Pointer to the page table.
3413 * @param u64Address The virtual address of the page table starts.
3414 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3415 * @param cMaxDepth The maxium depth.
3416 * @param pHlp Pointer to the output functions.
3417 */
3418static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3419{
3420 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3421 {
3422 X86PTEPAE Pte = pPT->a[i];
3423 if (Pte.n.u1Present)
3424 {
3425 pHlp->pfnPrintf(pHlp,
3426 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3427 ? "%016llx 3 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3428 : "%08llx 2 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3429 u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3430 Pte.n.u1Write ? 'W' : 'R',
3431 Pte.n.u1User ? 'U' : 'S',
3432 Pte.n.u1Accessed ? 'A' : '-',
3433 Pte.n.u1Dirty ? 'D' : '-',
3434 Pte.n.u1Global ? 'G' : '-',
3435 Pte.n.u1WriteThru ? "WT" : "--",
3436 Pte.n.u1CacheDisable? "CD" : "--",
3437 Pte.n.u1PAT ? "AT" : "--",
3438 Pte.n.u1NoExecute ? "NX" : "--",
3439 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3440 Pte.u & RT_BIT(10) ? '1' : '0',
3441 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3442 Pte.u & X86_PTE_PAE_PG_MASK);
3443 }
3444 }
3445 return VINF_SUCCESS;
3446}
3447
3448
3449/**
3450 * Dumps a PAE shadow page directory table.
3451 *
3452 * @returns VBox status code (VINF_SUCCESS).
3453 * @param pVM The VM handle.
3454 * @param HCPhys The physical address of the page directory table.
3455 * @param u64Address The virtual address of the page table starts.
3456 * @param cr4 The CR4, PSE is currently used.
3457 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3458 * @param cMaxDepth The maxium depth.
3459 * @param pHlp Pointer to the output functions.
3460 */
3461static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3462{
3463 PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3464 if (!pPD)
3465 {
3466 pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3467 fLongMode ? 16 : 8, u64Address, HCPhys);
3468 return VERR_INVALID_PARAMETER;
3469 }
3470 const bool fBigPagesSupported = fLongMode || !!(cr4 & X86_CR4_PSE);
3471
3472 int rc = VINF_SUCCESS;
3473 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3474 {
3475 X86PDEPAE Pde = pPD->a[i];
3476 if (Pde.n.u1Present)
3477 {
3478 if (fBigPagesSupported && Pde.b.u1Size)
3479 pHlp->pfnPrintf(pHlp,
3480 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3481 ? "%016llx 2 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3482 : "%08llx 1 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3483 u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3484 Pde.b.u1Write ? 'W' : 'R',
3485 Pde.b.u1User ? 'U' : 'S',
3486 Pde.b.u1Accessed ? 'A' : '-',
3487 Pde.b.u1Dirty ? 'D' : '-',
3488 Pde.b.u1Global ? 'G' : '-',
3489 Pde.b.u1WriteThru ? "WT" : "--",
3490 Pde.b.u1CacheDisable? "CD" : "--",
3491 Pde.b.u1PAT ? "AT" : "--",
3492 Pde.b.u1NoExecute ? "NX" : "--",
3493 Pde.u & RT_BIT_64(9) ? '1' : '0',
3494 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3495 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3496 Pde.u & X86_PDE_PAE_PG_MASK);
3497 else
3498 {
3499 pHlp->pfnPrintf(pHlp,
3500 fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
3501 ? "%016llx 2 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3502 : "%08llx 1 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3503 u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3504 Pde.n.u1Write ? 'W' : 'R',
3505 Pde.n.u1User ? 'U' : 'S',
3506 Pde.n.u1Accessed ? 'A' : '-',
3507 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3508 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3509 Pde.n.u1WriteThru ? "WT" : "--",
3510 Pde.n.u1CacheDisable? "CD" : "--",
3511 Pde.n.u1NoExecute ? "NX" : "--",
3512 Pde.u & RT_BIT_64(9) ? '1' : '0',
3513 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3514 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3515 Pde.u & X86_PDE_PAE_PG_MASK);
3516 if (cMaxDepth >= 1)
3517 {
3518 /** @todo what about using the page pool for mapping PTs? */
3519 uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3520 RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3521 PX86PTPAE pPT = NULL;
3522 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3523 pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3524 else
3525 {
3526 for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3527 {
3528 uint64_t off = u64AddressPT - pMap->GCPtr;
3529 if (off < pMap->cb)
3530 {
3531 const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3532 const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3533 if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3534 pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3535 fLongMode ? 16 : 8, u64AddressPT, iPDE,
3536 iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3537 pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3538 }
3539 }
3540 }
3541 int rc2 = VERR_INVALID_PARAMETER;
3542 if (pPT)
3543 rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3544 else
3545 pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3546 fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3547 if (rc2 < rc && RT_SUCCESS(rc))
3548 rc = rc2;
3549 }
3550 }
3551 }
3552 }
3553 return rc;
3554}
3555
3556
3557/**
3558 * Dumps a PAE shadow page directory pointer table.
3559 *
3560 * @returns VBox status code (VINF_SUCCESS).
3561 * @param pVM The VM handle.
3562 * @param HCPhys The physical address of the page directory pointer table.
3563 * @param u64Address The virtual address of the page table starts.
3564 * @param cr4 The CR4, PSE is currently used.
3565 * @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3566 * @param cMaxDepth The maxium depth.
3567 * @param pHlp Pointer to the output functions.
3568 */
3569static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3570{
3571 PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3572 if (!pPDPT)
3573 {
3574 pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3575 fLongMode ? 16 : 8, u64Address, HCPhys);
3576 return VERR_INVALID_PARAMETER;
3577 }
3578
3579 int rc = VINF_SUCCESS;
3580 const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3581 for (unsigned i = 0; i < c; i++)
3582 {
3583 X86PDPE Pdpe = pPDPT->a[i];
3584 if (Pdpe.n.u1Present)
3585 {
3586 if (fLongMode)
3587 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a p ? */
3588 "%016llx 1 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3589 u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3590 Pdpe.lm.u1Write ? 'W' : 'R',
3591 Pdpe.lm.u1User ? 'U' : 'S',
3592 Pdpe.lm.u1Accessed ? 'A' : '-',
3593 Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3594 Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3595 Pdpe.lm.u1WriteThru ? "WT" : "--",
3596 Pdpe.lm.u1CacheDisable? "CD" : "--",
3597 Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3598 Pdpe.lm.u1NoExecute ? "NX" : "--",
3599 Pdpe.u & RT_BIT(9) ? '1' : '0',
3600 Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3601 Pdpe.u & RT_BIT(11) ? '1' : '0',
3602 Pdpe.u & X86_PDPE_PG_MASK);
3603 else
3604 pHlp->pfnPrintf(pHlp, /*P G WT CD AT NX 4M a p ? */
3605 "%08x 0 | P %c %s %s %s %s .. %c%c%c %016llx\n",
3606 i << X86_PDPT_SHIFT,
3607 Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3608 Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3609 Pdpe.n.u1WriteThru ? "WT" : "--",
3610 Pdpe.n.u1CacheDisable? "CD" : "--",
3611 Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3612 Pdpe.u & RT_BIT(9) ? '1' : '0',
3613 Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3614 Pdpe.u & RT_BIT(11) ? '1' : '0',
3615 Pdpe.u & X86_PDPE_PG_MASK);
3616 if (cMaxDepth >= 1)
3617 {
3618 int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3619 cr4, fLongMode, cMaxDepth - 1, pHlp);
3620 if (rc2 < rc && RT_SUCCESS(rc))
3621 rc = rc2;
3622 }
3623 }
3624 }
3625 return rc;
3626}
3627
3628
3629/**
3630 * Dumps a 32-bit shadow page table.
3631 *
3632 * @returns VBox status code (VINF_SUCCESS).
3633 * @param pVM The VM handle.
3634 * @param HCPhys The physical address of the table.
3635 * @param cr4 The CR4, PSE is currently used.
3636 * @param cMaxDepth The maxium depth.
3637 * @param pHlp Pointer to the output functions.
3638 */
3639static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3640{
3641 PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3642 if (!pPML4)
3643 {
3644 pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3645 return VERR_INVALID_PARAMETER;
3646 }
3647
3648 int rc = VINF_SUCCESS;
3649 for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3650 {
3651 X86PML4E Pml4e = pPML4->a[i];
3652 if (Pml4e.n.u1Present)
3653 {
3654 uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) | (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3655 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a p ? */
3656 "%016llx 0 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3657 u64Address,
3658 Pml4e.n.u1Write ? 'W' : 'R',
3659 Pml4e.n.u1User ? 'U' : 'S',
3660 Pml4e.n.u1Accessed ? 'A' : '-',
3661 Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3662 Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3663 Pml4e.n.u1WriteThru ? "WT" : "--",
3664 Pml4e.n.u1CacheDisable? "CD" : "--",
3665 Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3666 Pml4e.n.u1NoExecute ? "NX" : "--",
3667 Pml4e.u & RT_BIT(9) ? '1' : '0',
3668 Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3669 Pml4e.u & RT_BIT(11) ? '1' : '0',
3670 Pml4e.u & X86_PML4E_PG_MASK);
3671
3672 if (cMaxDepth >= 1)
3673 {
3674 int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3675 if (rc2 < rc && RT_SUCCESS(rc))
3676 rc = rc2;
3677 }
3678 }
3679 }
3680 return rc;
3681}
3682
3683
3684/**
3685 * Dumps a 32-bit shadow page table.
3686 *
3687 * @returns VBox status code (VINF_SUCCESS).
3688 * @param pVM The VM handle.
3689 * @param pPT Pointer to the page table.
3690 * @param u32Address The virtual address this table starts at.
3691 * @param pHlp Pointer to the output functions.
3692 */
3693int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3694{
3695 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3696 {
3697 X86PTE Pte = pPT->a[i];
3698 if (Pte.n.u1Present)
3699 {
3700 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3701 "%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3702 u32Address + (i << X86_PT_SHIFT),
3703 Pte.n.u1Write ? 'W' : 'R',
3704 Pte.n.u1User ? 'U' : 'S',
3705 Pte.n.u1Accessed ? 'A' : '-',
3706 Pte.n.u1Dirty ? 'D' : '-',
3707 Pte.n.u1Global ? 'G' : '-',
3708 Pte.n.u1WriteThru ? "WT" : "--",
3709 Pte.n.u1CacheDisable? "CD" : "--",
3710 Pte.n.u1PAT ? "AT" : "--",
3711 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3712 Pte.u & RT_BIT(10) ? '1' : '0',
3713 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3714 Pte.u & X86_PDE_PG_MASK);
3715 }
3716 }
3717 return VINF_SUCCESS;
3718}
3719
3720
3721/**
3722 * Dumps a 32-bit shadow page directory and page tables.
3723 *
3724 * @returns VBox status code (VINF_SUCCESS).
3725 * @param pVM The VM handle.
3726 * @param cr3 The root of the hierarchy.
3727 * @param cr4 The CR4, PSE is currently used.
3728 * @param cMaxDepth How deep into the hierarchy the dumper should go.
3729 * @param pHlp Pointer to the output functions.
3730 */
3731int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3732{
3733 PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3734 if (!pPD)
3735 {
3736 pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3737 return VERR_INVALID_PARAMETER;
3738 }
3739
3740 int rc = VINF_SUCCESS;
3741 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3742 {
3743 X86PDE Pde = pPD->a[i];
3744 if (Pde.n.u1Present)
3745 {
3746 const uint32_t u32Address = i << X86_PD_SHIFT;
3747 if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3748 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3749 "%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3750 u32Address,
3751 Pde.b.u1Write ? 'W' : 'R',
3752 Pde.b.u1User ? 'U' : 'S',
3753 Pde.b.u1Accessed ? 'A' : '-',
3754 Pde.b.u1Dirty ? 'D' : '-',
3755 Pde.b.u1Global ? 'G' : '-',
3756 Pde.b.u1WriteThru ? "WT" : "--",
3757 Pde.b.u1CacheDisable? "CD" : "--",
3758 Pde.b.u1PAT ? "AT" : "--",
3759 Pde.u & RT_BIT_64(9) ? '1' : '0',
3760 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3761 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3762 Pde.u & X86_PDE4M_PG_MASK);
3763 else
3764 {
3765 pHlp->pfnPrintf(pHlp, /*P R S A D G WT CD AT NX 4M a m d */
3766 "%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3767 u32Address,
3768 Pde.n.u1Write ? 'W' : 'R',
3769 Pde.n.u1User ? 'U' : 'S',
3770 Pde.n.u1Accessed ? 'A' : '-',
3771 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3772 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3773 Pde.n.u1WriteThru ? "WT" : "--",
3774 Pde.n.u1CacheDisable? "CD" : "--",
3775 Pde.u & RT_BIT_64(9) ? '1' : '0',
3776 Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3777 Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3778 Pde.u & X86_PDE_PG_MASK);
3779 if (cMaxDepth >= 1)
3780 {
3781 /** @todo what about using the page pool for mapping PTs? */
3782 RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3783 PX86PT pPT = NULL;
3784 if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3785 pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3786 else
3787 {
3788 for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3789 if (u32Address - pMap->GCPtr < pMap->cb)
3790 {
3791 int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3792 if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3793 pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3794 u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3795 pPT = pMap->aPTs[iPDE].pPTR3;
3796 }
3797 }
3798 int rc2 = VERR_INVALID_PARAMETER;
3799 if (pPT)
3800 rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3801 else
3802 pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3803 if (rc2 < rc && RT_SUCCESS(rc))
3804 rc = rc2;
3805 }
3806 }
3807 }
3808 }
3809
3810 return rc;
3811}
3812
3813
3814/**
3815 * Dumps a 32-bit shadow page table.
3816 *
3817 * @returns VBox status code (VINF_SUCCESS).
3818 * @param pVM The VM handle.
3819 * @param pPT Pointer to the page table.
3820 * @param u32Address The virtual address this table starts at.
3821 * @param PhysSearch Address to search for.
3822 */
3823int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3824{
3825 for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3826 {
3827 X86PTE Pte = pPT->a[i];
3828 if (Pte.n.u1Present)
3829 {
3830 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3831 "%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3832 u32Address + (i << X86_PT_SHIFT),
3833 Pte.n.u1Write ? 'W' : 'R',
3834 Pte.n.u1User ? 'U' : 'S',
3835 Pte.n.u1Accessed ? 'A' : '-',
3836 Pte.n.u1Dirty ? 'D' : '-',
3837 Pte.n.u1Global ? 'G' : '-',
3838 Pte.n.u1WriteThru ? "WT" : "--",
3839 Pte.n.u1CacheDisable? "CD" : "--",
3840 Pte.n.u1PAT ? "AT" : "--",
3841 Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3842 Pte.u & RT_BIT(10) ? '1' : '0',
3843 Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3844 Pte.u & X86_PDE_PG_MASK));
3845
3846 if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3847 {
3848 uint64_t fPageShw = 0;
3849 RTHCPHYS pPhysHC = 0;
3850
3851 /** @todo SMP support!! */
3852 PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3853 Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3854 }
3855 }
3856 }
3857 return VINF_SUCCESS;
3858}
3859
3860
3861/**
3862 * Dumps a 32-bit guest page directory and page tables.
3863 *
3864 * @returns VBox status code (VINF_SUCCESS).
3865 * @param pVM The VM handle.
3866 * @param cr3 The root of the hierarchy.
3867 * @param cr4 The CR4, PSE is currently used.
3868 * @param PhysSearch Address to search for.
3869 */
3870VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3871{
3872 bool fLongMode = false;
3873 const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3874 PX86PD pPD = 0;
3875
3876 int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3877 if (RT_FAILURE(rc) || !pPD)
3878 {
3879 Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3880 return VERR_INVALID_PARAMETER;
3881 }
3882
3883 Log(("cr3=%08x cr4=%08x%s\n"
3884 "%-*s P - Present\n"
3885 "%-*s | R/W - Read (0) / Write (1)\n"
3886 "%-*s | | U/S - User (1) / Supervisor (0)\n"
3887 "%-*s | | | A - Accessed\n"
3888 "%-*s | | | | D - Dirty\n"
3889 "%-*s | | | | | G - Global\n"
3890 "%-*s | | | | | | WT - Write thru\n"
3891 "%-*s | | | | | | | CD - Cache disable\n"
3892 "%-*s | | | | | | | | AT - Attribute table (PAT)\n"
3893 "%-*s | | | | | | | | | NX - No execute (K8)\n"
3894 "%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
3895 "%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
3896 "%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
3897 "%-*s Level | | | | | | | | | | | | Page\n"
3898 /* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3899 - W U - - - -- -- -- -- -- 010 */
3900 , cr3, cr4, fLongMode ? " Long Mode" : "",
3901 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3902 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3903
3904 for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3905 {
3906 X86PDE Pde = pPD->a[i];
3907 if (Pde.n.u1Present)
3908 {
3909 const uint32_t u32Address = i << X86_PD_SHIFT;
3910
3911 if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3912 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3913 "%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3914 u32Address,
3915 Pde.b.u1Write ? 'W' : 'R',
3916 Pde.b.u1User ? 'U' : 'S',
3917 Pde.b.u1Accessed ? 'A' : '-',
3918 Pde.b.u1Dirty ? 'D' : '-',
3919 Pde.b.u1Global ? 'G' : '-',
3920 Pde.b.u1WriteThru ? "WT" : "--",
3921 Pde.b.u1CacheDisable? "CD" : "--",
3922 Pde.b.u1PAT ? "AT" : "--",
3923 Pde.u & RT_BIT(9) ? '1' : '0',
3924 Pde.u & RT_BIT(10) ? '1' : '0',
3925 Pde.u & RT_BIT(11) ? '1' : '0',
3926 pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3927 /** @todo PhysSearch */
3928 else
3929 {
3930 Log(( /*P R S A D G WT CD AT NX 4M a m d */
3931 "%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3932 u32Address,
3933 Pde.n.u1Write ? 'W' : 'R',
3934 Pde.n.u1User ? 'U' : 'S',
3935 Pde.n.u1Accessed ? 'A' : '-',
3936 Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3937 Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3938 Pde.n.u1WriteThru ? "WT" : "--",
3939 Pde.n.u1CacheDisable? "CD" : "--",
3940 Pde.u & RT_BIT(9) ? '1' : '0',
3941 Pde.u & RT_BIT(10) ? '1' : '0',
3942 Pde.u & RT_BIT(11) ? '1' : '0',
3943 Pde.u & X86_PDE_PG_MASK));
3944 ////if (cMaxDepth >= 1)
3945 {
3946 /** @todo what about using the page pool for mapping PTs? */
3947 RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3948 PX86PT pPT = NULL;
3949
3950 rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3951
3952 int rc2 = VERR_INVALID_PARAMETER;
3953 if (pPT)
3954 rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3955 else
3956 Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3957 if (rc2 < rc && RT_SUCCESS(rc))
3958 rc = rc2;
3959 }
3960 }
3961 }
3962 }
3963
3964 return rc;
3965}
3966
3967
3968/**
3969 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3970 *
3971 * @returns VBox status code (VINF_SUCCESS).
3972 * @param pVM The VM handle.
3973 * @param cr3 The root of the hierarchy.
3974 * @param cr4 The cr4, only PAE and PSE is currently used.
3975 * @param fLongMode Set if long mode, false if not long mode.
3976 * @param cMaxDepth Number of levels to dump.
3977 * @param pHlp Pointer to the output functions.
3978 */
3979VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3980{
3981 if (!pHlp)
3982 pHlp = DBGFR3InfoLogHlp();
3983 if (!cMaxDepth)
3984 return VINF_SUCCESS;
3985 const unsigned cch = fLongMode ? 16 : 8;
3986 pHlp->pfnPrintf(pHlp,
3987 "cr3=%08x cr4=%08x%s\n"
3988 "%-*s P - Present\n"
3989 "%-*s | R/W - Read (0) / Write (1)\n"
3990 "%-*s | | U/S - User (1) / Supervisor (0)\n"
3991 "%-*s | | | A - Accessed\n"
3992 "%-*s | | | | D - Dirty\n"
3993 "%-*s | | | | | G - Global\n"
3994 "%-*s | | | | | | WT - Write thru\n"
3995 "%-*s | | | | | | | CD - Cache disable\n"
3996 "%-*s | | | | | | | | AT - Attribute table (PAT)\n"
3997 "%-*s | | | | | | | | | NX - No execute (K8)\n"
3998 "%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
3999 "%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
4000 "%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
4001 "%-*s Level | | | | | | | | | | | | Page\n"
4002 /* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4003 - W U - - - -- -- -- -- -- 010 */
4004 , cr3, cr4, fLongMode ? " Long Mode" : "",
4005 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4006 cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4007 if (cr4 & X86_CR4_PAE)
4008 {
4009 if (fLongMode)
4010 return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4011 return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4012 }
4013 return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4014}
4015
4016#ifdef VBOX_WITH_DEBUGGER
4017
4018/**
4019 * The '.pgmram' command.
4020 *
4021 * @returns VBox status.
4022 * @param pCmd Pointer to the command descriptor (as registered).
4023 * @param pCmdHlp Pointer to command helper functions.
4024 * @param pVM Pointer to the current VM (if any).
4025 * @param paArgs Pointer to (readonly) array of arguments.
4026 * @param cArgs Number of arguments in the array.
4027 */
4028static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4029{
4030 /*
4031 * Validate input.
4032 */
4033 if (!pVM)
4034 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4035 if (!pVM->pgm.s.pRamRangesRC)
4036 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4037
4038 /*
4039 * Dump the ranges.
4040 */
4041 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4042 PPGMRAMRANGE pRam;
4043 for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4044 {
4045 rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4046 "%RGp - %RGp %p\n",
4047 pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4048 if (RT_FAILURE(rc))
4049 return rc;
4050 }
4051
4052 return VINF_SUCCESS;
4053}
4054
4055
4056/**
4057 * The '.pgmerror' and '.pgmerroroff' commands.
4058 *
4059 * @returns VBox status.
4060 * @param pCmd Pointer to the command descriptor (as registered).
4061 * @param pCmdHlp Pointer to command helper functions.
4062 * @param pVM Pointer to the current VM (if any).
4063 * @param paArgs Pointer to (readonly) array of arguments.
4064 * @param cArgs Number of arguments in the array.
4065 */
4066static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4067{
4068 /*
4069 * Validate input.
4070 */
4071 if (!pVM)
4072 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4073 AssertReturn(cArgs == 0 || (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4074 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4075
4076 if (!cArgs)
4077 {
4078 /*
4079 * Print the list of error injection locations with status.
4080 */
4081 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4082 pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4083 }
4084 else
4085 {
4086
4087 /*
4088 * String switch on where to inject the error.
4089 */
4090 bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4091 const char *pszWhere = paArgs[0].u.pszString;
4092 if (!strcmp(pszWhere, "handy"))
4093 ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4094 else
4095 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4096 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4097 }
4098 return VINF_SUCCESS;
4099}
4100
4101
4102/**
4103 * The '.pgmsync' command.
4104 *
4105 * @returns VBox status.
4106 * @param pCmd Pointer to the command descriptor (as registered).
4107 * @param pCmdHlp Pointer to command helper functions.
4108 * @param pVM Pointer to the current VM (if any).
4109 * @param paArgs Pointer to (readonly) array of arguments.
4110 * @param cArgs Number of arguments in the array.
4111 */
4112static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4113{
4114 /** @todo SMP support */
4115 PVMCPU pVCpu = &pVM->aCpus[0];
4116
4117 /*
4118 * Validate input.
4119 */
4120 if (!pVM)
4121 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4122
4123 /*
4124 * Force page directory sync.
4125 */
4126 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4127
4128 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4129 if (RT_FAILURE(rc))
4130 return rc;
4131
4132 return VINF_SUCCESS;
4133}
4134
4135
4136#ifdef VBOX_STRICT
4137/**
4138 * The '.pgmassertcr3' command.
4139 *
4140 * @returns VBox status.
4141 * @param pCmd Pointer to the command descriptor (as registered).
4142 * @param pCmdHlp Pointer to command helper functions.
4143 * @param pVM Pointer to the current VM (if any).
4144 * @param paArgs Pointer to (readonly) array of arguments.
4145 * @param cArgs Number of arguments in the array.
4146 */
4147static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4148{
4149 /** @todo SMP support!! */
4150 PVMCPU pVCpu = &pVM->aCpus[0];
4151
4152 /*
4153 * Validate input.
4154 */
4155 if (!pVM)
4156 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4157
4158 int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4159 if (RT_FAILURE(rc))
4160 return rc;
4161
4162 PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4163
4164 return VINF_SUCCESS;
4165}
4166#endif /* VBOX_STRICT */
4167
4168
4169/**
4170 * The '.pgmsyncalways' command.
4171 *
4172 * @returns VBox status.
4173 * @param pCmd Pointer to the command descriptor (as registered).
4174 * @param pCmdHlp Pointer to command helper functions.
4175 * @param pVM Pointer to the current VM (if any).
4176 * @param paArgs Pointer to (readonly) array of arguments.
4177 * @param cArgs Number of arguments in the array.
4178 */
4179static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4180{
4181 /** @todo SMP support!! */
4182 PVMCPU pVCpu = &pVM->aCpus[0];
4183
4184 /*
4185 * Validate input.
4186 */
4187 if (!pVM)
4188 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4189
4190 /*
4191 * Force page directory sync.
4192 */
4193 if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4194 {
4195 ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4196 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4197 }
4198 else
4199 {
4200 ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4201 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4202 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4203 }
4204}
4205
4206
4207/**
4208 * The '.pgmsyncalways' command.
4209 *
4210 * @returns VBox status.
4211 * @param pCmd Pointer to the command descriptor (as registered).
4212 * @param pCmdHlp Pointer to command helper functions.
4213 * @param pVM Pointer to the current VM (if any).
4214 * @param paArgs Pointer to (readonly) array of arguments.
4215 * @param cArgs Number of arguments in the array.
4216 */
4217static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4218{
4219 /*
4220 * Validate input.
4221 */
4222 if (!pVM)
4223 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4224 if ( cArgs < 1
4225 || cArgs > 2
4226 || paArgs[0].enmType != DBGCVAR_TYPE_STRING
4227 || ( cArgs > 1
4228 && paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4229 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4230 if ( cArgs >= 2
4231 && strcmp(paArgs[1].u.pszString, "nozero"))
4232 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4233 bool fIncZeroPgs = cArgs < 2;
4234
4235 /*
4236 * Open the output file and get the ram parameters.
4237 */
4238 RTFILE hFile;
4239 int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
4240 if (RT_FAILURE(rc))
4241 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4242
4243 uint32_t cbRamHole = 0;
4244 CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4245 uint64_t cbRam = 0;
4246 CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4247 RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4248
4249 /*
4250 * Dump the physical memory, page by page.
4251 */
4252 RTGCPHYS GCPhys = 0;
4253 char abZeroPg[PAGE_SIZE];
4254 RT_ZERO(abZeroPg);
4255
4256 pgmLock(pVM);
4257 for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4258 pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4259 pRam = pRam->pNextR3)
4260 {
4261 /* fill the gap */
4262 if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4263 {
4264 while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4265 {
4266 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4267 GCPhys += PAGE_SIZE;
4268 }
4269 }
4270
4271 PCPGMPAGE pPage = &pRam->aPages[0];
4272 while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4273 {
4274 if ( PGM_PAGE_IS_ZERO(pPage)
4275 || PGM_PAGE_IS_BALLOONED(pPage))
4276 {
4277 if (fIncZeroPgs)
4278 {
4279 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4280 if (RT_FAILURE(rc))
4281 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4282 }
4283 }
4284 else
4285 {
4286 switch (PGM_PAGE_GET_TYPE(pPage))
4287 {
4288 case PGMPAGETYPE_RAM:
4289 case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4290 case PGMPAGETYPE_ROM:
4291 case PGMPAGETYPE_MMIO2:
4292 {
4293 void const *pvPage;
4294 PGMPAGEMAPLOCK Lock;
4295 rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4296 if (RT_SUCCESS(rc))
4297 {
4298 rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4299 PGMPhysReleasePageMappingLock(pVM, &Lock);
4300 if (RT_FAILURE(rc))
4301 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4302 }
4303 else
4304 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4305 break;
4306 }
4307
4308 default:
4309 AssertFailed();
4310 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4311 case PGMPAGETYPE_MMIO:
4312 if (fIncZeroPgs)
4313 {
4314 rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4315 if (RT_FAILURE(rc))
4316 pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4317 }
4318 break;
4319 }
4320 }
4321
4322
4323 /* advance */
4324 GCPhys += PAGE_SIZE;
4325 pPage++;
4326 }
4327 }
4328 pgmUnlock(pVM);
4329
4330 RTFileClose(hFile);
4331 if (RT_SUCCESS(rc))
4332 return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4333 return VINF_SUCCESS;
4334}
4335
4336#endif /* VBOX_WITH_DEBUGGER */
4337
4338/**
4339 * pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4340 */
4341typedef struct PGMCHECKINTARGS
4342{
4343 bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
4344 PPGMPHYSHANDLER pPrevPhys;
4345 PPGMVIRTHANDLER pPrevVirt;
4346 PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4347 PVM pVM;
4348} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4349
4350/**
4351 * Validate a node in the physical handler tree.
4352 *
4353 * @returns 0 on if ok, other wise 1.
4354 * @param pNode The handler node.
4355 * @param pvUser pVM.
4356 */
4357static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4358{
4359 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4360 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4361 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4362 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4363 AssertReleaseMsg( !pArgs->pPrevPhys
4364 || (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4365 ("pPrevPhys=%p %RGp-%RGp %s\n"
4366 " pCur=%p %RGp-%RGp %s\n",
4367 pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4368 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4369 pArgs->pPrevPhys = pCur;
4370 return 0;
4371}
4372
4373
4374/**
4375 * Validate a node in the virtual handler tree.
4376 *
4377 * @returns 0 on if ok, other wise 1.
4378 * @param pNode The handler node.
4379 * @param pvUser pVM.
4380 */
4381static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4382{
4383 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4384 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4385 AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4386 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4387 AssertReleaseMsg( !pArgs->pPrevVirt
4388 || (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4389 ("pPrevVirt=%p %RGv-%RGv %s\n"
4390 " pCur=%p %RGv-%RGv %s\n",
4391 pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4392 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4393 for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4394 {
4395 AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4396 ("pCur=%p %RGv-%RGv %s\n"
4397 "iPage=%d offVirtHandle=%#x expected %#x\n",
4398 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4399 iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4400 }
4401 pArgs->pPrevVirt = pCur;
4402 return 0;
4403}
4404
4405
4406/**
4407 * Validate a node in the virtual handler tree.
4408 *
4409 * @returns 0 on if ok, other wise 1.
4410 * @param pNode The handler node.
4411 * @param pvUser pVM.
4412 */
4413static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4414{
4415 PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4416 PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4417 AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4418 AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4419 AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4420 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4421 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4422 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4423 " pCur=%p %RGp-%RGp\n",
4424 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4425 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4426 AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4427 || (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4428 ("pPrevPhys2Virt=%p %RGp-%RGp\n"
4429 " pCur=%p %RGp-%RGp\n",
4430 pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4431 pCur, pCur->Core.Key, pCur->Core.KeyLast));
4432 AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD),
4433 ("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4434 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4435 if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4436 {
4437 PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4438 for (;;)
4439 {
4440 pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4441 AssertReleaseMsg(pCur2 != pCur,
4442 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4443 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4444 AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4445 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4446 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4447 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4448 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4449 AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4450 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4451 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4452 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4453 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4454 AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4455 (" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4456 "pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4457 pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4458 pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4459 if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4460 break;
4461 }
4462 }
4463
4464 pArgs->pPrevPhys2Virt = pCur;
4465 return 0;
4466}
4467
4468
4469/**
4470 * Perform an integrity check on the PGM component.
4471 *
4472 * @returns VINF_SUCCESS if everything is fine.
4473 * @returns VBox error status after asserting on integrity breach.
4474 * @param pVM The VM handle.
4475 */
4476VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4477{
4478 AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4479
4480 /*
4481 * Check the trees.
4482 */
4483 int cErrors = 0;
4484 const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4485 const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4486 PGMCHECKINTARGS Args = s_LeftToRight;
4487 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4488 Args = s_RightToLeft;
4489 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4490 Args = s_LeftToRight;
4491 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4492 Args = s_RightToLeft;
4493 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4494 Args = s_LeftToRight;
4495 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4496 Args = s_RightToLeft;
4497 cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4498 Args = s_LeftToRight;
4499 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4500 Args = s_RightToLeft;
4501 cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4502
4503 return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4504}
4505
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