HWACCMInternal.h@ 9383

Last change on this file since 9383 was 9383, checked in by vboxsync, 17 years ago
VT-x/AMD-V updates for 64 bits guests
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File size: 14.0 KB

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1	/* $Id: HWACCMInternal.h 9383 2008-06-04 12:22:45Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35
36	/* Uncomment to enable experimental nested paging. */
37	//#define VBOX_WITH_NESTED_PAGING
38	/* Uncomment to enable 64 bits guest support. */
39	//#define VBOX_ENABLE_64_BITS_GUESTS
40
41	__BEGIN_DECLS
42
43
44	/** @defgroup grp_hwaccm_int Internal
45	* @ingroup grp_hwaccm
46	* @internal
47	* @{
48	*/
49
50
51	/**
52	* Converts a HWACCM pointer into a VM pointer.
53	* @returns Pointer to the VM structure the EM is part of.
54	* @param pHWACCM Pointer to HWACCM instance data.
55	*/
56	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
57
58	/** Maximum number of exit reason statistics counters. */
59	#define MAX_EXITREASON_STAT 0x100
60	#define MASK_EXITREASON_STAT 0xff
61
62	/** @name Changed flags
63	* These flags are used to keep track of which important registers that
64	* have been changed since last they were reset.
65	* @{
66	*/
67	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81	\| HWACCM_CHANGED_GUEST_CR0 \
82	\| HWACCM_CHANGED_GUEST_CR3 \
83	\| HWACCM_CHANGED_GUEST_CR4 \
84	\| HWACCM_CHANGED_GUEST_GDTR \
85	\| HWACCM_CHANGED_GUEST_IDTR \
86	\| HWACCM_CHANGED_GUEST_LDTR \
87	\| HWACCM_CHANGED_GUEST_TR \
88	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89	\| HWACCM_CHANGED_GUEST_FPU \
90	\| HWACCM_CHANGED_GUEST_DEBUG \
91	\| HWACCM_CHANGED_HOST_CONTEXT)
92
93	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94	\| HWACCM_CHANGED_GUEST_CR0 \
95	\| HWACCM_CHANGED_GUEST_CR3 \
96	\| HWACCM_CHANGED_GUEST_CR4 \
97	\| HWACCM_CHANGED_GUEST_GDTR \
98	\| HWACCM_CHANGED_GUEST_IDTR \
99	\| HWACCM_CHANGED_GUEST_LDTR \
100	\| HWACCM_CHANGED_GUEST_TR \
101	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_GUEST_FPU)
104
105	/** @} */
106
107	/** @name Intercepted traps
108	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109	* Currently #NM and #PF only
110	*/
111	#ifdef VBOX_STRICT
112	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
113	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114	#else
115	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
117	#endif
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** HWACCM SSM version
125	*/
126	#define HWACCM_SSM_VERSION 3
127
128	/**
129	* HWACCM VM Instance data.
130	* Changes to this must checked against the padding of the cfgm union in VM!
131	*/
132	typedef struct HWACCM
133	{
134	/** Offset to the VM structure.
135	* See HWACCM2VM(). */
136	RTUINT offVM;
137
138	/** Set when we've initialized VMX or SVM. */
139	bool fInitialized;
140	/** Set when we're using VMX/SVN at that moment. */
141	bool fActive;
142
143	/** Set when hardware acceleration is allowed. */
144	bool fAllowed;
145
146	/** Set if nested paging is enabled. */
147	bool fNestedPaging;
148
149	/** HWACCM_CHANGED_* flags. */
150	uint32_t fContextUseFlags;
151
152	/** Old style FPU reporting trap mask override performed (optimization) */
153	uint32_t fFPUOldStyleOverride;
154
155	struct
156	{
157	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
158	bool fSupported;
159
160	/** Set when we've enabled VMX. */
161	bool fEnabled;
162
163	/** Set if we can use VMXResume to execute guest code. */
164	bool fResumeVM;
165
166	/** R0 memory object for the VM control structure (VMCS). */
167	RTR0MEMOBJ pMemObjVMCS;
168	/** Physical address of the VM control structure (VMCS). */
169	RTHCPHYS pVMCSPhys;
170	/** Virtual address of the VM control structure (VMCS). */
171	R0PTRTYPE(void *) pVMCS;
172
173	/** R0 memory object for the TSS page used for real mode emulation. */
174	RTR0MEMOBJ pMemObjRealModeTSS;
175	/** Physical address of the TSS page used for real mode emulation. */
176	RTHCPHYS pRealModeTSSPhys;
177	/** Virtual address of the TSS page used for real mode emulation. */
178	R0PTRTYPE(PVBOXTSS) pRealModeTSS;
179
180	/** Host CR4 value (set by ring-0 VMX init) */
181	uint64_t hostCR4;
182
183	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
184	uint64_t proc_ctls;
185
186	/** Current CR0 mask. */
187	uint64_t cr0_mask;
188	/** Current CR4 mask. */
189	uint64_t cr4_mask;
190
191	/** VMX MSR values */
192	struct
193	{
194	uint64_t feature_ctrl;
195	uint64_t vmx_basic_info;
196	uint64_t vmx_pin_ctls;
197	uint64_t vmx_proc_ctls;
198	uint64_t vmx_exit;
199	uint64_t vmx_entry;
200	uint64_t vmx_misc;
201	uint64_t vmx_cr0_fixed0;
202	uint64_t vmx_cr0_fixed1;
203	uint64_t vmx_cr4_fixed0;
204	uint64_t vmx_cr4_fixed1;
205	uint64_t vmx_vmcs_enum;
206	} msr;
207
208	/* Last instruction error */
209	uint32_t ulLastInstrError;
210	} vmx;
211
212	struct
213	{
214	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
215	bool fSupported;
216	/** Set when we've enabled SVM. */
217	bool fEnabled;
218	/** Set if we don't have to flush the TLB on VM entry. */
219	bool fResumeVM;
220	/** Set if erratum 170 affects the AMD cpu. */
221	bool fAlwaysFlushTLB;
222	/** Set if we need to flush the TLB during the world switch. */
223	bool fForceTLBFlush;
224
225	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
226	RTCPUID idLastCpu;
227
228	/* TLB flush count */
229	uint32_t cTLBFlushes;
230
231	/** R0 memory object for the VM control block (VMCB). */
232	RTR0MEMOBJ pMemObjVMCB;
233	/** Physical address of the VM control block (VMCB). */
234	RTHCPHYS pVMCBPhys;
235	/** Virtual address of the VM control block (VMCB). */
236	R0PTRTYPE(void *) pVMCB;
237
238	/** R0 memory object for the host VM control block (VMCB). */
239	RTR0MEMOBJ pMemObjVMCBHost;
240	/** Physical address of the host VM control block (VMCB). */
241	RTHCPHYS pVMCBHostPhys;
242	/** Virtual address of the host VM control block (VMCB). */
243	R0PTRTYPE(void *) pVMCBHost;
244
245	/** R0 memory object for the IO bitmap (12kb). */
246	RTR0MEMOBJ pMemObjIOBitmap;
247	/** Physical address of the IO bitmap (12kb). */
248	RTHCPHYS pIOBitmapPhys;
249	/** Virtual address of the IO bitmap. */
250	R0PTRTYPE(void *) pIOBitmap;
251
252	/** R0 memory object for the MSR bitmap (8kb). */
253	RTR0MEMOBJ pMemObjMSRBitmap;
254	/** Physical address of the MSR bitmap (8kb). */
255	RTHCPHYS pMSRBitmapPhys;
256	/** Virtual address of the MSR bitmap. */
257	R0PTRTYPE(void *) pMSRBitmap;
258
259	/** SVM revision. */
260	uint32_t u32Rev;
261
262	/** Maximum ASID allowed. */
263	uint32_t u32MaxASID;
264
265	/** SVM feature bits from cpuid 0x8000000a */
266	uint32_t u32Features;
267	} svm;
268
269	struct
270	{
271	uint32_t u32AMDFeatureECX;
272	uint32_t u32AMDFeatureEDX;
273	} cpuid;
274
275	/* Event injection state. */
276	struct
277	{
278	uint32_t fPending;
279	uint32_t errCode;
280	uint64_t intInfo;
281	} Event;
282
283	/** Saved error from detection */
284	int32_t lLastError;
285
286	/** HWACCMR0Init was run */
287	bool fHWACCMR0Init;
288
289	/** Currenty shadow paging mode. */
290	PGMMODE enmShadowMode;
291
292	STAMPROFILEADV StatEntry;
293	STAMPROFILEADV StatExit;
294	STAMPROFILEADV StatInGC;
295
296	STAMCOUNTER StatIntInject;
297
298	STAMCOUNTER StatExitShadowNM;
299	STAMCOUNTER StatExitGuestNM;
300	STAMCOUNTER StatExitShadowPF;
301	STAMCOUNTER StatExitGuestPF;
302	STAMCOUNTER StatExitGuestUD;
303	STAMCOUNTER StatExitGuestSS;
304	STAMCOUNTER StatExitGuestNP;
305	STAMCOUNTER StatExitGuestGP;
306	STAMCOUNTER StatExitGuestDE;
307	STAMCOUNTER StatExitGuestMF;
308	STAMCOUNTER StatExitInvpg;
309	STAMCOUNTER StatExitInvd;
310	STAMCOUNTER StatExitCpuid;
311	STAMCOUNTER StatExitRdtsc;
312	STAMCOUNTER StatExitCRxWrite;
313	STAMCOUNTER StatExitCRxRead;
314	STAMCOUNTER StatExitDRxWrite;
315	STAMCOUNTER StatExitDRxRead;
316	STAMCOUNTER StatExitCLTS;
317	STAMCOUNTER StatExitLMSW;
318	STAMCOUNTER StatExitIOWrite;
319	STAMCOUNTER StatExitIORead;
320	STAMCOUNTER StatExitIOStringWrite;
321	STAMCOUNTER StatExitIOStringRead;
322	STAMCOUNTER StatExitIrqWindow;
323	STAMCOUNTER StatExitMaxResume;
324	STAMCOUNTER StatIntReinject;
325	STAMCOUNTER StatPendingHostIrq;
326
327	STAMCOUNTER StatFlushPageManual;
328	STAMCOUNTER StatFlushPhysPageManual;
329	STAMCOUNTER StatFlushTLBManual;
330	STAMCOUNTER StatFlushPageInvlpg;
331	STAMCOUNTER StatFlushTLBWorldSwitch;
332	STAMCOUNTER StatNoFlushTLBWorldSwitch;
333	STAMCOUNTER StatFlushTLBCRxChange;
334	STAMCOUNTER StatFlushASID;
335
336	STAMCOUNTER StatSwitchGuestIrq;
337	STAMCOUNTER StatSwitchToR3;
338
339	STAMCOUNTER StatTSCOffset;
340	STAMCOUNTER StatTSCIntercept;
341
342	STAMCOUNTER StatExitReasonNPF;
343	R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
344	R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
345	} HWACCM;
346	/** Pointer to HWACCM VM instance data. */
347	typedef HWACCM *PHWACCM;
348
349	typedef struct
350	{
351	RTCPUID idCpu;
352
353	RTR0MEMOBJ pMemObj;
354	/* Current ASID (AMD-V only) */
355	uint32_t uCurrentASID;
356	/* TLB flush count */
357	uint32_t cTLBFlushes;
358
359	bool fVMXConfigured;
360	bool fSVMConfigured;
361	} HWACCM_CPUINFO;
362	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
363
364	#ifdef IN_RING0
365
366	#ifdef VBOX_STRICT
367	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
368	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
369	#else
370	#define HWACCMDumpRegs(a) do { } while (0)
371	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
372	#endif
373
374	#endif
375
376	/** @} */
377
378	__END_DECLS
379
380	#endif
381

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 9383

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