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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 24912

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1/* $Id: HWACCMInternal.h 24832 2009-11-20 15:37:23Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/cpum.h>
33#include <iprt/memobj.h>
34#include <iprt/cpuset.h>
35#include <iprt/mp.h>
36#include <iprt/avl.h>
37
38#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
39/* Enable 64 bits guest support. */
40# define VBOX_ENABLE_64_BITS_GUESTS
41#endif
42
43#define VMX_USE_CACHED_VMCS_ACCESSES
44#define HWACCM_VMX_EMULATE_REALMODE
45#define HWACCM_VTX_WITH_EPT
46#define HWACCM_VTX_WITH_VPID
47
48
49#if 0
50/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
51 * for some strange reason the CPU doesn't save the MSRs during the VM-exit.
52 * Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
53 *
54 * Note: change the assembly files when enabling this! (remove the manual auto load/save)
55 */
56#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hwaccm_int Internal
63 * @ingroup grp_hwaccm
64 * @internal
65 * @{
66 */
67
68
69/** Maximum number of exit reason statistics counters. */
70#define MAX_EXITREASON_STAT 0x100
71#define MASK_EXITREASON_STAT 0xff
72#define MASK_INJECT_IRQ_STAT 0xff
73
74/** @name Changed flags
75 * These flags are used to keep track of which important registers that
76 * have been changed since last they were reset.
77 * @{
78 */
79#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
80#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
81#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
82#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
83#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
84#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
85#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
86#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
87#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
88#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
89#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
90#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
91
92#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93 | HWACCM_CHANGED_GUEST_CR0 \
94 | HWACCM_CHANGED_GUEST_CR3 \
95 | HWACCM_CHANGED_GUEST_CR4 \
96 | HWACCM_CHANGED_GUEST_GDTR \
97 | HWACCM_CHANGED_GUEST_IDTR \
98 | HWACCM_CHANGED_GUEST_LDTR \
99 | HWACCM_CHANGED_GUEST_TR \
100 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101 | HWACCM_CHANGED_GUEST_FPU \
102 | HWACCM_CHANGED_GUEST_DEBUG \
103 | HWACCM_CHANGED_HOST_CONTEXT)
104
105#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
106 | HWACCM_CHANGED_GUEST_CR0 \
107 | HWACCM_CHANGED_GUEST_CR3 \
108 | HWACCM_CHANGED_GUEST_CR4 \
109 | HWACCM_CHANGED_GUEST_GDTR \
110 | HWACCM_CHANGED_GUEST_IDTR \
111 | HWACCM_CHANGED_GUEST_LDTR \
112 | HWACCM_CHANGED_GUEST_TR \
113 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
114 | HWACCM_CHANGED_GUEST_DEBUG \
115 | HWACCM_CHANGED_GUEST_FPU)
116
117/** @} */
118
119/** @name Intercepted traps
120 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
121 * Currently #NM and #PF only
122 */
123#ifdef VBOX_STRICT
124#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
125#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
126#else
127#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
128#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
129#endif
130/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
131#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NMI) | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_DF) | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF) | RT_BIT(X86_XCPT_AC) | RT_BIT(X86_XCPT_MC) | RT_BIT(X86_XCPT_XF)
132/** @} */
133
134
135/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
136#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
137
138/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
139#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
140/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
141#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
142/** Total guest mapped memory needed. */
143#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
144
145/* Enable for TPR guest patching. */
146#define VBOX_HWACCM_WITH_GUEST_PATCHING
147
148/** HWACCM SSM version
149 */
150#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
151#define HWACCM_SSM_VERSION 5
152#define HWACCM_SSM_VERSION_NO_PATCHING 4
153#else
154#define HWACCM_SSM_VERSION 4
155#define HWACCM_SSM_VERSION_NO_PATCHING 4
156#endif
157#define HWACCM_SSM_VERSION_2_0_X 3
158
159/* Per-cpu information. (host) */
160typedef struct
161{
162 RTCPUID idCpu;
163
164 RTR0MEMOBJ pMemObj;
165 /* Current ASID (AMD-V)/VPID (Intel) */
166 uint32_t uCurrentASID;
167 /* TLB flush count */
168 uint32_t cTLBFlushes;
169
170 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
171 bool fFlushTLB;
172
173 /** Configured for VT-x or AMD-V. */
174 bool fConfigured;
175
176 /** In use by our code. (for power suspend) */
177 volatile bool fInUse;
178} HWACCM_CPUINFO;
179typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181typedef enum
182{
183 HWACCMPENDINGIO_INVALID = 0,
184 HWACCMPENDINGIO_PORT_READ,
185 HWACCMPENDINGIO_PORT_WRITE,
186 HWACCMPENDINGIO_STRING_READ,
187 HWACCMPENDINGIO_STRING_WRITE,
188 /** The usual 32-bit paranoia. */
189 HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190} HWACCMPENDINGIO;
191
192
193typedef enum
194{
195 HWACCMTPRINSTR_INVALID,
196 HWACCMTPRINSTR_READ,
197 HWACCMTPRINSTR_READ_SHR4,
198 HWACCMTPRINSTR_WRITE_REG,
199 HWACCMTPRINSTR_WRITE_IMM,
200 HWACCMTPRINSTR_JUMP_REPLACEMENT,
201 /** The usual 32-bit paranoia. */
202 HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203} HWACCMTPRINSTR;
204
205typedef struct
206{
207 /** The key is the address of patched instruction. (32 bits GC ptr) */
208 AVLOU32NODECORE Core;
209 /** Original opcode. */
210 uint8_t aOpcode[16];
211 /** Instruction size. */
212 uint32_t cbOp;
213 /** Replacement opcode. */
214 uint8_t aNewOpcode[16];
215 /** Replacement instruction size. */
216 uint32_t cbNewOp;
217 /** Instruction type. */
218 HWACCMTPRINSTR enmType;
219 /** Source operand. */
220 uint32_t uSrcOperand;
221 /** Destination operand. */
222 uint32_t uDstOperand;
223 /** Number of times the instruction caused a fault. */
224 uint32_t cFaults;
225 /** Patch address of the jump replacement. */
226 RTGCPTR32 pJumpTarget;
227} HWACCMTPRPATCH;
228/** Pointer to HWACCMTPRPATCH. */
229typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231/**
232 * Switcher function, HC to RC.
233 *
234 * @param pVM The VM handle.
235 * @returns Return code indicating the action to take.
236 */
237typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
238/** Pointer to switcher function. */
239typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
240
241/**
242 * HWACCM VM Instance data.
243 * Changes to this must checked against the padding of the cfgm union in VM!
244 */
245typedef struct HWACCM
246{
247 /** Set when we've initialized VMX or SVM. */
248 bool fInitialized;
249
250 /** Set when hardware acceleration is allowed. */
251 bool fAllowed;
252
253 /** Set if nested paging is enabled. */
254 bool fNestedPaging;
255
256 /** Set if nested paging is allowed. */
257 bool fAllowNestedPaging;
258
259 /** Set if we can support 64-bit guests or not. */
260 bool fAllow64BitGuests;
261
262 /** Set if an IO-APIC is configured for this VM. */
263 bool fHasIoApic;
264
265 /** Set when TPR patching is allowed. */
266 bool fTRPPatchingAllowed;
267
268 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
269 bool fGlobalInit;
270
271 /** Set when TPR patching is active. */
272 bool fTPRPatchingActive;
273 bool u8Alignment[7];
274
275 /** And mask for copying register contents. */
276 uint64_t u64RegisterMask;
277
278 /** Maximum ASID allowed. */
279 RTUINT uMaxASID;
280
281 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
282 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
283 uint32_t cMaxResumeLoops;
284
285 /** Guest allocated memory for patching purposes. */
286 RTGCPTR pGuestPatchMem;
287 /** Current free pointer inside the patch block. */
288 RTGCPTR pFreeGuestPatchMem;
289 /** Size of the guest patch memory block. */
290 uint32_t cbGuestPatchMem;
291 uint32_t uPadding1;
292
293#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
294 /** 32 to 64 bits switcher entrypoint. */
295 R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
296
297 /* AMD-V 64 bits vmrun handler */
298 RTRCPTR pfnSVMGCVMRun64;
299
300 /* VT-x 64 bits vmlaunch handler */
301 RTRCPTR pfnVMXGCStartVM64;
302
303 /* RC handler to setup the 64 bits FPU state. */
304 RTRCPTR pfnSaveGuestFPU64;
305
306 /* RC handler to setup the 64 bits debug state. */
307 RTRCPTR pfnSaveGuestDebug64;
308
309 /* Test handler */
310 RTRCPTR pfnTest64;
311
312 RTRCPTR uAlignment[2];
313/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
314 uint32_t u32Alignment[1]; */
315#endif
316
317 struct
318 {
319 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
320 bool fSupported;
321
322 /** Set when we've enabled VMX. */
323 bool fEnabled;
324
325 /** Set if VPID is supported. */
326 bool fVPID;
327
328 /** Set if VT-x VPID is allowed. */
329 bool fAllowVPID;
330
331 /** Virtual address of the TSS page used for real mode emulation. */
332 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
333
334 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
335 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
336
337 /** R0 memory object for the APIC physical page (serves for filtering accesses). */
338 RTR0MEMOBJ pMemObjAPIC;
339 /** Physical address of the APIC physical page (serves for filtering accesses). */
340 RTHCPHYS pAPICPhys;
341 /** Virtual address of the APIC physical page (serves for filtering accesses). */
342 R0PTRTYPE(uint8_t *) pAPIC;
343
344 /** R0 memory object for the MSR entry load page (guest MSRs). */
345 RTR0MEMOBJ pMemObjMSREntryLoad;
346 /** Physical address of the MSR entry load page (guest MSRs). */
347 RTHCPHYS pMSREntryLoadPhys;
348 /** Virtual address of the MSR entry load page (guest MSRs). */
349 R0PTRTYPE(uint8_t *) pMSREntryLoad;
350
351#ifdef VBOX_WITH_CRASHDUMP_MAGIC
352 RTR0MEMOBJ pMemObjScratch;
353 RTHCPHYS pScratchPhys;
354 R0PTRTYPE(uint8_t *) pScratch;
355#endif
356 /** R0 memory object for the MSR exit store page (guest MSRs). */
357 RTR0MEMOBJ pMemObjMSRExitStore;
358 /** Physical address of the MSR exit store page (guest MSRs). */
359 RTHCPHYS pMSRExitStorePhys;
360 /** Virtual address of the MSR exit store page (guest MSRs). */
361 R0PTRTYPE(uint8_t *) pMSRExitStore;
362
363 /** R0 memory object for the MSR exit load page (host MSRs). */
364 RTR0MEMOBJ pMemObjMSRExitLoad;
365 /** Physical address of the MSR exit load page (host MSRs). */
366 RTHCPHYS pMSRExitLoadPhys;
367 /** Virtual address of the MSR exit load page (host MSRs). */
368 R0PTRTYPE(uint8_t *) pMSRExitLoad;
369
370 /** Ring 0 handlers for VT-x. */
371 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
372
373 /** Host CR4 value (set by ring-0 VMX init) */
374 uint64_t hostCR4;
375
376 /** VMX MSR values */
377 struct
378 {
379 uint64_t feature_ctrl;
380 uint64_t vmx_basic_info;
381 VMX_CAPABILITY vmx_pin_ctls;
382 VMX_CAPABILITY vmx_proc_ctls;
383 VMX_CAPABILITY vmx_proc_ctls2;
384 VMX_CAPABILITY vmx_exit;
385 VMX_CAPABILITY vmx_entry;
386 uint64_t vmx_misc;
387 uint64_t vmx_cr0_fixed0;
388 uint64_t vmx_cr0_fixed1;
389 uint64_t vmx_cr4_fixed0;
390 uint64_t vmx_cr4_fixed1;
391 uint64_t vmx_vmcs_enum;
392 uint64_t vmx_eptcaps;
393 } msr;
394
395 /** Flush types for invept & invvpid; they depend on capabilities. */
396 VMX_FLUSH enmFlushPage;
397 VMX_FLUSH enmFlushContext;
398 } vmx;
399
400 struct
401 {
402 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
403 bool fSupported;
404 /** Set when we've enabled SVM. */
405 bool fEnabled;
406 /** Set if erratum 170 affects the AMD cpu. */
407 bool fAlwaysFlushTLB;
408 bool u8Alignment;
409
410 /** R0 memory object for the IO bitmap (12kb). */
411 RTR0MEMOBJ pMemObjIOBitmap;
412 /** Physical address of the IO bitmap (12kb). */
413 RTHCPHYS pIOBitmapPhys;
414 /** Virtual address of the IO bitmap. */
415 R0PTRTYPE(void *) pIOBitmap;
416
417 /* HWCR msr (for diagnostics) */
418 uint64_t msrHWCR;
419
420 /** SVM revision. */
421 uint32_t u32Rev;
422
423 /** SVM feature bits from cpuid 0x8000000a */
424 uint32_t u32Features;
425 } svm;
426
427 /**
428 * AVL tree with all patches (active or disabled) sorted by guest instruction address
429 */
430 AVLOU32TREE PatchTree;
431 uint32_t cPatches;
432 HWACCMTPRPATCH aPatches[64];
433
434 struct
435 {
436 uint32_t u32AMDFeatureECX;
437 uint32_t u32AMDFeatureEDX;
438 } cpuid;
439
440 /** Saved error from detection */
441 int32_t lLastError;
442
443 /** HWACCMR0Init was run */
444 bool fHWACCMR0Init;
445 bool u8Alignment1[7];
446
447 STAMCOUNTER StatTPRPatchSuccess;
448 STAMCOUNTER StatTPRPatchFailure;
449 STAMCOUNTER StatTPRReplaceSuccess;
450 STAMCOUNTER StatTPRReplaceFailure;
451} HWACCM;
452/** Pointer to HWACCM VM instance data. */
453typedef HWACCM *PHWACCM;
454
455/* Maximum number of cached entries. */
456#define VMCSCACHE_MAX_ENTRY 128
457
458/* Structure for storing read and write VMCS actions. */
459typedef struct VMCSCACHE
460{
461#ifdef VBOX_WITH_CRASHDUMP_MAGIC
462 /* Magic marker for searching in crash dumps. */
463 uint8_t aMagic[16];
464 uint64_t uMagic;
465 uint64_t u64TimeEntry;
466 uint64_t u64TimeSwitch;
467 uint64_t cResume;
468 uint64_t interPD;
469 uint64_t pSwitcher;
470 uint32_t uPos;
471 uint32_t idCpu;
472#endif
473 /* CR2 is saved here for EPT syncing. */
474 uint64_t cr2;
475 struct
476 {
477 uint32_t cValidEntries;
478 uint32_t uAlignment;
479 uint32_t aField[VMCSCACHE_MAX_ENTRY];
480 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
481 } Write;
482 struct
483 {
484 uint32_t cValidEntries;
485 uint32_t uAlignment;
486 uint32_t aField[VMCSCACHE_MAX_ENTRY];
487 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
488 } Read;
489#ifdef DEBUG
490 struct
491 {
492 RTHCPHYS pPageCpuPhys;
493 RTHCPHYS pVMCSPhys;
494 RTGCPTR pCache;
495 RTGCPTR pCtx;
496 } TestIn;
497 struct
498 {
499 RTHCPHYS pVMCSPhys;
500 RTGCPTR pCache;
501 RTGCPTR pCtx;
502 uint64_t eflags;
503 uint64_t cr8;
504 } TestOut;
505 struct
506 {
507 uint64_t param1;
508 uint64_t param2;
509 uint64_t param3;
510 uint64_t param4;
511 } ScratchPad;
512#endif
513} VMCSCACHE;
514/** Pointer to VMCSCACHE. */
515typedef VMCSCACHE *PVMCSCACHE;
516
517/** VMX StartVM function. */
518typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
519/** Pointer to a VMX StartVM function. */
520typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
521
522/** SVM VMRun function. */
523typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
524/** Pointer to a SVM VMRun function. */
525typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
526
527/**
528 * HWACCM VMCPU Instance data.
529 */
530typedef struct HWACCMCPU
531{
532 /** Old style FPU reporting trap mask override performed (optimization) */
533 bool fFPUOldStyleOverride;
534
535 /** Set if we don't have to flush the TLB on VM entry. */
536 bool fResumeVM;
537
538 /** Set if we need to flush the TLB during the world switch. */
539 bool fForceTLBFlush;
540
541 /** Set when we're using VT-x or AMD-V at that moment. */
542 bool fActive;
543
544 /** Set when the TLB has been checked until we return from the world switch. */
545 volatile uint8_t fCheckedTLBFlush;
546 uint8_t bAlignment[3];
547
548 /** HWACCM_CHANGED_* flags. */
549 RTUINT fContextUseFlags;
550
551 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
552 RTCPUID idLastCpu;
553
554 /** TLB flush count */
555 RTUINT cTLBFlushes;
556
557 /** Current ASID in use by the VM */
558 RTUINT uCurrentASID;
559
560 /** World switch exit counter. */
561 volatile uint32_t cWorldSwitchExit;
562 uint32_t u32Alignment;
563
564 struct
565 {
566 /** Physical address of the VM control structure (VMCS). */
567 RTHCPHYS pVMCSPhys;
568 /** R0 memory object for the VM control structure (VMCS). */
569 RTR0MEMOBJ pMemObjVMCS;
570 /** Virtual address of the VM control structure (VMCS). */
571 R0PTRTYPE(void *) pVMCS;
572
573 /** Ring 0 handlers for VT-x. */
574 PFNHWACCMVMXSTARTVM pfnStartVM;
575
576#if HC_ARCH_BITS == 32
577 uint32_t u32Alignment;
578#endif
579
580 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
581 uint64_t proc_ctls;
582
583 /** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
584 uint64_t proc_ctls2;
585
586 /** Physical address of the virtual APIC page for TPR caching. */
587 RTHCPHYS pVAPICPhys;
588 /** R0 memory object for the virtual APIC page for TPR caching. */
589 RTR0MEMOBJ pMemObjVAPIC;
590 /** Virtual address of the virtual APIC page for TPR caching. */
591 R0PTRTYPE(uint8_t *) pVAPIC;
592
593 /** Current CR0 mask. */
594 uint64_t cr0_mask;
595 /** Current CR4 mask. */
596 uint64_t cr4_mask;
597
598 /** Current EPTP. */
599 RTHCPHYS GCPhysEPTP;
600
601 /** Physical address of the MSR bitmap (1 page). */
602 RTHCPHYS pMSRBitmapPhys;
603 /** R0 memory object for the MSR bitmap (1 page). */
604 RTR0MEMOBJ pMemObjMSRBitmap;
605 /** Virtual address of the MSR bitmap (1 page). */
606 R0PTRTYPE(uint8_t *) pMSRBitmap;
607
608#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
609 /** Physical address of the guest MSR load area (1 page). */
610 RTHCPHYS pGuestMSRPhys;
611 /** R0 memory object for the guest MSR load area (1 page). */
612 RTR0MEMOBJ pMemObjGuestMSR;
613 /** Virtual address of the guest MSR load area (1 page). */
614 R0PTRTYPE(uint8_t *) pGuestMSR;
615
616 /** Physical address of the MSR load area (1 page). */
617 RTHCPHYS pHostMSRPhys;
618 /** R0 memory object for the MSR load area (1 page). */
619 RTR0MEMOBJ pMemObjHostMSR;
620 /** Virtual address of the MSR load area (1 page). */
621 R0PTRTYPE(uint8_t *) pHostMSR;
622#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
623
624 /* Number of automatically loaded/restored MSRs. */
625 uint32_t cCachedMSRs;
626 uint32_t uAlignement;
627
628 /* Last use TSC offset value. (cached) */
629 uint64_t u64TSCOffset;
630
631 /** VMCS cache. */
632 VMCSCACHE VMCSCache;
633
634 /** Real-mode emulation state. */
635 struct
636 {
637 X86EFLAGS eflags;
638 uint32_t fValid;
639 } RealMode;
640
641 struct
642 {
643 uint64_t u64VMCSPhys;
644 uint32_t ulVMCSRevision;
645 uint32_t ulInstrError;
646 uint32_t ulExitReason;
647 RTCPUID idEnteredCpu;
648 RTCPUID idCurrentCpu;
649 uint32_t padding;
650 } lasterror;
651
652 /** The last seen guest paging mode (by VT-x). */
653 PGMMODE enmLastSeenGuestMode;
654 /** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
655 PGMMODE enmCurrGuestMode;
656 /** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
657 PGMMODE enmPrevGuestMode;
658 } vmx;
659
660 struct
661 {
662 /** R0 memory object for the host VM control block (VMCB). */
663 RTR0MEMOBJ pMemObjVMCBHost;
664 /** Physical address of the host VM control block (VMCB). */
665 RTHCPHYS pVMCBHostPhys;
666 /** Virtual address of the host VM control block (VMCB). */
667 R0PTRTYPE(void *) pVMCBHost;
668
669 /** R0 memory object for the VM control block (VMCB). */
670 RTR0MEMOBJ pMemObjVMCB;
671 /** Physical address of the VM control block (VMCB). */
672 RTHCPHYS pVMCBPhys;
673 /** Virtual address of the VM control block (VMCB). */
674 R0PTRTYPE(void *) pVMCB;
675
676 /** Ring 0 handlers for VT-x. */
677 PFNHWACCMSVMVMRUN pfnVMRun;
678
679 /** R0 memory object for the MSR bitmap (8kb). */
680 RTR0MEMOBJ pMemObjMSRBitmap;
681 /** Physical address of the MSR bitmap (8kb). */
682 RTHCPHYS pMSRBitmapPhys;
683 /** Virtual address of the MSR bitmap. */
684 R0PTRTYPE(void *) pMSRBitmap;
685 } svm;
686
687 /** Event injection state. */
688 struct
689 {
690 uint32_t fPending;
691 uint32_t errCode;
692 uint64_t intInfo;
693 } Event;
694
695 /** IO Block emulation state. */
696 struct
697 {
698 bool fEnabled;
699 uint8_t u8Align[7];
700
701 /** RIP at the start of the io code we wish to emulate in the recompiler. */
702 RTGCPTR GCPtrFunctionEip;
703
704 uint64_t cr0;
705 } EmulateIoBlock;
706
707 struct
708 {
709 /* Pending IO operation type. */
710 HWACCMPENDINGIO enmType;
711 uint32_t uPadding;
712 RTGCPTR GCPtrRip;
713 RTGCPTR GCPtrRipNext;
714 union
715 {
716 struct
717 {
718 unsigned uPort;
719 unsigned uAndVal;
720 unsigned cbSize;
721 } Port;
722 uint64_t aRaw[2];
723 } s;
724 } PendingIO;
725
726 /** Currenty shadow paging mode. */
727 PGMMODE enmShadowMode;
728
729 /** The CPU ID of the CPU currently owning the VMCS. Set in
730 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
731 RTCPUID idEnteredCpu;
732
733 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
734 struct
735 {
736 RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
737 unsigned cPages;
738 } TlbShootdown;
739
740 /** For saving stack space, the disassembler state is allocated here instead of
741 * on the stack.
742 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
743 union
744 {
745 /** The disassembler scratch space. */
746 DISCPUSTATE DisState;
747 /** Padding. */
748 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
749 };
750
751 RTUINT padding2[1];
752
753 STAMPROFILEADV StatEntry;
754 STAMPROFILEADV StatExit1;
755 STAMPROFILEADV StatExit2;
756#if 1 /* temporary for tracking down darwin issues. */
757 STAMPROFILEADV StatExit2Sub1;
758 STAMPROFILEADV StatExit2Sub2;
759 STAMPROFILEADV StatExit2Sub3;
760#endif
761 STAMPROFILEADV StatInGC;
762
763#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
764 STAMPROFILEADV StatWorldSwitch3264;
765#endif
766 STAMPROFILEADV StatPoke;
767 STAMPROFILEADV StatSpinPoke;
768 STAMPROFILEADV StatSpinPokeFailed;
769
770 STAMCOUNTER StatIntInject;
771
772 STAMCOUNTER StatExitShadowNM;
773 STAMCOUNTER StatExitGuestNM;
774 STAMCOUNTER StatExitShadowPF;
775 STAMCOUNTER StatExitGuestPF;
776 STAMCOUNTER StatExitGuestUD;
777 STAMCOUNTER StatExitGuestSS;
778 STAMCOUNTER StatExitGuestNP;
779 STAMCOUNTER StatExitGuestGP;
780 STAMCOUNTER StatExitGuestDE;
781 STAMCOUNTER StatExitGuestDB;
782 STAMCOUNTER StatExitGuestMF;
783 STAMCOUNTER StatExitInvpg;
784 STAMCOUNTER StatExitInvd;
785 STAMCOUNTER StatExitCpuid;
786 STAMCOUNTER StatExitRdtsc;
787 STAMCOUNTER StatExitRdpmc;
788 STAMCOUNTER StatExitCli;
789 STAMCOUNTER StatExitSti;
790 STAMCOUNTER StatExitPushf;
791 STAMCOUNTER StatExitPopf;
792 STAMCOUNTER StatExitIret;
793 STAMCOUNTER StatExitInt;
794 STAMCOUNTER StatExitCRxWrite[16];
795 STAMCOUNTER StatExitCRxRead[16];
796 STAMCOUNTER StatExitDRxWrite;
797 STAMCOUNTER StatExitDRxRead;
798 STAMCOUNTER StatExitRdmsr;
799 STAMCOUNTER StatExitWrmsr;
800 STAMCOUNTER StatExitCLTS;
801 STAMCOUNTER StatExitHlt;
802 STAMCOUNTER StatExitMwait;
803 STAMCOUNTER StatExitLMSW;
804 STAMCOUNTER StatExitIOWrite;
805 STAMCOUNTER StatExitIORead;
806 STAMCOUNTER StatExitIOStringWrite;
807 STAMCOUNTER StatExitIOStringRead;
808 STAMCOUNTER StatExitIrqWindow;
809 STAMCOUNTER StatExitMaxResume;
810 STAMCOUNTER StatExitPreemptPending;
811 STAMCOUNTER StatIntReinject;
812 STAMCOUNTER StatPendingHostIrq;
813
814 STAMCOUNTER StatFlushPage;
815 STAMCOUNTER StatFlushPageManual;
816 STAMCOUNTER StatFlushPhysPageManual;
817 STAMCOUNTER StatFlushTLB;
818 STAMCOUNTER StatFlushTLBManual;
819 STAMCOUNTER StatFlushPageInvlpg;
820 STAMCOUNTER StatFlushTLBWorldSwitch;
821 STAMCOUNTER StatNoFlushTLBWorldSwitch;
822 STAMCOUNTER StatFlushTLBCRxChange;
823 STAMCOUNTER StatFlushASID;
824 STAMCOUNTER StatFlushTLBInvlpga;
825 STAMCOUNTER StatTlbShootdown;
826 STAMCOUNTER StatTlbShootdownFlush;
827
828 STAMCOUNTER StatSwitchGuestIrq;
829 STAMCOUNTER StatSwitchToR3;
830
831 STAMCOUNTER StatTSCOffset;
832 STAMCOUNTER StatTSCIntercept;
833 STAMCOUNTER StatTSCInterceptOverFlow;
834
835 STAMCOUNTER StatExitReasonNPF;
836 STAMCOUNTER StatDRxArmed;
837 STAMCOUNTER StatDRxContextSwitch;
838 STAMCOUNTER StatDRxIOCheck;
839
840
841#ifdef VBOX_WITH_STATISTICS
842 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
843 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
844 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
845 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
846#endif
847} HWACCMCPU;
848/** Pointer to HWACCM VM instance data. */
849typedef HWACCMCPU *PHWACCMCPU;
850
851
852#ifdef IN_RING0
853
854VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
855VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
856
857
858#ifdef VBOX_STRICT
859VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
860VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
861#else
862# define HWACCMDumpRegs(a, b ,c) do { } while (0)
863# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
864#endif
865
866/* Dummy callback handlers. */
867VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
868VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
869VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
870VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
871VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
872VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
873VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
874VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
875VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
876VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
877
878# ifdef VBOX_WITH_KERNEL_USING_XMM
879DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
880DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
881# endif
882
883# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
884/**
885 * Gets 64-bit GDTR and IDTR on darwin.
886 * @param pGdtr Where to store the 64-bit GDTR.
887 * @param pIdtr Where to store the 64-bit IDTR.
888 */
889DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
890
891/**
892 * Gets 64-bit CR3 on darwin.
893 * @returns CR3
894 */
895DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
896# endif
897
898#endif /* IN_RING0 */
899
900/** @} */
901
902RT_C_DECLS_END
903
904#endif
905
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