VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 16560

Last change on this file since 16560 was 15962, checked in by vboxsync, 15 years ago

Added debugging code (inactive) for tracking the state of the 32/64 switcher in crash dumps
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 24.7 KB
Line 
1/* $Id: HWACCMInternal.h 15962 2009-01-15 12:33:49Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/cpum.h>
33#include <iprt/memobj.h>
34#include <iprt/cpuset.h>
35#include <iprt/mp.h>
36
37#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
38/* Enable 64 bits guest support. */
39# define VBOX_ENABLE_64_BITS_GUESTS
40#endif
41
42#define VMX_USE_CACHED_VMCS_ACCESSES
43#define HWACCM_VMX_EMULATE_REALMODE
44#define HWACCM_VTX_WITH_EPT
45#define HWACCM_VTX_WITH_VPID
46
47__BEGIN_DECLS
48
49
50/** @defgroup grp_hwaccm_int Internal
51 * @ingroup grp_hwaccm
52 * @internal
53 * @{
54 */
55
56
57/** Maximum number of exit reason statistics counters. */
58#define MAX_EXITREASON_STAT 0x100
59#define MASK_EXITREASON_STAT 0xff
60
61/** @name Changed flags
62 * These flags are used to keep track of which important registers that
63 * have been changed since last they were reset.
64 * @{
65 */
66#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80 | HWACCM_CHANGED_GUEST_CR0 \
81 | HWACCM_CHANGED_GUEST_CR3 \
82 | HWACCM_CHANGED_GUEST_CR4 \
83 | HWACCM_CHANGED_GUEST_GDTR \
84 | HWACCM_CHANGED_GUEST_IDTR \
85 | HWACCM_CHANGED_GUEST_LDTR \
86 | HWACCM_CHANGED_GUEST_TR \
87 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88 | HWACCM_CHANGED_GUEST_FPU \
89 | HWACCM_CHANGED_GUEST_DEBUG \
90 | HWACCM_CHANGED_HOST_CONTEXT)
91
92#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93 | HWACCM_CHANGED_GUEST_CR0 \
94 | HWACCM_CHANGED_GUEST_CR3 \
95 | HWACCM_CHANGED_GUEST_CR4 \
96 | HWACCM_CHANGED_GUEST_GDTR \
97 | HWACCM_CHANGED_GUEST_IDTR \
98 | HWACCM_CHANGED_GUEST_LDTR \
99 | HWACCM_CHANGED_GUEST_TR \
100 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101 | HWACCM_CHANGED_GUEST_DEBUG \
102 | HWACCM_CHANGED_GUEST_FPU)
103
104/** @} */
105
106/** @name Intercepted traps
107 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108 * Currently #NM and #PF only
109 */
110#ifdef VBOX_STRICT
111#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
112#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113#else
114#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
115#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
116#endif
117/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NMI) | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_DF) | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF) | RT_BIT(X86_XCPT_AC) | RT_BIT(X86_XCPT_MC) | RT_BIT(X86_XCPT_XF)
119/** @} */
120
121
122/** Maxium resume loops allowed in ring 0 (safety precaution) */
123#define HWACCM_MAX_RESUME_LOOPS 1024
124
125/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
126#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
127/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
128#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
129/** Total guest mapped memory needed. */
130#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
131
132/** HWACCM SSM version
133 */
134#define HWACCM_SSM_VERSION 4
135#define HWACCM_SSM_VERSION_2_0_X 3
136
137/* Per-cpu information. (host) */
138typedef struct
139{
140 RTCPUID idCpu;
141
142 RTR0MEMOBJ pMemObj;
143 /* Current ASID (AMD-V)/VPID (Intel) */
144 uint32_t uCurrentASID;
145 /* TLB flush count */
146 uint32_t cTLBFlushes;
147
148 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
149 bool fFlushTLB;
150
151 /** Configured for VT-x or AMD-V. */
152 bool fConfigured;
153
154 /** In use by our code. (for power suspend) */
155 volatile bool fInUse;
156} HWACCM_CPUINFO;
157typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
158
159/* VT-x capability qword. */
160typedef union
161{
162 struct
163 {
164 uint32_t disallowed0;
165 uint32_t allowed1;
166 } n;
167 uint64_t u;
168} VMX_CAPABILITY;
169
170/**
171 * Switcher function, HC to RC.
172 *
173 * @param pVM The VM handle.
174 * @returns Return code indicating the action to take.
175 */
176typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
177/** Pointer to switcher function. */
178typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
179
180/**
181 * HWACCM VM Instance data.
182 * Changes to this must checked against the padding of the cfgm union in VM!
183 */
184typedef struct HWACCM
185{
186 /** Set when we've initialized VMX or SVM. */
187 bool fInitialized;
188
189 /** Set when we're using VMX/SVN at that moment. */
190 bool fActive;
191
192 /** Set when hardware acceleration is allowed. */
193 bool fAllowed;
194
195 /** Set if nested paging is enabled. */
196 bool fNestedPaging;
197
198 /** Set if nested paging is allowed. */
199 bool fAllowNestedPaging;
200
201 /** Set if we're supposed to inject an NMI. */
202 bool fInjectNMI;
203
204 /** Set if we can support 64-bit guests or not. */
205 bool fAllow64BitGuests;
206
207 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
208 * naturally. */
209 bool padding[1];
210
211 /** And mask for copying register contents. */
212 uint64_t u64RegisterMask;
213
214 /** Maximum ASID allowed. */
215 RTUINT uMaxASID;
216
217#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
218 /** 32 to 64 bits switcher entrypoint. */
219 R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
220
221 /* AMD-V 64 bits vmrun handler */
222 RTRCPTR pfnSVMGCVMRun64;
223
224 /* VT-x 64 bits vmlaunch handler */
225 RTRCPTR pfnVMXGCStartVM64;
226
227 /* RC handler to setup the 64 bits FPU state. */
228 RTRCPTR pfnSaveGuestFPU64;
229
230 /* RC handler to setup the 64 bits debug state. */
231 RTRCPTR pfnSaveGuestDebug64;
232
233 /* Test handler */
234 RTRCPTR pfnTest64;
235
236 RTRCPTR uAlignment[1];
237#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
238 uint32_t u32Alignment[1];
239#endif
240
241 struct
242 {
243 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
244 bool fSupported;
245
246 /** Set when we've enabled VMX. */
247 bool fEnabled;
248
249 /** Set if VPID is supported. */
250 bool fVPID;
251
252 /** Set if VT-x VPID is allowed. */
253 bool fAllowVPID;
254
255 /** Virtual address of the TSS page used for real mode emulation. */
256 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
257
258 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
259 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
260
261 /** R0 memory object for the virtual APIC mmio cache. */
262 RTR0MEMOBJ pMemObjAPIC;
263 /** Physical address of the virtual APIC mmio cache. */
264 RTHCPHYS pAPICPhys;
265 /** Virtual address of the virtual APIC mmio cache. */
266 R0PTRTYPE(uint8_t *) pAPIC;
267
268 /** R0 memory object for the MSR bitmap (1 page). */
269 RTR0MEMOBJ pMemObjMSRBitmap;
270 /** Physical address of the MSR bitmap (1 page). */
271 RTHCPHYS pMSRBitmapPhys;
272 /** Virtual address of the MSR bitmap (1 page). */
273 R0PTRTYPE(uint8_t *) pMSRBitmap;
274
275 /** R0 memory object for the MSR entry load page (guest MSRs). */
276 RTR0MEMOBJ pMemObjMSREntryLoad;
277 /** Physical address of the MSR entry load page (guest MSRs). */
278 RTHCPHYS pMSREntryLoadPhys;
279 /** Virtual address of the MSR entry load page (guest MSRs). */
280 R0PTRTYPE(uint8_t *) pMSREntryLoad;
281
282#ifdef VBOX_WITH_CRASHDUMP_MAGIC
283 RTR0MEMOBJ pMemObjScratch;
284 RTHCPHYS pScratchPhys;
285 R0PTRTYPE(uint8_t *) pScratch;
286#endif
287 /** R0 memory object for the MSR exit store page (guest MSRs). */
288 RTR0MEMOBJ pMemObjMSRExitStore;
289 /** Physical address of the MSR exit store page (guest MSRs). */
290 RTHCPHYS pMSRExitStorePhys;
291 /** Virtual address of the MSR exit store page (guest MSRs). */
292 R0PTRTYPE(uint8_t *) pMSRExitStore;
293
294 /** R0 memory object for the MSR exit load page (host MSRs). */
295 RTR0MEMOBJ pMemObjMSRExitLoad;
296 /** Physical address of the MSR exit load page (host MSRs). */
297 RTHCPHYS pMSRExitLoadPhys;
298 /** Virtual address of the MSR exit load page (host MSRs). */
299 R0PTRTYPE(uint8_t *) pMSRExitLoad;
300
301 /** Ring 0 handlers for VT-x. */
302 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
303
304 /** Host CR4 value (set by ring-0 VMX init) */
305 uint64_t hostCR4;
306
307 /** VMX MSR values */
308 struct
309 {
310 uint64_t feature_ctrl;
311 uint64_t vmx_basic_info;
312 VMX_CAPABILITY vmx_pin_ctls;
313 VMX_CAPABILITY vmx_proc_ctls;
314 VMX_CAPABILITY vmx_proc_ctls2;
315 VMX_CAPABILITY vmx_exit;
316 VMX_CAPABILITY vmx_entry;
317 uint64_t vmx_misc;
318 uint64_t vmx_cr0_fixed0;
319 uint64_t vmx_cr0_fixed1;
320 uint64_t vmx_cr4_fixed0;
321 uint64_t vmx_cr4_fixed1;
322 uint64_t vmx_vmcs_enum;
323 uint64_t vmx_eptcaps;
324 } msr;
325
326 /** Flush types for invept & invvpid; they depend on capabilities. */
327 VMX_FLUSH enmFlushPage;
328 VMX_FLUSH enmFlushContext;
329 } vmx;
330
331 struct
332 {
333 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
334 bool fSupported;
335 /** Set when we've enabled SVM. */
336 bool fEnabled;
337 /** Set if erratum 170 affects the AMD cpu. */
338 bool fAlwaysFlushTLB;
339 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
340 * naturally. */
341 bool padding[1];
342
343 /** R0 memory object for the host VM control block (VMCB). */
344 RTR0MEMOBJ pMemObjVMCBHost;
345 /** Physical address of the host VM control block (VMCB). */
346 RTHCPHYS pVMCBHostPhys;
347 /** Virtual address of the host VM control block (VMCB). */
348 R0PTRTYPE(void *) pVMCBHost;
349
350 /** R0 memory object for the IO bitmap (12kb). */
351 RTR0MEMOBJ pMemObjIOBitmap;
352 /** Physical address of the IO bitmap (12kb). */
353 RTHCPHYS pIOBitmapPhys;
354 /** Virtual address of the IO bitmap. */
355 R0PTRTYPE(void *) pIOBitmap;
356
357 /** R0 memory object for the MSR bitmap (8kb). */
358 RTR0MEMOBJ pMemObjMSRBitmap;
359 /** Physical address of the MSR bitmap (8kb). */
360 RTHCPHYS pMSRBitmapPhys;
361 /** Virtual address of the MSR bitmap. */
362 R0PTRTYPE(void *) pMSRBitmap;
363
364 /** SVM revision. */
365 uint32_t u32Rev;
366
367 /** SVM feature bits from cpuid 0x8000000a */
368 uint32_t u32Features;
369 } svm;
370
371 struct
372 {
373 uint32_t u32AMDFeatureECX;
374 uint32_t u32AMDFeatureEDX;
375 } cpuid;
376
377 /** Saved error from detection */
378 int32_t lLastError;
379
380 /** HWACCMR0Init was run */
381 bool fHWACCMR0Init;
382} HWACCM;
383/** Pointer to HWACCM VM instance data. */
384typedef HWACCM *PHWACCM;
385
386/* Maximum number of cached entries. */
387#define VMCSCACHE_MAX_ENTRY 128
388
389/* Structure for storing read and write VMCS actions. */
390typedef struct VMCSCACHE
391{
392#ifdef VBOX_WITH_CRASHDUMP_MAGIC
393 /* Magic marker for searching in crash dumps. */
394 uint8_t aMagic[16];
395 uint64_t uMagic;
396 uint64_t u64TimeEntry;
397 uint64_t u64TimeSwitch;
398 uint64_t cResume;
399 uint64_t interPD;
400 uint64_t pSwitcher;
401 uint32_t uPos;
402 uint32_t idCpu;
403#endif
404 /* CR2 is saved here for EPT syncing. */
405 uint64_t cr2;
406 struct
407 {
408 uint32_t cValidEntries;
409 uint32_t uAlignment;
410 uint32_t aField[VMCSCACHE_MAX_ENTRY];
411 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
412 } Write;
413 struct
414 {
415 uint32_t cValidEntries;
416 uint32_t uAlignment;
417 uint32_t aField[VMCSCACHE_MAX_ENTRY];
418 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
419 } Read;
420#ifdef DEBUG
421 struct
422 {
423 RTHCPHYS pPageCpuPhys;
424 RTHCPHYS pVMCSPhys;
425 RTGCPTR pCache;
426 RTGCPTR pCtx;
427 } TestIn;
428 struct
429 {
430 RTHCPHYS pVMCSPhys;
431 RTGCPTR pCache;
432 RTGCPTR pCtx;
433 uint64_t eflags;
434 uint64_t cr8;
435 } TestOut;
436 struct
437 {
438 uint64_t param1;
439 uint64_t param2;
440 uint64_t param3;
441 uint64_t param4;
442 } ScratchPad;
443#endif
444} VMCSCACHE;
445/** Pointer to VMCSCACHE. */
446typedef VMCSCACHE *PVMCSCACHE;
447
448/**
449 * HWACCM VMCPU Instance data.
450 */
451typedef struct HWACCMCPU
452{
453 /** Old style FPU reporting trap mask override performed (optimization) */
454 bool fFPUOldStyleOverride;
455
456 /** Set if we don't have to flush the TLB on VM entry. */
457 bool fResumeVM;
458
459 /** Set if we need to flush the TLB during the world switch. */
460 bool fForceTLBFlush;
461
462 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
463 * naturally. */
464 bool padding[1];
465
466 /** HWACCM_CHANGED_* flags. */
467 RTUINT fContextUseFlags;
468
469 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
470 RTCPUID idLastCpu;
471
472 /* TLB flush count */
473 RTUINT cTLBFlushes;
474
475 /* Current ASID in use by the VM */
476 RTUINT uCurrentASID;
477
478 struct
479 {
480 /** R0 memory object for the VM control structure (VMCS). */
481 RTR0MEMOBJ pMemObjVMCS;
482 /** Physical address of the VM control structure (VMCS). */
483 RTHCPHYS pVMCSPhys;
484 /** Virtual address of the VM control structure (VMCS). */
485 R0PTRTYPE(void *) pVMCS;
486
487 /** Ring 0 handlers for VT-x. */
488 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
489
490 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
491 uint64_t proc_ctls;
492
493 /** Current CR0 mask. */
494 uint64_t cr0_mask;
495 /** Current CR4 mask. */
496 uint64_t cr4_mask;
497
498 /** Current EPTP. */
499 RTHCPHYS GCPhysEPTP;
500
501 /** VMCS cache. */
502 VMCSCACHE VMCSCache;
503
504 /** Real-mode emulation state. */
505 struct
506 {
507 X86EFLAGS eflags;
508 uint32_t fValid;
509 } RealMode;
510
511 struct
512 {
513 uint64_t u64VMCSPhys;
514 uint32_t ulVMCSRevision;
515 uint32_t ulInstrError;
516 uint32_t ulExitReason;
517 RTCPUID idEnteredCpu;
518 RTCPUID idCurrentCpu;
519 uint32_t padding;
520 } lasterror;
521
522 /** The last seen guest paging mode (by VT-x). */
523 PGMMODE enmLastSeenGuestMode;
524 /** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
525 PGMMODE enmCurrGuestMode;
526 /** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
527 PGMMODE enmPrevGuestMode;
528 } vmx;
529
530 struct
531 {
532 /** R0 memory object for the VM control block (VMCB). */
533 RTR0MEMOBJ pMemObjVMCB;
534 /** Physical address of the VM control block (VMCB). */
535 RTHCPHYS pVMCBPhys;
536 /** Virtual address of the VM control block (VMCB). */
537 R0PTRTYPE(void *) pVMCB;
538
539 /** Ring 0 handlers for VT-x. */
540 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
541
542 } svm;
543
544 /** Event injection state. */
545 struct
546 {
547 uint32_t fPending;
548 uint32_t errCode;
549 uint64_t intInfo;
550 } Event;
551
552 /** Currenty shadow paging mode. */
553 PGMMODE enmShadowMode;
554
555 /** The CPU ID of the CPU currently owning the VMCS. Set in
556 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
557 RTCPUID idEnteredCpu;
558
559 STAMPROFILEADV StatEntry;
560 STAMPROFILEADV StatExit1;
561 STAMPROFILEADV StatExit2;
562#if 1 /* temporary for tracking down darwin issues. */
563 STAMPROFILEADV StatExit2Sub1;
564 STAMPROFILEADV StatExit2Sub2;
565 STAMPROFILEADV StatExit2Sub3;
566#endif
567 STAMPROFILEADV StatInGC;
568
569#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
570 STAMPROFILEADV StatWorldSwitch3264;
571#endif
572
573 STAMCOUNTER StatIntInject;
574
575 STAMCOUNTER StatExitShadowNM;
576 STAMCOUNTER StatExitGuestNM;
577 STAMCOUNTER StatExitShadowPF;
578 STAMCOUNTER StatExitGuestPF;
579 STAMCOUNTER StatExitGuestUD;
580 STAMCOUNTER StatExitGuestSS;
581 STAMCOUNTER StatExitGuestNP;
582 STAMCOUNTER StatExitGuestGP;
583 STAMCOUNTER StatExitGuestDE;
584 STAMCOUNTER StatExitGuestDB;
585 STAMCOUNTER StatExitGuestMF;
586 STAMCOUNTER StatExitInvpg;
587 STAMCOUNTER StatExitInvd;
588 STAMCOUNTER StatExitCpuid;
589 STAMCOUNTER StatExitRdtsc;
590 STAMCOUNTER StatExitCRxWrite[16];
591 STAMCOUNTER StatExitCRxRead[16];
592 STAMCOUNTER StatExitDRxWrite;
593 STAMCOUNTER StatExitDRxRead;
594 STAMCOUNTER StatExitCLTS;
595 STAMCOUNTER StatExitLMSW;
596 STAMCOUNTER StatExitIOWrite;
597 STAMCOUNTER StatExitIORead;
598 STAMCOUNTER StatExitIOStringWrite;
599 STAMCOUNTER StatExitIOStringRead;
600 STAMCOUNTER StatExitIrqWindow;
601 STAMCOUNTER StatExitMaxResume;
602 STAMCOUNTER StatIntReinject;
603 STAMCOUNTER StatPendingHostIrq;
604
605 STAMCOUNTER StatFlushPageManual;
606 STAMCOUNTER StatFlushPhysPageManual;
607 STAMCOUNTER StatFlushTLBManual;
608 STAMCOUNTER StatFlushPageInvlpg;
609 STAMCOUNTER StatFlushTLBWorldSwitch;
610 STAMCOUNTER StatNoFlushTLBWorldSwitch;
611 STAMCOUNTER StatFlushTLBCRxChange;
612 STAMCOUNTER StatFlushASID;
613 STAMCOUNTER StatFlushTLBInvlpga;
614
615 STAMCOUNTER StatSwitchGuestIrq;
616 STAMCOUNTER StatSwitchToR3;
617
618 STAMCOUNTER StatTSCOffset;
619 STAMCOUNTER StatTSCIntercept;
620
621 STAMCOUNTER StatExitReasonNPF;
622 STAMCOUNTER StatDRxArmed;
623 STAMCOUNTER StatDRxContextSwitch;
624 STAMCOUNTER StatDRxIOCheck;
625
626
627 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
628 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
629} HWACCMCPU;
630/** Pointer to HWACCM VM instance data. */
631typedef HWACCMCPU *PHWACCMCPU;
632
633
634#ifdef IN_RING0
635
636VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
637VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
638
639
640#ifdef VBOX_STRICT
641VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
642VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
643#else
644#define HWACCMDumpRegs(a, b) do { } while (0)
645#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
646#endif
647
648/* Dummy callback handlers. */
649VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
650VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
651VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
652VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
653VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
654VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
655VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
656VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
657VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
658VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
659
660
661# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
662/**
663 * Gets 64-bit GDTR and IDTR on darwin.
664 * @param pGdtr Where to store the 64-bit GDTR.
665 * @param pIdtr Where to store the 64-bit IDTR.
666 */
667DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
668
669/**
670 * Gets 64-bit CR3 on darwin.
671 * @returns CR3
672 */
673DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
674# endif
675
676#endif /* IN_RING0 */
677
678/** @} */
679
680__END_DECLS
681
682#endif
683
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use