VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 28800

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1/* $Id: HWACCM.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/cpum.h>
23#include <VBox/stam.h>
24#include <VBox/mm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/pgm.h>
27#include <VBox/ssm.h>
28#include <VBox/trpm.h>
29#include <VBox/dbgf.h>
30#include <VBox/iom.h>
31#include <VBox/patm.h>
32#include <VBox/csam.h>
33#include <VBox/selm.h>
34#include <VBox/rem.h>
35#include <VBox/hwacc_vmx.h>
36#include <VBox/hwacc_svm.h>
37#include "HWACCMInternal.h"
38#include <VBox/vm.h>
39#include <VBox/err.h>
40#include <VBox/param.h>
41
42#include <iprt/assert.h>
43#include <VBox/log.h>
44#include <iprt/asm.h>
45#include <iprt/string.h>
46#include <iprt/env.h>
47#include <iprt/thread.h>
48
49/*******************************************************************************
50* Global Variables *
51*******************************************************************************/
52#ifdef VBOX_WITH_STATISTICS
53# define EXIT_REASON(def, val, str) #def " - " #val " - " str
54# define EXIT_REASON_NIL() NULL
55/** Exit reason descriptions for VT-x, used to describe statistics. */
56static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
57{
58 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
59 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
60 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
61 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
62 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
63 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
64 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
65 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
66 EXIT_REASON_NIL(),
67 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
68 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
71 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
72 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
73 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
74 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
75 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
76 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
77 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
78 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
79 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
80 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
81 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
82 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
83 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
84 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
85 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
86 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
87 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
88 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
89 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
90 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
91 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
92 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
93 EXIT_REASON_NIL(),
94 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
95 EXIT_REASON_NIL(),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
98 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
99 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
102 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
105 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
106 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
107 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
108 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
111 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
112 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
113 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
114 EXIT_REASON_NIL()
115};
116/** Exit reason descriptions for AMD-V, used to describe statistics. */
117static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
118{
119 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
120 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
121 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
122 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
123 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
124 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
125 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
126 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
127 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
128 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
129 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
130 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
131 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
132 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
133 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
134 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
135 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
151 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
152 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
153 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
154 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
155 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
156 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
157 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
158 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
159 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
160 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
161 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
162 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
163 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
164 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
165 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
166 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
167 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
183 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
229 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
230 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
231 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
232 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
233 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
234 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
235 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
236 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
237 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
238 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
239 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
240 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
242 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
243 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
244 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
245 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
246 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
247 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
248 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
258 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
259 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
260 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
261 EXIT_REASON_NIL()
262};
263# undef EXIT_REASON
264# undef EXIT_REASON_NIL
265#endif /* VBOX_WITH_STATISTICS */
266
267/*******************************************************************************
268* Internal Functions *
269*******************************************************************************/
270static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
271static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
272
273
274/**
275 * Initializes the HWACCM.
276 *
277 * @returns VBox status code.
278 * @param pVM The VM to operate on.
279 */
280VMMR3DECL(int) HWACCMR3Init(PVM pVM)
281{
282 LogFlow(("HWACCMR3Init\n"));
283
284 /*
285 * Assert alignment and sizes.
286 */
287 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
288 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
289
290 /* Some structure checks. */
291 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
295
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
302 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
303
304
305 /*
306 * Register the saved state data unit.
307 */
308 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
309 NULL, NULL, NULL,
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322 pVM->hwaccm.s.fLargePages = false;
323
324 /* Disabled by default. */
325 pVM->fHWACCMEnabled = false;
326
327 /*
328 * Check CFGM options.
329 */
330 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
331 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
332 /* Nested paging: disabled by default. */
333 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
334 AssertRC(rc);
335
336 /* Large pages: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
338 AssertRC(rc);
339
340 /* VT-x VPID: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
342 AssertRC(rc);
343
344 /* HWACCM support must be explicitely enabled in the configuration file. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
346 AssertRC(rc);
347
348 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
350 AssertRC(rc);
351
352#ifdef RT_OS_DARWIN
353 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
354#else
355 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
356#endif
357 {
358 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
359 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
360 return VERR_HWACCM_CONFIG_MISMATCH;
361 }
362
363 if (VMMIsHwVirtExtForced(pVM))
364 pVM->fHWACCMEnabled = true;
365
366#if HC_ARCH_BITS == 32
367 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
368 * (To use the default, don't set 64bitEnabled in CFGM.) */
369 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
370 AssertLogRelRCReturn(rc, rc);
371 if (pVM->hwaccm.s.fAllow64BitGuests)
372 {
373# ifdef RT_OS_DARWIN
374 if (!VMMIsHwVirtExtForced(pVM))
375# else
376 if (!pVM->hwaccm.s.fAllowed)
377# endif
378 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
379 }
380#else
381 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
382 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
383 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
384 AssertLogRelRCReturn(rc, rc);
385#endif
386
387
388 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
389 * or local init each time we wish to execute guest code.
390 *
391 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
392 */
393 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
394#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
395 false
396#else
397 true
398#endif
399 );
400
401 /* Max number of resume loops. */
402 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
403 AssertRC(rc);
404
405 return VINF_SUCCESS;
406}
407
408/**
409 * Initializes the per-VCPU HWACCM.
410 *
411 * @returns VBox status code.
412 * @param pVM The VM to operate on.
413 */
414VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
415{
416 LogFlow(("HWACCMR3InitCPU\n"));
417
418 for (VMCPUID i = 0; i < pVM->cCpus; i++)
419 {
420 PVMCPU pVCpu = &pVM->aCpus[i];
421
422 pVCpu->hwaccm.s.fActive = false;
423 }
424
425#ifdef VBOX_WITH_STATISTICS
426 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
427 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
428 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
429 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
430
431 /*
432 * Statistics.
433 */
434 for (VMCPUID i = 0; i < pVM->cCpus; i++)
435 {
436 PVMCPU pVCpu = &pVM->aCpus[i];
437 int rc;
438
439 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
440 "/PROF/HWACCM/CPU%d/Poke", i);
441 AssertRC(rc);
442 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
443 "/PROF/HWACCM/CPU%d/PokeWait", i);
444 AssertRC(rc);
445 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
446 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
447 AssertRC(rc);
448 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
449 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
450 AssertRC(rc);
451 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
452 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
453 AssertRC(rc);
454 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
455 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
456 AssertRC(rc);
457# if 1 /* temporary for tracking down darwin holdup. */
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
460 AssertRC(rc);
461 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
462 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
463 AssertRC(rc);
464 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
465 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
466 AssertRC(rc);
467# endif
468 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
469 "/PROF/HWACCM/CPU%d/InGC", i);
470 AssertRC(rc);
471
472# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
473 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
474 "/PROF/HWACCM/CPU%d/Switcher3264", i);
475 AssertRC(rc);
476# endif
477
478# define HWACCM_REG_COUNTER(a, b) \
479 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
480 AssertRC(rc);
481
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
520
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
523
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
527
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
541
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
545
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
549
550 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
551 {
552 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
553 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
554 AssertRC(rc);
555 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
556 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
557 AssertRC(rc);
558 }
559
560#undef HWACCM_REG_COUNTER
561
562 pVCpu->hwaccm.s.paStatExitReason = NULL;
563
564 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
565 AssertRC(rc);
566 if (RT_SUCCESS(rc))
567 {
568 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
569 for (int j=0;j<MAX_EXITREASON_STAT;j++)
570 {
571 if (papszDesc[j])
572 {
573 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
574 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
575 AssertRC(rc);
576 }
577 }
578 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
579 AssertRC(rc);
580 }
581 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
582# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
583 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
584# else
585 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
586# endif
587
588 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
589 AssertRCReturn(rc, rc);
590 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
591# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
592 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
593# else
594 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
595# endif
596 for (unsigned j = 0; j < 255; j++)
597 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
598 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
599
600 }
601#endif /* VBOX_WITH_STATISTICS */
602
603#ifdef VBOX_WITH_CRASHDUMP_MAGIC
604 /* Magic marker for searching in crash dumps. */
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
606 {
607 PVMCPU pVCpu = &pVM->aCpus[i];
608
609 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
610 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
611 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
612 }
613#endif
614 return VINF_SUCCESS;
615}
616
617/**
618 * Turns off normal raw mode features
619 *
620 * @param pVM The VM to operate on.
621 */
622static void hwaccmR3DisableRawMode(PVM pVM)
623{
624 /* Disable PATM & CSAM. */
625 PATMR3AllowPatching(pVM, false);
626 CSAMDisableScanning(pVM);
627
628 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
629 SELMR3DisableMonitoring(pVM);
630 TRPMR3DisableMonitoring(pVM);
631
632 /* Disable the switcher code (safety precaution). */
633 VMMR3DisableSwitcher(pVM);
634
635 /* Disable mapping of the hypervisor into the shadow page table. */
636 PGMR3MappingsDisable(pVM);
637
638 /* Disable the switcher */
639 VMMR3DisableSwitcher(pVM);
640
641 /* Reinit the paging mode to force the new shadow mode. */
642 for (VMCPUID i = 0; i < pVM->cCpus; i++)
643 {
644 PVMCPU pVCpu = &pVM->aCpus[i];
645
646 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
647 }
648}
649
650/**
651 * Initialize VT-x or AMD-V.
652 *
653 * @returns VBox status code.
654 * @param pVM The VM handle.
655 */
656VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
657{
658 int rc;
659
660 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
661 * is already using AMD-V.
662 */
663 if ( !pVM->hwaccm.s.vmx.fSupported
664 && !pVM->hwaccm.s.svm.fSupported
665 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
666 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
667 {
668 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
669 pVM->hwaccm.s.svm.fSupported = true;
670 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
671 }
672 else
673 if ( !pVM->hwaccm.s.vmx.fSupported
674 && !pVM->hwaccm.s.svm.fSupported)
675 {
676 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
677 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
678
679 if (VMMIsHwVirtExtForced(pVM))
680 {
681 switch (pVM->hwaccm.s.lLastError)
682 {
683 case VERR_VMX_NO_VMX:
684 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
685 case VERR_VMX_IN_VMX_ROOT_MODE:
686 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
687 case VERR_SVM_IN_USE:
688 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
689 case VERR_SVM_NO_SVM:
690 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
691 case VERR_SVM_DISABLED:
692 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
693 default:
694 return pVM->hwaccm.s.lLastError;
695 }
696 }
697 return VINF_SUCCESS;
698 }
699
700 if (pVM->hwaccm.s.vmx.fSupported)
701 {
702 rc = SUPR3QueryVTxSupported();
703 if (RT_FAILURE(rc))
704 {
705#ifdef RT_OS_LINUX
706 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
707#else
708 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
709#endif
710 if ( pVM->cCpus > 1
711 || VMMIsHwVirtExtForced(pVM))
712 return rc;
713
714 /* silently fall back to raw mode */
715 return VINF_SUCCESS;
716 }
717 }
718
719 if (!pVM->hwaccm.s.fAllowed)
720 return VINF_SUCCESS; /* nothing to do */
721
722 /* Enable VT-x or AMD-V on all host CPUs. */
723 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
724 if (RT_FAILURE(rc))
725 {
726 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
727 return rc;
728 }
729 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
730
731 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
732 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
733 if (!pVM->hwaccm.s.fHasIoApic)
734 {
735 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
736 pVM->hwaccm.s.fTRPPatchingAllowed = false;
737 }
738
739 if (pVM->hwaccm.s.vmx.fSupported)
740 {
741 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
742
743 if ( pVM->hwaccm.s.fInitialized == false
744 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
745 {
746 uint64_t val;
747 RTGCPHYS GCPhys = 0;
748
749 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
750 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
751 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
752 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
753 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
754 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
755 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
756 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
757
758 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
759 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
760 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
761 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
762 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
763 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
764 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
766 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
767 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
768 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
769 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
771 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
773 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
775 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
776 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
777
778 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
779 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
780 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
806 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
807 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
808 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
810 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
812 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
814 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
816 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
818 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
820 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
822
823 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
824 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
826 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
828 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
830 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
832 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
833 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
866
867 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
868 {
869 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
870 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
871 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
875 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
877 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
879 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
887 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
888 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
889
890 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
891 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
892 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
894 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
900 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
906 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
907 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
908 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
909 }
910
911 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
912 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
913 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
914 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
915 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
916 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
917 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
919 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
920 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
921 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
922 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
923 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
924 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
925 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
926 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
927 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
930 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
934 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
936 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
937 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
938 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
939 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
940 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
941 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
942
943 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
944 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
945 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
947 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
949 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
951 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
953 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
955 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
957 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
958 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
959 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
960 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
961 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
964 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
965 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
968 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
970 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
972 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
974 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
975 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
976 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
977 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
978
979 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
980 {
981 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
982
983 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
984 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
985 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
986 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
987 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
988 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
989 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
990 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
991 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
992 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
993 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
994 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
995 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
996 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
997 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
998 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
999 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1000 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1001 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1002 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1003 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1004 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1005 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1006 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1007 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1008 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1009 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1010 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1011 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1012 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1013 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1014 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1015 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1016 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1017 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1018 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1019 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1020 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1021 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1022 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1023 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1024 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1025 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1026 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1027 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1028 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1029 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1030 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1031 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1032 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1033 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1034 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1035 }
1036
1037 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1038 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1039 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1040 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1041 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1042 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1043
1044 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1045 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1046 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1047 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1048 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1049
1050 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1051
1052 /* Paranoia */
1053 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1054
1055 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1056 {
1057 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1058 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1059 }
1060
1061#ifdef HWACCM_VTX_WITH_EPT
1062 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1063 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1064#endif /* HWACCM_VTX_WITH_EPT */
1065#ifdef HWACCM_VTX_WITH_VPID
1066 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1067 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1068 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1069#endif /* HWACCM_VTX_WITH_VPID */
1070
1071 /* Unrestricted guest execution relies on EPT. */
1072 if ( pVM->hwaccm.s.fNestedPaging
1073 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1074 {
1075 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1076 }
1077
1078 /* Only try once. */
1079 pVM->hwaccm.s.fInitialized = true;
1080
1081 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1082 {
1083 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1084 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1085 if (RT_SUCCESS(rc))
1086 {
1087 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1088 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1089 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1090 /* Bit set to 0 means redirection enabled. */
1091 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1092 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1093 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1094 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1095
1096 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1097 * real and protected mode without paging with EPT.
1098 */
1099 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1100 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1101 {
1102 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1103 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1104 }
1105
1106 /* We convert it here every time as pci regions could be reconfigured. */
1107 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1108 AssertRC(rc);
1109 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1110
1111 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1112 AssertRC(rc);
1113 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1114 }
1115 else
1116 {
1117 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1118 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1119 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1120 }
1121 }
1122
1123 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1124 AssertRC(rc);
1125 if (rc == VINF_SUCCESS)
1126 {
1127 pVM->fHWACCMEnabled = true;
1128 pVM->hwaccm.s.vmx.fEnabled = true;
1129 hwaccmR3DisableRawMode(pVM);
1130
1131 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1132#ifdef VBOX_ENABLE_64_BITS_GUESTS
1133 if (pVM->hwaccm.s.fAllow64BitGuests)
1134 {
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1136 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1137 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1138 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1139 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1140 }
1141 else
1142 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1143 /* Todo: this needs to be fixed properly!! */
1144 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1145 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1146 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1147
1148 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1149 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1150 : "HWACCM: 32-bit guests supported.\n"));
1151#else
1152 LogRel(("HWACCM: 32-bit guests supported.\n"));
1153#endif
1154 LogRel(("HWACCM: VMX enabled!\n"));
1155 if (pVM->hwaccm.s.fNestedPaging)
1156 {
1157 LogRel(("HWACCM: Enabled nested paging\n"));
1158 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1159 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1160 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1161
1162#if HC_ARCH_BITS == 64
1163 if (pVM->hwaccm.s.fLargePages)
1164 {
1165 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1166 PGMSetLargePageUsage(pVM, true);
1167 LogRel(("HWACCM: Large page support enabled!\n"));
1168 }
1169#endif
1170 }
1171 else
1172 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1173
1174 if (pVM->hwaccm.s.vmx.fVPID)
1175 LogRel(("HWACCM: Enabled VPID\n"));
1176
1177 if ( pVM->hwaccm.s.fNestedPaging
1178 || pVM->hwaccm.s.vmx.fVPID)
1179 {
1180 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1181 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1182 }
1183
1184 /* TPR patching status logging. */
1185 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1186 {
1187 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1188 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1189 {
1190 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1191 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1192 }
1193 else
1194 {
1195 uint32_t u32Eax, u32Dummy;
1196
1197 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1198 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1199 if ( u32Eax < 0x80000001
1200 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1201 {
1202 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1203 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1204 }
1205 }
1206 }
1207 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1208 }
1209 else
1210 {
1211 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1212 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1213 pVM->fHWACCMEnabled = false;
1214 }
1215 }
1216 }
1217 else
1218 if (pVM->hwaccm.s.svm.fSupported)
1219 {
1220 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1221
1222 if (pVM->hwaccm.s.fInitialized == false)
1223 {
1224 /* Erratum 170 which requires a forced TLB flush for each world switch:
1225 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1226 *
1227 * All BH-G1/2 and DH-G1/2 models include a fix:
1228 * Athlon X2: 0x6b 1/2
1229 * 0x68 1/2
1230 * Athlon 64: 0x7f 1
1231 * 0x6f 2
1232 * Sempron: 0x7f 1/2
1233 * 0x6f 2
1234 * 0x6c 2
1235 * 0x7c 2
1236 * Turion 64: 0x68 2
1237 *
1238 */
1239 uint32_t u32Dummy;
1240 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1241 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1242 u32BaseFamily= (u32Version >> 8) & 0xf;
1243 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1244 u32Model = ((u32Version >> 4) & 0xf);
1245 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1246 u32Stepping = u32Version & 0xf;
1247 if ( u32Family == 0xf
1248 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1249 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1250 {
1251 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1252 }
1253
1254 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1255 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1256 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1257 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1258 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1259 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1260
1261 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1262 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1263 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1264 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1265 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1266 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1267 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1268 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1269 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1270 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1271 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1272 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1273
1274 /* Only try once. */
1275 pVM->hwaccm.s.fInitialized = true;
1276
1277 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1278 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1279
1280 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1281 AssertRC(rc);
1282 if (rc == VINF_SUCCESS)
1283 {
1284 pVM->fHWACCMEnabled = true;
1285 pVM->hwaccm.s.svm.fEnabled = true;
1286
1287 if (pVM->hwaccm.s.fNestedPaging)
1288 {
1289 LogRel(("HWACCM: Enabled nested paging\n"));
1290#if HC_ARCH_BITS == 64
1291 if (pVM->hwaccm.s.fLargePages)
1292 {
1293 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1294 PGMSetLargePageUsage(pVM, true);
1295 LogRel(("HWACCM: Large page support enabled!\n"));
1296 }
1297#endif
1298 }
1299
1300 hwaccmR3DisableRawMode(pVM);
1301 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1302 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1303 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1304#ifdef VBOX_ENABLE_64_BITS_GUESTS
1305 if (pVM->hwaccm.s.fAllow64BitGuests)
1306 {
1307 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1308 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1309 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1311 }
1312 else
1313 /* Turn on NXE if PAE has been enabled. */
1314 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1315 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1316#endif
1317
1318 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1319 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1320 : "HWACCM: 32-bit guest supported.\n"));
1321
1322 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1323 }
1324 else
1325 {
1326 pVM->fHWACCMEnabled = false;
1327 }
1328 }
1329 }
1330 if (pVM->fHWACCMEnabled)
1331 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1332 return VINF_SUCCESS;
1333}
1334
1335/**
1336 * Applies relocations to data and code managed by this
1337 * component. This function will be called at init and
1338 * whenever the VMM need to relocate it self inside the GC.
1339 *
1340 * @param pVM The VM.
1341 */
1342VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1343{
1344 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1345
1346 /* Fetch the current paging mode during the relocate callback during state loading. */
1347 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1348 {
1349 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1350 {
1351 PVMCPU pVCpu = &pVM->aCpus[i];
1352
1353 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1354 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1355 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1356 }
1357 }
1358#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1359 if (pVM->fHWACCMEnabled)
1360 {
1361 int rc;
1362
1363 switch(PGMGetHostMode(pVM))
1364 {
1365 case PGMMODE_32_BIT:
1366 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1367 break;
1368
1369 case PGMMODE_PAE:
1370 case PGMMODE_PAE_NX:
1371 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1372 break;
1373
1374 default:
1375 AssertFailed();
1376 break;
1377 }
1378 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1379 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1380
1381 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1382 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1383
1384 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1385 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1386
1387 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1388 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1389
1390# ifdef DEBUG
1391 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1392 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1393# endif
1394 }
1395#endif
1396 return;
1397}
1398
1399/**
1400 * Checks hardware accelerated raw mode is allowed.
1401 *
1402 * @returns boolean
1403 * @param pVM The VM to operate on.
1404 */
1405VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1406{
1407 return pVM->hwaccm.s.fAllowed;
1408}
1409
1410/**
1411 * Notification callback which is called whenever there is a chance that a CR3
1412 * value might have changed.
1413 *
1414 * This is called by PGM.
1415 *
1416 * @param pVM The VM to operate on.
1417 * @param pVCpu The VMCPU to operate on.
1418 * @param enmShadowMode New shadow paging mode.
1419 * @param enmGuestMode New guest paging mode.
1420 */
1421VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1422{
1423 /* Ignore page mode changes during state loading. */
1424 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1425 return;
1426
1427 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1428
1429 if ( pVM->hwaccm.s.vmx.fEnabled
1430 && pVM->fHWACCMEnabled)
1431 {
1432 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1433 && enmGuestMode >= PGMMODE_PROTECTED)
1434 {
1435 PCPUMCTX pCtx;
1436
1437 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1438
1439 /* After a real mode switch to protected mode we must force
1440 * CPL to 0. Our real mode emulation had to set it to 3.
1441 */
1442 pCtx->ssHid.Attr.n.u2Dpl = 0;
1443 }
1444 }
1445
1446 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1447 {
1448 /* Keep track of paging mode changes. */
1449 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1450 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1451
1452 /* Did we miss a change, because all code was executed in the recompiler? */
1453 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1454 {
1455 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1456 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1457 }
1458 }
1459
1460 /* Reset the contents of the read cache. */
1461 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1462 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1463 pCache->Read.aFieldVal[j] = 0;
1464}
1465
1466/**
1467 * Terminates the HWACCM.
1468 *
1469 * Termination means cleaning up and freeing all resources,
1470 * the VM it self is at this point powered off or suspended.
1471 *
1472 * @returns VBox status code.
1473 * @param pVM The VM to operate on.
1474 */
1475VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1476{
1477 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1478 {
1479 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1480 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1481 }
1482 HWACCMR3TermCPU(pVM);
1483 return 0;
1484}
1485
1486/**
1487 * Terminates the per-VCPU HWACCM.
1488 *
1489 * Termination means cleaning up and freeing all resources,
1490 * the VM it self is at this point powered off or suspended.
1491 *
1492 * @returns VBox status code.
1493 * @param pVM The VM to operate on.
1494 */
1495VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1496{
1497 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1498 {
1499 PVMCPU pVCpu = &pVM->aCpus[i];
1500
1501#ifdef VBOX_WITH_STATISTICS
1502 if (pVCpu->hwaccm.s.paStatExitReason)
1503 {
1504 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1505 pVCpu->hwaccm.s.paStatExitReason = NULL;
1506 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1507 }
1508 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1509 {
1510 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1511 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1512 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1513 }
1514#endif
1515
1516#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1517 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1518 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1519 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1520#endif
1521 }
1522 return 0;
1523}
1524
1525/**
1526 * Resets a virtual CPU.
1527 *
1528 * Used by HWACCMR3Reset and CPU hot plugging.
1529 *
1530 * @param pVCpu The CPU to reset.
1531 */
1532VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1533{
1534 /* On first entry we'll sync everything. */
1535 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1536
1537 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1538 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1539
1540 pVCpu->hwaccm.s.fActive = false;
1541 pVCpu->hwaccm.s.Event.fPending = false;
1542
1543 /* Reset state information for real-mode emulation in VT-x. */
1544 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1545 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1546 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1547
1548 /* Reset the contents of the read cache. */
1549 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1550 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1551 pCache->Read.aFieldVal[j] = 0;
1552
1553#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1554 /* Magic marker for searching in crash dumps. */
1555 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1556 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1557#endif
1558}
1559
1560/**
1561 * The VM is being reset.
1562 *
1563 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1564 * needs to be removed.
1565 *
1566 * @param pVM VM handle.
1567 */
1568VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1569{
1570 LogFlow(("HWACCMR3Reset:\n"));
1571
1572 if (pVM->fHWACCMEnabled)
1573 hwaccmR3DisableRawMode(pVM);
1574
1575 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1576 {
1577 PVMCPU pVCpu = &pVM->aCpus[i];
1578
1579 HWACCMR3ResetCpu(pVCpu);
1580 }
1581
1582 /* Clear all patch information. */
1583 pVM->hwaccm.s.pGuestPatchMem = 0;
1584 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1585 pVM->hwaccm.s.cbGuestPatchMem = 0;
1586 pVM->hwaccm.s.cPatches = 0;
1587 pVM->hwaccm.s.PatchTree = 0;
1588 pVM->hwaccm.s.fTPRPatchingActive = false;
1589 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1590}
1591
1592/**
1593 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1594 *
1595 * @returns VBox strict status code.
1596 * @param pVM The VM handle.
1597 * @param pVCpu The VMCPU for the EMT we're being called on.
1598 * @param pvUser Unused
1599 *
1600 */
1601DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1602{
1603 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1604
1605 /* Only execute the handler on the VCPU the original patch request was issued. */
1606 if (pVCpu->idCpu != idCpu)
1607 return VINF_SUCCESS;
1608
1609 Log(("hwaccmR3RemovePatches\n"));
1610 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1611 {
1612 uint8_t szInstr[15];
1613 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1614 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1615 int rc;
1616
1617#ifdef LOG_ENABLED
1618 char szOutput[256];
1619
1620 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1621 if (RT_SUCCESS(rc))
1622 Log(("Patched instr: %s\n", szOutput));
1623#endif
1624
1625 /* Check if the instruction is still the same. */
1626 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1627 if (rc != VINF_SUCCESS)
1628 {
1629 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1630 continue; /* swapped out or otherwise removed; skip it. */
1631 }
1632
1633 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1634 {
1635 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1636 continue; /* skip it. */
1637 }
1638
1639 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1640 AssertRC(rc);
1641
1642#ifdef LOG_ENABLED
1643 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1644 if (RT_SUCCESS(rc))
1645 Log(("Original instr: %s\n", szOutput));
1646#endif
1647 }
1648 pVM->hwaccm.s.cPatches = 0;
1649 pVM->hwaccm.s.PatchTree = 0;
1650 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1651 pVM->hwaccm.s.fTPRPatchingActive = false;
1652 return VINF_SUCCESS;
1653}
1654
1655/**
1656 * Enable patching in a VT-x/AMD-V guest
1657 *
1658 * @returns VBox status code.
1659 * @param pVM The VM to operate on.
1660 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1661 * @param pPatchMem Patch memory range
1662 * @param cbPatchMem Size of the memory range
1663 */
1664int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1665{
1666 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1667 AssertRC(rc);
1668
1669 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1670 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1671 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1672 return VINF_SUCCESS;
1673}
1674
1675/**
1676 * Enable patching in a VT-x/AMD-V guest
1677 *
1678 * @returns VBox status code.
1679 * @param pVM The VM to operate on.
1680 * @param pPatchMem Patch memory range
1681 * @param cbPatchMem Size of the memory range
1682 */
1683VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1684{
1685 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1686 if (pVM->cCpus > 1)
1687 {
1688 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1689 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1690 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1691 AssertRC(rc);
1692 return rc;
1693 }
1694 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1695}
1696
1697/**
1698 * Disable patching in a VT-x/AMD-V guest
1699 *
1700 * @returns VBox status code.
1701 * @param pVM The VM to operate on.
1702 * @param pPatchMem Patch memory range
1703 * @param cbPatchMem Size of the memory range
1704 */
1705VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1706{
1707 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1708
1709 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1710 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1711
1712 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1713 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1714 AssertRC(rc);
1715
1716 pVM->hwaccm.s.pGuestPatchMem = 0;
1717 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1718 pVM->hwaccm.s.cbGuestPatchMem = 0;
1719 pVM->hwaccm.s.fTPRPatchingActive = false;
1720 return VINF_SUCCESS;
1721}
1722
1723
1724/**
1725 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1726 *
1727 * @returns VBox strict status code.
1728 * @param pVM The VM handle.
1729 * @param pVCpu The VMCPU for the EMT we're being called on.
1730 * @param pvUser User specified CPU context
1731 *
1732 */
1733DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1734{
1735 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1736 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1737 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1738 unsigned cbOp;
1739
1740 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1741 if (pVCpu->idCpu != idCpu)
1742 return VINF_SUCCESS;
1743
1744 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1745
1746 /* Two or more VCPUs were racing to patch this instruction. */
1747 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1748 if (pPatch)
1749 return VINF_SUCCESS;
1750
1751 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1752
1753 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1754 AssertRC(rc);
1755 if ( rc == VINF_SUCCESS
1756 && pDis->pCurInstr->opcode == OP_MOV
1757 && cbOp >= 3)
1758 {
1759 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1760 uint32_t idx = pVM->hwaccm.s.cPatches;
1761
1762 pPatch = &pVM->hwaccm.s.aPatches[idx];
1763
1764 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1765 AssertRC(rc);
1766
1767 pPatch->cbOp = cbOp;
1768
1769 if (pDis->param1.flags == USE_DISPLACEMENT32)
1770 {
1771 /* write. */
1772 if (pDis->param2.flags == USE_REG_GEN32)
1773 {
1774 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1775 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1776 }
1777 else
1778 {
1779 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1780 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1781 pPatch->uSrcOperand = pDis->param2.parval;
1782 }
1783 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1784 AssertRC(rc);
1785
1786 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1787 pPatch->cbNewOp = sizeof(aVMMCall);
1788 }
1789 else
1790 {
1791 RTGCPTR oldrip = pCtx->rip;
1792 uint32_t oldcbOp = cbOp;
1793 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1794
1795 /* read */
1796 Assert(pDis->param1.flags == USE_REG_GEN32);
1797
1798 /* Found:
1799 * mov eax, dword [fffe0080] (5 bytes)
1800 * Check if next instruction is:
1801 * shr eax, 4
1802 */
1803 pCtx->rip += cbOp;
1804 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1805 pCtx->rip = oldrip;
1806 if ( rc == VINF_SUCCESS
1807 && pDis->pCurInstr->opcode == OP_SHR
1808 && pDis->param1.flags == USE_REG_GEN32
1809 && pDis->param1.base.reg_gen == uMmioReg
1810 && pDis->param2.flags == USE_IMMEDIATE8
1811 && pDis->param2.parval == 4
1812 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1813 {
1814 uint8_t szInstr[15];
1815
1816 /* Replacing two instructions now. */
1817 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1818 AssertRC(rc);
1819
1820 pPatch->cbOp = oldcbOp + cbOp;
1821
1822 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1823 szInstr[0] = 0xF0;
1824 szInstr[1] = 0x0F;
1825 szInstr[2] = 0x20;
1826 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1827 for (unsigned i = 4; i < pPatch->cbOp; i++)
1828 szInstr[i] = 0x90; /* nop */
1829
1830 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1831 AssertRC(rc);
1832
1833 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1834 pPatch->cbNewOp = pPatch->cbOp;
1835
1836 Log(("Acceptable read/shr candidate!\n"));
1837 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1838 }
1839 else
1840 {
1841 pPatch->enmType = HWACCMTPRINSTR_READ;
1842 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1843
1844 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1845 AssertRC(rc);
1846
1847 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1848 pPatch->cbNewOp = sizeof(aVMMCall);
1849 }
1850 }
1851
1852 pPatch->Core.Key = pCtx->eip;
1853 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1854 AssertRC(rc);
1855
1856 pVM->hwaccm.s.cPatches++;
1857 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1858 return VINF_SUCCESS;
1859 }
1860
1861 /* Save invalid patch, so we will not try again. */
1862 uint32_t idx = pVM->hwaccm.s.cPatches;
1863
1864#ifdef LOG_ENABLED
1865 char szOutput[256];
1866 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1867 if (RT_SUCCESS(rc))
1868 Log(("Failed to patch instr: %s\n", szOutput));
1869#endif
1870
1871 pPatch = &pVM->hwaccm.s.aPatches[idx];
1872 pPatch->Core.Key = pCtx->eip;
1873 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1874 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1875 AssertRC(rc);
1876 pVM->hwaccm.s.cPatches++;
1877 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1878 return VINF_SUCCESS;
1879}
1880
1881/**
1882 * Callback to patch a TPR instruction (jump to generated code)
1883 *
1884 * @returns VBox strict status code.
1885 * @param pVM The VM handle.
1886 * @param pVCpu The VMCPU for the EMT we're being called on.
1887 * @param pvUser User specified CPU context
1888 *
1889 */
1890DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1891{
1892 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1893 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1894 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1895 unsigned cbOp;
1896 int rc;
1897#ifdef LOG_ENABLED
1898 RTGCPTR pInstr;
1899 char szOutput[256];
1900#endif
1901
1902 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1903 if (pVCpu->idCpu != idCpu)
1904 return VINF_SUCCESS;
1905
1906 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1907
1908 /* Two or more VCPUs were racing to patch this instruction. */
1909 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1910 if (pPatch)
1911 {
1912 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1913 return VINF_SUCCESS;
1914 }
1915
1916 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1917
1918 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1919 AssertRC(rc);
1920 if ( rc == VINF_SUCCESS
1921 && pDis->pCurInstr->opcode == OP_MOV
1922 && cbOp >= 5)
1923 {
1924 uint32_t idx = pVM->hwaccm.s.cPatches;
1925 uint8_t aPatch[64];
1926 uint32_t off = 0;
1927
1928 pPatch = &pVM->hwaccm.s.aPatches[idx];
1929
1930#ifdef LOG_ENABLED
1931 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1932 if (RT_SUCCESS(rc))
1933 Log(("Original instr: %s\n", szOutput));
1934#endif
1935
1936 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1937 AssertRC(rc);
1938
1939 pPatch->cbOp = cbOp;
1940 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1941
1942 if (pDis->param1.flags == USE_DISPLACEMENT32)
1943 {
1944 /*
1945 * TPR write:
1946 *
1947 * push ECX [51]
1948 * push EDX [52]
1949 * push EAX [50]
1950 * xor EDX,EDX [31 D2]
1951 * mov EAX,EAX [89 C0]
1952 * or
1953 * mov EAX,0000000CCh [B8 CC 00 00 00]
1954 * mov ECX,0C0000082h [B9 82 00 00 C0]
1955 * wrmsr [0F 30]
1956 * pop EAX [58]
1957 * pop EDX [5A]
1958 * pop ECX [59]
1959 * jmp return_address [E9 return_address]
1960 *
1961 */
1962 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1963
1964 aPatch[off++] = 0x51; /* push ecx */
1965 aPatch[off++] = 0x52; /* push edx */
1966 if (!fUsesEax)
1967 aPatch[off++] = 0x50; /* push eax */
1968 aPatch[off++] = 0x31; /* xor edx, edx */
1969 aPatch[off++] = 0xD2;
1970 if (pDis->param2.flags == USE_REG_GEN32)
1971 {
1972 if (!fUsesEax)
1973 {
1974 aPatch[off++] = 0x89; /* mov eax, src_reg */
1975 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1976 }
1977 }
1978 else
1979 {
1980 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1981 aPatch[off++] = 0xB8; /* mov eax, immediate */
1982 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1983 off += sizeof(uint32_t);
1984 }
1985 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1986 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1987 off += sizeof(uint32_t);
1988
1989 aPatch[off++] = 0x0F; /* wrmsr */
1990 aPatch[off++] = 0x30;
1991 if (!fUsesEax)
1992 aPatch[off++] = 0x58; /* pop eax */
1993 aPatch[off++] = 0x5A; /* pop edx */
1994 aPatch[off++] = 0x59; /* pop ecx */
1995 }
1996 else
1997 {
1998 /*
1999 * TPR read:
2000 *
2001 * push ECX [51]
2002 * push EDX [52]
2003 * push EAX [50]
2004 * mov ECX,0C0000082h [B9 82 00 00 C0]
2005 * rdmsr [0F 32]
2006 * mov EAX,EAX [89 C0]
2007 * pop EAX [58]
2008 * pop EDX [5A]
2009 * pop ECX [59]
2010 * jmp return_address [E9 return_address]
2011 *
2012 */
2013 Assert(pDis->param1.flags == USE_REG_GEN32);
2014
2015 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2016 aPatch[off++] = 0x51; /* push ecx */
2017 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2018 aPatch[off++] = 0x52; /* push edx */
2019 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2020 aPatch[off++] = 0x50; /* push eax */
2021
2022 aPatch[off++] = 0x31; /* xor edx, edx */
2023 aPatch[off++] = 0xD2;
2024
2025 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2026 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2027 off += sizeof(uint32_t);
2028
2029 aPatch[off++] = 0x0F; /* rdmsr */
2030 aPatch[off++] = 0x32;
2031
2032 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2033 {
2034 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2035 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2036 }
2037
2038 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2039 aPatch[off++] = 0x58; /* pop eax */
2040 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2041 aPatch[off++] = 0x5A; /* pop edx */
2042 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2043 aPatch[off++] = 0x59; /* pop ecx */
2044 }
2045 aPatch[off++] = 0xE9; /* jmp return_address */
2046 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2047 off += sizeof(RTRCUINTPTR);
2048
2049 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2050 {
2051 /* Write new code to the patch buffer. */
2052 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2053 AssertRC(rc);
2054
2055#ifdef LOG_ENABLED
2056 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2057 while (true)
2058 {
2059 uint32_t cb;
2060
2061 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2062 if (RT_SUCCESS(rc))
2063 Log(("Patch instr %s\n", szOutput));
2064
2065 pInstr += cb;
2066
2067 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2068 break;
2069 }
2070#endif
2071
2072 pPatch->aNewOpcode[0] = 0xE9;
2073 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2074
2075 /* Overwrite the TPR instruction with a jump. */
2076 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2077 AssertRC(rc);
2078
2079#ifdef LOG_ENABLED
2080 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2081 if (RT_SUCCESS(rc))
2082 Log(("Jump: %s\n", szOutput));
2083#endif
2084 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2085 pPatch->cbNewOp = 5;
2086
2087 pPatch->Core.Key = pCtx->eip;
2088 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2089 AssertRC(rc);
2090
2091 pVM->hwaccm.s.cPatches++;
2092 pVM->hwaccm.s.fTPRPatchingActive = true;
2093 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2094 return VINF_SUCCESS;
2095 }
2096 else
2097 Log(("Ran out of space in our patch buffer!\n"));
2098 }
2099
2100 /* Save invalid patch, so we will not try again. */
2101 uint32_t idx = pVM->hwaccm.s.cPatches;
2102
2103#ifdef LOG_ENABLED
2104 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2105 if (RT_SUCCESS(rc))
2106 Log(("Failed to patch instr: %s\n", szOutput));
2107#endif
2108
2109 pPatch = &pVM->hwaccm.s.aPatches[idx];
2110 pPatch->Core.Key = pCtx->eip;
2111 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2112 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2113 AssertRC(rc);
2114 pVM->hwaccm.s.cPatches++;
2115 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2116 return VINF_SUCCESS;
2117}
2118
2119/**
2120 * Attempt to patch TPR mmio instructions
2121 *
2122 * @returns VBox status code.
2123 * @param pVM The VM to operate on.
2124 * @param pVCpu The VM CPU to operate on.
2125 * @param pCtx CPU context
2126 */
2127VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2128{
2129 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2130 AssertRC(rc);
2131 return rc;
2132}
2133
2134/**
2135 * Force execution of the current IO code in the recompiler
2136 *
2137 * @returns VBox status code.
2138 * @param pVM The VM to operate on.
2139 * @param pCtx Partial VM execution context
2140 */
2141VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2142{
2143 PVMCPU pVCpu = VMMGetCpu(pVM);
2144
2145 Assert(pVM->fHWACCMEnabled);
2146 Log(("HWACCMR3EmulateIoBlock\n"));
2147
2148 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2149 if (HWACCMCanEmulateIoBlockEx(pCtx))
2150 {
2151 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2152 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2153 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2154 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2155 return VINF_EM_RESCHEDULE_REM;
2156 }
2157 return VINF_SUCCESS;
2158}
2159
2160/**
2161 * Checks if we can currently use hardware accelerated raw mode.
2162 *
2163 * @returns boolean
2164 * @param pVM The VM to operate on.
2165 * @param pCtx Partial VM execution context
2166 */
2167VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2168{
2169 PVMCPU pVCpu = VMMGetCpu(pVM);
2170
2171 Assert(pVM->fHWACCMEnabled);
2172
2173 /* If we're still executing the IO code, then return false. */
2174 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2175 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2176 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2177 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2178 return false;
2179
2180 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2181
2182 /* AMD-V supports real & protected mode with or without paging. */
2183 if (pVM->hwaccm.s.svm.fEnabled)
2184 {
2185 pVCpu->hwaccm.s.fActive = true;
2186 return true;
2187 }
2188
2189 pVCpu->hwaccm.s.fActive = false;
2190
2191 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2192#ifdef HWACCM_VMX_EMULATE_REALMODE
2193 bool fVMMDeviceHeapEnabled = PDMVMMDevHeapIsEnabled(pVM);
2194
2195 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2196
2197 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2198 if (fVMMDeviceHeapEnabled)
2199 {
2200 if (CPUMIsGuestInRealModeEx(pCtx))
2201 {
2202 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2203 * The base must also be equal to (sel << 4).
2204 */
2205 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2206 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2207 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2208 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2209 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2210 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2211 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2212 {
2213 return false;
2214 }
2215 }
2216 else
2217 {
2218 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2219 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2220 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2221 */
2222 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2223 && enmGuestMode >= PGMMODE_PROTECTED)
2224 {
2225 if ( (pCtx->cs & X86_SEL_RPL)
2226 || (pCtx->ds & X86_SEL_RPL)
2227 || (pCtx->es & X86_SEL_RPL)
2228 || (pCtx->fs & X86_SEL_RPL)
2229 || (pCtx->gs & X86_SEL_RPL)
2230 || (pCtx->ss & X86_SEL_RPL))
2231 {
2232 return false;
2233 }
2234 }
2235 }
2236 }
2237 else
2238#endif /* HWACCM_VMX_EMULATE_REALMODE */
2239 {
2240 if ( !CPUMIsGuestInLongModeEx(pCtx)
2241 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2242 {
2243 /** @todo This should (probably) be set on every excursion to the REM,
2244 * however it's too risky right now. So, only apply it when we go
2245 * back to REM for real mode execution. (The XP hack below doesn't
2246 * work reliably without this.)
2247 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2248 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2249
2250 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2251 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2252 return false;
2253
2254 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2255 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2256 return false;
2257
2258 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2259 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2260 * hidden registers (possible recompiler bug; see load_seg_vm) */
2261 if (pCtx->csHid.Attr.n.u1Present == 0)
2262 return false;
2263 if (pCtx->ssHid.Attr.n.u1Present == 0)
2264 return false;
2265
2266 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2267 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2268 /** @todo This check is actually wrong, it doesn't take the direction of the
2269 * stack segment into account. But, it does the job for now. */
2270 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2271 return false;
2272#if 0
2273 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2274 || pCtx->ss >= pCtx->gdtr.cbGdt
2275 || pCtx->ds >= pCtx->gdtr.cbGdt
2276 || pCtx->es >= pCtx->gdtr.cbGdt
2277 || pCtx->fs >= pCtx->gdtr.cbGdt
2278 || pCtx->gs >= pCtx->gdtr.cbGdt)
2279 return false;
2280#endif
2281 }
2282 }
2283
2284 if (pVM->hwaccm.s.vmx.fEnabled)
2285 {
2286 uint32_t mask;
2287
2288 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2289 {
2290 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2291 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2292 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2293 mask &= ~X86_CR0_NE;
2294
2295#ifdef HWACCM_VMX_EMULATE_REALMODE
2296 if (fVMMDeviceHeapEnabled)
2297 {
2298 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2299 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2300 }
2301 else
2302#endif
2303 {
2304 /* We support protected mode without paging using identity mapping. */
2305 mask &= ~X86_CR0_PG;
2306 }
2307 if ((pCtx->cr0 & mask) != mask)
2308 return false;
2309
2310 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2311 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2312 if ((pCtx->cr0 & mask) != 0)
2313 return false;
2314 }
2315
2316 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2317 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2318 mask &= ~X86_CR4_VMXE;
2319 if ((pCtx->cr4 & mask) != mask)
2320 return false;
2321
2322 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2323 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2324 if ((pCtx->cr4 & mask) != 0)
2325 return false;
2326
2327 pVCpu->hwaccm.s.fActive = true;
2328 return true;
2329 }
2330
2331 return false;
2332}
2333
2334/**
2335 * Checks if we need to reschedule due to VMM device heap changes
2336 *
2337 * @returns boolean
2338 * @param pVM The VM to operate on.
2339 * @param pCtx VM execution context
2340 */
2341VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2342{
2343 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2344 if ( pVM->hwaccm.s.vmx.fEnabled
2345 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2346 && !PDMVMMDevHeapIsEnabled(pVM)
2347 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2348 return true;
2349
2350 return false;
2351}
2352
2353
2354/**
2355 * Notifcation from EM about a rescheduling into hardware assisted execution
2356 * mode.
2357 *
2358 * @param pVCpu Pointer to the current virtual cpu structure.
2359 */
2360VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2361{
2362 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2363}
2364
2365/**
2366 * Notifcation from EM about returning from instruction emulation (REM / EM).
2367 *
2368 * @param pVCpu Pointer to the current virtual cpu structure.
2369 */
2370VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2371{
2372 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2373}
2374
2375/**
2376 * Checks if we are currently using hardware accelerated raw mode.
2377 *
2378 * @returns boolean
2379 * @param pVCpu The VMCPU to operate on.
2380 */
2381VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2382{
2383 return pVCpu->hwaccm.s.fActive;
2384}
2385
2386/**
2387 * Checks if we are currently using nested paging.
2388 *
2389 * @returns boolean
2390 * @param pVM The VM to operate on.
2391 */
2392VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2393{
2394 return pVM->hwaccm.s.fNestedPaging;
2395}
2396
2397/**
2398 * Checks if we are currently using VPID in VT-x mode.
2399 *
2400 * @returns boolean
2401 * @param pVM The VM to operate on.
2402 */
2403VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2404{
2405 return pVM->hwaccm.s.vmx.fVPID;
2406}
2407
2408
2409/**
2410 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2411 *
2412 * @returns boolean
2413 * @param pVM The VM to operate on.
2414 */
2415VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2416{
2417 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2418}
2419
2420/**
2421 * Restart an I/O instruction that was refused in ring-0
2422 *
2423 * @returns Strict VBox status code. Informational status codes other than the one documented
2424 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2425 * @retval VINF_SUCCESS Success.
2426 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2427 * status code must be passed on to EM.
2428 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2429 *
2430 * @param pVM The VM to operate on.
2431 * @param pVCpu The VMCPU to operate on.
2432 * @param pCtx VCPU register context
2433 */
2434VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2435{
2436 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2437
2438 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2439
2440 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2441 || enmType == HWACCMPENDINGIO_INVALID)
2442 return VERR_NOT_FOUND;
2443
2444 VBOXSTRICTRC rcStrict;
2445 switch (enmType)
2446 {
2447 case HWACCMPENDINGIO_PORT_READ:
2448 {
2449 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2450 uint32_t u32Val = 0;
2451
2452 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2453 &u32Val,
2454 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2455 if (IOM_SUCCESS(rcStrict))
2456 {
2457 /* Write back to the EAX register. */
2458 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2459 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2460 }
2461 break;
2462 }
2463
2464 case HWACCMPENDINGIO_PORT_WRITE:
2465 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2466 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2467 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2468 if (IOM_SUCCESS(rcStrict))
2469 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2470 break;
2471
2472 default:
2473 AssertFailed();
2474 return VERR_INTERNAL_ERROR;
2475 }
2476
2477 return rcStrict;
2478}
2479
2480/**
2481 * Inject an NMI into a running VM (only VCPU 0!)
2482 *
2483 * @returns boolean
2484 * @param pVM The VM to operate on.
2485 */
2486VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2487{
2488 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2489 return VINF_SUCCESS;
2490}
2491
2492/**
2493 * Check fatal VT-x/AMD-V error and produce some meaningful
2494 * log release message.
2495 *
2496 * @param pVM The VM to operate on.
2497 * @param iStatusCode VBox status code
2498 */
2499VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2500{
2501 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2502 {
2503 switch(iStatusCode)
2504 {
2505 case VERR_VMX_INVALID_VMCS_FIELD:
2506 break;
2507
2508 case VERR_VMX_INVALID_VMCS_PTR:
2509 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2510 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2511 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2512 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2513 break;
2514
2515 case VERR_VMX_UNABLE_TO_START_VM:
2516 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2517 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2518#if 0 /* @todo dump the current control fields to the release log */
2519 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2520 {
2521
2522 }
2523#endif
2524 break;
2525
2526 case VERR_VMX_UNABLE_TO_RESUME_VM:
2527 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2528 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2529 break;
2530
2531 case VERR_VMX_INVALID_VMXON_PTR:
2532 break;
2533 }
2534 }
2535}
2536
2537/**
2538 * Execute state save operation.
2539 *
2540 * @returns VBox status code.
2541 * @param pVM VM Handle.
2542 * @param pSSM SSM operation handle.
2543 */
2544static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2545{
2546 int rc;
2547
2548 Log(("hwaccmR3Save:\n"));
2549
2550 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2551 {
2552 /*
2553 * Save the basic bits - fortunately all the other things can be resynced on load.
2554 */
2555 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2556 AssertRCReturn(rc, rc);
2557 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2558 AssertRCReturn(rc, rc);
2559 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2560 AssertRCReturn(rc, rc);
2561
2562 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2563 AssertRCReturn(rc, rc);
2564 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2565 AssertRCReturn(rc, rc);
2566 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2567 AssertRCReturn(rc, rc);
2568 }
2569#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2570 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2571 AssertRCReturn(rc, rc);
2572 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2573 AssertRCReturn(rc, rc);
2574 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2575 AssertRCReturn(rc, rc);
2576
2577 /* Store all the guest patch records too. */
2578 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2579 AssertRCReturn(rc, rc);
2580
2581 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2582 {
2583 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2584
2585 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2586 AssertRCReturn(rc, rc);
2587
2588 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2589 AssertRCReturn(rc, rc);
2590
2591 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2592 AssertRCReturn(rc, rc);
2593
2594 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2595 AssertRCReturn(rc, rc);
2596
2597 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2598 AssertRCReturn(rc, rc);
2599
2600 AssertCompileSize(HWACCMTPRINSTR, 4);
2601 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2602 AssertRCReturn(rc, rc);
2603
2604 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2605 AssertRCReturn(rc, rc);
2606
2607 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2608 AssertRCReturn(rc, rc);
2609
2610 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2611 AssertRCReturn(rc, rc);
2612
2613 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2614 AssertRCReturn(rc, rc);
2615 }
2616#endif
2617 return VINF_SUCCESS;
2618}
2619
2620/**
2621 * Execute state load operation.
2622 *
2623 * @returns VBox status code.
2624 * @param pVM VM Handle.
2625 * @param pSSM SSM operation handle.
2626 * @param uVersion Data layout version.
2627 * @param uPass The data pass.
2628 */
2629static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2630{
2631 int rc;
2632
2633 Log(("hwaccmR3Load:\n"));
2634 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2635
2636 /*
2637 * Validate version.
2638 */
2639 if ( uVersion != HWACCM_SSM_VERSION
2640 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2641 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2642 {
2643 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2644 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2645 }
2646 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2647 {
2648 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2649 AssertRCReturn(rc, rc);
2650 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2651 AssertRCReturn(rc, rc);
2652 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2653 AssertRCReturn(rc, rc);
2654
2655 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2656 {
2657 uint32_t val;
2658
2659 rc = SSMR3GetU32(pSSM, &val);
2660 AssertRCReturn(rc, rc);
2661 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2662
2663 rc = SSMR3GetU32(pSSM, &val);
2664 AssertRCReturn(rc, rc);
2665 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2666
2667 rc = SSMR3GetU32(pSSM, &val);
2668 AssertRCReturn(rc, rc);
2669 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2670 }
2671 }
2672#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2673 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2674 {
2675 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2676 AssertRCReturn(rc, rc);
2677 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2678 AssertRCReturn(rc, rc);
2679 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2680 AssertRCReturn(rc, rc);
2681
2682 /* Fetch all TPR patch records. */
2683 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2684 AssertRCReturn(rc, rc);
2685
2686 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2687 {
2688 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2689
2690 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2691 AssertRCReturn(rc, rc);
2692
2693 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2694 AssertRCReturn(rc, rc);
2695
2696 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2697 AssertRCReturn(rc, rc);
2698
2699 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2700 AssertRCReturn(rc, rc);
2701
2702 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2703 AssertRCReturn(rc, rc);
2704
2705 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2706 AssertRCReturn(rc, rc);
2707
2708 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2709 pVM->hwaccm.s.fTPRPatchingActive = true;
2710
2711 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2712
2713 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2714 AssertRCReturn(rc, rc);
2715
2716 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2717 AssertRCReturn(rc, rc);
2718
2719 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2720 AssertRCReturn(rc, rc);
2721
2722 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2723 AssertRCReturn(rc, rc);
2724
2725 Log(("hwaccmR3Load: patch %d\n", i));
2726 Log(("Key = %x\n", pPatch->Core.Key));
2727 Log(("cbOp = %d\n", pPatch->cbOp));
2728 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2729 Log(("type = %d\n", pPatch->enmType));
2730 Log(("srcop = %d\n", pPatch->uSrcOperand));
2731 Log(("dstop = %d\n", pPatch->uDstOperand));
2732 Log(("cFaults = %d\n", pPatch->cFaults));
2733 Log(("target = %x\n", pPatch->pJumpTarget));
2734 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2735 AssertRC(rc);
2736 }
2737 }
2738#endif
2739
2740 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2741 if (HWACCMIsEnabled(pVM))
2742 {
2743 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2744 {
2745 PVMCPU pVCpu = &pVM->aCpus[i];
2746
2747 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2748 }
2749 }
2750 return VINF_SUCCESS;
2751}
2752
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