VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 13538

Last change on this file since 13538 was 13532, checked in by vboxsync, 16 years ago

CPUMQueryGuestCtxPtr doesn't need to return a status. It can never fail.
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1/* $Id: HWACCM.cpp 13532 2008-10-23 12:39:48Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48
49/*******************************************************************************
50* Internal Functions *
51*******************************************************************************/
52static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
53static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
54
55
56/**
57 * Initializes the HWACCM.
58 *
59 * @returns VBox status code.
60 * @param pVM The VM to operate on.
61 */
62VMMR3DECL(int) HWACCMR3Init(PVM pVM)
63{
64 LogFlow(("HWACCMR3Init\n"));
65
66 /*
67 * Assert alignment and sizes.
68 */
69 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
70 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
71
72 /* Some structure checks. */
73 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
74 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
75 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
77
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
84 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
85
86
87 /*
88 * Register the saved state data unit.
89 */
90 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
91 NULL, hwaccmR3Save, NULL,
92 NULL, hwaccmR3Load, NULL);
93 if (VBOX_FAILURE(rc))
94 return rc;
95
96 /* Misc initialisation. */
97 pVM->hwaccm.s.vmx.fSupported = false;
98 pVM->hwaccm.s.svm.fSupported = false;
99 pVM->hwaccm.s.vmx.fEnabled = false;
100 pVM->hwaccm.s.svm.fEnabled = false;
101
102 pVM->hwaccm.s.fActive = false;
103 pVM->hwaccm.s.fNestedPaging = false;
104
105 /* On first entry we'll sync everything. */
106 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
107
108 pVM->hwaccm.s.vmx.cr0_mask = 0;
109 pVM->hwaccm.s.vmx.cr4_mask = 0;
110
111 /*
112 * Statistics.
113 */
114 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
115 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
116 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
117
118 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
119 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
121 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
123 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
124 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
125 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
126 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
127 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
128 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDB, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DB", STAMUNIT_OCCURENCES, "Nr of occurances");
129 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
130 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
131 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
132 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
133 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
134 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
135 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
136 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
137 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
138 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
139 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
140 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
141 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
142 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
143 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
144 STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
145
146 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
147 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
148
149 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
150 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
151 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
152
153 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
154 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
155 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
157 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
158 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
159 STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
160 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
161 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBInvlpga, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/PhysInvlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
162
163 STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
164 STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
165
166 STAM_REG(pVM, &pVM->hwaccm.s.StatDRxArmed, STAMTYPE_COUNTER, "/HWACCM/Debug/Armed", STAMUNIT_OCCURENCES, "Nr of occurances");
167 STAM_REG(pVM, &pVM->hwaccm.s.StatDRxContextSwitch, STAMTYPE_COUNTER, "/HWACCM/Debug/ContextSwitch", STAMUNIT_OCCURENCES, "Nr of occurances");
168 STAM_REG(pVM, &pVM->hwaccm.s.StatDRxIOCheck, STAMTYPE_COUNTER, "/HWACCM/Debug/IOCheck", STAMUNIT_OCCURENCES, "Nr of occurances");
169
170 pVM->hwaccm.s.paStatExitReason = NULL;
171
172#ifdef VBOX_WITH_STATISTICS
173 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.paStatExitReason);
174 AssertRC(rc);
175 if (VBOX_SUCCESS(rc))
176 {
177 for (int i=0;i<MAX_EXITREASON_STAT;i++)
178 {
179 int rc = STAMR3RegisterF(pVM, &pVM->hwaccm.s.paStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
180 "/HWACCM/Exit/Reason/%02x", i);
181 AssertRC(rc);
182 }
183 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
184 AssertRC(rc);
185 }
186 pVM->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.paStatExitReason);
187 Assert(pVM->hwaccm.s.paStatExitReasonR0);
188#endif
189
190 /* Disabled by default. */
191 pVM->fHWACCMEnabled = false;
192
193 /*
194 * Check CFGM options.
195 */
196 /* Nested paging: disabled by default. */
197 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
198 AssertRC(rc);
199
200 /* VT-x VPID: disabled by default. */
201 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.fAllowVPID, false);
202 AssertRC(rc);
203
204 /* HWACCM support must be explicitely enabled in the configuration file. */
205 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
206 AssertRC(rc);
207
208 return VINF_SUCCESS;
209}
210
211/**
212 * Turns off normal raw mode features
213 *
214 * @param pVM The VM to operate on.
215 */
216static void hwaccmR3DisableRawMode(PVM pVM)
217{
218 /* Disable PATM & CSAM. */
219 PATMR3AllowPatching(pVM, false);
220 CSAMDisableScanning(pVM);
221
222 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
223 SELMR3DisableMonitoring(pVM);
224 TRPMR3DisableMonitoring(pVM);
225
226 /* The hidden selector registers are now valid. */
227 CPUMSetHiddenSelRegsValid(pVM, true);
228
229 /* Disable the switcher code (safety precaution). */
230 VMMR3DisableSwitcher(pVM);
231
232 /* Disable mapping of the hypervisor into the shadow page table. */
233 PGMR3ChangeShwPDMappings(pVM, false);
234
235 /* Disable the switcher */
236 VMMR3DisableSwitcher(pVM);
237
238 if (pVM->hwaccm.s.fNestedPaging)
239 {
240 /* Reinit the paging mode to force the new shadow mode. */
241 PGMR3ChangeMode(pVM, PGMMODE_REAL);
242 }
243}
244
245/**
246 * Initialize VT-x or AMD-V.
247 *
248 * @returns VBox status code.
249 * @param pVM The VM handle.
250 */
251VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
252{
253 int rc;
254
255 if ( !pVM->hwaccm.s.vmx.fSupported
256 && !pVM->hwaccm.s.svm.fSupported)
257 {
258 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
259 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
260 return VINF_SUCCESS;
261 }
262
263 /*
264 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
265 * because it turns off paging, which is not allowed in VMX root mode.
266 *
267 * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
268 *
269 */
270 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
271 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
272 if (VBOX_FAILURE(rc))
273 {
274 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
275 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
276 /* Invert the selection */
277 pVM->hwaccm.s.fAllowed ^= 1;
278 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
279
280 if (pVM->hwaccm.s.fAllowed)
281 {
282 if (pVM->hwaccm.s.vmx.fSupported)
283 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
284 else
285 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
286 }
287 else
288 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
289 }
290
291 if (pVM->hwaccm.s.fAllowed == false)
292 return VINF_SUCCESS; /* disabled */
293
294 Assert(!pVM->fHWACCMEnabled);
295
296 if (pVM->hwaccm.s.vmx.fSupported)
297 {
298 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
299
300 if ( pVM->hwaccm.s.fInitialized == false
301 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
302 {
303 uint64_t val;
304 RTGCPHYS GCPhys = 0;
305
306 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
307 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
308 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
309 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
310 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
311 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
312 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
313 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
314
315 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
316 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
317 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
318 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
319 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
320 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
321 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
322 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
323 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
324 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
325 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
326
327 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
328 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
329 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
330 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
331 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
332 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
333 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
334 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
335 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
336 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
337 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
338 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
339 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
340 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
341 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
342 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
343 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
344 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
345 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
346 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
347 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
348 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
349 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
350 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
351 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
352 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
353 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
354 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
355 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
356 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
357 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
358 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
359 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
360 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
361 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
362 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
363 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
364 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
365 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
366 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
367 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
368 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
369
370 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
371 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
372 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
373 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
374 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
375 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
376 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
377 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
378 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
379 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
380 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
381 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
382 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
383 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
384 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
385 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
386 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
387 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
389 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
390 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
391 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
393 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
394 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
395 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
396 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
397 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
398 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
399 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
400 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
401 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
403 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
404 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
405 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
406 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
407 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
408 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
409 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
410 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
411
412 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
413 {
414 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
415 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
416 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
417 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
418 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
419 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
420 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
421 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
422 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
423 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
424
425 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
426 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
427 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
428 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
429 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
430 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
431 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
432 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
433 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
434 }
435
436 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
437 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
438 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
439 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
440 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
441 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
442 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
443 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
444 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
445 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
446 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
447 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
448 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
449 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
450 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
451 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
452 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
453 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
454 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
455 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
456 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
457 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
458 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
459 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
460 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
461 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
462 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
463 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
464 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
465 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
466 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
467
468 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
469 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
470 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
471 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
472 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
473 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
474 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
475 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
476 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
477 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
478 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
479 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
480 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
481 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
482 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
483 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
484 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
485 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
486 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
487 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
488 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
489 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
490 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
491 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
492 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
493 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
494 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
495 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
496 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
497 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
498 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
499 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
500 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
501 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
502 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
503
504 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
505 {
506 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
507
508 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
509 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
510 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
511 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
512 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
513 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
514 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
515 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
516 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
517 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
518 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
519 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
520 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
521 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
522 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
523 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
524 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
525 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
526 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
527 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
528 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
529 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
530 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
531 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
532 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
533 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
534 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
535 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
536 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
537 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
538 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
539 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
540 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
541 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
542 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
543 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
544 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
545 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
547 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
548 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
549 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
550 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
551 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
553 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
554 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
555 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
556 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
557 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
558 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
559 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
560 }
561
562 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
563 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
564 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
565 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
566 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
567
568 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
569 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
570 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
571 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
572 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
573
574 LogRel(("HWACCM: VMCS physaddr = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
575 LogRel(("HWACCM: TPR shadow physaddr = %VHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
576 LogRel(("HWACCM: MSR bitmap physaddr = %VHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
577
578#ifdef HWACCM_VTX_WITH_EPT
579 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
580 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
581#endif /* HWACCM_VTX_WITH_EPT */
582#ifdef HWACCM_VTX_WITH_VPID
583 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
584 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
585 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.fAllowVPID;
586#endif /* HWACCM_VTX_WITH_VPID */
587
588 /* Only try once. */
589 pVM->hwaccm.s.fInitialized = true;
590
591 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
592 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
593 AssertRC(rc);
594 if (RT_FAILURE(rc))
595 return rc;
596
597 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
598 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
599 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
600 /* Bit set to 0 means redirection enabled. */
601 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
602 /* Allow all port IO, so the VT-x IO intercepts do their job. */
603 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
604 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
605
606 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
607 * real and protected mode without paging with EPT.
608 */
609 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
610 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
611 {
612 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
613 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
614 }
615
616 /* We convert it here every time as pci regions could be reconfigured. */
617 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
618 AssertRC(rc);
619 LogRel(("HWACCM: Real Mode TSS guest physaddr = %VGp\n", GCPhys));
620
621 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
622 AssertRC(rc);
623 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %VGp\n", GCPhys));
624
625 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
626 AssertRC(rc);
627 if (rc == VINF_SUCCESS)
628 {
629 pVM->fHWACCMEnabled = true;
630 pVM->hwaccm.s.vmx.fEnabled = true;
631 hwaccmR3DisableRawMode(pVM);
632
633 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
634#ifdef VBOX_ENABLE_64_BITS_GUESTS
635 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
636 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
637 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
638 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
639 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
640#endif
641 LogRel(("HWACCM: VMX enabled!\n"));
642 if (pVM->hwaccm.s.fNestedPaging)
643 {
644 LogRel(("HWACCM: Enabled nested paging\n"));
645 LogRel(("HWACCM: EPT root page = %VHp\n", PGMGetEPTCR3(pVM)));
646 }
647 if (pVM->hwaccm.s.vmx.fVPID)
648 LogRel(("HWACCM: Enabled VPID\n"));
649
650 if ( pVM->hwaccm.s.fNestedPaging
651 || pVM->hwaccm.s.vmx.fVPID)
652 {
653 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
654 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
655 }
656 }
657 else
658 {
659 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
660 LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
661 pVM->fHWACCMEnabled = false;
662 }
663 }
664 }
665 else
666 if (pVM->hwaccm.s.svm.fSupported)
667 {
668 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
669
670 if (pVM->hwaccm.s.fInitialized == false)
671 {
672 /* Erratum 170 which requires a forced TLB flush for each world switch:
673 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
674 *
675 * All BH-G1/2 and DH-G1/2 models include a fix:
676 * Athlon X2: 0x6b 1/2
677 * 0x68 1/2
678 * Athlon 64: 0x7f 1
679 * 0x6f 2
680 * Sempron: 0x7f 1/2
681 * 0x6f 2
682 * 0x6c 2
683 * 0x7c 2
684 * Turion 64: 0x68 2
685 *
686 */
687 uint32_t u32Dummy;
688 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
689 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
690 u32BaseFamily= (u32Version >> 8) & 0xf;
691 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
692 u32Model = ((u32Version >> 4) & 0xf);
693 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
694 u32Stepping = u32Version & 0xf;
695 if ( u32Family == 0xf
696 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
697 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
698 {
699 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
700 }
701
702 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
703 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
704 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
705 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
706 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
707
708 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
709 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
710 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
711 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
712 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
713 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
714 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
715 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
716 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
717 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
718
719 /* Only try once. */
720 pVM->hwaccm.s.fInitialized = true;
721
722 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
723 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
724
725 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
726 AssertRC(rc);
727 if (rc == VINF_SUCCESS)
728 {
729 pVM->fHWACCMEnabled = true;
730 pVM->hwaccm.s.svm.fEnabled = true;
731
732 if (pVM->hwaccm.s.fNestedPaging)
733 LogRel(("HWACCM: Enabled nested paging\n"));
734
735 hwaccmR3DisableRawMode(pVM);
736 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
737 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
738#ifdef VBOX_ENABLE_64_BITS_GUESTS
739 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
740 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
741 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
742 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
743#endif
744 }
745 else
746 {
747 pVM->fHWACCMEnabled = false;
748 }
749 }
750 }
751 return VINF_SUCCESS;
752}
753
754/**
755 * Applies relocations to data and code managed by this
756 * component. This function will be called at init and
757 * whenever the VMM need to relocate it self inside the GC.
758 *
759 * @param pVM The VM.
760 */
761VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
762{
763 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
764 return;
765}
766
767/**
768 * Checks hardware accelerated raw mode is allowed.
769 *
770 * @returns boolean
771 * @param pVM The VM to operate on.
772 */
773VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
774{
775 return pVM->hwaccm.s.fAllowed;
776}
777
778/**
779 * Notification callback which is called whenever there is a chance that a CR3
780 * value might have changed.
781 *
782 * This is called by PGM.
783 *
784 * @param pVM The VM to operate on.
785 * @param enmShadowMode New shadow paging mode.
786 * @param enmGuestMode New guest paging mode.
787 */
788VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
789{
790 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
791 if ( pVM->hwaccm.s.vmx.fEnabled
792 && pVM->fHWACCMEnabled)
793 {
794 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
795 && enmGuestMode >= PGMMODE_PROTECTED)
796 {
797 PCPUMCTX pCtx;
798
799 pCtx = CPUMQueryGuestCtxPtr(pVM);
800
801 /* After a real mode switch to protected mode we must force
802 * CPL to 0. Our real mode emulation had to set it to 3.
803 */
804 pCtx->ssHid.Attr.n.u2Dpl = 0;
805 }
806 }
807}
808
809/**
810 * Terminates the HWACCM.
811 *
812 * Termination means cleaning up and freeing all resources,
813 * the VM it self is at this point powered off or suspended.
814 *
815 * @returns VBox status code.
816 * @param pVM The VM to operate on.
817 */
818VMMR3DECL(int) HWACCMR3Term(PVM pVM)
819{
820 if (pVM->hwaccm.s.vmx.pRealModeTSS)
821 {
822 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
823 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
824 }
825
826 if (pVM->hwaccm.s.paStatExitReason)
827 {
828 MMHyperFree(pVM, pVM->hwaccm.s.paStatExitReason);
829 pVM->hwaccm.s.paStatExitReason = NULL;
830 }
831 return 0;
832}
833
834/**
835 * The VM is being reset.
836 *
837 * For the HWACCM component this means that any GDT/LDT/TSS monitors
838 * needs to be removed.
839 *
840 * @param pVM VM handle.
841 */
842VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
843{
844 LogFlow(("HWACCMR3Reset:\n"));
845
846 if (pVM->fHWACCMEnabled)
847 hwaccmR3DisableRawMode(pVM);
848
849 /* On first entry we'll sync everything. */
850 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
851
852 pVM->hwaccm.s.vmx.cr0_mask = 0;
853 pVM->hwaccm.s.vmx.cr4_mask = 0;
854
855 pVM->hwaccm.s.Event.fPending = false;
856
857 /* Reset state information for real-mode emulation in VT-x. */
858 pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
859}
860
861/**
862 * Checks if we can currently use hardware accelerated raw mode.
863 *
864 * @returns boolean
865 * @param pVM The VM to operate on.
866 * @param pCtx Partial VM execution context
867 */
868VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
869{
870 Assert(pVM->fHWACCMEnabled);
871
872 /* AMD SVM supports real & protected mode with or without paging. */
873 if (pVM->hwaccm.s.svm.fEnabled)
874 {
875 pVM->hwaccm.s.fActive = true;
876 return true;
877 }
878
879 pVM->hwaccm.s.fActive = false;
880
881 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
882#ifdef HWACCM_VMX_EMULATE_REALMODE
883 if (CPUMIsGuestInRealModeEx(pCtx))
884 {
885 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
886 * The base must also be equal to (sel << 4).
887 */
888 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
889 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
890 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
891 || pCtx->es != (pCtx->esHid.u64Base >> 4)
892 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
893 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
894 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
895 return false;
896 }
897 else
898 {
899 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
900 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
901 * from real to protected mode. (all sorts of RPL & DPL assumptions)
902 */
903 if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
904 && enmGuestMode >= PGMMODE_PROTECTED)
905 {
906 if ( (pCtx->cs & X86_SEL_RPL)
907 || (pCtx->ds & X86_SEL_RPL)
908 || (pCtx->es & X86_SEL_RPL)
909 || (pCtx->fs & X86_SEL_RPL)
910 || (pCtx->gs & X86_SEL_RPL)
911 || (pCtx->ss & X86_SEL_RPL))
912 {
913 /* Flush the translation blocks as code pages may have been
914 * changed (Fedora4 boot image, reset, boot iso)
915 */
916 EMFlushREMTBs(pVM);
917 return false;
918 }
919 }
920 }
921#else
922 if (!CPUMIsGuestInLongModeEx(pCtx))
923 {
924 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
925 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
926 return false;
927
928 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
929 /* Windows XP; switch to protected mode; all selectors are marked not present in the
930 * hidden registers (possible recompiler bug; see load_seg_vm) */
931 if (pCtx->csHid.Attr.n.u1Present == 0)
932 return false;
933 if (pCtx->ssHid.Attr.n.u1Present == 0)
934 return false;
935 }
936#endif
937
938 if (pVM->hwaccm.s.vmx.fEnabled)
939 {
940 uint32_t mask;
941
942 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
943 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
944 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
945 mask &= ~X86_CR0_NE;
946
947#ifdef HWACCM_VMX_EMULATE_REALMODE
948 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
949 mask &= ~(X86_CR0_PG|X86_CR0_PE);
950#else
951 /* We support protected mode without paging using identity mapping. */
952 mask &= ~X86_CR0_PG;
953#endif
954 if ((pCtx->cr0 & mask) != mask)
955 return false;
956
957 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
958 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
959 if ((pCtx->cr0 & mask) != 0)
960 return false;
961
962 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
963 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
964 mask &= ~X86_CR4_VMXE;
965 if ((pCtx->cr4 & mask) != mask)
966 return false;
967
968 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
969 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
970 if ((pCtx->cr4 & mask) != 0)
971 return false;
972
973 pVM->hwaccm.s.fActive = true;
974 return true;
975 }
976
977 return false;
978}
979
980/**
981 * Checks if we are currently using hardware accelerated raw mode.
982 *
983 * @returns boolean
984 * @param pVM The VM to operate on.
985 */
986VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
987{
988 return pVM->hwaccm.s.fActive;
989}
990
991/**
992 * Checks if we are currently using nested paging.
993 *
994 * @returns boolean
995 * @param pVM The VM to operate on.
996 */
997VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
998{
999 return pVM->hwaccm.s.fNestedPaging;
1000}
1001
1002/**
1003 * Checks if we are currently using VPID in VT-x mode.
1004 *
1005 * @returns boolean
1006 * @param pVM The VM to operate on.
1007 */
1008VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1009{
1010 return pVM->hwaccm.s.vmx.fVPID;
1011}
1012
1013
1014/**
1015 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1016 *
1017 * @returns boolean
1018 * @param pVM The VM to operate on.
1019 */
1020VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1021{
1022 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
1023}
1024
1025/**
1026 * Check fatal VT-x/AMD-V error and produce some meaningful
1027 * log release message.
1028 *
1029 * @param pVM The VM to operate on.
1030 * @param iStatusCode VBox status code
1031 */
1032VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1033{
1034 switch(iStatusCode)
1035 {
1036 case VERR_VMX_INVALID_VMCS_FIELD:
1037 break;
1038
1039 case VERR_VMX_INVALID_VMCS_PTR:
1040 LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current pointer %VGp vs %VGp\n", pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->hwaccm.s.vmx.pVMCSPhys));
1041 LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current VMCS version %x\n", pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision));
1042 break;
1043
1044 case VERR_VMX_INVALID_VMXON_PTR:
1045 break;
1046 }
1047}
1048
1049/**
1050 * Execute state save operation.
1051 *
1052 * @returns VBox status code.
1053 * @param pVM VM Handle.
1054 * @param pSSM SSM operation handle.
1055 */
1056static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1057{
1058 int rc;
1059
1060 Log(("hwaccmR3Save:\n"));
1061
1062 /*
1063 * Save the basic bits - fortunately all the other things can be resynced on load.
1064 */
1065 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
1066 AssertRCReturn(rc, rc);
1067 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
1068 AssertRCReturn(rc, rc);
1069 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
1070 AssertRCReturn(rc, rc);
1071
1072 return VINF_SUCCESS;
1073}
1074
1075/**
1076 * Execute state load operation.
1077 *
1078 * @returns VBox status code.
1079 * @param pVM VM Handle.
1080 * @param pSSM SSM operation handle.
1081 * @param u32Version Data layout version.
1082 */
1083static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1084{
1085 int rc;
1086
1087 Log(("hwaccmR3Load:\n"));
1088
1089 /*
1090 * Validate version.
1091 */
1092 if (u32Version != HWACCM_SSM_VERSION)
1093 {
1094 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1095 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1096 }
1097 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
1098 AssertRCReturn(rc, rc);
1099 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
1100 AssertRCReturn(rc, rc);
1101 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
1102 AssertRCReturn(rc, rc);
1103
1104 return VINF_SUCCESS;
1105}
1106
1107
1108
1109
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