VirtualBox

source: vbox/trunk/src/VBox/VMM/EMRaw.cpp@ 28800

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1/* $Id: EMRaw.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager - software virtualization
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/em.h>
39#include <VBox/vmm.h>
40#ifdef VBOX_WITH_VMI
41# include <VBox/parav.h>
42#endif
43#include <VBox/patm.h>
44#include <VBox/csam.h>
45#include <VBox/selm.h>
46#include <VBox/trpm.h>
47#include <VBox/iom.h>
48#include <VBox/dbgf.h>
49#include <VBox/pgm.h>
50#include <VBox/rem.h>
51#include <VBox/tm.h>
52#include <VBox/mm.h>
53#include <VBox/ssm.h>
54#include <VBox/pdmapi.h>
55#include <VBox/pdmcritsect.h>
56#include <VBox/pdmqueue.h>
57#include <VBox/patm.h>
58#include "EMInternal.h"
59#include <VBox/vm.h>
60#include <VBox/cpumdis.h>
61#include <VBox/dis.h>
62#include <VBox/disopcode.h>
63#include <VBox/dbgf.h>
64
65#include <VBox/log.h>
66#include <iprt/string.h>
67#include <iprt/stream.h>
68
69/*******************************************************************************
70* Defined Constants And Macros *
71*******************************************************************************/
72
73
74/*******************************************************************************
75* Internal Functions *
76*******************************************************************************/
77static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
78DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
79static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
80static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
81static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
82static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
83static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
84static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
85
86#define EMHANDLERC_WITH_PATM
87#include "EMHandleRCTmpl.h"
88
89/**
90 * Enables or disables a set of raw-mode execution modes.
91 *
92 * @returns VINF_SUCCESS on success.
93 * @returns VINF_RESCHEDULE if a rescheduling might be required.
94 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
95 *
96 * @param pVM The VM to operate on.
97 * @param enmMode The execution mode change.
98 * @thread The emulation thread.
99 */
100VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
101{
102 switch (enmMode)
103 {
104 case EMRAW_NONE:
105 pVM->fRawR3Enabled = false;
106 pVM->fRawR0Enabled = false;
107 break;
108 case EMRAW_RING3_ENABLE:
109 pVM->fRawR3Enabled = true;
110 break;
111 case EMRAW_RING3_DISABLE:
112 pVM->fRawR3Enabled = false;
113 break;
114 case EMRAW_RING0_ENABLE:
115 pVM->fRawR0Enabled = true;
116 break;
117 case EMRAW_RING0_DISABLE:
118 pVM->fRawR0Enabled = false;
119 break;
120 default:
121 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
122 return VERR_INVALID_PARAMETER;
123 }
124 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
125 pVM->fRawR3Enabled, pVM->fRawR0Enabled));
126 return pVM->aCpus[0].em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
127}
128
129
130
131#ifdef VBOX_WITH_STATISTICS
132/**
133 * Just a braindead function to keep track of cli addresses.
134 * @param pVM VM handle.
135 * @param pVMCPU VMCPU handle.
136 * @param GCPtrInstr The EIP of the cli instruction.
137 */
138static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
139{
140 PCLISTAT pRec;
141
142 pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
143 if (!pRec)
144 {
145 /* New cli instruction; insert into the tree. */
146 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
147 Assert(pRec);
148 if (!pRec)
149 return;
150 pRec->Core.Key = GCPtrInstr;
151
152 char szCliStatName[32];
153 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
154 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
155
156 bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
157 Assert(fRc); NOREF(fRc);
158 }
159 STAM_COUNTER_INC(&pRec->Counter);
160 STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
161}
162#endif /* VBOX_WITH_STATISTICS */
163
164
165
166/**
167 * Resumes executing hypervisor after a debug event.
168 *
169 * This is kind of special since our current guest state is
170 * potentially out of sync.
171 *
172 * @returns VBox status code.
173 * @param pVM The VM handle.
174 * @param pVCpu The VMCPU handle.
175 */
176int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
177{
178 int rc;
179 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
180 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
181 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
182
183 /*
184 * Resume execution.
185 */
186 CPUMRawEnter(pVCpu, NULL);
187 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
188 rc = VMMR3ResumeHyper(pVM, pVCpu);
189 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
190 rc = CPUMRawLeave(pVCpu, NULL, rc);
191 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
192
193 /*
194 * Deal with the return code.
195 */
196 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
197 rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
198 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
199 return rc;
200}
201
202
203/**
204 * Steps rawmode.
205 *
206 * @returns VBox status code.
207 * @param pVM The VM handle.
208 * @param pVCpu The VMCPU handle.
209 */
210int emR3RawStep(PVM pVM, PVMCPU pVCpu)
211{
212 Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
213 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
214 || pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
215 int rc;
216 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
217 bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
218#ifndef DEBUG_sandervl
219 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
220 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
221#endif
222 if (fGuest)
223 {
224 /*
225 * Check vital forced actions, but ignore pending interrupts and timers.
226 */
227 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
228 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
229 {
230 rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
231 if (rc != VINF_SUCCESS)
232 return rc;
233 }
234
235 /*
236 * Set flags for single stepping.
237 */
238 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
239 }
240 else
241 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
242
243 /*
244 * Single step.
245 * We do not start time or anything, if anything we should just do a few nanoseconds.
246 */
247 CPUMRawEnter(pVCpu, NULL);
248 do
249 {
250 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
251 rc = VMMR3ResumeHyper(pVM, pVCpu);
252 else
253 rc = VMMR3RawRunGC(pVM, pVCpu);
254#ifndef DEBUG_sandervl
255 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
256 fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
257#endif
258 } while ( rc == VINF_SUCCESS
259 || rc == VINF_EM_RAW_INTERRUPT);
260 rc = CPUMRawLeave(pVCpu, NULL, rc);
261 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
262
263 /*
264 * Make sure the trap flag is cleared.
265 * (Too bad if the guest is trying to single step too.)
266 */
267 if (fGuest)
268 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
269 else
270 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
271
272 /*
273 * Deal with the return codes.
274 */
275 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
276 rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
277 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
278 return rc;
279}
280
281
282#ifdef DEBUG
283
284
285int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
286{
287 int rc = VINF_SUCCESS;
288 EMSTATE enmOldState = pVCpu->em.s.enmState;
289 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
290
291 Log(("Single step BEGIN:\n"));
292 for (uint32_t i = 0; i < cIterations; i++)
293 {
294 DBGFR3PrgStep(pVCpu);
295 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
296 rc = emR3RawStep(pVM, pVCpu);
297 if (rc != VINF_SUCCESS)
298 break;
299 }
300 Log(("Single step END: rc=%Rrc\n", rc));
301 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
302 pVCpu->em.s.enmState = enmOldState;
303 return rc;
304}
305
306#endif /* DEBUG */
307
308
309/**
310 * Executes one (or perhaps a few more) instruction(s).
311 *
312 * @returns VBox status code suitable for EM.
313 *
314 * @param pVM VM handle.
315 * @param pVCpu VMCPU handle
316 * @param rcGC GC return code
317 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
318 * instruction and prefix the log output with this text.
319 */
320#ifdef LOG_ENABLED
321static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
322#else
323static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
324#endif
325{
326 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
327 int rc;
328
329 /*
330 *
331 * The simple solution is to use the recompiler.
332 * The better solution is to disassemble the current instruction and
333 * try handle as many as possible without using REM.
334 *
335 */
336
337#ifdef LOG_ENABLED
338 /*
339 * Disassemble the instruction if requested.
340 */
341 if (pszPrefix)
342 {
343 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
344 DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
345 }
346#endif /* LOG_ENABLED */
347
348 /*
349 * PATM is making life more interesting.
350 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
351 * tell PATM there is a trap in this code and have it take the appropriate actions
352 * to allow us execute the code in REM.
353 */
354 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
355 {
356 Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
357
358 RTGCPTR pNewEip;
359 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
360 switch (rc)
361 {
362 /*
363 * It's not very useful to emulate a single instruction and then go back to raw
364 * mode; just execute the whole block until IF is set again.
365 */
366 case VINF_SUCCESS:
367 Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
368 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
369 pCtx->eip = pNewEip;
370 Assert(pCtx->eip);
371
372 if (pCtx->eflags.Bits.u1IF)
373 {
374 /*
375 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
376 */
377 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
378 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
379 }
380 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
381 {
382 /* special case: iret, that sets IF, detected a pending irq/event */
383 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
384 }
385 return VINF_EM_RESCHEDULE_REM;
386
387 /*
388 * One instruction.
389 */
390 case VINF_PATCH_EMULATE_INSTR:
391 Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
392 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
393 pCtx->eip = pNewEip;
394 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
395
396 /*
397 * The patch was disabled, hand it to the REM.
398 */
399 case VERR_PATCH_DISABLED:
400 Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
401 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
402 pCtx->eip = pNewEip;
403 if (pCtx->eflags.Bits.u1IF)
404 {
405 /*
406 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
407 */
408 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
409 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
410 }
411 return VINF_EM_RESCHEDULE_REM;
412
413 /* Force continued patch exection; usually due to write monitored stack. */
414 case VINF_PATCH_CONTINUE:
415 return VINF_SUCCESS;
416
417 default:
418 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
419 return VERR_IPE_UNEXPECTED_STATUS;
420 }
421 }
422
423#if 0
424 /* Try our own instruction emulator before falling back to the recompiler. */
425 DISCPUSTATE Cpu;
426 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
427 if (RT_SUCCESS(rc))
428 {
429 uint32_t size;
430
431 switch (Cpu.pCurInstr->opcode)
432 {
433 /* @todo we can do more now */
434 case OP_MOV:
435 case OP_AND:
436 case OP_OR:
437 case OP_XOR:
438 case OP_POP:
439 case OP_INC:
440 case OP_DEC:
441 case OP_XCHG:
442 STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
443 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
444 if (RT_SUCCESS(rc))
445 {
446 pCtx->rip += Cpu.opsize;
447 STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
448 return rc;
449 }
450 if (rc != VERR_EM_INTERPRETER)
451 AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
452 STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
453 break;
454 }
455 }
456#endif /* 0 */
457 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
458 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
459 EMRemLock(pVM);
460 /* Flush the recompiler TLB if the VCPU has changed. */
461 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
462 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
463 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
464
465 rc = REMR3EmulateInstruction(pVM, pVCpu);
466 EMRemUnlock(pVM);
467 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
468
469 return rc;
470}
471
472
473/**
474 * Executes one (or perhaps a few more) instruction(s).
475 * This is just a wrapper for discarding pszPrefix in non-logging builds.
476 *
477 * @returns VBox status code suitable for EM.
478 * @param pVM VM handle.
479 * @param pVCpu VMCPU handle.
480 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
481 * instruction and prefix the log output with this text.
482 * @param rcGC GC return code
483 */
484DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
485{
486#ifdef LOG_ENABLED
487 return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
488#else
489 return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
490#endif
491}
492
493/**
494 * Executes one (or perhaps a few more) IO instruction(s).
495 *
496 * @returns VBox status code suitable for EM.
497 * @param pVM VM handle.
498 * @param pVCpu VMCPU handle.
499 */
500static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
501{
502 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
503
504 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
505
506 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
507 * as io instructions tend to come in packages of more than one
508 */
509 DISCPUSTATE Cpu;
510 int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
511 if (RT_SUCCESS(rc))
512 {
513 VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
514
515 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
516 {
517 switch (Cpu.pCurInstr->opcode)
518 {
519 case OP_IN:
520 {
521 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
522 rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
523 break;
524 }
525
526 case OP_OUT:
527 {
528 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
529 rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
530 break;
531 }
532 }
533 }
534 else if (Cpu.prefix & PREFIX_REP)
535 {
536 switch (Cpu.pCurInstr->opcode)
537 {
538 case OP_INSB:
539 case OP_INSWD:
540 {
541 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
542 rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
543 break;
544 }
545
546 case OP_OUTSB:
547 case OP_OUTSWD:
548 {
549 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
550 rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
551 break;
552 }
553 }
554 }
555
556 /*
557 * Handled the I/O return codes.
558 * (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
559 */
560 if (IOM_SUCCESS(rcStrict))
561 {
562 pCtx->rip += Cpu.opsize;
563 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
564 return VBOXSTRICTRC_TODO(rcStrict);
565 }
566
567 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
568 {
569 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
570 rcStrict = emR3RawGuestTrap(pVM, pVCpu);
571 return VBOXSTRICTRC_TODO(rcStrict);
572 }
573 AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
574
575 if (RT_FAILURE(rcStrict))
576 {
577 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
578 return VBOXSTRICTRC_TODO(rcStrict);
579 }
580 AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR || rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
581 }
582 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
583 return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
584}
585
586
587/**
588 * Handle a guest context trap.
589 *
590 * @returns VBox status code suitable for EM.
591 * @param pVM VM handle.
592 * @param pVCpu VMCPU handle.
593 */
594static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
595{
596 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
597
598 /*
599 * Get the trap info.
600 */
601 uint8_t u8TrapNo;
602 TRPMEVENT enmType;
603 RTGCUINT uErrorCode;
604 RTGCUINTPTR uCR2;
605 int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
606 if (RT_FAILURE(rc))
607 {
608 AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
609 return rc;
610 }
611
612
613#if 1 /* Experimental: Review, disable if it causes trouble. */
614 /*
615 * Handle traps in patch code first.
616 *
617 * We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
618 * but several traps isn't handled specially by TRPM in RC and we end up here
619 * instead. One example is #DE.
620 */
621 uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
622 if ( uCpl == 0
623 && PATMIsPatchGCAddr(pVM, pCtx->eip))
624 {
625 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
626 return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
627 }
628#endif
629
630 /*
631 * If the guest gate is marked unpatched, then we will check again if we can patch it.
632 * (This assumes that we've already tried and failed to dispatch the trap in
633 * RC for the gates that already has been patched. Which is true for most high
634 * volume traps, because these are handled specially, but not for odd ones like #DE.)
635 */
636 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
637 {
638 CSAMR3CheckGates(pVM, u8TrapNo, 1);
639 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
640
641 /* If it was successful, then we could go back to raw mode. */
642 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
643 {
644 /* Must check pending forced actions as our IDT or GDT might be out of sync. */
645 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
646 AssertRCReturn(rc, rc);
647
648 TRPMERRORCODE enmError = uErrorCode != ~0U
649 ? TRPM_TRAP_HAS_ERRORCODE
650 : TRPM_TRAP_NO_ERRORCODE;
651 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
652 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
653 {
654 TRPMResetTrap(pVCpu);
655 return VINF_EM_RESCHEDULE_RAW;
656 }
657 AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
658 }
659 }
660
661 /*
662 * Scan kernel code that traps; we might not get another chance.
663 */
664 /** @todo move this up before the dispatching? */
665 if ( (pCtx->ss & X86_SEL_RPL) <= 1
666 && !pCtx->eflags.Bits.u1VM)
667 {
668 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
669 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
670 }
671
672 /*
673 * Trap specific handling.
674 */
675 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
676 {
677 /*
678 * If MONITOR & MWAIT are supported, then interpret them here.
679 */
680 DISCPUSTATE cpu;
681 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
682 if ( RT_SUCCESS(rc)
683 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
684 {
685 uint32_t u32Dummy, u32Features, u32ExtFeatures;
686 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
687 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
688 {
689 rc = TRPMResetTrap(pVCpu);
690 AssertRC(rc);
691
692 uint32_t opsize;
693 rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
694 if (RT_SUCCESS(rc))
695 {
696 pCtx->rip += cpu.opsize;
697 return rc;
698 }
699 return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
700 }
701 }
702 }
703 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
704 {
705 /*
706 * Handle I/O bitmap?
707 */
708 /** @todo We're not supposed to be here with a false guest trap concerning
709 * I/O access. We can easily handle those in RC. */
710 DISCPUSTATE cpu;
711 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
712 if ( RT_SUCCESS(rc)
713 && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
714 {
715 /*
716 * We should really check the TSS for the IO bitmap, but it's not like this
717 * lazy approach really makes things worse.
718 */
719 rc = TRPMResetTrap(pVCpu);
720 AssertRC(rc);
721 return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
722 }
723 }
724
725#ifdef LOG_ENABLED
726 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
727 DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
728
729 /* Get guest page information. */
730 uint64_t fFlags = 0;
731 RTGCPHYS GCPhys = 0;
732 int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
733 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
734 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
735 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
736 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
737#endif
738
739 /*
740 * #PG has CR2.
741 * (Because of stuff like above we must set CR2 in a delayed fashion.)
742 */
743 if (u8TrapNo == 14 /* #PG */)
744 pCtx->cr2 = uCR2;
745
746 return VINF_EM_RESCHEDULE_REM;
747}
748
749
750/**
751 * Handle a ring switch trap.
752 * Need to do statistics and to install patches. The result is going to REM.
753 *
754 * @returns VBox status code suitable for EM.
755 * @param pVM VM handle.
756 * @param pVCpu VMCPU handle.
757 */
758static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
759{
760 int rc;
761 DISCPUSTATE Cpu;
762 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
763
764 /*
765 * sysenter, syscall & callgate
766 */
767 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
768 if (RT_SUCCESS(rc))
769 {
770 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
771 {
772 if (pCtx->SysEnter.cs != 0)
773 {
774 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
775 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
776 if (RT_SUCCESS(rc))
777 {
778 DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
779 return VINF_EM_RESCHEDULE_RAW;
780 }
781 }
782 }
783
784#ifdef VBOX_WITH_STATISTICS
785 switch (Cpu.pCurInstr->opcode)
786 {
787 case OP_SYSENTER:
788 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
789 break;
790 case OP_SYSEXIT:
791 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
792 break;
793 case OP_SYSCALL:
794 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
795 break;
796 case OP_SYSRET:
797 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
798 break;
799 }
800#endif
801 }
802 else
803 AssertRC(rc);
804
805 /* go to the REM to emulate a single instruction */
806 return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
807}
808
809
810/**
811 * Handle a trap (\#PF or \#GP) in patch code
812 *
813 * @returns VBox status code suitable for EM.
814 * @param pVM VM handle.
815 * @param pVCpu VMCPU handle.
816 * @param pCtx CPU context
817 * @param gcret GC return code
818 */
819static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
820{
821 uint8_t u8TrapNo;
822 int rc;
823 TRPMEVENT enmType;
824 RTGCUINT uErrorCode;
825 RTGCUINTPTR uCR2;
826
827 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
828
829 if (gcret == VINF_PATM_PATCH_INT3)
830 {
831 u8TrapNo = 3;
832 uCR2 = 0;
833 uErrorCode = 0;
834 }
835 else if (gcret == VINF_PATM_PATCH_TRAP_GP)
836 {
837 /* No active trap in this case. Kind of ugly. */
838 u8TrapNo = X86_XCPT_GP;
839 uCR2 = 0;
840 uErrorCode = 0;
841 }
842 else
843 {
844 rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
845 if (RT_FAILURE(rc))
846 {
847 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
848 return rc;
849 }
850 /* Reset the trap as we'll execute the original instruction again. */
851 TRPMResetTrap(pVCpu);
852 }
853
854 /*
855 * Deal with traps inside patch code.
856 * (This code won't run outside GC.)
857 */
858 if (u8TrapNo != 1)
859 {
860#ifdef LOG_ENABLED
861 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
862 DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
863
864 DISCPUSTATE Cpu;
865 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
866 if ( RT_SUCCESS(rc)
867 && Cpu.pCurInstr->opcode == OP_IRET)
868 {
869 uint32_t eip, selCS, uEFlags;
870
871 /* Iret crashes are bad as we have already changed the flags on the stack */
872 rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
873 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
874 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
875 if (rc == VINF_SUCCESS)
876 {
877 if ( (uEFlags & X86_EFL_VM)
878 || (selCS & X86_SEL_RPL) == 3)
879 {
880 uint32_t selSS, esp;
881
882 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
883 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
884
885 if (uEFlags & X86_EFL_VM)
886 {
887 uint32_t selDS, selES, selFS, selGS;
888 rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
889 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
890 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
891 rc |= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
892 if (rc == VINF_SUCCESS)
893 {
894 Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
895 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
896 }
897 }
898 else
899 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
900 }
901 else
902 Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
903 }
904 }
905#endif /* LOG_ENABLED */
906 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
907 pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
908
909 RTGCPTR pNewEip;
910 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
911 switch (rc)
912 {
913 /*
914 * Execute the faulting instruction.
915 */
916 case VINF_SUCCESS:
917 {
918 /** @todo execute a whole block */
919 Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
920 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
921 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
922
923 pCtx->eip = pNewEip;
924 AssertRelease(pCtx->eip);
925
926 if (pCtx->eflags.Bits.u1IF)
927 {
928 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
929 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
930 */
931 if ( u8TrapNo == X86_XCPT_GP
932 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
933 {
934 /** @todo move to PATMR3HandleTrap */
935 Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
936 PATMR3RemovePatch(pVM, pCtx->eip);
937 }
938
939 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
940 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
941
942 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
943 /* Interrupts are enabled; just go back to the original instruction.
944 return VINF_SUCCESS; */
945 }
946 return VINF_EM_RESCHEDULE_REM;
947 }
948
949 /*
950 * One instruction.
951 */
952 case VINF_PATCH_EMULATE_INSTR:
953 Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
954 pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
955 pCtx->eip = pNewEip;
956 AssertRelease(pCtx->eip);
957 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
958
959 /*
960 * The patch was disabled, hand it to the REM.
961 */
962 case VERR_PATCH_DISABLED:
963 if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
964 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
965 pCtx->eip = pNewEip;
966 AssertRelease(pCtx->eip);
967
968 if (pCtx->eflags.Bits.u1IF)
969 {
970 /*
971 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
972 */
973 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
974 return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
975 }
976 return VINF_EM_RESCHEDULE_REM;
977
978 /* Force continued patch exection; usually due to write monitored stack. */
979 case VINF_PATCH_CONTINUE:
980 return VINF_SUCCESS;
981
982 /*
983 * Anything else is *fatal*.
984 */
985 default:
986 AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
987 return VERR_IPE_UNEXPECTED_STATUS;
988 }
989 }
990 return VINF_SUCCESS;
991}
992
993
994/**
995 * Handle a privileged instruction.
996 *
997 * @returns VBox status code suitable for EM.
998 * @param pVM VM handle.
999 * @param pVCpu VMCPU handle;
1000 */
1001static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
1002{
1003 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1004
1005 Assert(!pCtx->eflags.Bits.u1VM);
1006
1007 if (PATMIsEnabled(pVM))
1008 {
1009 /*
1010 * Check if in patch code.
1011 */
1012 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1013 {
1014#ifdef LOG_ENABLED
1015 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1016#endif
1017 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1018 return VERR_EM_RAW_PATCH_CONFLICT;
1019 }
1020 if ( (pCtx->ss & X86_SEL_RPL) == 0
1021 && !pCtx->eflags.Bits.u1VM
1022 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1023 {
1024 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1025 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1026 if (RT_SUCCESS(rc))
1027 {
1028#ifdef LOG_ENABLED
1029 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1030#endif
1031 DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
1032 return VINF_SUCCESS;
1033 }
1034 }
1035 }
1036
1037#ifdef LOG_ENABLED
1038 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1039 {
1040 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1041 DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1042 }
1043#endif
1044
1045 /*
1046 * Instruction statistics and logging.
1047 */
1048 DISCPUSTATE Cpu;
1049 int rc;
1050
1051 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1052 if (RT_SUCCESS(rc))
1053 {
1054#ifdef VBOX_WITH_STATISTICS
1055 PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
1056 switch (Cpu.pCurInstr->opcode)
1057 {
1058 case OP_INVLPG:
1059 STAM_COUNTER_INC(&pStats->StatInvlpg);
1060 break;
1061 case OP_IRET:
1062 STAM_COUNTER_INC(&pStats->StatIret);
1063 break;
1064 case OP_CLI:
1065 STAM_COUNTER_INC(&pStats->StatCli);
1066 emR3RecordCli(pVM, pVCpu, pCtx->rip);
1067 break;
1068 case OP_STI:
1069 STAM_COUNTER_INC(&pStats->StatSti);
1070 break;
1071 case OP_INSB:
1072 case OP_INSWD:
1073 case OP_IN:
1074 case OP_OUTSB:
1075 case OP_OUTSWD:
1076 case OP_OUT:
1077 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1078 break;
1079
1080 case OP_MOV_CR:
1081 if (Cpu.param1.flags & USE_REG_GEN32)
1082 {
1083 //read
1084 Assert(Cpu.param2.flags & USE_REG_CR);
1085 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1086 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1087 }
1088 else
1089 {
1090 //write
1091 Assert(Cpu.param1.flags & USE_REG_CR);
1092 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1093 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1094 }
1095 break;
1096
1097 case OP_MOV_DR:
1098 STAM_COUNTER_INC(&pStats->StatMovDRx);
1099 break;
1100 case OP_LLDT:
1101 STAM_COUNTER_INC(&pStats->StatMovLldt);
1102 break;
1103 case OP_LIDT:
1104 STAM_COUNTER_INC(&pStats->StatMovLidt);
1105 break;
1106 case OP_LGDT:
1107 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1108 break;
1109 case OP_SYSENTER:
1110 STAM_COUNTER_INC(&pStats->StatSysEnter);
1111 break;
1112 case OP_SYSEXIT:
1113 STAM_COUNTER_INC(&pStats->StatSysExit);
1114 break;
1115 case OP_SYSCALL:
1116 STAM_COUNTER_INC(&pStats->StatSysCall);
1117 break;
1118 case OP_SYSRET:
1119 STAM_COUNTER_INC(&pStats->StatSysRet);
1120 break;
1121 case OP_HLT:
1122 STAM_COUNTER_INC(&pStats->StatHlt);
1123 break;
1124 default:
1125 STAM_COUNTER_INC(&pStats->StatMisc);
1126 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1127 break;
1128 }
1129#endif /* VBOX_WITH_STATISTICS */
1130 if ( (pCtx->ss & X86_SEL_RPL) == 0
1131 && !pCtx->eflags.Bits.u1VM
1132 && SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1133 {
1134 uint32_t size;
1135
1136 STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1137 switch (Cpu.pCurInstr->opcode)
1138 {
1139 case OP_CLI:
1140 pCtx->eflags.u32 &= ~X86_EFL_IF;
1141 Assert(Cpu.opsize == 1);
1142 pCtx->rip += Cpu.opsize;
1143 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1144 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1145
1146 case OP_STI:
1147 pCtx->eflags.u32 |= X86_EFL_IF;
1148 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
1149 Assert(Cpu.opsize == 1);
1150 pCtx->rip += Cpu.opsize;
1151 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1152 return VINF_SUCCESS;
1153
1154 case OP_HLT:
1155 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1156 {
1157 PATMTRANSSTATE enmState;
1158 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1159
1160 if (enmState == PATMTRANS_OVERWRITTEN)
1161 {
1162 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1163 Assert(rc == VERR_PATCH_DISABLED);
1164 /* Conflict detected, patch disabled */
1165 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1166
1167 enmState = PATMTRANS_SAFE;
1168 }
1169
1170 /* The translation had better be successful. Otherwise we can't recover. */
1171 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1172 if (enmState != PATMTRANS_OVERWRITTEN)
1173 pCtx->eip = pOrgInstrGC;
1174 }
1175 /* no break; we could just return VINF_EM_HALT here */
1176
1177 case OP_MOV_CR:
1178 case OP_MOV_DR:
1179#ifdef LOG_ENABLED
1180 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1181 {
1182 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1183 DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1184 }
1185#endif
1186
1187 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1188 if (RT_SUCCESS(rc))
1189 {
1190 pCtx->rip += Cpu.opsize;
1191 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1192
1193 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1194 && Cpu.param1.flags == USE_REG_CR /* write */
1195 )
1196 {
1197 /* Deal with CR0 updates inside patch code that force
1198 * us to go to the recompiler.
1199 */
1200 if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1201 && (pCtx->cr0 & (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE)) != (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE))
1202 {
1203 PATMTRANSSTATE enmState;
1204 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1205
1206 Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1207 if (enmState == PATMTRANS_OVERWRITTEN)
1208 {
1209 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1210 Assert(rc == VERR_PATCH_DISABLED);
1211 /* Conflict detected, patch disabled */
1212 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1213 enmState = PATMTRANS_SAFE;
1214 }
1215 /* The translation had better be successful. Otherwise we can't recover. */
1216 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1217 if (enmState != PATMTRANS_OVERWRITTEN)
1218 pCtx->rip = pOrgInstrGC;
1219 }
1220
1221 /* Reschedule is necessary as the execution/paging mode might have changed. */
1222 return VINF_EM_RESCHEDULE;
1223 }
1224 return rc; /* can return VINF_EM_HALT as well. */
1225 }
1226 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1227 break; /* fall back to the recompiler */
1228 }
1229 STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1230 }
1231 }
1232
1233 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1234 return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1235
1236 return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1237}
1238
1239
1240/**
1241 * Update the forced rawmode execution modifier.
1242 *
1243 * This function is called when we're returning from the raw-mode loop(s). If we're
1244 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1245 * if not in patch code, the flag will be cleared.
1246 *
1247 * We should never interrupt patch code while it's being executed. Cli patches can
1248 * contain big code blocks, but they are always executed with IF=0. Other patches
1249 * replace single instructions and should be atomic.
1250 *
1251 * @returns Updated rc.
1252 *
1253 * @param pVM The VM handle.
1254 * @param pVCpu The VMCPU handle.
1255 * @param pCtx The guest CPU context.
1256 * @param rc The result code.
1257 */
1258int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1259{
1260 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1261 {
1262 /* ignore reschedule attempts. */
1263 switch (rc)
1264 {
1265 case VINF_EM_RESCHEDULE:
1266 case VINF_EM_RESCHEDULE_REM:
1267 LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1268 rc = VINF_SUCCESS;
1269 break;
1270 }
1271 pVCpu->em.s.fForceRAW = true;
1272 }
1273 else
1274 pVCpu->em.s.fForceRAW = false;
1275 return rc;
1276}
1277
1278
1279/**
1280 * Check for pending raw actions
1281 *
1282 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1283 * EM statuses.
1284 * @param pVM The VM to operate on.
1285 * @param pVCpu The VMCPU handle.
1286 */
1287VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1288{
1289 return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1290}
1291
1292
1293/**
1294 * Process raw-mode specific forced actions.
1295 *
1296 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1297 *
1298 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1299 * EM statuses.
1300 * @param pVM The VM handle.
1301 * @param pVCpu The VMCPU handle.
1302 * @param pCtx The guest CPUM register context.
1303 */
1304static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1305{
1306 /*
1307 * Note that the order is *vitally* important!
1308 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1309 */
1310
1311
1312 /*
1313 * Sync selector tables.
1314 */
1315 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT))
1316 {
1317 int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1318 if (RT_FAILURE(rc))
1319 return rc;
1320 }
1321
1322 /*
1323 * Sync IDT.
1324 *
1325 * The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1326 * and PGMShwModifyPage, so we're in for trouble if for instance a
1327 * PGMSyncCR3+pgmR3PoolClearAll is pending.
1328 */
1329 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1330 {
1331 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1332 && EMIsRawRing0Enabled(pVM)
1333 && CSAMIsEnabled(pVM))
1334 {
1335 int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1336 if (RT_FAILURE(rc))
1337 return rc;
1338 }
1339
1340 int rc = TRPMR3SyncIDT(pVM, pVCpu);
1341 if (RT_FAILURE(rc))
1342 return rc;
1343 }
1344
1345 /*
1346 * Sync TSS.
1347 */
1348 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1349 {
1350 int rc = SELMR3SyncTSS(pVM, pVCpu);
1351 if (RT_FAILURE(rc))
1352 return rc;
1353 }
1354
1355 /*
1356 * Sync page directory.
1357 */
1358 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1359 {
1360 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1361 int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1362 if (RT_FAILURE(rc))
1363 return rc;
1364
1365 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1366
1367 /* Prefetch pages for EIP and ESP. */
1368 /** @todo This is rather expensive. Should investigate if it really helps at all. */
1369 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1370 if (rc == VINF_SUCCESS)
1371 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1372 if (rc != VINF_SUCCESS)
1373 {
1374 if (rc != VINF_PGM_SYNC_CR3)
1375 {
1376 AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1377 return rc;
1378 }
1379 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1380 if (RT_FAILURE(rc))
1381 return rc;
1382 }
1383 /** @todo maybe prefetch the supervisor stack page as well */
1384 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
1385 }
1386
1387 /*
1388 * Allocate handy pages (just in case the above actions have consumed some pages).
1389 */
1390 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1391 {
1392 int rc = PGMR3PhysAllocateHandyPages(pVM);
1393 if (RT_FAILURE(rc))
1394 return rc;
1395 }
1396
1397 /*
1398 * Check whether we're out of memory now.
1399 *
1400 * This may stem from some of the above actions or operations that has been executed
1401 * since we ran FFs. The allocate handy pages must for instance always be followed by
1402 * this check.
1403 */
1404 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1405 return VINF_EM_NO_MEMORY;
1406
1407 return VINF_SUCCESS;
1408}
1409
1410
1411/**
1412 * Executes raw code.
1413 *
1414 * This function contains the raw-mode version of the inner
1415 * execution loop (the outer loop being in EMR3ExecuteVM()).
1416 *
1417 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1418 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1419 *
1420 * @param pVM VM handle.
1421 * @param pVCpu VMCPU handle.
1422 * @param pfFFDone Where to store an indicator telling whether or not
1423 * FFs were done before returning.
1424 */
1425int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1426{
1427 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1428
1429 int rc = VERR_INTERNAL_ERROR;
1430 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1431 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
1432 pVCpu->em.s.fForceRAW = false;
1433 *pfFFDone = false;
1434
1435
1436 /*
1437 *
1438 * Spin till we get a forced action or raw mode status code resulting in
1439 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1440 *
1441 */
1442 for (;;)
1443 {
1444 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1445
1446 /*
1447 * Check various preconditions.
1448 */
1449#ifdef VBOX_STRICT
1450 Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1451 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
1452 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1453 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1454 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1455 if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1456 && PGMMapHasConflicts(pVM))
1457 {
1458 PGMMapCheck(pVM);
1459 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1460 return VERR_INTERNAL_ERROR;
1461 }
1462#endif /* VBOX_STRICT */
1463
1464 /*
1465 * Process high priority pre-execution raw-mode FFs.
1466 */
1467 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1468 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1469 {
1470 rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1471 if (rc != VINF_SUCCESS)
1472 break;
1473 }
1474
1475 /*
1476 * If we're going to execute ring-0 code, the guest state needs to
1477 * be modified a bit and some of the state components (IF, SS/CS RPL,
1478 * and perhaps EIP) needs to be stored with PATM.
1479 */
1480 rc = CPUMRawEnter(pVCpu, NULL);
1481 if (rc != VINF_SUCCESS)
1482 {
1483 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1484 break;
1485 }
1486
1487 /*
1488 * Scan code before executing it. Don't bother with user mode or V86 code
1489 */
1490 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1491 && !pCtx->eflags.Bits.u1VM
1492 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1493 {
1494 STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1495 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1496 STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1497 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1498 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1499 {
1500 rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1501 if (rc != VINF_SUCCESS)
1502 {
1503 rc = CPUMRawLeave(pVCpu, NULL, rc);
1504 break;
1505 }
1506 }
1507 }
1508
1509#ifdef LOG_ENABLED
1510 /*
1511 * Log important stuff before entering GC.
1512 */
1513 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1514 if (pCtx->eflags.Bits.u1VM)
1515 Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1516 else if ((pCtx->ss & X86_SEL_RPL) == 1)
1517 {
1518 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1519 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
1520 }
1521 else if ((pCtx->ss & X86_SEL_RPL) == 3)
1522 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1523#endif /* LOG_ENABLED */
1524
1525
1526
1527 /*
1528 * Execute the code.
1529 */
1530 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1531 STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1532 rc = VMMR3RawRunGC(pVM, pVCpu);
1533 STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1534 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1535
1536 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
1537 LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1538
1539
1540
1541 /*
1542 * Restore the real CPU state and deal with high priority post
1543 * execution FFs before doing anything else.
1544 */
1545 rc = CPUMRawLeave(pVCpu, NULL, rc);
1546 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1547 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1548 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1549 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1550
1551#ifdef VBOX_STRICT
1552 /*
1553 * Assert TSS consistency & rc vs patch code.
1554 */
1555 if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1556 && EMIsRawRing0Enabled(pVM))
1557 SELMR3CheckTSS(pVM);
1558 switch (rc)
1559 {
1560 case VINF_SUCCESS:
1561 case VINF_EM_RAW_INTERRUPT:
1562 case VINF_PATM_PATCH_TRAP_PF:
1563 case VINF_PATM_PATCH_TRAP_GP:
1564 case VINF_PATM_PATCH_INT3:
1565 case VINF_PATM_CHECK_PATCH_PAGE:
1566 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1567 case VINF_EM_RAW_GUEST_TRAP:
1568 case VINF_EM_RESCHEDULE_RAW:
1569 break;
1570
1571 default:
1572 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1573 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1574 break;
1575 }
1576 /*
1577 * Let's go paranoid!
1578 */
1579 if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1580 && PGMMapHasConflicts(pVM))
1581 {
1582 PGMMapCheck(pVM);
1583 AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1584 return VERR_INTERNAL_ERROR;
1585 }
1586#endif /* VBOX_STRICT */
1587
1588 /*
1589 * Process the returned status code.
1590 */
1591 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1592 {
1593 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1594 break;
1595 }
1596 rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1597 if (rc != VINF_SUCCESS)
1598 {
1599 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1600 if (rc != VINF_SUCCESS)
1601 {
1602 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1603 break;
1604 }
1605 }
1606
1607 /*
1608 * Check and execute forced actions.
1609 */
1610#ifdef VBOX_HIGH_RES_TIMERS_HACK
1611 TMTimerPollVoid(pVM, pVCpu);
1612#endif
1613 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1614 if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK | VM_FF_PGM_NO_MEMORY)
1615 || VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1616 {
1617 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
1618
1619 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1620 rc = emR3ForcedActions(pVM, pVCpu, rc);
1621 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1622 if ( rc != VINF_SUCCESS
1623 && rc != VINF_EM_RESCHEDULE_RAW)
1624 {
1625 rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1626 if (rc != VINF_SUCCESS)
1627 {
1628 *pfFFDone = true;
1629 break;
1630 }
1631 }
1632 }
1633 }
1634
1635 /*
1636 * Return to outer loop.
1637 */
1638#if defined(LOG_ENABLED) && defined(DEBUG)
1639 RTLogFlush(NULL);
1640#endif
1641 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1642 return rc;
1643}
1644
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