VirtualBox

source: vbox/trunk/src/VBox/VMM/EMHwaccm.cpp@ 30037

Last change on this file since 30037 was 29329, checked in by vboxsync, 14 years ago

removed VBOX_WITH_VMI
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1/* $Id: EMHwaccm.cpp 29329 2010-05-11 10:18:30Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager - hardware virtualization
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/em.h>
39#include <VBox/vmm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42#include <VBox/trpm.h>
43#include <VBox/iom.h>
44#include <VBox/dbgf.h>
45#include <VBox/pgm.h>
46#include <VBox/rem.h>
47#include <VBox/tm.h>
48#include <VBox/mm.h>
49#include <VBox/ssm.h>
50#include <VBox/pdmapi.h>
51#include <VBox/pdmcritsect.h>
52#include <VBox/pdmqueue.h>
53#include <VBox/hwaccm.h>
54#include "EMInternal.h"
55#include <VBox/vm.h>
56#include <VBox/cpumdis.h>
57#include <VBox/dis.h>
58#include <VBox/disopcode.h>
59#include <VBox/dbgf.h>
60
61#include <iprt/asm.h>
62
63
64/*******************************************************************************
65* Defined Constants And Macros *
66*******************************************************************************/
67#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
68#define EM_NOTIFY_HWACCM
69#endif
70
71
72/*******************************************************************************
73* Internal Functions *
74*******************************************************************************/
75DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
76static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
77static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
78
79#define EMHANDLERC_WITH_HWACCM
80#include "EMHandleRCTmpl.h"
81
82
83#ifdef DEBUG
84
85/**
86 * Steps hardware accelerated mode.
87 *
88 * @returns VBox status code.
89 * @param pVM The VM handle.
90 * @param pVCpu The VMCPU handle.
91 */
92static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
93{
94 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
95
96 int rc;
97 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
98 VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
99
100 /*
101 * Check vital forced actions, but ignore pending interrupts and timers.
102 */
103 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
104 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
105 {
106 rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
107 if (rc != VINF_SUCCESS)
108 return rc;
109 }
110 /*
111 * Set flags for single stepping.
112 */
113 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
114
115 /*
116 * Single step.
117 * We do not start time or anything, if anything we should just do a few nanoseconds.
118 */
119 do
120 {
121 rc = VMMR3HwAccRunGC(pVM, pVCpu);
122 } while ( rc == VINF_SUCCESS
123 || rc == VINF_EM_RAW_INTERRUPT);
124 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
125
126 /*
127 * Make sure the trap flag is cleared.
128 * (Too bad if the guest is trying to single step too.)
129 */
130 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
131
132 /*
133 * Deal with the return codes.
134 */
135 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
136 rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
137 return rc;
138}
139
140
141static int emR3SingleStepExecHwAcc(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
142{
143 int rc = VINF_SUCCESS;
144 EMSTATE enmOldState = pVCpu->em.s.enmState;
145 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
146
147 Log(("Single step BEGIN:\n"));
148 for (uint32_t i = 0; i < cIterations; i++)
149 {
150 DBGFR3PrgStep(pVCpu);
151 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
152 rc = emR3HwAccStep(pVM, pVCpu);
153 if ( rc != VINF_SUCCESS
154 || !HWACCMR3CanExecuteGuest(pVM, pVCpu->em.s.pCtx))
155 break;
156 }
157 Log(("Single step END: rc=%Rrc\n", rc));
158 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
159 pVCpu->em.s.enmState = enmOldState;
160 return rc == VINF_SUCCESS ? VINF_EM_RESCHEDULE_REM : rc;
161}
162
163#endif /* DEBUG */
164
165
166/**
167 * Executes one (or perhaps a few more) instruction(s).
168 *
169 * @returns VBox status code suitable for EM.
170 *
171 * @param pVM VM handle.
172 * @param pVCpu VMCPU handle
173 * @param rcGC GC return code
174 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
175 * instruction and prefix the log output with this text.
176 */
177#ifdef LOG_ENABLED
178static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
179#else
180static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
181#endif
182{
183 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
184 int rc;
185
186 /*
187 *
188 * The simple solution is to use the recompiler.
189 * The better solution is to disassemble the current instruction and
190 * try handle as many as possible without using REM.
191 *
192 */
193
194#ifdef LOG_ENABLED
195 /*
196 * Disassemble the instruction if requested.
197 */
198 if (pszPrefix)
199 {
200 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
201 DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
202 }
203#endif /* LOG_ENABLED */
204
205#if 0
206 /* Try our own instruction emulator before falling back to the recompiler. */
207 DISCPUSTATE Cpu;
208 rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
209 if (RT_SUCCESS(rc))
210 {
211 uint32_t size;
212
213 switch (Cpu.pCurInstr->opcode)
214 {
215 /* @todo we can do more now */
216 case OP_MOV:
217 case OP_AND:
218 case OP_OR:
219 case OP_XOR:
220 case OP_POP:
221 case OP_INC:
222 case OP_DEC:
223 case OP_XCHG:
224 STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
225 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
226 if (RT_SUCCESS(rc))
227 {
228 pCtx->rip += Cpu.opsize;
229#ifdef EM_NOTIFY_HWACCM
230 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
231 HWACCMR3NotifyEmulated(pVCpu);
232#endif
233 STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
234 return rc;
235 }
236 if (rc != VERR_EM_INTERPRETER)
237 AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
238 STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
239 break;
240 }
241 }
242#endif /* 0 */
243 STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
244 Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
245 EMRemLock(pVM);
246 /* Flush the recompiler TLB if the VCPU has changed. */
247 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
248 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
249 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
250
251 rc = REMR3EmulateInstruction(pVM, pVCpu);
252 EMRemUnlock(pVM);
253 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
254
255#ifdef EM_NOTIFY_HWACCM
256 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC)
257 HWACCMR3NotifyEmulated(pVCpu);
258#endif
259 return rc;
260}
261
262
263/**
264 * Executes one (or perhaps a few more) instruction(s).
265 * This is just a wrapper for discarding pszPrefix in non-logging builds.
266 *
267 * @returns VBox status code suitable for EM.
268 * @param pVM VM handle.
269 * @param pVCpu VMCPU handle.
270 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
271 * instruction and prefix the log output with this text.
272 * @param rcGC GC return code
273 */
274DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
275{
276#ifdef LOG_ENABLED
277 return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
278#else
279 return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
280#endif
281}
282
283/**
284 * Executes one (or perhaps a few more) IO instruction(s).
285 *
286 * @returns VBox status code suitable for EM.
287 * @param pVM VM handle.
288 * @param pVCpu VMCPU handle.
289 */
290static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
291{
292 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
293
294 STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
295
296 /* Try to restart the io instruction that was refused in ring-0. */
297 VBOXSTRICTRC rcStrict = HWACCMR3RestartPendingIOInstr(pVM, pVCpu, pCtx);
298 if (IOM_SUCCESS(rcStrict))
299 {
300 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
301 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
302 return VBOXSTRICTRC_TODO(rcStrict); /* rip already updated. */
303 }
304 AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)),
305 RT_SUCCESS_NP(rcStrict) ? VERR_INTERNAL_ERROR_5 : VBOXSTRICTRC_TODO(rcStrict));
306
307 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
308 * as io instructions tend to come in packages of more than one
309 */
310 DISCPUSTATE Cpu;
311 int rc2 = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
312 if (RT_SUCCESS(rc2))
313 {
314 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
315
316 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
317 {
318 switch (Cpu.pCurInstr->opcode)
319 {
320 case OP_IN:
321 {
322 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
323 rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
324 break;
325 }
326
327 case OP_OUT:
328 {
329 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
330 rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
331 break;
332 }
333 }
334 }
335 else if (Cpu.prefix & PREFIX_REP)
336 {
337 switch (Cpu.pCurInstr->opcode)
338 {
339 case OP_INSB:
340 case OP_INSWD:
341 {
342 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
343 rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
344 break;
345 }
346
347 case OP_OUTSB:
348 case OP_OUTSWD:
349 {
350 STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
351 rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
352 break;
353 }
354 }
355 }
356
357 /*
358 * Handled the I/O return codes.
359 * (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
360 */
361 if (IOM_SUCCESS(rcStrict))
362 {
363 pCtx->rip += Cpu.opsize;
364 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
365 return VBOXSTRICTRC_TODO(rcStrict);
366 }
367
368 if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
369 {
370 /* The active trap will be dispatched. */
371 Assert(TRPMHasTrap(pVCpu));
372 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
373 return VINF_SUCCESS;
374 }
375 AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
376
377 if (RT_FAILURE(rcStrict))
378 {
379 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
380 return VBOXSTRICTRC_TODO(rcStrict);
381 }
382 AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR || rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
383 }
384
385 STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
386 return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
387}
388
389
390/**
391 * Process raw-mode specific forced actions.
392 *
393 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
394 *
395 * @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
396 * EM statuses.
397 * @param pVM The VM handle.
398 * @param pVCpu The VMCPU handle.
399 * @param pCtx The guest CPUM register context.
400 */
401static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
402{
403 /*
404 * Sync page directory.
405 */
406 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
407 {
408 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
409 int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
410 if (RT_FAILURE(rc))
411 return rc;
412
413 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
414
415 /* Prefetch pages for EIP and ESP. */
416 /** @todo This is rather expensive. Should investigate if it really helps at all. */
417 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
418 if (rc == VINF_SUCCESS)
419 rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
420 if (rc != VINF_SUCCESS)
421 {
422 if (rc != VINF_PGM_SYNC_CR3)
423 {
424 AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
425 return rc;
426 }
427 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
428 if (RT_FAILURE(rc))
429 return rc;
430 }
431 /** @todo maybe prefetch the supervisor stack page as well */
432 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
433 }
434
435 /*
436 * Allocate handy pages (just in case the above actions have consumed some pages).
437 */
438 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
439 {
440 int rc = PGMR3PhysAllocateHandyPages(pVM);
441 if (RT_FAILURE(rc))
442 return rc;
443 }
444
445 /*
446 * Check whether we're out of memory now.
447 *
448 * This may stem from some of the above actions or operations that has been executed
449 * since we ran FFs. The allocate handy pages must for instance always be followed by
450 * this check.
451 */
452 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
453 return VINF_EM_NO_MEMORY;
454
455 return VINF_SUCCESS;
456}
457
458
459/**
460 * Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
461 *
462 * This function contains the raw-mode version of the inner
463 * execution loop (the outer loop being in EMR3ExecuteVM()).
464 *
465 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
466 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
467 *
468 * @param pVM VM handle.
469 * @param pVCpu VMCPU handle.
470 * @param pfFFDone Where to store an indicator telling whether or not
471 * FFs were done before returning.
472 */
473int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
474{
475 int rc = VERR_INTERNAL_ERROR;
476 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
477
478 LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip));
479 *pfFFDone = false;
480
481 STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
482
483#ifdef EM_NOTIFY_HWACCM
484 HWACCMR3NotifyScheduled(pVCpu);
485#endif
486
487 /*
488 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
489 */
490 for (;;)
491 {
492 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
493
494 /* Check if a forced reschedule is pending. */
495 if (HWACCMR3IsRescheduleRequired(pVM, pCtx))
496 {
497 rc = VINF_EM_RESCHEDULE;
498 break;
499 }
500
501 /*
502 * Process high priority pre-execution raw-mode FFs.
503 */
504 VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
505 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
506 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
507 {
508 rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
509 if (rc != VINF_SUCCESS)
510 break;
511 }
512
513#ifdef LOG_ENABLED
514 /*
515 * Log important stuff before entering GC.
516 */
517 if (TRPMHasTrap(pVCpu))
518 Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
519
520 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
521
522 if (pVM->cCpus == 1)
523 {
524 if (pCtx->eflags.Bits.u1VM)
525 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
526 else if (CPUMIsGuestIn64BitCodeEx(pCtx))
527 Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
528 else
529 Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
530 }
531 else
532 {
533 if (pCtx->eflags.Bits.u1VM)
534 Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
535 else if (CPUMIsGuestIn64BitCodeEx(pCtx))
536 Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
537 else
538 Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
539 }
540#endif /* LOG_ENABLED */
541
542 /*
543 * Execute the code.
544 */
545 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
546 STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
547 rc = VMMR3HwAccRunGC(pVM, pVCpu);
548 STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
549
550 /*
551 * Deal with high priority post execution FFs before doing anything else.
552 */
553 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
554 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
555 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
556 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
557
558 /*
559 * Process the returned status code.
560 */
561 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
562 break;
563
564 rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
565 if (rc != VINF_SUCCESS)
566 break;
567
568 /*
569 * Check and execute forced actions.
570 */
571#ifdef VBOX_HIGH_RES_TIMERS_HACK
572 TMTimerPollVoid(pVM, pVCpu);
573#endif
574 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
575 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
576 {
577 rc = emR3ForcedActions(pVM, pVCpu, rc);
578 if ( rc != VINF_SUCCESS
579 && rc != VINF_EM_RESCHEDULE_HWACC)
580 {
581 *pfFFDone = true;
582 break;
583 }
584 }
585 }
586
587 /*
588 * Return to outer loop.
589 */
590#if defined(LOG_ENABLED) && defined(DEBUG)
591 RTLogFlush(NULL);
592#endif
593 return rc;
594}
595
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