EM.cpp@ 13702

Last change on this file since 13702 was 13702, checked in by vboxsync, 17 years ago
VMM++: new EM status code VINF_EM_DBG_RING0_ASSERTION for distinguishing ring-0 and hyper assertions. Resynched the .mac files, hacking the x86.h sed transformations in the process.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 151.0 KB

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1	/* $Id: EM.cpp 13702 2008-10-31 00:03:32Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/hwaccm.h>
62	#include <VBox/patm.h>
63	#include "EMInternal.h"
64	#include <VBox/vm.h>
65	#include <VBox/cpumdis.h>
66	#include <VBox/dis.h>
67	#include <VBox/disopcode.h>
68	#include <VBox/dbgf.h>
69
70	#include <VBox/log.h>
71	#include <iprt/thread.h>
72	#include <iprt/assert.h>
73	#include <iprt/asm.h>
74	#include <iprt/semaphore.h>
75	#include <iprt/string.h>
76	#include <iprt/avl.h>
77	#include <iprt/stream.h>
78	#include <VBox/param.h>
79	#include <VBox/err.h>
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
87	static int emR3Debug(PVM pVM, int rc);
88	static int emR3RemStep(PVM pVM);
89	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
90	static int emR3RawResumeHyper(PVM pVM);
91	static int emR3RawStep(PVM pVM);
92	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
93	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
94	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
95	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
96	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
97	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
98	static int emR3ForcedActions(PVM pVM, int rc);
99	static int emR3RawGuestTrap(PVM pVM);
100	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret);
101
102
103	/**
104	* Initializes the EM.
105	*
106	* @returns VBox status code.
107	* @param pVM The VM to operate on.
108	*/
109	VMMR3DECL(int) EMR3Init(PVM pVM)
110	{
111	LogFlow(("EMR3Init\n"));
112	/*
113	* Assert alignment and sizes.
114	*/
115	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
116	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
117	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
118	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
119
120	/*
121	* Init the structure.
122	*/
123	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
124	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
125	if (VBOX_FAILURE(rc))
126	pVM->fRawR3Enabled = true;
127	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
128	if (VBOX_FAILURE(rc))
129	pVM->fRawR0Enabled = true;
130	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
131	pVM->em.s.enmState = EMSTATE_NONE;
132	pVM->em.s.fForceRAW = false;
133
134	pVM->em.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
135	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
136	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
137
138	/*
139	* Saved state.
140	*/
141	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
142	NULL, emR3Save, NULL,
143	NULL, emR3Load, NULL);
144	if (VBOX_FAILURE(rc))
145	return rc;
146
147	/*
148	* Statistics.
149	*/
150	#ifdef VBOX_WITH_STATISTICS
151	PEMSTATS pStats;
152	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
153	if (VBOX_FAILURE(rc))
154	return rc;
155	pVM->em.s.pStatsR3 = pStats;
156	pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
157	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
158
159	STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
160	STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
161
162	STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
163	STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
164
165	STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatRZLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatR3Lmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
235
236	STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
237	STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
238
239	STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
278	STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
279	STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
280	STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
281	STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
282	STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
283	STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatRZFailedLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatR3FailedLmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
287
288	STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
289	STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
290	STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
292	STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
293	STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
294	STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
295	STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
296	STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
297	STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
298	STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
299	STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
300	STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
301	STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
302	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
303	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
304	STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
305	STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
306	STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
307	STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
308	STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
309	STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
310	STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
311	STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
312	STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
313	STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
314	STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
315	STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
316
317	STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
318	STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
319	STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
320	STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
321
322	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
323	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
324	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
325	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
326	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
327	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
328	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
329	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
330	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
331	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
332	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
333	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
334	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
335	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
336	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
337	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
338	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
339	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
340	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
341	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
342	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
343	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
344	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
345	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
346	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
347	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
348
349	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
350	pVM->em.s.pCliStatTree = 0;
351	#endif /* VBOX_WITH_STATISTICS */
352
353	/* these should be considered for release statistics. */
354	STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
355	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
356	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
357	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
358
359	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
360	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
361	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
362	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
363	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
364	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
365	STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
366	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
367	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
368	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
369	STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
370	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
371
372
373	return VINF_SUCCESS;
374	}
375
376
377	/**
378	* Applies relocations to data and code managed by this
379	* component. This function will be called at init and
380	* whenever the VMM need to relocate it self inside the GC.
381	*
382	* @param pVM The VM.
383	*/
384	VMMR3DECL(void) EMR3Relocate(PVM pVM)
385	{
386	LogFlow(("EMR3Relocate\n"));
387	if (pVM->em.s.pStatsR3)
388	pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
389	}
390
391
392	/**
393	* Reset notification.
394	*
395	* @param pVM
396	*/
397	VMMR3DECL(void) EMR3Reset(PVM pVM)
398	{
399	LogFlow(("EMR3Reset: \n"));
400	pVM->em.s.fForceRAW = false;
401	}
402
403
404	/**
405	* Terminates the EM.
406	*
407	* Termination means cleaning up and freeing all resources,
408	* the VM it self is at this point powered off or suspended.
409	*
410	* @returns VBox status code.
411	* @param pVM The VM to operate on.
412	*/
413	VMMR3DECL(int) EMR3Term(PVM pVM)
414	{
415	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
416
417	return VINF_SUCCESS;
418	}
419
420
421	/**
422	* Execute state save operation.
423	*
424	* @returns VBox status code.
425	* @param pVM VM Handle.
426	* @param pSSM SSM operation handle.
427	*/
428	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
429	{
430	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
431	}
432
433
434	/**
435	* Execute state load operation.
436	*
437	* @returns VBox status code.
438	* @param pVM VM Handle.
439	* @param pSSM SSM operation handle.
440	* @param u32Version Data layout version.
441	*/
442	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
443	{
444	/*
445	* Validate version.
446	*/
447	if (u32Version != EM_SAVED_STATE_VERSION)
448	{
449	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
450	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
451	}
452
453	/*
454	* Load the saved state.
455	*/
456	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
457	if (VBOX_FAILURE(rc))
458	pVM->em.s.fForceRAW = false;
459
460	Assert(!pVM->em.s.pCliStatTree);
461	return rc;
462	}
463
464
465	/**
466	* Enables or disables a set of raw-mode execution modes.
467	*
468	* @returns VINF_SUCCESS on success.
469	* @returns VINF_RESCHEDULE if a rescheduling might be required.
470	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
471	*
472	* @param pVM The VM to operate on.
473	* @param enmMode The execution mode change.
474	* @thread The emulation thread.
475	*/
476	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
477	{
478	switch (enmMode)
479	{
480	case EMRAW_NONE:
481	pVM->fRawR3Enabled = false;
482	pVM->fRawR0Enabled = false;
483	break;
484	case EMRAW_RING3_ENABLE:
485	pVM->fRawR3Enabled = true;
486	break;
487	case EMRAW_RING3_DISABLE:
488	pVM->fRawR3Enabled = false;
489	break;
490	case EMRAW_RING0_ENABLE:
491	pVM->fRawR0Enabled = true;
492	break;
493	case EMRAW_RING0_DISABLE:
494	pVM->fRawR0Enabled = false;
495	break;
496	default:
497	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
498	return VERR_INVALID_PARAMETER;
499	}
500	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
501	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
502	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
503	}
504
505
506	/**
507	* Raise a fatal error.
508	*
509	* Safely terminate the VM with full state report and stuff. This function
510	* will naturally never return.
511	*
512	* @param pVM VM handle.
513	* @param rc VBox status code.
514	*/
515	VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
516	{
517	longjmp(pVM->em.s.u.FatalLongJump, rc);
518	AssertReleaseMsgFailed(("longjmp returned!\n"));
519	}
520
521
522	/**
523	* Gets the EM state name.
524	*
525	* @returns pointer to read only state name,
526	* @param enmState The state.
527	*/
528	VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
529	{
530	switch (enmState)
531	{
532	case EMSTATE_NONE: return "EMSTATE_NONE";
533	case EMSTATE_RAW: return "EMSTATE_RAW";
534	case EMSTATE_HWACC: return "EMSTATE_HWACC";
535	case EMSTATE_REM: return "EMSTATE_REM";
536	case EMSTATE_PARAV: return "EMSTATE_PARAV";
537	case EMSTATE_HALTED: return "EMSTATE_HALTED";
538	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
539	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
540	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
541	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
542	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
543	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
544	default: return "Unknown!";
545	}
546	}
547
548
549	#ifdef VBOX_WITH_STATISTICS
550	/**
551	* Just a braindead function to keep track of cli addresses.
552	* @param pVM VM handle.
553	* @param pInstrGC The EIP of the cli instruction.
554	*/
555	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
556	{
557	PCLISTAT pRec;
558
559	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
560	if (!pRec)
561	{
562	/* New cli instruction; insert into the tree. */
563	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
564	Assert(pRec);
565	if (!pRec)
566	return;
567	pRec->Core.Key = (AVLPVKEY)pInstrGC;
568
569	char szCliStatName[32];
570	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
571	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
572
573	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
574	Assert(fRc); NOREF(fRc);
575	}
576	STAM_COUNTER_INC(&pRec->Counter);
577	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
578	}
579	#endif /* VBOX_WITH_STATISTICS */
580
581
582	/**
583	* Debug loop.
584	*
585	* @returns VBox status code for EM.
586	* @param pVM VM handle.
587	* @param rc Current EM VBox status code..
588	*/
589	static int emR3Debug(PVM pVM, int rc)
590	{
591	for (;;)
592	{
593	Log(("emR3Debug: rc=%Vrc\n", rc));
594	const int rcLast = rc;
595
596	/*
597	* Debug related RC.
598	*/
599	switch (rc)
600	{
601	/*
602	* Single step an instruction.
603	*/
604	case VINF_EM_DBG_STEP:
605	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
606	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
607	\|\| pVM->em.s.fForceRAW /* paranoia */)
608	rc = emR3RawStep(pVM);
609	else
610	{
611	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
612	rc = emR3RemStep(pVM);
613	}
614	break;
615
616	/*
617	* Simple events: stepped, breakpoint, stop/assertion.
618	*/
619	case VINF_EM_DBG_STEPPED:
620	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
621	break;
622
623	case VINF_EM_DBG_BREAKPOINT:
624	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
625	break;
626
627	case VINF_EM_DBG_STOP:
628	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
629	break;
630
631	case VINF_EM_DBG_HYPER_STEPPED:
632	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
633	break;
634
635	case VINF_EM_DBG_HYPER_BREAKPOINT:
636	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
637	break;
638
639	case VINF_EM_DBG_HYPER_ASSERTION:
640	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
641	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
642	break;
643
644	/*
645	* Guru meditation.
646	*/
647	case VINF_EM_DBG_RING0_ASSERTION: /** @todo Make a guru meditation event! */
648	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VINF_EM_DBG_RING0_ASSERTION", 0, NULL, NULL);
649	break;
650	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
651	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
652	break;
653
654	default: /** @todo don't use default for guru, but make special errors code! */
655	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
656	break;
657	}
658
659	/*
660	* Process the result.
661	*/
662	do
663	{
664	switch (rc)
665	{
666	/*
667	* Continue the debugging loop.
668	*/
669	case VINF_EM_DBG_STEP:
670	case VINF_EM_DBG_STOP:
671	case VINF_EM_DBG_STEPPED:
672	case VINF_EM_DBG_BREAKPOINT:
673	case VINF_EM_DBG_HYPER_STEPPED:
674	case VINF_EM_DBG_HYPER_BREAKPOINT:
675	case VINF_EM_DBG_HYPER_ASSERTION:
676	case VINF_EM_DBG_RING0_ASSERTION:
677	break;
678
679	/*
680	* Resuming execution (in some form) has to be done here if we got
681	* a hypervisor debug event.
682	*/
683	case VINF_SUCCESS:
684	case VINF_EM_RESUME:
685	case VINF_EM_SUSPEND:
686	case VINF_EM_RESCHEDULE:
687	case VINF_EM_RESCHEDULE_RAW:
688	case VINF_EM_RESCHEDULE_REM:
689	case VINF_EM_HALT:
690	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
691	{
692	rc = emR3RawResumeHyper(pVM);
693	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
694	continue;
695	}
696	if (rc == VINF_SUCCESS)
697	rc = VINF_EM_RESCHEDULE;
698	return rc;
699
700	/*
701	* The debugger isn't attached.
702	* We'll simply turn the thing off since that's the easiest thing to do.
703	*/
704	case VERR_DBGF_NOT_ATTACHED:
705	switch (rcLast)
706	{
707	case VINF_EM_DBG_HYPER_STEPPED:
708	case VINF_EM_DBG_HYPER_BREAKPOINT:
709	case VINF_EM_DBG_HYPER_ASSERTION:
710	case VINF_EM_DBG_RING0_ASSERTION:
711	return rcLast;
712	}
713	return VINF_EM_OFF;
714
715	/*
716	* Status codes terminating the VM in one or another sense.
717	*/
718	case VINF_EM_TERMINATE:
719	case VINF_EM_OFF:
720	case VINF_EM_RESET:
721	case VINF_EM_RAW_STALE_SELECTOR:
722	case VINF_EM_RAW_IRET_TRAP:
723	case VERR_TRPM_PANIC:
724	case VERR_TRPM_DONT_PANIC:
725	case VERR_INTERNAL_ERROR:
726	return rc;
727
728	/*
729	* The rest is unexpected, and will keep us here.
730	*/
731	default:
732	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
733	break;
734	}
735	} while (false);
736	} /* debug for ever */
737	}
738
739
740	/**
741	* Steps recompiled code.
742	*
743	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
744	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
745	*
746	* @param pVM VM handle.
747	*/
748	static int emR3RemStep(PVM pVM)
749	{
750	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
751
752	/*
753	* Switch to REM, step instruction, switch back.
754	*/
755	int rc = REMR3State(pVM);
756	if (VBOX_SUCCESS(rc))
757	{
758	rc = REMR3Step(pVM);
759	REMR3StateBack(pVM);
760	}
761	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
762	return rc;
763	}
764
765
766	/**
767	* Executes recompiled code.
768	*
769	* This function contains the recompiler version of the inner
770	* execution loop (the outer loop being in EMR3ExecuteVM()).
771	*
772	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
773	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
774	*
775	* @param pVM VM handle.
776	* @param pfFFDone Where to store an indicator telling wheter or not
777	* FFs were done before returning.
778	*
779	*/
780	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
781	{
782	#ifdef LOG_ENABLED
783	PCPUMCTX pCtx = pVM->em.s.pCtx;
784	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
785
786	if (pCtx->eflags.Bits.u1VM)
787	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
788	else
789	Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
790	#endif
791	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
792
793	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
794	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
795	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
796	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
797	#endif
798
799	/*
800	* Spin till we get a forced action which returns anything but VINF_SUCCESS
801	* or the REM suggests raw-mode execution.
802	*/
803	*pfFFDone = false;
804	bool fInREMState = false;
805	int rc = VINF_SUCCESS;
806	for (;;)
807	{
808	/*
809	* Update REM state if not already in sync.
810	*/
811	if (!fInREMState)
812	{
813	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
814	rc = REMR3State(pVM);
815	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
816	if (VBOX_FAILURE(rc))
817	break;
818	fInREMState = true;
819
820	/*
821	* We might have missed the raising of VMREQ, TIMER and some other
822	* imporant FFs while we were busy switching the state. So, check again.
823	*/
824	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
825	{
826	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
827	goto l_REMDoForcedActions;
828	}
829	}
830
831
832	/*
833	* Execute REM.
834	*/
835	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
836	rc = REMR3Run(pVM);
837	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
838
839
840	/*
841	* Deal with high priority post execution FFs before doing anything else.
842	*/
843	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
844	rc = emR3HighPriorityPostForcedActions(pVM, rc);
845
846	/*
847	* Process the returned status code.
848	* (Try keep this short! Call functions!)
849	*/
850	if (rc != VINF_SUCCESS)
851	{
852	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
853	break;
854	if (rc != VINF_REM_INTERRUPED_FF)
855	{
856	/*
857	* Anything which is not known to us means an internal error
858	* and the termination of the VM!
859	*/
860	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Vra\n", rc));
861	break;
862	}
863	}
864
865
866	/*
867	* Check and execute forced actions.
868	* Sync back the VM state before calling any of these.
869	*/
870	#ifdef VBOX_HIGH_RES_TIMERS_HACK
871	TMTimerPoll(pVM);
872	#endif
873	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
874	{
875	l_REMDoForcedActions:
876	if (fInREMState)
877	{
878	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
879	REMR3StateBack(pVM);
880	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
881	fInREMState = false;
882	}
883	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
884	rc = emR3ForcedActions(pVM, rc);
885	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
886	if ( rc != VINF_SUCCESS
887	&& rc != VINF_EM_RESCHEDULE_REM)
888	{
889	*pfFFDone = true;
890	break;
891	}
892	}
893
894	} /* The Inner Loop, recompiled execution mode version. */
895
896
897	/*
898	* Returning. Sync back the VM state if required.
899	*/
900	if (fInREMState)
901	{
902	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
903	REMR3StateBack(pVM);
904	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
905	}
906
907	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
908	return rc;
909	}
910
911
912	/**
913	* Resumes executing hypervisor after a debug event.
914	*
915	* This is kind of special since our current guest state is
916	* potentially out of sync.
917	*
918	* @returns VBox status code.
919	* @param pVM The VM handle.
920	*/
921	static int emR3RawResumeHyper(PVM pVM)
922	{
923	int rc;
924	PCPUMCTX pCtx = pVM->em.s.pCtx;
925	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
926	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
927
928	/*
929	* Resume execution.
930	*/
931	CPUMRawEnter(pVM, NULL);
932	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
933	rc = VMMR3ResumeHyper(pVM);
934	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
935	rc = CPUMRawLeave(pVM, NULL, rc);
936	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
937
938	/*
939	* Deal with the return code.
940	*/
941	rc = emR3HighPriorityPostForcedActions(pVM, rc);
942	rc = emR3RawHandleRC(pVM, pCtx, rc);
943	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
944	return rc;
945	}
946
947
948	/**
949	* Steps rawmode.
950	*
951	* @returns VBox status code.
952	* @param pVM The VM handle.
953	*/
954	static int emR3RawStep(PVM pVM)
955	{
956	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
957	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
958	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
959	int rc;
960	PCPUMCTX pCtx = pVM->em.s.pCtx;
961	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
962	#ifndef DEBUG_sandervl
963	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
964	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
965	#endif
966	if (fGuest)
967	{
968	/*
969	* Check vital forced actions, but ignore pending interrupts and timers.
970	*/
971	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
972	{
973	rc = emR3RawForcedActions(pVM, pCtx);
974	if (VBOX_FAILURE(rc))
975	return rc;
976	}
977
978	/*
979	* Set flags for single stepping.
980	*/
981	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
982	}
983	else
984	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
985
986	/*
987	* Single step.
988	* We do not start time or anything, if anything we should just do a few nanoseconds.
989	*/
990	CPUMRawEnter(pVM, NULL);
991	do
992	{
993	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
994	rc = VMMR3ResumeHyper(pVM);
995	else
996	rc = VMMR3RawRunGC(pVM);
997	#ifndef DEBUG_sandervl
998	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
999	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
1000	#endif
1001	} while ( rc == VINF_SUCCESS
1002	\|\| rc == VINF_EM_RAW_INTERRUPT);
1003	rc = CPUMRawLeave(pVM, NULL, rc);
1004	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1005
1006	/*
1007	* Make sure the trap flag is cleared.
1008	* (Too bad if the guest is trying to single step too.)
1009	*/
1010	if (fGuest)
1011	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1012	else
1013	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1014
1015	/*
1016	* Deal with the return codes.
1017	*/
1018	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1019	rc = emR3RawHandleRC(pVM, pCtx, rc);
1020	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1021	return rc;
1022	}
1023
1024
1025	#ifdef DEBUG
1026
1027	/**
1028	* Steps hardware accelerated mode.
1029	*
1030	* @returns VBox status code.
1031	* @param pVM The VM handle.
1032	*/
1033	static int emR3HwAccStep(PVM pVM)
1034	{
1035	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1036
1037	int rc;
1038	PCPUMCTX pCtx = pVM->em.s.pCtx;
1039	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1040
1041	/*
1042	* Check vital forced actions, but ignore pending interrupts and timers.
1043	*/
1044	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1045	{
1046	rc = emR3RawForcedActions(pVM, pCtx);
1047	if (VBOX_FAILURE(rc))
1048	return rc;
1049	}
1050	/*
1051	* Set flags for single stepping.
1052	*/
1053	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1054
1055	/*
1056	* Single step.
1057	* We do not start time or anything, if anything we should just do a few nanoseconds.
1058	*/
1059	do
1060	{
1061	rc = VMMR3HwAccRunGC(pVM);
1062	} while ( rc == VINF_SUCCESS
1063	\|\| rc == VINF_EM_RAW_INTERRUPT);
1064	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1065
1066	/*
1067	* Make sure the trap flag is cleared.
1068	* (Too bad if the guest is trying to single step too.)
1069	*/
1070	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1071
1072	/*
1073	* Deal with the return codes.
1074	*/
1075	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1076	rc = emR3RawHandleRC(pVM, pCtx, rc);
1077	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1078	return rc;
1079	}
1080
1081
1082	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1083	{
1084	EMSTATE enmOldState = pVM->em.s.enmState;
1085
1086	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1087
1088	Log(("Single step BEGIN:\n"));
1089	for (uint32_t i = 0; i < cIterations; i++)
1090	{
1091	DBGFR3PrgStep(pVM);
1092	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1093	emR3RawStep(pVM);
1094	}
1095	Log(("Single step END:\n"));
1096	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1097	pVM->em.s.enmState = enmOldState;
1098	}
1099
1100
1101	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1102	{
1103	EMSTATE enmOldState = pVM->em.s.enmState;
1104
1105	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1106
1107	Log(("Single step BEGIN:\n"));
1108	for (uint32_t i = 0; i < cIterations; i++)
1109	{
1110	DBGFR3PrgStep(pVM);
1111	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1112	emR3HwAccStep(pVM);
1113	}
1114	Log(("Single step END:\n"));
1115	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1116	pVM->em.s.enmState = enmOldState;
1117	}
1118
1119
1120	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1121	{
1122	EMSTATE enmOldState = pVM->em.s.enmState;
1123
1124	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1125
1126	Log(("Single step BEGIN:\n"));
1127	for (uint32_t i = 0; i < cIterations; i++)
1128	{
1129	DBGFR3PrgStep(pVM);
1130	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1131	emR3RemStep(pVM);
1132	}
1133	Log(("Single step END:\n"));
1134	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1135	pVM->em.s.enmState = enmOldState;
1136	}
1137
1138	#endif /* DEBUG */
1139
1140
1141	/**
1142	* Executes one (or perhaps a few more) instruction(s).
1143	*
1144	* @returns VBox status code suitable for EM.
1145	*
1146	* @param pVM VM handle.
1147	* @param rcGC GC return code
1148	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1149	* instruction and prefix the log output with this text.
1150	*/
1151	#ifdef LOG_ENABLED
1152	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1153	#else
1154	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1155	#endif
1156	{
1157	PCPUMCTX pCtx = pVM->em.s.pCtx;
1158	int rc;
1159
1160	/*
1161	*
1162	* The simple solution is to use the recompiler.
1163	* The better solution is to disassemble the current instruction and
1164	* try handle as many as possible without using REM.
1165	*
1166	*/
1167
1168	#ifdef LOG_ENABLED
1169	/*
1170	* Disassemble the instruction if requested.
1171	*/
1172	if (pszPrefix)
1173	{
1174	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1175	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1176	}
1177	#endif /* LOG_ENABLED */
1178
1179	/*
1180	* PATM is making life more interesting.
1181	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1182	* tell PATM there is a trap in this code and have it take the appropriate actions
1183	* to allow us execute the code in REM.
1184	*/
1185	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1186	{
1187	Log(("emR3RawExecuteInstruction: In patch block. eip=%VRv\n", pCtx->eip));
1188
1189	RTGCPTR pNewEip;
1190	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1191	switch (rc)
1192	{
1193	/*
1194	* It's not very useful to emulate a single instruction and then go back to raw
1195	* mode; just execute the whole block until IF is set again.
1196	*/
1197	case VINF_SUCCESS:
1198	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1199	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1200	pCtx->eip = pNewEip;
1201	Assert(pCtx->eip);
1202
1203	if (pCtx->eflags.Bits.u1IF)
1204	{
1205	/*
1206	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1207	*/
1208	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1209	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1210	}
1211	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1212	{
1213	/* special case: iret, that sets IF, detected a pending irq/event */
1214	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1215	}
1216	return VINF_EM_RESCHEDULE_REM;
1217
1218	/*
1219	* One instruction.
1220	*/
1221	case VINF_PATCH_EMULATE_INSTR:
1222	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1223	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1224	pCtx->eip = pNewEip;
1225	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1226
1227	/*
1228	* The patch was disabled, hand it to the REM.
1229	*/
1230	case VERR_PATCH_DISABLED:
1231	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1232	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1233	pCtx->eip = pNewEip;
1234	if (pCtx->eflags.Bits.u1IF)
1235	{
1236	/*
1237	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1238	*/
1239	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1240	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1241	}
1242	return VINF_EM_RESCHEDULE_REM;
1243
1244	/* Force continued patch exection; usually due to write monitored stack. */
1245	case VINF_PATCH_CONTINUE:
1246	return VINF_SUCCESS;
1247
1248	default:
1249	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1250	return VERR_INTERNAL_ERROR;
1251	}
1252	}
1253
1254	#if 0
1255	/* Try our own instruction emulator before falling back to the recompiler. */
1256	DISCPUSTATE Cpu;
1257	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1258	if (VBOX_SUCCESS(rc))
1259	{
1260	uint32_t size;
1261
1262	switch (Cpu.pCurInstr->opcode)
1263	{
1264	/* @todo we can do more now */
1265	case OP_MOV:
1266	case OP_AND:
1267	case OP_OR:
1268	case OP_XOR:
1269	case OP_POP:
1270	case OP_INC:
1271	case OP_DEC:
1272	case OP_XCHG:
1273	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1274	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1275	if (VBOX_SUCCESS(rc))
1276	{
1277	pCtx->rip += Cpu.opsize;
1278	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1279	return rc;
1280	}
1281	if (rc != VERR_EM_INTERPRETER)
1282	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1283	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1284	break;
1285	}
1286	}
1287	#endif /* 0 */
1288	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1289	rc = REMR3EmulateInstruction(pVM);
1290	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1291
1292	return rc;
1293	}
1294
1295
1296	/**
1297	* Executes one (or perhaps a few more) instruction(s).
1298	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1299	*
1300	* @returns VBox status code suitable for EM.
1301	* @param pVM VM handle.
1302	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1303	* instruction and prefix the log output with this text.
1304	* @param rcGC GC return code
1305	*/
1306	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1307	{
1308	#ifdef LOG_ENABLED
1309	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1310	#else
1311	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1312	#endif
1313	}
1314
1315	/**
1316	* Executes one (or perhaps a few more) IO instruction(s).
1317	*
1318	* @returns VBox status code suitable for EM.
1319	* @param pVM VM handle.
1320	*/
1321	int emR3RawExecuteIOInstruction(PVM pVM)
1322	{
1323	int rc;
1324	PCPUMCTX pCtx = pVM->em.s.pCtx;
1325
1326	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1327
1328	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1329	* as io instructions tend to come in packages of more than one
1330	*/
1331	DISCPUSTATE Cpu;
1332	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1333	if (VBOX_SUCCESS(rc))
1334	{
1335	rc = VINF_EM_RAW_EMULATE_INSTR;
1336
1337	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1338	{
1339	switch (Cpu.pCurInstr->opcode)
1340	{
1341	case OP_IN:
1342	{
1343	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1344	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1345	break;
1346	}
1347
1348	case OP_OUT:
1349	{
1350	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1351	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1352	break;
1353	}
1354	}
1355	}
1356	else if (Cpu.prefix & PREFIX_REP)
1357	{
1358	switch (Cpu.pCurInstr->opcode)
1359	{
1360	case OP_INSB:
1361	case OP_INSWD:
1362	{
1363	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1364	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1365	break;
1366	}
1367
1368	case OP_OUTSB:
1369	case OP_OUTSWD:
1370	{
1371	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1372	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1373	break;
1374	}
1375	}
1376	}
1377
1378	/*
1379	* Handled the I/O return codes.
1380	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1381	*/
1382	if (IOM_SUCCESS(rc))
1383	{
1384	pCtx->rip += Cpu.opsize;
1385	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1386	return rc;
1387	}
1388
1389	if (rc == VINF_EM_RAW_GUEST_TRAP)
1390	{
1391	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1392	rc = emR3RawGuestTrap(pVM);
1393	return rc;
1394	}
1395	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1396
1397	if (VBOX_FAILURE(rc))
1398	{
1399	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1400	return rc;
1401	}
1402	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1403	}
1404	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1405	return emR3RawExecuteInstruction(pVM, "IO: ");
1406	}
1407
1408
1409	/**
1410	* Handle a guest context trap.
1411	*
1412	* @returns VBox status code suitable for EM.
1413	* @param pVM VM handle.
1414	*/
1415	static int emR3RawGuestTrap(PVM pVM)
1416	{
1417	PCPUMCTX pCtx = pVM->em.s.pCtx;
1418
1419	/*
1420	* Get the trap info.
1421	*/
1422	uint8_t u8TrapNo;
1423	TRPMEVENT enmType;
1424	RTGCUINT uErrorCode;
1425	RTGCUINTPTR uCR2;
1426	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1427	if (VBOX_FAILURE(rc))
1428	{
1429	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1430	return rc;
1431	}
1432
1433	/*
1434	* Traps can be directly forwarded in hardware accelerated mode.
1435	*/
1436	if (HWACCMR3IsActive(pVM))
1437	{
1438	#ifdef LOGGING_ENABLED
1439	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1440	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1441	#endif
1442	return VINF_EM_RESCHEDULE_HWACC;
1443	}
1444
1445	#if 1 /* Experimental: Review, disable if it causes trouble. */
1446	/*
1447	* Handle traps in patch code first.
1448	*
1449	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1450	* but several traps isn't handled specially by TRPM in RC and we end up here
1451	* instead. One example is #DE.
1452	*/
1453	uint32_t uCpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
1454	if ( uCpl == 0
1455	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1456	{
1457	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1458	return emR3PatchTrap(pVM, pCtx, rc);
1459	}
1460	#endif
1461
1462	/*
1463	* If the guest gate is marked unpatched, then we will check again if we can patch it.
1464	* (This assumes that we've already tried and failed to dispatch the trap in
1465	* RC for the gates that already has been patched. Which is true for most high
1466	* volume traps, because these are handled specially, but not for odd ones like #DE.)
1467	*/
1468	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1469	{
1470	CSAMR3CheckGates(pVM, u8TrapNo, 1);
1471	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1472
1473	/* If it was successful, then we could go back to raw mode. */
1474	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1475	{
1476	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
1477	rc = EMR3CheckRawForcedActions(pVM);
1478	AssertRCReturn(rc, rc);
1479
1480	TRPMERRORCODE enmError = uErrorCode != ~0U
1481	? TRPM_TRAP_HAS_ERRORCODE
1482	: TRPM_TRAP_NO_ERRORCODE;
1483	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1484	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
1485	{
1486	TRPMResetTrap(pVM);
1487	return VINF_EM_RESCHEDULE_RAW;
1488	}
1489	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1490	}
1491	}
1492
1493	/*
1494	* Scan kernel code that traps; we might not get another chance.
1495	*/
1496	/** @todo move this up before the dispatching? */
1497	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1498	&& !pCtx->eflags.Bits.u1VM)
1499	{
1500	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1501	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1502	}
1503
1504	/*
1505	* Trap specific handling.
1506	*/
1507	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1508	{
1509	/*
1510	* If MONITOR & MWAIT are supported, then interpret them here.
1511	*/
1512	DISCPUSTATE cpu;
1513	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1514	if ( VBOX_SUCCESS(rc)
1515	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1516	{
1517	uint32_t u32Dummy, u32Features, u32ExtFeatures;
1518	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1519	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1520	{
1521	rc = TRPMResetTrap(pVM);
1522	AssertRC(rc);
1523
1524	uint32_t opsize;
1525	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1526	if (VBOX_SUCCESS(rc))
1527	{
1528	pCtx->rip += cpu.opsize;
1529	return rc;
1530	}
1531	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1532	}
1533	}
1534	}
1535	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1536	{
1537	/*
1538	* Handle I/O bitmap?
1539	*/
1540	/** @todo We're not supposed to be here with a false guest trap concerning
1541	* I/O access. We can easily handle those in RC. */
1542	DISCPUSTATE cpu;
1543	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1544	if ( VBOX_SUCCESS(rc)
1545	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1546	{
1547	/*
1548	* We should really check the TSS for the IO bitmap, but it's not like this
1549	* lazy approach really makes things worse.
1550	*/
1551	rc = TRPMResetTrap(pVM);
1552	AssertRC(rc);
1553	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1554	}
1555	}
1556
1557	#ifdef LOG_ENABLED
1558	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1559	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1560
1561	/* Get guest page information. */
1562	uint64_t fFlags = 0;
1563	RTGCPHYS GCPhys = 0;
1564	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1565	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1566	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1567	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1568	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1569	#endif
1570
1571	/*
1572	* #PG has CR2.
1573	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1574	*/
1575	if (u8TrapNo == 14 /* #PG */)
1576	pCtx->cr2 = uCR2;
1577
1578	return VINF_EM_RESCHEDULE_REM;
1579	}
1580
1581
1582	/**
1583	* Handle a ring switch trap.
1584	* Need to do statistics and to install patches. The result is going to REM.
1585	*
1586	* @returns VBox status code suitable for EM.
1587	* @param pVM VM handle.
1588	*/
1589	int emR3RawRingSwitch(PVM pVM)
1590	{
1591	int rc;
1592	DISCPUSTATE Cpu;
1593	PCPUMCTX pCtx = pVM->em.s.pCtx;
1594
1595	/*
1596	* sysenter, syscall & callgate
1597	*/
1598	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1599	if (VBOX_SUCCESS(rc))
1600	{
1601	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1602	{
1603	if (pCtx->SysEnter.cs != 0)
1604	{
1605	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1606	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1607	if (VBOX_SUCCESS(rc))
1608	{
1609	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1610	return VINF_EM_RESCHEDULE_RAW;
1611	}
1612	}
1613	}
1614
1615	#ifdef VBOX_WITH_STATISTICS
1616	switch (Cpu.pCurInstr->opcode)
1617	{
1618	case OP_SYSENTER:
1619	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1620	break;
1621	case OP_SYSEXIT:
1622	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1623	break;
1624	case OP_SYSCALL:
1625	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1626	break;
1627	case OP_SYSRET:
1628	STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1629	break;
1630	}
1631	#endif
1632	}
1633	else
1634	AssertRC(rc);
1635
1636	/* go to the REM to emulate a single instruction */
1637	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1638	}
1639
1640
1641	/**
1642	* Handle a trap (\#PF or \#GP) in patch code
1643	*
1644	* @returns VBox status code suitable for EM.
1645	* @param pVM VM handle.
1646	* @param pCtx CPU context
1647	* @param gcret GC return code
1648	*/
1649	static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1650	{
1651	uint8_t u8TrapNo;
1652	int rc;
1653	TRPMEVENT enmType;
1654	RTGCUINT uErrorCode;
1655	RTGCUINTPTR uCR2;
1656
1657	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1658
1659	if (gcret == VINF_PATM_PATCH_INT3)
1660	{
1661	u8TrapNo = 3;
1662	uCR2 = 0;
1663	uErrorCode = 0;
1664	}
1665	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1666	{
1667	/* No active trap in this case. Kind of ugly. */
1668	u8TrapNo = X86_XCPT_GP;
1669	uCR2 = 0;
1670	uErrorCode = 0;
1671	}
1672	else
1673	{
1674	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1675	if (VBOX_FAILURE(rc))
1676	{
1677	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1678	return rc;
1679	}
1680	/* Reset the trap as we'll execute the original instruction again. */
1681	TRPMResetTrap(pVM);
1682	}
1683
1684	/*
1685	* Deal with traps inside patch code.
1686	* (This code won't run outside GC.)
1687	*/
1688	if (u8TrapNo != 1)
1689	{
1690	#ifdef LOG_ENABLED
1691	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1692	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1693
1694	DISCPUSTATE Cpu;
1695	int rc;
1696
1697	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1698	if ( VBOX_SUCCESS(rc)
1699	&& Cpu.pCurInstr->opcode == OP_IRET)
1700	{
1701	uint32_t eip, selCS, uEFlags;
1702
1703	/* Iret crashes are bad as we have already changed the flags on the stack */
1704	rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1705	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1706	rc \|= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1707	if (rc == VINF_SUCCESS)
1708	{
1709	if ( (uEFlags & X86_EFL_VM)
1710	\|\| (selCS & X86_SEL_RPL) == 3)
1711	{
1712	uint32_t selSS, esp;
1713
1714	rc \|= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1715	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1716
1717	if (uEFlags & X86_EFL_VM)
1718	{
1719	uint32_t selDS, selES, selFS, selGS;
1720	rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1721	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1722	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1723	rc \|= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1724	if (rc == VINF_SUCCESS)
1725	{
1726	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1727	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1728	}
1729	}
1730	else
1731	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1732	}
1733	else
1734	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1735	}
1736	}
1737	#endif /* LOG_ENABLED */
1738	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1739	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1740
1741	RTGCPTR pNewEip;
1742	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1743	switch (rc)
1744	{
1745	/*
1746	* Execute the faulting instruction.
1747	*/
1748	case VINF_SUCCESS:
1749	{
1750	/** @todo execute a whole block */
1751	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1752	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1753	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1754
1755	pCtx->eip = pNewEip;
1756	AssertRelease(pCtx->eip);
1757
1758	if (pCtx->eflags.Bits.u1IF)
1759	{
1760	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1761	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1762	*/
1763	if ( u8TrapNo == X86_XCPT_GP
1764	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1765	{
1766	/** @todo move to PATMR3HandleTrap */
1767	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1768	PATMR3RemovePatch(pVM, pCtx->eip);
1769	}
1770
1771	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1772	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1773
1774	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1775	/* Interrupts are enabled; just go back to the original instruction.
1776	return VINF_SUCCESS; */
1777	}
1778	return VINF_EM_RESCHEDULE_REM;
1779	}
1780
1781	/*
1782	* One instruction.
1783	*/
1784	case VINF_PATCH_EMULATE_INSTR:
1785	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1786	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1787	pCtx->eip = pNewEip;
1788	AssertRelease(pCtx->eip);
1789	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1790
1791	/*
1792	* The patch was disabled, hand it to the REM.
1793	*/
1794	case VERR_PATCH_DISABLED:
1795	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1796	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1797	pCtx->eip = pNewEip;
1798	AssertRelease(pCtx->eip);
1799
1800	if (pCtx->eflags.Bits.u1IF)
1801	{
1802	/*
1803	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1804	*/
1805	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1806	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1807	}
1808	return VINF_EM_RESCHEDULE_REM;
1809
1810	/* Force continued patch exection; usually due to write monitored stack. */
1811	case VINF_PATCH_CONTINUE:
1812	return VINF_SUCCESS;
1813
1814	/*
1815	* Anything else is fatal.
1816	*/
1817	default:
1818	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1819	return VERR_INTERNAL_ERROR;
1820	}
1821	}
1822	return VINF_SUCCESS;
1823	}
1824
1825
1826	/**
1827	* Handle a privileged instruction.
1828	*
1829	* @returns VBox status code suitable for EM.
1830	* @param pVM VM handle.
1831	*/
1832	int emR3RawPrivileged(PVM pVM)
1833	{
1834	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1835	PCPUMCTX pCtx = pVM->em.s.pCtx;
1836
1837	Assert(!pCtx->eflags.Bits.u1VM);
1838
1839	if (PATMIsEnabled(pVM))
1840	{
1841	/*
1842	* Check if in patch code.
1843	*/
1844	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1845	{
1846	#ifdef LOG_ENABLED
1847	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1848	#endif
1849	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1850	return VERR_EM_RAW_PATCH_CONFLICT;
1851	}
1852	if ( (pCtx->ss & X86_SEL_RPL) == 0
1853	&& !pCtx->eflags.Bits.u1VM
1854	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1855	{
1856	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1857	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1858	if (VBOX_SUCCESS(rc))
1859	{
1860	#ifdef LOG_ENABLED
1861	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1862	#endif
1863	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1864	return VINF_SUCCESS;
1865	}
1866	}
1867	}
1868
1869	#ifdef LOG_ENABLED
1870	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1871	{
1872	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1873	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1874	}
1875	#endif
1876
1877	/*
1878	* Instruction statistics and logging.
1879	*/
1880	DISCPUSTATE Cpu;
1881	int rc;
1882
1883	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1884	if (VBOX_SUCCESS(rc))
1885	{
1886	#ifdef VBOX_WITH_STATISTICS
1887	PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1888	switch (Cpu.pCurInstr->opcode)
1889	{
1890	case OP_INVLPG:
1891	STAM_COUNTER_INC(&pStats->StatInvlpg);
1892	break;
1893	case OP_IRET:
1894	STAM_COUNTER_INC(&pStats->StatIret);
1895	break;
1896	case OP_CLI:
1897	STAM_COUNTER_INC(&pStats->StatCli);
1898	emR3RecordCli(pVM, pCtx->rip);
1899	break;
1900	case OP_STI:
1901	STAM_COUNTER_INC(&pStats->StatSti);
1902	break;
1903	case OP_INSB:
1904	case OP_INSWD:
1905	case OP_IN:
1906	case OP_OUTSB:
1907	case OP_OUTSWD:
1908	case OP_OUT:
1909	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1910	break;
1911
1912	case OP_MOV_CR:
1913	if (Cpu.param1.flags & USE_REG_GEN32)
1914	{
1915	//read
1916	Assert(Cpu.param2.flags & USE_REG_CR);
1917	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1918	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1919	}
1920	else
1921	{
1922	//write
1923	Assert(Cpu.param1.flags & USE_REG_CR);
1924	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1925	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1926	}
1927	break;
1928
1929	case OP_MOV_DR:
1930	STAM_COUNTER_INC(&pStats->StatMovDRx);
1931	break;
1932	case OP_LLDT:
1933	STAM_COUNTER_INC(&pStats->StatMovLldt);
1934	break;
1935	case OP_LIDT:
1936	STAM_COUNTER_INC(&pStats->StatMovLidt);
1937	break;
1938	case OP_LGDT:
1939	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1940	break;
1941	case OP_SYSENTER:
1942	STAM_COUNTER_INC(&pStats->StatSysEnter);
1943	break;
1944	case OP_SYSEXIT:
1945	STAM_COUNTER_INC(&pStats->StatSysExit);
1946	break;
1947	case OP_SYSCALL:
1948	STAM_COUNTER_INC(&pStats->StatSysCall);
1949	break;
1950	case OP_SYSRET:
1951	STAM_COUNTER_INC(&pStats->StatSysRet);
1952	break;
1953	case OP_HLT:
1954	STAM_COUNTER_INC(&pStats->StatHlt);
1955	break;
1956	default:
1957	STAM_COUNTER_INC(&pStats->StatMisc);
1958	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1959	break;
1960	}
1961	#endif /* VBOX_WITH_STATISTICS */
1962	if ( (pCtx->ss & X86_SEL_RPL) == 0
1963	&& !pCtx->eflags.Bits.u1VM
1964	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1965	{
1966	uint32_t size;
1967
1968	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1969	switch (Cpu.pCurInstr->opcode)
1970	{
1971	case OP_CLI:
1972	pCtx->eflags.u32 &= ~X86_EFL_IF;
1973	Assert(Cpu.opsize == 1);
1974	pCtx->rip += Cpu.opsize;
1975	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1976	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1977
1978	case OP_STI:
1979	pCtx->eflags.u32 \|= X86_EFL_IF;
1980	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
1981	Assert(Cpu.opsize == 1);
1982	pCtx->rip += Cpu.opsize;
1983	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1984	return VINF_SUCCESS;
1985
1986	case OP_HLT:
1987	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1988	{
1989	PATMTRANSSTATE enmState;
1990	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1991
1992	if (enmState == PATMTRANS_OVERWRITTEN)
1993	{
1994	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1995	Assert(rc == VERR_PATCH_DISABLED);
1996	/* Conflict detected, patch disabled */
1997	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1998
1999	enmState = PATMTRANS_SAFE;
2000	}
2001
2002	/* The translation had better be successful. Otherwise we can't recover. */
2003	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
2004	if (enmState != PATMTRANS_OVERWRITTEN)
2005	pCtx->eip = pOrgInstrGC;
2006	}
2007	/* no break; we could just return VINF_EM_HALT here */
2008
2009	case OP_MOV_CR:
2010	case OP_MOV_DR:
2011	#ifdef LOG_ENABLED
2012	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2013	{
2014	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2015	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2016	}
2017	#endif
2018
2019	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2020	if (VBOX_SUCCESS(rc))
2021	{
2022	pCtx->rip += Cpu.opsize;
2023	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2024
2025	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2026	&& Cpu.param1.flags == USE_REG_CR /* write */
2027	)
2028	{
2029	/* Deal with CR0 updates inside patch code that force
2030	* us to go to the recompiler.
2031	*/
2032	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2033	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
2034	{
2035	PATMTRANSSTATE enmState;
2036	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2037
2038	Assert(pCtx->eflags.Bits.u1IF == 0);
2039	Log(("Force recompiler switch due to cr0 (%VGp) update\n", pCtx->cr0));
2040	if (enmState == PATMTRANS_OVERWRITTEN)
2041	{
2042	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2043	Assert(rc == VERR_PATCH_DISABLED);
2044	/* Conflict detected, patch disabled */
2045	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->rip));
2046	enmState = PATMTRANS_SAFE;
2047	}
2048	/* The translation had better be successful. Otherwise we can't recover. */
2049	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->rip));
2050	if (enmState != PATMTRANS_OVERWRITTEN)
2051	pCtx->rip = pOrgInstrGC;
2052	}
2053
2054	/* Reschedule is necessary as the execution/paging mode might have changed. */
2055	return VINF_EM_RESCHEDULE;
2056	}
2057	return rc; /* can return VINF_EM_HALT as well. */
2058	}
2059	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
2060	break; /* fall back to the recompiler */
2061	}
2062	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2063	}
2064	}
2065
2066	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2067	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2068
2069	return emR3RawExecuteInstruction(pVM, "PRIV");
2070	}
2071
2072
2073	/**
2074	* Update the forced rawmode execution modifier.
2075	*
2076	* This function is called when we're returning from the raw-mode loop(s). If we're
2077	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2078	* if not in patch code, the flag will be cleared.
2079	*
2080	* We should never interrupt patch code while it's being executed. Cli patches can
2081	* contain big code blocks, but they are always executed with IF=0. Other patches
2082	* replace single instructions and should be atomic.
2083	*
2084	* @returns Updated rc.
2085	*
2086	* @param pVM The VM handle.
2087	* @param pCtx The guest CPU context.
2088	* @param rc The result code.
2089	*/
2090	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2091	{
2092	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2093	{
2094	/* ignore reschedule attempts. */
2095	switch (rc)
2096	{
2097	case VINF_EM_RESCHEDULE:
2098	case VINF_EM_RESCHEDULE_REM:
2099	rc = VINF_SUCCESS;
2100	break;
2101	}
2102	pVM->em.s.fForceRAW = true;
2103	}
2104	else
2105	pVM->em.s.fForceRAW = false;
2106	return rc;
2107	}
2108
2109
2110	/**
2111	* Process a subset of the raw-mode return code.
2112	*
2113	* Since we have to share this with raw-mode single stepping, this inline
2114	* function has been created to avoid code duplication.
2115	*
2116	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2117	* @returns VBox status code to return to the EM main loop.
2118	*
2119	* @param pVM The VM handle
2120	* @param rc The return code.
2121	* @param pCtx The guest cpu context.
2122	*/
2123	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2124	{
2125	switch (rc)
2126	{
2127	/*
2128	* Common & simple ones.
2129	*/
2130	case VINF_SUCCESS:
2131	break;
2132	case VINF_EM_RESCHEDULE_RAW:
2133	case VINF_EM_RESCHEDULE_HWACC:
2134	case VINF_EM_RAW_INTERRUPT:
2135	case VINF_EM_RAW_TO_R3:
2136	case VINF_EM_RAW_TIMER_PENDING:
2137	case VINF_EM_PENDING_REQUEST:
2138	rc = VINF_SUCCESS;
2139	break;
2140
2141	/*
2142	* Privileged instruction.
2143	*/
2144	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2145	case VINF_PATM_PATCH_TRAP_GP:
2146	rc = emR3RawPrivileged(pVM);
2147	break;
2148
2149	/*
2150	* Got a trap which needs dispatching.
2151	*/
2152	case VINF_EM_RAW_GUEST_TRAP:
2153	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2154	{
2155	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2156	rc = VERR_EM_RAW_PATCH_CONFLICT;
2157	break;
2158	}
2159	rc = emR3RawGuestTrap(pVM);
2160	break;
2161
2162	/*
2163	* Trap in patch code.
2164	*/
2165	case VINF_PATM_PATCH_TRAP_PF:
2166	case VINF_PATM_PATCH_INT3:
2167	rc = emR3PatchTrap(pVM, pCtx, rc);
2168	break;
2169
2170	case VINF_PATM_DUPLICATE_FUNCTION:
2171	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2172	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2173	AssertRC(rc);
2174	rc = VINF_SUCCESS;
2175	break;
2176
2177	case VINF_PATM_CHECK_PATCH_PAGE:
2178	rc = PATMR3HandleMonitoredPage(pVM);
2179	AssertRC(rc);
2180	rc = VINF_SUCCESS;
2181	break;
2182
2183	/*
2184	* Patch manager.
2185	*/
2186	case VERR_EM_RAW_PATCH_CONFLICT:
2187	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2188	break;
2189
2190	#ifdef VBOX_WITH_VMI
2191	/*
2192	* PARAV function.
2193	*/
2194	case VINF_EM_RESCHEDULE_PARAV:
2195	rc = PARAVCallFunction(pVM);
2196	break;
2197	#endif
2198
2199	/*
2200	* Memory mapped I/O access - attempt to patch the instruction
2201	*/
2202	case VINF_PATM_HC_MMIO_PATCH_READ:
2203	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2204	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2205	if (VBOX_FAILURE(rc))
2206	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2207	break;
2208
2209	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2210	AssertFailed(); /* not yet implemented. */
2211	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2212	break;
2213
2214	/*
2215	* Conflict or out of page tables.
2216	*
2217	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2218	* do here is to execute the pending forced actions.
2219	*/
2220	case VINF_PGM_SYNC_CR3:
2221	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2222	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2223	rc = VINF_SUCCESS;
2224	break;
2225
2226	/*
2227	* Paging mode change.
2228	*/
2229	case VINF_PGM_CHANGE_MODE:
2230	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2231	if (VBOX_SUCCESS(rc))
2232	rc = VINF_EM_RESCHEDULE;
2233	break;
2234
2235	/*
2236	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2237	*/
2238	case VINF_CSAM_PENDING_ACTION:
2239	rc = VINF_SUCCESS;
2240	break;
2241
2242	/*
2243	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2244	*/
2245	case VINF_EM_RAW_INTERRUPT_PENDING:
2246	case VINF_EM_RAW_RING_SWITCH_INT:
2247	Assert(TRPMHasTrap(pVM));
2248	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2249
2250	if (TRPMHasTrap(pVM))
2251	{
2252	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2253	uint8_t u8Interrupt = TRPMGetTrapNo(pVM);
2254	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2255	{
2256	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2257	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2258	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2259	}
2260	}
2261	rc = VINF_EM_RESCHEDULE_REM;
2262	break;
2263
2264	/*
2265	* Other ring switch types.
2266	*/
2267	case VINF_EM_RAW_RING_SWITCH:
2268	rc = emR3RawRingSwitch(pVM);
2269	break;
2270
2271	/*
2272	* REMGCNotifyInvalidatePage() failed because of overflow.
2273	*/
2274	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2275	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2276	REMR3ReplayInvalidatedPages(pVM);
2277	rc = VINF_SUCCESS;
2278	break;
2279
2280	/*
2281	* I/O Port access - emulate the instruction.
2282	*/
2283	case VINF_IOM_HC_IOPORT_READ:
2284	case VINF_IOM_HC_IOPORT_WRITE:
2285	rc = emR3RawExecuteIOInstruction(pVM);
2286	break;
2287
2288	/*
2289	* Memory mapped I/O access - emulate the instruction.
2290	*/
2291	case VINF_IOM_HC_MMIO_READ:
2292	case VINF_IOM_HC_MMIO_WRITE:
2293	case VINF_IOM_HC_MMIO_READ_WRITE:
2294	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2295	break;
2296
2297	/*
2298	* Execute instruction.
2299	*/
2300	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2301	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2302	break;
2303	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2304	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2305	break;
2306	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2307	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2308	break;
2309	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2310	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2311	break;
2312	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2313	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2314	break;
2315
2316	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2317	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2318	rc = emR3RawPrivileged(pVM);
2319	break;
2320
2321	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2322	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2323	break;
2324
2325	case VINF_EM_RAW_EMULATE_INSTR:
2326	case VINF_PATCH_EMULATE_INSTR:
2327	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2328	break;
2329
2330	/*
2331	* Stale selector and iret traps => REM.
2332	*/
2333	case VINF_EM_RAW_STALE_SELECTOR:
2334	case VINF_EM_RAW_IRET_TRAP:
2335	/* We will not go to the recompiler if EIP points to patch code. */
2336	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2337	{
2338	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2339	}
2340	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2341	rc = VINF_EM_RESCHEDULE_REM;
2342	break;
2343
2344	/*
2345	* Up a level.
2346	*/
2347	case VINF_EM_TERMINATE:
2348	case VINF_EM_OFF:
2349	case VINF_EM_RESET:
2350	case VINF_EM_SUSPEND:
2351	case VINF_EM_HALT:
2352	case VINF_EM_RESUME:
2353	case VINF_EM_RESCHEDULE:
2354	case VINF_EM_RESCHEDULE_REM:
2355	break;
2356
2357	/*
2358	* Up a level and invoke the debugger.
2359	*/
2360	case VINF_EM_DBG_STEPPED:
2361	case VINF_EM_DBG_BREAKPOINT:
2362	case VINF_EM_DBG_STEP:
2363	case VINF_EM_DBG_HYPER_BREAKPOINT:
2364	case VINF_EM_DBG_HYPER_STEPPED:
2365	case VINF_EM_DBG_HYPER_ASSERTION:
2366	case VINF_EM_DBG_STOP:
2367	break;
2368
2369	/*
2370	* Up a level, dump and debug.
2371	*/
2372	case VERR_TRPM_DONT_PANIC:
2373	case VERR_TRPM_PANIC:
2374	case VINF_EM_DBG_RING0_ASSERTION:
2375	break;
2376
2377	/*
2378	* Up a level, after HwAccM have done some release logging.
2379	*/
2380	case VERR_VMX_INVALID_VMCS_FIELD:
2381	case VERR_VMX_INVALID_VMCS_PTR:
2382	case VERR_VMX_INVALID_VMXON_PTR:
2383	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2384	case VERR_VMX_UNEXPECTED_EXCEPTION:
2385	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2386	case VERR_VMX_INVALID_GUEST_STATE:
2387	case VERR_VMX_UNABLE_TO_START_VM:
2388	case VERR_VMX_UNABLE_TO_RESUME_VM:
2389	HWACCMR3CheckError(pVM, rc);
2390	break;
2391	/*
2392	* Anything which is not known to us means an internal error
2393	* and the termination of the VM!
2394	*/
2395	default:
2396	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2397	break;
2398	}
2399	return rc;
2400	}
2401
2402
2403	/**
2404	* Check for pending raw actions
2405	*
2406	* @returns VBox status code.
2407	* @param pVM The VM to operate on.
2408	*/
2409	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2410	{
2411	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2412	}
2413
2414
2415	/**
2416	* Process raw-mode specific forced actions.
2417	*
2418	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2419	*
2420	* @returns VBox status code.
2421	* Only the normal success/failure stuff, no VINF_EM_*.
2422	* @param pVM The VM handle.
2423	* @param pCtx The guest CPUM register context.
2424	*/
2425	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2426	{
2427	/*
2428	* Note that the order is vitally important!
2429	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2430	*/
2431
2432
2433	/*
2434	* Sync selector tables.
2435	*/
2436	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2437	{
2438	int rc = SELMR3UpdateFromCPUM(pVM);
2439	if (VBOX_FAILURE(rc))
2440	return rc;
2441	}
2442
2443	/*
2444	* Sync IDT.
2445	*/
2446	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2447	{
2448	int rc = TRPMR3SyncIDT(pVM);
2449	if (VBOX_FAILURE(rc))
2450	return rc;
2451	}
2452
2453	/*
2454	* Sync TSS.
2455	*/
2456	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2457	{
2458	int rc = SELMR3SyncTSS(pVM);
2459	if (VBOX_FAILURE(rc))
2460	return rc;
2461	}
2462
2463	/*
2464	* Sync page directory.
2465	*/
2466	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2467	{
2468	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2469	if (VBOX_FAILURE(rc))
2470	return rc;
2471
2472	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2473
2474	/* Prefetch pages for EIP and ESP */
2475	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2476	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2477	if (rc == VINF_SUCCESS)
2478	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2479	if (rc != VINF_SUCCESS)
2480	{
2481	if (rc != VINF_PGM_SYNC_CR3)
2482	return rc;
2483	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2484	if (VBOX_FAILURE(rc))
2485	return rc;
2486	}
2487	/** @todo maybe prefetch the supervisor stack page as well */
2488	}
2489
2490	/*
2491	* Allocate handy pages (just in case the above actions have consumed some pages).
2492	*/
2493	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2494	{
2495	int rc = PGMR3PhysAllocateHandyPages(pVM);
2496	if (VBOX_FAILURE(rc))
2497	return rc;
2498	}
2499
2500	return VINF_SUCCESS;
2501	}
2502
2503
2504	/**
2505	* Executes raw code.
2506	*
2507	* This function contains the raw-mode version of the inner
2508	* execution loop (the outer loop being in EMR3ExecuteVM()).
2509	*
2510	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2511	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2512	*
2513	* @param pVM VM handle.
2514	* @param pfFFDone Where to store an indicator telling whether or not
2515	* FFs were done before returning.
2516	*/
2517	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2518	{
2519	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2520
2521	int rc = VERR_INTERNAL_ERROR;
2522	PCPUMCTX pCtx = pVM->em.s.pCtx;
2523	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2524	pVM->em.s.fForceRAW = false;
2525	*pfFFDone = false;
2526
2527
2528	/*
2529	*
2530	* Spin till we get a forced action or raw mode status code resulting in
2531	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2532	*
2533	*/
2534	for (;;)
2535	{
2536	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2537
2538	/*
2539	* Check various preconditions.
2540	*/
2541	#ifdef VBOX_STRICT
2542	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2543	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2544	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2545	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2546	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2547	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2548	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2549	{
2550	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2551	return VERR_INTERNAL_ERROR;
2552	}
2553	#endif /* VBOX_STRICT */
2554
2555	/*
2556	* Process high priority pre-execution raw-mode FFs.
2557	*/
2558	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2559	{
2560	rc = emR3RawForcedActions(pVM, pCtx);
2561	if (VBOX_FAILURE(rc))
2562	break;
2563	}
2564
2565	/*
2566	* If we're going to execute ring-0 code, the guest state needs to
2567	* be modified a bit and some of the state components (IF, SS/CS RPL,
2568	* and perhaps EIP) needs to be stored with PATM.
2569	*/
2570	rc = CPUMRawEnter(pVM, NULL);
2571	if (rc != VINF_SUCCESS)
2572	{
2573	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2574	break;
2575	}
2576
2577	/*
2578	* Scan code before executing it. Don't bother with user mode or V86 code
2579	*/
2580	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2581	&& !pCtx->eflags.Bits.u1VM
2582	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2583	{
2584	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2585	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2586	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2587	}
2588
2589	#ifdef LOG_ENABLED
2590	/*
2591	* Log important stuff before entering GC.
2592	*/
2593	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2594	if (pCtx->eflags.Bits.u1VM)
2595	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2596	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2597	{
2598	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2599	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2600	}
2601	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2602	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2603	#endif /* LOG_ENABLED */
2604
2605
2606
2607	/*
2608	* Execute the code.
2609	*/
2610	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2611	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2612	VMMR3Unlock(pVM);
2613	rc = VMMR3RawRunGC(pVM);
2614	VMMR3Lock(pVM);
2615	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2616	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2617
2618	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2619	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2620
2621
2622
2623	/*
2624	* Restore the real CPU state and deal with high priority post
2625	* execution FFs before doing anything else.
2626	*/
2627	rc = CPUMRawLeave(pVM, NULL, rc);
2628	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2629	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2630	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2631
2632	#ifdef VBOX_STRICT
2633	/*
2634	* Assert TSS consistency & rc vs patch code.
2635	*/
2636	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2637	&& EMIsRawRing0Enabled(pVM))
2638	SELMR3CheckTSS(pVM);
2639	switch (rc)
2640	{
2641	case VINF_SUCCESS:
2642	case VINF_EM_RAW_INTERRUPT:
2643	case VINF_PATM_PATCH_TRAP_PF:
2644	case VINF_PATM_PATCH_TRAP_GP:
2645	case VINF_PATM_PATCH_INT3:
2646	case VINF_PATM_CHECK_PATCH_PAGE:
2647	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2648	case VINF_EM_RAW_GUEST_TRAP:
2649	case VINF_EM_RESCHEDULE_RAW:
2650	break;
2651
2652	default:
2653	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2654	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VRv for reason %Vrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2655	break;
2656	}
2657	/*
2658	* Let's go paranoid!
2659	*/
2660	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2661	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2662	{
2663	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2664	return VERR_INTERNAL_ERROR;
2665	}
2666	#endif /* VBOX_STRICT */
2667
2668	/*
2669	* Process the returned status code.
2670	*/
2671	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2672	{
2673	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2674	break;
2675	}
2676	rc = emR3RawHandleRC(pVM, pCtx, rc);
2677	if (rc != VINF_SUCCESS)
2678	{
2679	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2680	if (rc != VINF_SUCCESS)
2681	{
2682	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2683	break;
2684	}
2685	}
2686
2687	/*
2688	* Check and execute forced actions.
2689	*/
2690	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2691	TMTimerPoll(pVM);
2692	#endif
2693	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2694	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2695	{
2696	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2697
2698	STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2699	rc = emR3ForcedActions(pVM, rc);
2700	STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2701	if ( rc != VINF_SUCCESS
2702	&& rc != VINF_EM_RESCHEDULE_RAW)
2703	{
2704	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2705	if (rc != VINF_SUCCESS)
2706	{
2707	*pfFFDone = true;
2708	break;
2709	}
2710	}
2711	}
2712	}
2713
2714	/*
2715	* Return to outer loop.
2716	*/
2717	#if defined(LOG_ENABLED) && defined(DEBUG)
2718	RTLogFlush(NULL);
2719	#endif
2720	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2721	return rc;
2722	}
2723
2724
2725	/**
2726	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2727	*
2728	* This function contains the raw-mode version of the inner
2729	* execution loop (the outer loop being in EMR3ExecuteVM()).
2730	*
2731	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2732	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2733	*
2734	* @param pVM VM handle.
2735	* @param pfFFDone Where to store an indicator telling whether or not
2736	* FFs were done before returning.
2737	*/
2738	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2739	{
2740	int rc = VERR_INTERNAL_ERROR;
2741	PCPUMCTX pCtx = pVM->em.s.pCtx;
2742
2743	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%VGv)\n", pCtx->cs, pCtx->rip));
2744	*pfFFDone = false;
2745
2746	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2747
2748	/*
2749	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2750	*/
2751	for (;;)
2752	{
2753	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2754
2755	/*
2756	* Check various preconditions.
2757	*/
2758	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2759
2760	/*
2761	* Process high priority pre-execution raw-mode FFs.
2762	*/
2763	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2764	{
2765	rc = emR3RawForcedActions(pVM, pCtx);
2766	if (VBOX_FAILURE(rc))
2767	break;
2768	}
2769
2770	#ifdef LOG_ENABLED
2771	/*
2772	* Log important stuff before entering GC.
2773	*/
2774	if (TRPMHasTrap(pVM))
2775	Log(("Pending hardware interrupt=0x%x cs:eip=%04X:%VGv\n", TRPMGetTrapNo(pVM), pCtx->cs, pCtx->rip));
2776
2777	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2778	if (pCtx->eflags.Bits.u1VM)
2779	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2780	else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2781	Log(("HWR%d: %04X:%VGv ESP=%VGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2782	else
2783	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2784	#endif /* LOG_ENABLED */
2785
2786	/*
2787	* Execute the code.
2788	*/
2789	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2790	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2791	VMMR3Unlock(pVM);
2792	rc = VMMR3HwAccRunGC(pVM);
2793	VMMR3Lock(pVM);
2794	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2795
2796	/*
2797	* Deal with high priority post execution FFs before doing anything else.
2798	*/
2799	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2800	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2801	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2802
2803	/*
2804	* Process the returned status code.
2805	*/
2806	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2807	break;
2808
2809	rc = emR3RawHandleRC(pVM, pCtx, rc);
2810	if (rc != VINF_SUCCESS)
2811	break;
2812
2813	/*
2814	* Check and execute forced actions.
2815	*/
2816	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2817	TMTimerPoll(pVM);
2818	#endif
2819	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2820	{
2821	rc = emR3ForcedActions(pVM, rc);
2822	if ( rc != VINF_SUCCESS
2823	&& rc != VINF_EM_RESCHEDULE_HWACC)
2824	{
2825	*pfFFDone = true;
2826	break;
2827	}
2828	}
2829	}
2830	/*
2831	* Return to outer loop.
2832	*/
2833	#if defined(LOG_ENABLED) && defined(DEBUG)
2834	RTLogFlush(NULL);
2835	#endif
2836	return rc;
2837	}
2838
2839
2840	/**
2841	* Decides whether to execute RAW, HWACC or REM.
2842	*
2843	* @returns new EM state
2844	* @param pVM The VM.
2845	* @param pCtx The CPU context.
2846	*/
2847	DECLINLINE(EMSTATE) emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2848	{
2849	/*
2850	* When forcing raw-mode execution, things are simple.
2851	*/
2852	if (pVM->em.s.fForceRAW)
2853	return EMSTATE_RAW;
2854
2855	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2856	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2857	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2858
2859	X86EFLAGS EFlags = pCtx->eflags;
2860	if (HWACCMIsEnabled(pVM))
2861	{
2862	/* Hardware accelerated raw-mode:
2863	*
2864	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2865	*/
2866	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2867	return EMSTATE_HWACC;
2868
2869	/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2870	* off monitoring features essential for raw mode! */
2871	return EMSTATE_REM;
2872	}
2873
2874	/*
2875	* Standard raw-mode:
2876	*
2877	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2878	* or 32 bits protected mode ring 0 code
2879	*
2880	* The tests are ordered by the likelyhood of being true during normal execution.
2881	*/
2882	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2883	{
2884	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2885	return EMSTATE_REM;
2886	}
2887
2888	#ifndef VBOX_RAW_V86
2889	if (EFlags.u32 & X86_EFL_VM) {
2890	Log2(("raw mode refused: VM_MASK\n"));
2891	return EMSTATE_REM;
2892	}
2893	#endif
2894
2895	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2896	uint32_t u32CR0 = pCtx->cr0;
2897	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2898	{
2899	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2900	return EMSTATE_REM;
2901	}
2902
2903	if (pCtx->cr4 & X86_CR4_PAE)
2904	{
2905	uint32_t u32Dummy, u32Features;
2906
2907	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2908	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2909	return EMSTATE_REM;
2910	}
2911
2912	unsigned uSS = pCtx->ss;
2913	if ( pCtx->eflags.Bits.u1VM
2914	\|\| (uSS & X86_SEL_RPL) == 3)
2915	{
2916	if (!EMIsRawRing3Enabled(pVM))
2917	return EMSTATE_REM;
2918
2919	if (!(EFlags.u32 & X86_EFL_IF))
2920	{
2921	Log2(("raw mode refused: IF (RawR3)\n"));
2922	return EMSTATE_REM;
2923	}
2924
2925	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2926	{
2927	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2928	return EMSTATE_REM;
2929	}
2930	}
2931	else
2932	{
2933	if (!EMIsRawRing0Enabled(pVM))
2934	return EMSTATE_REM;
2935
2936	/* Only ring 0 supervisor code. */
2937	if ((uSS & X86_SEL_RPL) != 0)
2938	{
2939	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2940	return EMSTATE_REM;
2941	}
2942
2943	// Let's start with pure 32 bits ring 0 code first
2944	/** @todo What's pure 32-bit mode? flat? */
2945	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2946	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2947	{
2948	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2949	return EMSTATE_REM;
2950	}
2951
2952	/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
2953	if (!(u32CR0 & X86_CR0_WP))
2954	{
2955	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2956	return EMSTATE_REM;
2957	}
2958
2959	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2960	{
2961	Log2(("raw r0 mode forced: patch code\n"));
2962	return EMSTATE_RAW;
2963	}
2964
2965	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2966	if (!(EFlags.u32 & X86_EFL_IF))
2967	{
2968	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2969	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2970	return EMSTATE_REM;
2971	}
2972	#endif
2973
2974	/** @todo still necessary??? */
2975	if (EFlags.Bits.u2IOPL != 0)
2976	{
2977	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2978	return EMSTATE_REM;
2979	}
2980	}
2981
2982	Assert(PGMPhysIsA20Enabled(pVM));
2983	return EMSTATE_RAW;
2984	}
2985
2986
2987	/**
2988	* Executes all high priority post execution force actions.
2989	*
2990	* @returns rc or a fatal status code.
2991	*
2992	* @param pVM VM handle.
2993	* @param rc The current rc.
2994	*/
2995	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2996	{
2997	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2998	PDMR3CritSectFF(pVM);
2999
3000	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
3001	CSAMR3DoPendingAction(pVM);
3002
3003	return rc;
3004	}
3005
3006
3007	/**
3008	* Executes all pending forced actions.
3009	*
3010	* Forced actions can cause execution delays and execution
3011	* rescheduling. The first we deal with using action priority, so
3012	* that for instance pending timers aren't scheduled and ran until
3013	* right before execution. The rescheduling we deal with using
3014	* return codes. The same goes for VM termination, only in that case
3015	* we exit everything.
3016	*
3017	* @returns VBox status code of equal or greater importance/severity than rc.
3018	* The most important ones are: VINF_EM_RESCHEDULE,
3019	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3020	*
3021	* @param pVM VM handle.
3022	* @param rc The current rc.
3023	*
3024	*/
3025	static int emR3ForcedActions(PVM pVM, int rc)
3026	{
3027	STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3028	#ifdef VBOX_STRICT
3029	int rcIrq = VINF_SUCCESS;
3030	#endif
3031	int rc2;
3032	#define UPDATE_RC() \
3033	do { \
3034	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
3035	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
3036	break; \
3037	if (!rc \|\| rc2 < rc) \
3038	rc = rc2; \
3039	} while (0)
3040
3041	/*
3042	* Post execution chunk first.
3043	*/
3044	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3045	{
3046	/*
3047	* Termination request.
3048	*/
3049	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3050	{
3051	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3052	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3053	return VINF_EM_TERMINATE;
3054	}
3055
3056	/*
3057	* Debugger Facility polling.
3058	*/
3059	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3060	{
3061	rc2 = DBGFR3VMMForcedAction(pVM);
3062	UPDATE_RC();
3063	}
3064
3065	/*
3066	* Postponed reset request.
3067	*/
3068	if (VM_FF_ISSET(pVM, VM_FF_RESET))
3069	{
3070	rc2 = VMR3Reset(pVM);
3071	UPDATE_RC();
3072	VM_FF_CLEAR(pVM, VM_FF_RESET);
3073	}
3074
3075	/*
3076	* CSAM page scanning.
3077	*/
3078	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3079	{
3080	PCPUMCTX pCtx = pVM->em.s.pCtx;
3081
3082	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3083	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3084
3085	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3086	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3087	}
3088
3089	/* check that we got them all */
3090	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3091	}
3092
3093	/*
3094	* Normal priority then.
3095	* (Executed in no particular order.)
3096	*/
3097	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3098	{
3099	/*
3100	* PDM Queues are pending.
3101	*/
3102	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3103	PDMR3QueueFlushAll(pVM);
3104
3105	/*
3106	* PDM DMA transfers are pending.
3107	*/
3108	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3109	PDMR3DmaRun(pVM);
3110
3111	/*
3112	* Requests from other threads.
3113	*/
3114	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3115	{
3116	rc2 = VMR3ReqProcessU(pVM->pUVM);
3117	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3118	{
3119	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3120	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3121	return rc2;
3122	}
3123	UPDATE_RC();
3124	}
3125
3126	/* Replay the handler notification changes. */
3127	if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3128	REMR3ReplayHandlerNotifications(pVM);
3129
3130	/* check that we got them all */
3131	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3132	}
3133
3134	/*
3135	* Execute polling function ever so often.
3136	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING "SOON"!
3137	*/
3138	static unsigned cLast = 0;
3139	if (!((++cLast) % 4))
3140	PDMR3Poll(pVM);
3141
3142	/*
3143	* High priority pre execution chunk last.
3144	* (Executed in ascending priority order.)
3145	*/
3146	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3147	{
3148	/*
3149	* Timers before interrupts.
3150	*/
3151	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3152	TMR3TimerQueuesDo(pVM);
3153
3154	/*
3155	* The instruction following an emulated STI should always be executed!
3156	*/
3157	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3158	{
3159	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3160	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3161	{
3162	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3163	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3164	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3165	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3166	*/
3167	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3168	}
3169	if (HWACCMR3IsActive(pVM))
3170	rc2 = VINF_EM_RESCHEDULE_HWACC;
3171	else
3172	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3173
3174	UPDATE_RC();
3175	}
3176
3177	/*
3178	* Interrupts.
3179	*/
3180	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3181	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3182	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3183	&& PATMAreInterruptsEnabled(pVM)
3184	&& !HWACCMR3IsEventPending(pVM))
3185	{
3186	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3187	{
3188	/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3189	/** @todo this really isn't nice, should properly handle this */
3190	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3191	#ifdef VBOX_STRICT
3192	rcIrq = rc2;
3193	#endif
3194	UPDATE_RC();
3195	}
3196	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3197	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3198	{
3199	rc2 = VINF_EM_RESCHEDULE_REM;
3200	UPDATE_RC();
3201	}
3202	}
3203
3204	/*
3205	* Allocate handy pages.
3206	*/
3207	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3208	{
3209	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3210	UPDATE_RC();
3211	}
3212
3213	/*
3214	* Debugger Facility request.
3215	*/
3216	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3217	{
3218	rc2 = DBGFR3VMMForcedAction(pVM);
3219	UPDATE_RC();
3220	}
3221
3222	/*
3223	* Termination request.
3224	*/
3225	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3226	{
3227	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3228	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3229	return VINF_EM_TERMINATE;
3230	}
3231
3232	#ifdef DEBUG
3233	/*
3234	* Debug, pause the VM.
3235	*/
3236	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3237	{
3238	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3239	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3240	return VINF_EM_SUSPEND;
3241	}
3242
3243	#endif
3244	/* check that we got them all */
3245	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES)));
3246	}
3247
3248	#undef UPDATE_RC
3249	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3250	STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3251	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3252	return rc;
3253	}
3254
3255
3256	/**
3257	* Execute VM.
3258	*
3259	* This function is the main loop of the VM. The emulation thread
3260	* calls this function when the VM has been successfully constructed
3261	* and we're ready for executing the VM.
3262	*
3263	* Returning from this function means that the VM is turned off or
3264	* suspended (state already saved) and deconstruction in next in line.
3265	*
3266	* All interaction from other thread are done using forced actions
3267	* and signaling of the wait object.
3268	*
3269	* @returns VBox status code, informational status codes may indicate failure.
3270	* @param pVM The VM to operate on.
3271	*/
3272	VMMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3273	{
3274	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3275	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3276	VM_ASSERT_EMT(pVM);
3277	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3278
3279	VMMR3Lock(pVM);
3280
3281	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3282	if (rc == 0)
3283	{
3284	/*
3285	* Start the virtual time.
3286	*/
3287	rc = TMVirtualResume(pVM);
3288	Assert(rc == VINF_SUCCESS);
3289	rc = TMCpuTickResume(pVM);
3290	Assert(rc == VINF_SUCCESS);
3291
3292	/*
3293	* The Outer Main Loop.
3294	*/
3295	bool fFFDone = false;
3296	rc = VINF_EM_RESCHEDULE;
3297	pVM->em.s.enmState = EMSTATE_REM;
3298	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3299	for (;;)
3300	{
3301	/*
3302	* Before we can schedule anything (we're here because
3303	* scheduling is required) we must service any pending
3304	* forced actions to avoid any pending action causing
3305	* immediate rescheduling upon entering an inner loop
3306	*
3307	* Do forced actions.
3308	*/
3309	if ( !fFFDone
3310	&& rc != VINF_EM_TERMINATE
3311	&& rc != VINF_EM_OFF
3312	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3313	{
3314	rc = emR3ForcedActions(pVM, rc);
3315	if ( ( rc == VINF_EM_RESCHEDULE_REM
3316	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3317	&& pVM->em.s.fForceRAW)
3318	rc = VINF_EM_RESCHEDULE_RAW;
3319	}
3320	else if (fFFDone)
3321	fFFDone = false;
3322
3323	/*
3324	* Now what to do?
3325	*/
3326	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3327	switch (rc)
3328	{
3329	/*
3330	* Keep doing what we're currently doing.
3331	*/
3332	case VINF_SUCCESS:
3333	break;
3334
3335	/*
3336	* Reschedule - to raw-mode execution.
3337	*/
3338	case VINF_EM_RESCHEDULE_RAW:
3339	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3340	pVM->em.s.enmState = EMSTATE_RAW;
3341	break;
3342
3343	/*
3344	* Reschedule - to hardware accelerated raw-mode execution.
3345	*/
3346	case VINF_EM_RESCHEDULE_HWACC:
3347	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3348	Assert(!pVM->em.s.fForceRAW);
3349	pVM->em.s.enmState = EMSTATE_HWACC;
3350	break;
3351
3352	/*
3353	* Reschedule - to recompiled execution.
3354	*/
3355	case VINF_EM_RESCHEDULE_REM:
3356	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3357	pVM->em.s.enmState = EMSTATE_REM;
3358	break;
3359
3360	#ifdef VBOX_WITH_VMI
3361	/*
3362	* Reschedule - parav call.
3363	*/
3364	case VINF_EM_RESCHEDULE_PARAV:
3365	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVM->em.s.enmState, EMSTATE_PARAV));
3366	pVM->em.s.enmState = EMSTATE_PARAV;
3367	break;
3368	#endif
3369
3370	/*
3371	* Resume.
3372	*/
3373	case VINF_EM_RESUME:
3374	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3375	/* fall through and get scheduled. */
3376
3377	/*
3378	* Reschedule.
3379	*/
3380	case VINF_EM_RESCHEDULE:
3381	{
3382	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3383	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3384	pVM->em.s.enmState = enmState;
3385	break;
3386	}
3387
3388	/*
3389	* Halted.
3390	*/
3391	case VINF_EM_HALT:
3392	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3393	pVM->em.s.enmState = EMSTATE_HALTED;
3394	break;
3395
3396	/*
3397	* Suspend.
3398	*/
3399	case VINF_EM_SUSPEND:
3400	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3401	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3402	break;
3403
3404	/*
3405	* Reset.
3406	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3407	*/
3408	case VINF_EM_RESET:
3409	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3410	pVM->em.s.enmState = EMSTATE_REM;
3411	break;
3412
3413	/*
3414	* Power Off.
3415	*/
3416	case VINF_EM_OFF:
3417	pVM->em.s.enmState = EMSTATE_TERMINATING;
3418	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3419	TMVirtualPause(pVM);
3420	TMCpuTickPause(pVM);
3421	VMMR3Unlock(pVM);
3422	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3423	return rc;
3424
3425	/*
3426	* Terminate the VM.
3427	*/
3428	case VINF_EM_TERMINATE:
3429	pVM->em.s.enmState = EMSTATE_TERMINATING;
3430	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3431	TMVirtualPause(pVM);
3432	TMCpuTickPause(pVM);
3433	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3434	return rc;
3435
3436	/*
3437	* Guest debug events.
3438	*/
3439	case VINF_EM_DBG_STEPPED:
3440	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3441	case VINF_EM_DBG_STOP:
3442	case VINF_EM_DBG_BREAKPOINT:
3443	case VINF_EM_DBG_STEP:
3444	if (pVM->em.s.enmState == EMSTATE_RAW)
3445	{
3446	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3447	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3448	}
3449	else
3450	{
3451	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3452	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3453	}
3454	break;
3455
3456	/*
3457	* Hypervisor debug events.
3458	*/
3459	case VINF_EM_DBG_HYPER_STEPPED:
3460	case VINF_EM_DBG_HYPER_BREAKPOINT:
3461	case VINF_EM_DBG_HYPER_ASSERTION:
3462	Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3463	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3464	break;
3465
3466	/*
3467	* Guru mediations.
3468	*/
3469	case VINF_EM_DBG_RING0_ASSERTION:
3470	Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVM->em.s.enmState, EMSTATE_GURU_MEDITATION));
3471	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3472	break;
3473
3474	/*
3475	* Any error code showing up here other than the ones we
3476	* know and process above are considered to be FATAL.
3477	*
3478	* Unknown warnings and informational status codes are also
3479	* included in this.
3480	*/
3481	default:
3482	if (VBOX_SUCCESS(rc))
3483	{
3484	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3485	rc = VERR_EM_INTERNAL_ERROR;
3486	}
3487	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3488	Log(("EMR3ExecuteVM returns %d\n", rc));
3489	break;
3490	}
3491
3492
3493	/*
3494	* Any waiters can now be woken up
3495	*/
3496	VMMR3Unlock(pVM);
3497	VMMR3Lock(pVM);
3498
3499	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3500	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3501
3502	/*
3503	* Act on the state.
3504	*/
3505	switch (pVM->em.s.enmState)
3506	{
3507	/*
3508	* Execute raw.
3509	*/
3510	case EMSTATE_RAW:
3511	rc = emR3RawExecute(pVM, &fFFDone);
3512	break;
3513
3514	/*
3515	* Execute hardware accelerated raw.
3516	*/
3517	case EMSTATE_HWACC:
3518	rc = emR3HwAccExecute(pVM, &fFFDone);
3519	break;
3520
3521	/*
3522	* Execute recompiled.
3523	*/
3524	case EMSTATE_REM:
3525	rc = emR3RemExecute(pVM, &fFFDone);
3526	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3527	break;
3528
3529	#ifdef VBOX_WITH_VMI
3530	/*
3531	* Execute PARAV function.
3532	*/
3533	case EMSTATE_PARAV:
3534	rc = PARAVCallFunction(pVM);
3535	pVM->em.s.enmState = EMSTATE_REM;
3536	break;
3537	#endif
3538
3539	/*
3540	* hlt - execution halted until interrupt.
3541	*/
3542	case EMSTATE_HALTED:
3543	{
3544	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3545	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3546	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3547	break;
3548	}
3549
3550	/*
3551	* Suspended - return to VM.cpp.
3552	*/
3553	case EMSTATE_SUSPENDED:
3554	TMVirtualPause(pVM);
3555	TMCpuTickPause(pVM);
3556	VMMR3Unlock(pVM);
3557	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3558	return VINF_EM_SUSPEND;
3559
3560	/*
3561	* Debugging in the guest.
3562	*/
3563	case EMSTATE_DEBUG_GUEST_REM:
3564	case EMSTATE_DEBUG_GUEST_RAW:
3565	TMVirtualPause(pVM);
3566	TMCpuTickPause(pVM);
3567	rc = emR3Debug(pVM, rc);
3568	TMVirtualResume(pVM);
3569	TMCpuTickResume(pVM);
3570	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3571	break;
3572
3573	/*
3574	* Debugging in the hypervisor.
3575	*/
3576	case EMSTATE_DEBUG_HYPER:
3577	{
3578	TMVirtualPause(pVM);
3579	TMCpuTickPause(pVM);
3580	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3581
3582	rc = emR3Debug(pVM, rc);
3583	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3584	if (rc != VINF_SUCCESS)
3585	{
3586	/* switch to guru meditation mode */
3587	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3588	VMMR3FatalDump(pVM, rc);
3589	return rc;
3590	}
3591
3592	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3593	TMVirtualResume(pVM);
3594	TMCpuTickResume(pVM);
3595	break;
3596	}
3597
3598	/*
3599	* Guru meditation takes place in the debugger.
3600	*/
3601	case EMSTATE_GURU_MEDITATION:
3602	{
3603	TMVirtualPause(pVM);
3604	TMCpuTickPause(pVM);
3605	VMMR3FatalDump(pVM, rc);
3606	emR3Debug(pVM, rc);
3607	VMMR3Unlock(pVM);
3608	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3609	return rc;
3610	}
3611
3612	/*
3613	* The states we don't expect here.
3614	*/
3615	case EMSTATE_NONE:
3616	case EMSTATE_TERMINATING:
3617	default:
3618	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3619	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3620	TMVirtualPause(pVM);
3621	TMCpuTickPause(pVM);
3622	VMMR3Unlock(pVM);
3623	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3624	return VERR_EM_INTERNAL_ERROR;
3625	}
3626	} /* The Outer Main Loop */
3627	}
3628	else
3629	{
3630	/*
3631	* Fatal error.
3632	*/
3633	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3634	TMVirtualPause(pVM);
3635	TMCpuTickPause(pVM);
3636	VMMR3FatalDump(pVM, rc);
3637	emR3Debug(pVM, rc);
3638	VMMR3Unlock(pVM);
3639	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3640	/** @todo change the VM state! */
3641	return rc;
3642	}
3643
3644	/* (won't ever get here). */
3645	AssertFailed();
3646	}
3647

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 13702

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