VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 13538

Last change on this file since 13538 was 13532, checked in by vboxsync, 16 years ago

CPUMQueryGuestCtxPtr doesn't need to return a status. It can never fail.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 150.2 KB
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1/* $Id: EM.cpp 13532 2008-10-23 12:39:48Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_em EM - The Execution Monitor / Manager
23 *
24 * The Execution Monitor/Manager is responsible for running the VM, scheduling
25 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26 * Interpreted), and keeping the CPU states in sync. The function
27 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29 * emR3RemExecute).
30 *
31 * The interpreted execution is only used to avoid switching between
32 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33 * The interpretation is thus implemented as part of EM.
34 *
35 * @see grp_em
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_EM
42#include <VBox/em.h>
43#include <VBox/vmm.h>
44#ifdef VBOX_WITH_VMI
45# include <VBox/parav.h>
46#endif
47#include <VBox/patm.h>
48#include <VBox/csam.h>
49#include <VBox/selm.h>
50#include <VBox/trpm.h>
51#include <VBox/iom.h>
52#include <VBox/dbgf.h>
53#include <VBox/pgm.h>
54#include <VBox/rem.h>
55#include <VBox/tm.h>
56#include <VBox/mm.h>
57#include <VBox/ssm.h>
58#include <VBox/pdmapi.h>
59#include <VBox/pdmcritsect.h>
60#include <VBox/pdmqueue.h>
61#include <VBox/hwaccm.h>
62#include <VBox/patm.h>
63#include "EMInternal.h"
64#include <VBox/vm.h>
65#include <VBox/cpumdis.h>
66#include <VBox/dis.h>
67#include <VBox/disopcode.h>
68#include <VBox/dbgf.h>
69
70#include <VBox/log.h>
71#include <iprt/thread.h>
72#include <iprt/assert.h>
73#include <iprt/asm.h>
74#include <iprt/semaphore.h>
75#include <iprt/string.h>
76#include <iprt/avl.h>
77#include <iprt/stream.h>
78#include <VBox/param.h>
79#include <VBox/err.h>
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
87static int emR3Debug(PVM pVM, int rc);
88static int emR3RemStep(PVM pVM);
89static int emR3RemExecute(PVM pVM, bool *pfFFDone);
90static int emR3RawResumeHyper(PVM pVM);
91static int emR3RawStep(PVM pVM);
92DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
93DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
94static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
95static int emR3RawExecute(PVM pVM, bool *pfFFDone);
96DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
97static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
98static int emR3ForcedActions(PVM pVM, int rc);
99static int emR3RawGuestTrap(PVM pVM);
100static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret);
101
102
103/**
104 * Initializes the EM.
105 *
106 * @returns VBox status code.
107 * @param pVM The VM to operate on.
108 */
109VMMR3DECL(int) EMR3Init(PVM pVM)
110{
111 LogFlow(("EMR3Init\n"));
112 /*
113 * Assert alignment and sizes.
114 */
115 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
116 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
117 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
118 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
119
120 /*
121 * Init the structure.
122 */
123 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
124 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
125 if (VBOX_FAILURE(rc))
126 pVM->fRawR3Enabled = true;
127 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
128 if (VBOX_FAILURE(rc))
129 pVM->fRawR0Enabled = true;
130 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
131 pVM->em.s.enmState = EMSTATE_NONE;
132 pVM->em.s.fForceRAW = false;
133
134 pVM->em.s.pCtx = CPUMQueryGuestCtxPtr(pVM);
135 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
136 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
137
138 /*
139 * Saved state.
140 */
141 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
142 NULL, emR3Save, NULL,
143 NULL, emR3Load, NULL);
144 if (VBOX_FAILURE(rc))
145 return rc;
146
147 /*
148 * Statistics.
149 */
150#ifdef VBOX_WITH_STATISTICS
151 PEMSTATS pStats;
152 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
153 if (VBOX_FAILURE(rc))
154 return rc;
155 pVM->em.s.pStatsR3 = pStats;
156 pVM->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
157 pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
158
159 STAM_REG(pVM, &pStats->StatRZEmulate, STAMTYPE_PROFILE, "/EM/RZ/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
160 STAM_REG(pVM, &pStats->StatR3Emulate, STAMTYPE_PROFILE, "/EM/R3/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
161
162 STAM_REG(pVM, &pStats->StatRZInterpretSucceeded, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
163 STAM_REG(pVM, &pStats->StatR3InterpretSucceeded, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
164
165 STAM_REG_USED(pVM, &pStats->StatRZAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
166 STAM_REG_USED(pVM, &pStats->StatR3And, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
167 STAM_REG_USED(pVM, &pStats->StatRZAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
168 STAM_REG_USED(pVM, &pStats->StatR3Add, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
169 STAM_REG_USED(pVM, &pStats->StatRZAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
170 STAM_REG_USED(pVM, &pStats->StatR3Adc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
171 STAM_REG_USED(pVM, &pStats->StatRZSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
172 STAM_REG_USED(pVM, &pStats->StatR3Sub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
173 STAM_REG_USED(pVM, &pStats->StatRZCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
174 STAM_REG_USED(pVM, &pStats->StatR3CpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatRZDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatR3Dec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatRZHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatR3Hlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatRZInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatR3Inc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatRZInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatR3InvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatRZIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatR3Iret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
185 STAM_REG_USED(pVM, &pStats->StatRZLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatR3LLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatRZLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatR3LIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatRZLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatR3LGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatRZMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatR3Mov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatRZMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
194 STAM_REG_USED(pVM, &pStats->StatR3MovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
195 STAM_REG_USED(pVM, &pStats->StatRZMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
196 STAM_REG_USED(pVM, &pStats->StatR3MovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
197 STAM_REG_USED(pVM, &pStats->StatRZOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
198 STAM_REG_USED(pVM, &pStats->StatR3Or, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
199 STAM_REG_USED(pVM, &pStats->StatRZPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
200 STAM_REG_USED(pVM, &pStats->StatR3Pop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatRZRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatR3Rdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
203 STAM_REG_USED(pVM, &pStats->StatRZSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
204 STAM_REG_USED(pVM, &pStats->StatR3Sti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
205 STAM_REG_USED(pVM, &pStats->StatRZXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
206 STAM_REG_USED(pVM, &pStats->StatR3Xchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
207 STAM_REG_USED(pVM, &pStats->StatRZXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
208 STAM_REG_USED(pVM, &pStats->StatR3Xor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatRZMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatR3Monitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatRZMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatR3MWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatRZBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatR3Btr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatRZBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatR3Bts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
217 STAM_REG_USED(pVM, &pStats->StatRZBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
218 STAM_REG_USED(pVM, &pStats->StatR3Btc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
219 STAM_REG_USED(pVM, &pStats->StatRZCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
220 STAM_REG_USED(pVM, &pStats->StatR3CmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
221 STAM_REG_USED(pVM, &pStats->StatRZCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatR3CmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatRZXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatR3XAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatR3Rdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatRZRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was successfully interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatR3Wrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatRZWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was successfully interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatR3StosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatRZStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was successfully interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatRZWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatR3WbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was successfully interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatRZLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
234 STAM_REG_USED(pVM, &pStats->StatR3Lmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Success/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was successfully interpreted.");
235
236 STAM_REG(pVM, &pStats->StatRZInterpretFailed, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
237 STAM_REG(pVM, &pStats->StatR3InterpretFailed, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
238
239 STAM_REG_USED(pVM, &pStats->StatRZFailedAnd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
240 STAM_REG_USED(pVM, &pStats->StatR3FailedAnd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
241 STAM_REG_USED(pVM, &pStats->StatRZFailedCpuId, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatR3FailedCpuId, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatRZFailedDec, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
244 STAM_REG_USED(pVM, &pStats->StatR3FailedDec, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
245 STAM_REG_USED(pVM, &pStats->StatRZFailedHlt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
246 STAM_REG_USED(pVM, &pStats->StatR3FailedHlt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
247 STAM_REG_USED(pVM, &pStats->StatRZFailedInc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
248 STAM_REG_USED(pVM, &pStats->StatR3FailedInc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
249 STAM_REG_USED(pVM, &pStats->StatRZFailedInvlPg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatR3FailedInvlPg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatRZFailedIret, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatR3FailedIret, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatRZFailedLLdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatR3FailedLLdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatRZFailedLIdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatR3FailedLIdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LIdt", STAMUNIT_OCCURENCES, "The number of times LIDT was not interpreted.");
257 STAM_REG_USED(pVM, &pStats->StatRZFailedLGdt, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
258 STAM_REG_USED(pVM, &pStats->StatR3FailedLGdt, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/LGdt", STAMUNIT_OCCURENCES, "The number of times LGDT was not interpreted.");
259 STAM_REG_USED(pVM, &pStats->StatRZFailedMov, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
260 STAM_REG_USED(pVM, &pStats->StatR3FailedMov, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
261 STAM_REG_USED(pVM, &pStats->StatRZFailedMovCRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
262 STAM_REG_USED(pVM, &pStats->StatR3FailedMovCRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
263 STAM_REG_USED(pVM, &pStats->StatRZFailedMovDRx, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
264 STAM_REG_USED(pVM, &pStats->StatR3FailedMovDRx, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
265 STAM_REG_USED(pVM, &pStats->StatRZFailedOr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
266 STAM_REG_USED(pVM, &pStats->StatR3FailedOr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
267 STAM_REG_USED(pVM, &pStats->StatRZFailedPop, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
268 STAM_REG_USED(pVM, &pStats->StatR3FailedPop, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
269 STAM_REG_USED(pVM, &pStats->StatRZFailedSti, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
270 STAM_REG_USED(pVM, &pStats->StatR3FailedSti, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
271 STAM_REG_USED(pVM, &pStats->StatRZFailedXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
272 STAM_REG_USED(pVM, &pStats->StatR3FailedXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
273 STAM_REG_USED(pVM, &pStats->StatRZFailedXor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
274 STAM_REG_USED(pVM, &pStats->StatR3FailedXor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
275 STAM_REG_USED(pVM, &pStats->StatRZFailedMonitor, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
276 STAM_REG_USED(pVM, &pStats->StatR3FailedMonitor, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
277 STAM_REG_USED(pVM, &pStats->StatRZFailedMWait, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
278 STAM_REG_USED(pVM, &pStats->StatR3FailedMWait, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
279 STAM_REG_USED(pVM, &pStats->StatRZFailedRdtsc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
280 STAM_REG_USED(pVM, &pStats->StatR3FailedRdtsc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
281 STAM_REG_USED(pVM, &pStats->StatRZFailedRdmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
282 STAM_REG_USED(pVM, &pStats->StatR3FailedRdmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
283 STAM_REG_USED(pVM, &pStats->StatRZFailedWrmsr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
284 STAM_REG_USED(pVM, &pStats->StatR3FailedWrmsr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
285 STAM_REG_USED(pVM, &pStats->StatRZFailedLmsw, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
286 STAM_REG_USED(pVM, &pStats->StatR3FailedLmsw, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Lmsw", STAMUNIT_OCCURENCES, "The number of times LMSW was not interpreted.");
287
288 STAM_REG_USED(pVM, &pStats->StatRZFailedMisc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
289 STAM_REG_USED(pVM, &pStats->StatR3FailedMisc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
290 STAM_REG_USED(pVM, &pStats->StatRZFailedAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
291 STAM_REG_USED(pVM, &pStats->StatR3FailedAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
292 STAM_REG_USED(pVM, &pStats->StatRZFailedAdc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
293 STAM_REG_USED(pVM, &pStats->StatR3FailedAdc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
294 STAM_REG_USED(pVM, &pStats->StatRZFailedBtr, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
295 STAM_REG_USED(pVM, &pStats->StatR3FailedBtr, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
296 STAM_REG_USED(pVM, &pStats->StatRZFailedBts, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
297 STAM_REG_USED(pVM, &pStats->StatR3FailedBts, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
298 STAM_REG_USED(pVM, &pStats->StatRZFailedBtc, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
299 STAM_REG_USED(pVM, &pStats->StatR3FailedBtc, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
300 STAM_REG_USED(pVM, &pStats->StatRZFailedCli, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
301 STAM_REG_USED(pVM, &pStats->StatR3FailedCli, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
302 STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
303 STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
304 STAM_REG_USED(pVM, &pStats->StatRZFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
305 STAM_REG_USED(pVM, &pStats->StatR3FailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
306 STAM_REG_USED(pVM, &pStats->StatRZFailedXAdd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
307 STAM_REG_USED(pVM, &pStats->StatR3FailedXAdd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
308 STAM_REG_USED(pVM, &pStats->StatRZFailedMovNTPS, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
309 STAM_REG_USED(pVM, &pStats->StatR3FailedMovNTPS, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
310 STAM_REG_USED(pVM, &pStats->StatRZFailedStosWD, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
311 STAM_REG_USED(pVM, &pStats->StatR3FailedStosWD, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
312 STAM_REG_USED(pVM, &pStats->StatRZFailedSub, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
313 STAM_REG_USED(pVM, &pStats->StatR3FailedSub, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
314 STAM_REG_USED(pVM, &pStats->StatRZFailedWbInvd, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
315 STAM_REG_USED(pVM, &pStats->StatR3FailedWbInvd, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
316
317 STAM_REG_USED(pVM, &pStats->StatRZFailedUserMode, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
318 STAM_REG_USED(pVM, &pStats->StatR3FailedUserMode, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
319 STAM_REG_USED(pVM, &pStats->StatRZFailedPrefix, STAMTYPE_COUNTER, "/EM/RZ/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
320 STAM_REG_USED(pVM, &pStats->StatR3FailedPrefix, STAMTYPE_COUNTER, "/EM/R3/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
321
322 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
323 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
324 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/R3/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
325 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
326 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
327 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
328 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
329 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
330 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
331 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
332 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
333 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
334 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
335 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
336 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
337 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
338 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/R3/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
339 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/R3/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
340 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
341 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
342 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
343 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
344 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
345 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
346 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
347 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/R3/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
348
349 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
350 pVM->em.s.pCliStatTree = 0;
351#endif /* VBOX_WITH_STATISTICS */
352
353 /* these should be considered for release statistics. */
354 STAM_REL_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
355 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
356 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
357 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
358
359 STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
360 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
361 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
362 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
363 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
364 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
365 STAM_REL_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
366 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
367 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
368 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
369 STAM_REL_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
370 STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
371
372
373 return VINF_SUCCESS;
374}
375
376
377/**
378 * Applies relocations to data and code managed by this
379 * component. This function will be called at init and
380 * whenever the VMM need to relocate it self inside the GC.
381 *
382 * @param pVM The VM.
383 */
384VMMR3DECL(void) EMR3Relocate(PVM pVM)
385{
386 LogFlow(("EMR3Relocate\n"));
387 if (pVM->em.s.pStatsR3)
388 pVM->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->em.s.pStatsR3);
389}
390
391
392/**
393 * Reset notification.
394 *
395 * @param pVM
396 */
397VMMR3DECL(void) EMR3Reset(PVM pVM)
398{
399 LogFlow(("EMR3Reset: \n"));
400 pVM->em.s.fForceRAW = false;
401}
402
403
404/**
405 * Terminates the EM.
406 *
407 * Termination means cleaning up and freeing all resources,
408 * the VM it self is at this point powered off or suspended.
409 *
410 * @returns VBox status code.
411 * @param pVM The VM to operate on.
412 */
413VMMR3DECL(int) EMR3Term(PVM pVM)
414{
415 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
416
417 return VINF_SUCCESS;
418}
419
420
421/**
422 * Execute state save operation.
423 *
424 * @returns VBox status code.
425 * @param pVM VM Handle.
426 * @param pSSM SSM operation handle.
427 */
428static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
429{
430 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
431}
432
433
434/**
435 * Execute state load operation.
436 *
437 * @returns VBox status code.
438 * @param pVM VM Handle.
439 * @param pSSM SSM operation handle.
440 * @param u32Version Data layout version.
441 */
442static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
443{
444 /*
445 * Validate version.
446 */
447 if (u32Version != EM_SAVED_STATE_VERSION)
448 {
449 AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
450 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
451 }
452
453 /*
454 * Load the saved state.
455 */
456 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
457 if (VBOX_FAILURE(rc))
458 pVM->em.s.fForceRAW = false;
459
460 Assert(!pVM->em.s.pCliStatTree);
461 return rc;
462}
463
464
465/**
466 * Enables or disables a set of raw-mode execution modes.
467 *
468 * @returns VINF_SUCCESS on success.
469 * @returns VINF_RESCHEDULE if a rescheduling might be required.
470 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
471 *
472 * @param pVM The VM to operate on.
473 * @param enmMode The execution mode change.
474 * @thread The emulation thread.
475 */
476VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
477{
478 switch (enmMode)
479 {
480 case EMRAW_NONE:
481 pVM->fRawR3Enabled = false;
482 pVM->fRawR0Enabled = false;
483 break;
484 case EMRAW_RING3_ENABLE:
485 pVM->fRawR3Enabled = true;
486 break;
487 case EMRAW_RING3_DISABLE:
488 pVM->fRawR3Enabled = false;
489 break;
490 case EMRAW_RING0_ENABLE:
491 pVM->fRawR0Enabled = true;
492 break;
493 case EMRAW_RING0_DISABLE:
494 pVM->fRawR0Enabled = false;
495 break;
496 default:
497 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
498 return VERR_INVALID_PARAMETER;
499 }
500 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
501 pVM->fRawR3Enabled, pVM->fRawR0Enabled));
502 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
503}
504
505
506/**
507 * Raise a fatal error.
508 *
509 * Safely terminate the VM with full state report and stuff. This function
510 * will naturally never return.
511 *
512 * @param pVM VM handle.
513 * @param rc VBox status code.
514 */
515VMMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
516{
517 longjmp(pVM->em.s.u.FatalLongJump, rc);
518 AssertReleaseMsgFailed(("longjmp returned!\n"));
519}
520
521
522/**
523 * Gets the EM state name.
524 *
525 * @returns pointer to read only state name,
526 * @param enmState The state.
527 */
528VMMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
529{
530 switch (enmState)
531 {
532 case EMSTATE_NONE: return "EMSTATE_NONE";
533 case EMSTATE_RAW: return "EMSTATE_RAW";
534 case EMSTATE_HWACC: return "EMSTATE_HWACC";
535 case EMSTATE_REM: return "EMSTATE_REM";
536 case EMSTATE_PARAV: return "EMSTATE_PARAV";
537 case EMSTATE_HALTED: return "EMSTATE_HALTED";
538 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
539 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
540 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
541 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
542 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
543 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
544 default: return "Unknown!";
545 }
546}
547
548
549#ifdef VBOX_WITH_STATISTICS
550/**
551 * Just a braindead function to keep track of cli addresses.
552 * @param pVM VM handle.
553 * @param pInstrGC The EIP of the cli instruction.
554 */
555static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
556{
557 PCLISTAT pRec;
558
559 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
560 if (!pRec)
561 {
562 /* New cli instruction; insert into the tree. */
563 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
564 Assert(pRec);
565 if (!pRec)
566 return;
567 pRec->Core.Key = (AVLPVKEY)pInstrGC;
568
569 char szCliStatName[32];
570 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
571 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
572
573 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
574 Assert(fRc); NOREF(fRc);
575 }
576 STAM_COUNTER_INC(&pRec->Counter);
577 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
578}
579#endif /* VBOX_WITH_STATISTICS */
580
581
582/**
583 * Debug loop.
584 *
585 * @returns VBox status code for EM.
586 * @param pVM VM handle.
587 * @param rc Current EM VBox status code..
588 */
589static int emR3Debug(PVM pVM, int rc)
590{
591 for (;;)
592 {
593 Log(("emR3Debug: rc=%Vrc\n", rc));
594 const int rcLast = rc;
595
596 /*
597 * Debug related RC.
598 */
599 switch (rc)
600 {
601 /*
602 * Single step an instruction.
603 */
604 case VINF_EM_DBG_STEP:
605 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
606 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
607 || pVM->em.s.fForceRAW /* paranoia */)
608 rc = emR3RawStep(pVM);
609 else
610 {
611 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
612 rc = emR3RemStep(pVM);
613 }
614 break;
615
616 /*
617 * Simple events: stepped, breakpoint, stop/assertion.
618 */
619 case VINF_EM_DBG_STEPPED:
620 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
621 break;
622
623 case VINF_EM_DBG_BREAKPOINT:
624 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
625 break;
626
627 case VINF_EM_DBG_STOP:
628 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
629 break;
630
631 case VINF_EM_DBG_HYPER_STEPPED:
632 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
633 break;
634
635 case VINF_EM_DBG_HYPER_BREAKPOINT:
636 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
637 break;
638
639 case VINF_EM_DBG_HYPER_ASSERTION:
640 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
641 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
642 break;
643
644 /*
645 * Guru meditation.
646 */
647 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
648 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
649 break;
650
651 default: /** @todo don't use default for guru, but make special errors code! */
652 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
653 break;
654 }
655
656 /*
657 * Process the result.
658 */
659 do
660 {
661 switch (rc)
662 {
663 /*
664 * Continue the debugging loop.
665 */
666 case VINF_EM_DBG_STEP:
667 case VINF_EM_DBG_STOP:
668 case VINF_EM_DBG_STEPPED:
669 case VINF_EM_DBG_BREAKPOINT:
670 case VINF_EM_DBG_HYPER_STEPPED:
671 case VINF_EM_DBG_HYPER_BREAKPOINT:
672 case VINF_EM_DBG_HYPER_ASSERTION:
673 break;
674
675 /*
676 * Resuming execution (in some form) has to be done here if we got
677 * a hypervisor debug event.
678 */
679 case VINF_SUCCESS:
680 case VINF_EM_RESUME:
681 case VINF_EM_SUSPEND:
682 case VINF_EM_RESCHEDULE:
683 case VINF_EM_RESCHEDULE_RAW:
684 case VINF_EM_RESCHEDULE_REM:
685 case VINF_EM_HALT:
686 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
687 {
688 rc = emR3RawResumeHyper(pVM);
689 if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
690 continue;
691 }
692 if (rc == VINF_SUCCESS)
693 rc = VINF_EM_RESCHEDULE;
694 return rc;
695
696 /*
697 * The debugger isn't attached.
698 * We'll simply turn the thing off since that's the easiest thing to do.
699 */
700 case VERR_DBGF_NOT_ATTACHED:
701 switch (rcLast)
702 {
703 case VINF_EM_DBG_HYPER_ASSERTION:
704 case VINF_EM_DBG_HYPER_STEPPED:
705 case VINF_EM_DBG_HYPER_BREAKPOINT:
706 return rcLast;
707 }
708 return VINF_EM_OFF;
709
710 /*
711 * Status codes terminating the VM in one or another sense.
712 */
713 case VINF_EM_TERMINATE:
714 case VINF_EM_OFF:
715 case VINF_EM_RESET:
716 case VINF_EM_RAW_STALE_SELECTOR:
717 case VINF_EM_RAW_IRET_TRAP:
718 case VERR_TRPM_PANIC:
719 case VERR_TRPM_DONT_PANIC:
720 case VERR_INTERNAL_ERROR:
721 return rc;
722
723 /*
724 * The rest is unexpected, and will keep us here.
725 */
726 default:
727 AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
728 break;
729 }
730 } while (false);
731 } /* debug for ever */
732}
733
734
735/**
736 * Steps recompiled code.
737 *
738 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
739 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
740 *
741 * @param pVM VM handle.
742 */
743static int emR3RemStep(PVM pVM)
744{
745 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
746
747 /*
748 * Switch to REM, step instruction, switch back.
749 */
750 int rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
751 if (VBOX_SUCCESS(rc))
752 {
753 rc = REMR3Step(pVM);
754 REMR3StateBack(pVM);
755 pVM->em.s.fREMFlushTBs = false;
756 }
757 LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
758 return rc;
759}
760
761
762/**
763 * Executes recompiled code.
764 *
765 * This function contains the recompiler version of the inner
766 * execution loop (the outer loop being in EMR3ExecuteVM()).
767 *
768 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
769 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
770 *
771 * @param pVM VM handle.
772 * @param pfFFDone Where to store an indicator telling wheter or not
773 * FFs were done before returning.
774 *
775 */
776static int emR3RemExecute(PVM pVM, bool *pfFFDone)
777{
778#ifdef LOG_ENABLED
779 PCPUMCTX pCtx = pVM->em.s.pCtx;
780 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
781
782 if (pCtx->eflags.Bits.u1VM)
783 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
784 else
785 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
786#endif
787 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
788
789#if defined(VBOX_STRICT) && defined(DEBUG_bird)
790 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
791 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
792 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
793#endif
794
795 /*
796 * Spin till we get a forced action which returns anything but VINF_SUCCESS
797 * or the REM suggests raw-mode execution.
798 */
799 *pfFFDone = false;
800 bool fInREMState = false;
801 int rc = VINF_SUCCESS;
802 for (;;)
803 {
804 /*
805 * Update REM state if not already in sync.
806 */
807 if (!fInREMState)
808 {
809 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
810 rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
811 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
812 if (VBOX_FAILURE(rc))
813 break;
814 fInREMState = true;
815 pVM->em.s.fREMFlushTBs = false;
816
817 /*
818 * We might have missed the raising of VMREQ, TIMER and some other
819 * imporant FFs while we were busy switching the state. So, check again.
820 */
821 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
822 {
823 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
824 goto l_REMDoForcedActions;
825 }
826 }
827
828
829 /*
830 * Execute REM.
831 */
832 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
833 rc = REMR3Run(pVM);
834 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
835
836
837 /*
838 * Deal with high priority post execution FFs before doing anything else.
839 */
840 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
841 rc = emR3HighPriorityPostForcedActions(pVM, rc);
842
843 /*
844 * Process the returned status code.
845 * (Try keep this short! Call functions!)
846 */
847 if (rc != VINF_SUCCESS)
848 {
849 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
850 break;
851 if (rc != VINF_REM_INTERRUPED_FF)
852 {
853 /*
854 * Anything which is not known to us means an internal error
855 * and the termination of the VM!
856 */
857 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Vra\n", rc));
858 break;
859 }
860 }
861
862
863 /*
864 * Check and execute forced actions.
865 * Sync back the VM state before calling any of these.
866 */
867#ifdef VBOX_HIGH_RES_TIMERS_HACK
868 TMTimerPoll(pVM);
869#endif
870 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION | VM_FF_CSAM_SCAN_PAGE)))
871 {
872l_REMDoForcedActions:
873 if (fInREMState)
874 {
875 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
876 REMR3StateBack(pVM);
877 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
878 fInREMState = false;
879 }
880 STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
881 rc = emR3ForcedActions(pVM, rc);
882 STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
883 if ( rc != VINF_SUCCESS
884 && rc != VINF_EM_RESCHEDULE_REM)
885 {
886 *pfFFDone = true;
887 break;
888 }
889 }
890
891 } /* The Inner Loop, recompiled execution mode version. */
892
893
894 /*
895 * Returning. Sync back the VM state if required.
896 */
897 if (fInREMState)
898 {
899 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
900 REMR3StateBack(pVM);
901 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
902 }
903
904 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
905 return rc;
906}
907
908
909/**
910 * Resumes executing hypervisor after a debug event.
911 *
912 * This is kind of special since our current guest state is
913 * potentially out of sync.
914 *
915 * @returns VBox status code.
916 * @param pVM The VM handle.
917 */
918static int emR3RawResumeHyper(PVM pVM)
919{
920 int rc;
921 PCPUMCTX pCtx = pVM->em.s.pCtx;
922 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
923 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
924
925 /*
926 * Resume execution.
927 */
928 CPUMRawEnter(pVM, NULL);
929 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
930 rc = VMMR3ResumeHyper(pVM);
931 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
932 rc = CPUMRawLeave(pVM, NULL, rc);
933 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
934
935 /*
936 * Deal with the return code.
937 */
938 rc = emR3HighPriorityPostForcedActions(pVM, rc);
939 rc = emR3RawHandleRC(pVM, pCtx, rc);
940 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
941 return rc;
942}
943
944
945/**
946 * Steps rawmode.
947 *
948 * @returns VBox status code.
949 * @param pVM The VM handle.
950 */
951static int emR3RawStep(PVM pVM)
952{
953 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
954 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
955 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
956 int rc;
957 PCPUMCTX pCtx = pVM->em.s.pCtx;
958 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
959#ifndef DEBUG_sandervl
960 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
961 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
962#endif
963 if (fGuest)
964 {
965 /*
966 * Check vital forced actions, but ignore pending interrupts and timers.
967 */
968 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
969 {
970 rc = emR3RawForcedActions(pVM, pCtx);
971 if (VBOX_FAILURE(rc))
972 return rc;
973 }
974
975 /*
976 * Set flags for single stepping.
977 */
978 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
979 }
980 else
981 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
982
983 /*
984 * Single step.
985 * We do not start time or anything, if anything we should just do a few nanoseconds.
986 */
987 CPUMRawEnter(pVM, NULL);
988 do
989 {
990 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
991 rc = VMMR3ResumeHyper(pVM);
992 else
993 rc = VMMR3RawRunGC(pVM);
994#ifndef DEBUG_sandervl
995 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
996 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
997#endif
998 } while ( rc == VINF_SUCCESS
999 || rc == VINF_EM_RAW_INTERRUPT);
1000 rc = CPUMRawLeave(pVM, NULL, rc);
1001 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1002
1003 /*
1004 * Make sure the trap flag is cleared.
1005 * (Too bad if the guest is trying to single step too.)
1006 */
1007 if (fGuest)
1008 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1009 else
1010 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
1011
1012 /*
1013 * Deal with the return codes.
1014 */
1015 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1016 rc = emR3RawHandleRC(pVM, pCtx, rc);
1017 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1018 return rc;
1019}
1020
1021
1022#ifdef DEBUG
1023
1024/**
1025 * Steps hardware accelerated mode.
1026 *
1027 * @returns VBox status code.
1028 * @param pVM The VM handle.
1029 */
1030static int emR3HwAccStep(PVM pVM)
1031{
1032 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1033
1034 int rc;
1035 PCPUMCTX pCtx = pVM->em.s.pCtx;
1036 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
1037
1038 /*
1039 * Check vital forced actions, but ignore pending interrupts and timers.
1040 */
1041 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1042 {
1043 rc = emR3RawForcedActions(pVM, pCtx);
1044 if (VBOX_FAILURE(rc))
1045 return rc;
1046 }
1047 /*
1048 * Set flags for single stepping.
1049 */
1050 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
1051
1052 /*
1053 * Single step.
1054 * We do not start time or anything, if anything we should just do a few nanoseconds.
1055 */
1056 do
1057 {
1058 rc = VMMR3HwAccRunGC(pVM);
1059 } while ( rc == VINF_SUCCESS
1060 || rc == VINF_EM_RAW_INTERRUPT);
1061 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1062
1063 /*
1064 * Make sure the trap flag is cleared.
1065 * (Too bad if the guest is trying to single step too.)
1066 */
1067 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1068
1069 /*
1070 * Deal with the return codes.
1071 */
1072 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1073 rc = emR3RawHandleRC(pVM, pCtx, rc);
1074 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1075 return rc;
1076}
1077
1078
1079void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1080{
1081 EMSTATE enmOldState = pVM->em.s.enmState;
1082
1083 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1084
1085 Log(("Single step BEGIN:\n"));
1086 for (uint32_t i = 0; i < cIterations; i++)
1087 {
1088 DBGFR3PrgStep(pVM);
1089 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1090 emR3RawStep(pVM);
1091 }
1092 Log(("Single step END:\n"));
1093 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1094 pVM->em.s.enmState = enmOldState;
1095}
1096
1097
1098void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1099{
1100 EMSTATE enmOldState = pVM->em.s.enmState;
1101
1102 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1103
1104 Log(("Single step BEGIN:\n"));
1105 for (uint32_t i = 0; i < cIterations; i++)
1106 {
1107 DBGFR3PrgStep(pVM);
1108 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1109 emR3HwAccStep(pVM);
1110 }
1111 Log(("Single step END:\n"));
1112 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1113 pVM->em.s.enmState = enmOldState;
1114}
1115
1116
1117void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1118{
1119 EMSTATE enmOldState = pVM->em.s.enmState;
1120
1121 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1122
1123 Log(("Single step BEGIN:\n"));
1124 for (uint32_t i = 0; i < cIterations; i++)
1125 {
1126 DBGFR3PrgStep(pVM);
1127 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1128 emR3RemStep(pVM);
1129 }
1130 Log(("Single step END:\n"));
1131 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1132 pVM->em.s.enmState = enmOldState;
1133}
1134
1135#endif /* DEBUG */
1136
1137
1138/**
1139 * Executes one (or perhaps a few more) instruction(s).
1140 *
1141 * @returns VBox status code suitable for EM.
1142 *
1143 * @param pVM VM handle.
1144 * @param rcGC GC return code
1145 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1146 * instruction and prefix the log output with this text.
1147 */
1148#ifdef LOG_ENABLED
1149static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1150#else
1151static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1152#endif
1153{
1154 PCPUMCTX pCtx = pVM->em.s.pCtx;
1155 int rc;
1156
1157 /*
1158 *
1159 * The simple solution is to use the recompiler.
1160 * The better solution is to disassemble the current instruction and
1161 * try handle as many as possible without using REM.
1162 *
1163 */
1164
1165#ifdef LOG_ENABLED
1166 /*
1167 * Disassemble the instruction if requested.
1168 */
1169 if (pszPrefix)
1170 {
1171 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1172 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1173 }
1174#endif /* LOG_ENABLED */
1175
1176 /*
1177 * PATM is making life more interesting.
1178 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1179 * tell PATM there is a trap in this code and have it take the appropriate actions
1180 * to allow us execute the code in REM.
1181 */
1182 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1183 {
1184 Log(("emR3RawExecuteInstruction: In patch block. eip=%VRv\n", pCtx->eip));
1185
1186 RTGCPTR pNewEip;
1187 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1188 switch (rc)
1189 {
1190 /*
1191 * It's not very useful to emulate a single instruction and then go back to raw
1192 * mode; just execute the whole block until IF is set again.
1193 */
1194 case VINF_SUCCESS:
1195 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1196 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1197 pCtx->eip = pNewEip;
1198 Assert(pCtx->eip);
1199
1200 if (pCtx->eflags.Bits.u1IF)
1201 {
1202 /*
1203 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1204 */
1205 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1206 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1207 }
1208 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1209 {
1210 /* special case: iret, that sets IF, detected a pending irq/event */
1211 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1212 }
1213 return VINF_EM_RESCHEDULE_REM;
1214
1215 /*
1216 * One instruction.
1217 */
1218 case VINF_PATCH_EMULATE_INSTR:
1219 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1220 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1221 pCtx->eip = pNewEip;
1222 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1223
1224 /*
1225 * The patch was disabled, hand it to the REM.
1226 */
1227 case VERR_PATCH_DISABLED:
1228 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1229 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1230 pCtx->eip = pNewEip;
1231 if (pCtx->eflags.Bits.u1IF)
1232 {
1233 /*
1234 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1235 */
1236 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1237 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1238 }
1239 return VINF_EM_RESCHEDULE_REM;
1240
1241 /* Force continued patch exection; usually due to write monitored stack. */
1242 case VINF_PATCH_CONTINUE:
1243 return VINF_SUCCESS;
1244
1245 default:
1246 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1247 return VERR_INTERNAL_ERROR;
1248 }
1249 }
1250
1251#if 0
1252 /* Try our own instruction emulator before falling back to the recompiler. */
1253 DISCPUSTATE Cpu;
1254 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1255 if (VBOX_SUCCESS(rc))
1256 {
1257 uint32_t size;
1258
1259 switch (Cpu.pCurInstr->opcode)
1260 {
1261 /* @todo we can do more now */
1262 case OP_MOV:
1263 case OP_AND:
1264 case OP_OR:
1265 case OP_XOR:
1266 case OP_POP:
1267 case OP_INC:
1268 case OP_DEC:
1269 case OP_XCHG:
1270 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1271 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1272 if (VBOX_SUCCESS(rc))
1273 {
1274 pCtx->rip += Cpu.opsize;
1275 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1276 return rc;
1277 }
1278 if (rc != VERR_EM_INTERPRETER)
1279 AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1280 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1281 break;
1282 }
1283 }
1284#endif /* 0 */
1285 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1286 rc = REMR3EmulateInstruction(pVM);
1287 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1288
1289 return rc;
1290}
1291
1292
1293/**
1294 * Executes one (or perhaps a few more) instruction(s).
1295 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1296 *
1297 * @returns VBox status code suitable for EM.
1298 * @param pVM VM handle.
1299 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1300 * instruction and prefix the log output with this text.
1301 * @param rcGC GC return code
1302 */
1303DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1304{
1305#ifdef LOG_ENABLED
1306 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1307#else
1308 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1309#endif
1310}
1311
1312/**
1313 * Executes one (or perhaps a few more) IO instruction(s).
1314 *
1315 * @returns VBox status code suitable for EM.
1316 * @param pVM VM handle.
1317 */
1318int emR3RawExecuteIOInstruction(PVM pVM)
1319{
1320 int rc;
1321 PCPUMCTX pCtx = pVM->em.s.pCtx;
1322
1323 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1324
1325 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1326 * as io instructions tend to come in packages of more than one
1327 */
1328 DISCPUSTATE Cpu;
1329 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1330 if (VBOX_SUCCESS(rc))
1331 {
1332 rc = VINF_EM_RAW_EMULATE_INSTR;
1333
1334 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1335 {
1336 switch (Cpu.pCurInstr->opcode)
1337 {
1338 case OP_IN:
1339 {
1340 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1341 rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1342 break;
1343 }
1344
1345 case OP_OUT:
1346 {
1347 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1348 rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1349 break;
1350 }
1351 }
1352 }
1353 else if (Cpu.prefix & PREFIX_REP)
1354 {
1355 switch (Cpu.pCurInstr->opcode)
1356 {
1357 case OP_INSB:
1358 case OP_INSWD:
1359 {
1360 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatIn);
1361 rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1362 break;
1363 }
1364
1365 case OP_OUTSB:
1366 case OP_OUTSWD:
1367 {
1368 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatOut);
1369 rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1370 break;
1371 }
1372 }
1373 }
1374
1375 /*
1376 * Handled the I/O return codes.
1377 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1378 */
1379 if (IOM_SUCCESS(rc))
1380 {
1381 pCtx->rip += Cpu.opsize;
1382 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1383 return rc;
1384 }
1385
1386 if (rc == VINF_EM_RAW_GUEST_TRAP)
1387 {
1388 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1389 rc = emR3RawGuestTrap(pVM);
1390 return rc;
1391 }
1392 AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1393
1394 if (VBOX_FAILURE(rc))
1395 {
1396 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1397 return rc;
1398 }
1399 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1400 }
1401 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1402 return emR3RawExecuteInstruction(pVM, "IO: ");
1403}
1404
1405
1406/**
1407 * Handle a guest context trap.
1408 *
1409 * @returns VBox status code suitable for EM.
1410 * @param pVM VM handle.
1411 */
1412static int emR3RawGuestTrap(PVM pVM)
1413{
1414 PCPUMCTX pCtx = pVM->em.s.pCtx;
1415
1416 /*
1417 * Get the trap info.
1418 */
1419 uint8_t u8TrapNo;
1420 TRPMEVENT enmType;
1421 RTGCUINT uErrorCode;
1422 RTGCUINTPTR uCR2;
1423 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1424 if (VBOX_FAILURE(rc))
1425 {
1426 AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1427 return rc;
1428 }
1429
1430 /*
1431 * Traps can be directly forwarded in hardware accelerated mode.
1432 */
1433 if (HWACCMR3IsActive(pVM))
1434 {
1435#ifdef LOGGING_ENABLED
1436 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1437 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1438#endif
1439 return VINF_EM_RESCHEDULE_HWACC;
1440 }
1441
1442#if 1 /* Experimental: Review, disable if it causes trouble. */
1443 /*
1444 * Handle traps in patch code first.
1445 *
1446 * We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
1447 * but several traps isn't handled specially by TRPM in RC and we end up here
1448 * instead. One example is #DE.
1449 */
1450 uint32_t uCpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
1451 if ( uCpl == 0
1452 && PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1453 {
1454 LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
1455 return emR3PatchTrap(pVM, pCtx, rc);
1456 }
1457#endif
1458
1459 /*
1460 * If the guest gate is marked unpatched, then we will check again if we can patch it.
1461 * (This assumes that we've already tried and failed to dispatch the trap in
1462 * RC for the gates that already has been patched. Which is true for most high
1463 * volume traps, because these are handled specially, but not for odd ones like #DE.)
1464 */
1465 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
1466 {
1467 CSAMR3CheckGates(pVM, u8TrapNo, 1);
1468 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
1469
1470 /* If it was successful, then we could go back to raw mode. */
1471 if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
1472 {
1473 /* Must check pending forced actions as our IDT or GDT might be out of sync. */
1474 rc = EMR3CheckRawForcedActions(pVM);
1475 AssertRCReturn(rc, rc);
1476
1477 TRPMERRORCODE enmError = uErrorCode != ~0U
1478 ? TRPM_TRAP_HAS_ERRORCODE
1479 : TRPM_TRAP_NO_ERRORCODE;
1480 rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
1481 if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
1482 {
1483 TRPMResetTrap(pVM);
1484 return VINF_EM_RESCHEDULE_RAW;
1485 }
1486 AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
1487 }
1488 }
1489
1490 /*
1491 * Scan kernel code that traps; we might not get another chance.
1492 */
1493 /** @todo move this up before the dispatching? */
1494 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1495 && !pCtx->eflags.Bits.u1VM)
1496 {
1497 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1498 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1499 }
1500
1501 /*
1502 * Trap specific handling.
1503 */
1504 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1505 {
1506 /*
1507 * If MONITOR & MWAIT are supported, then interpret them here.
1508 */
1509 DISCPUSTATE cpu;
1510 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1511 if ( VBOX_SUCCESS(rc)
1512 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1513 {
1514 uint32_t u32Dummy, u32Features, u32ExtFeatures;
1515 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1516 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1517 {
1518 rc = TRPMResetTrap(pVM);
1519 AssertRC(rc);
1520
1521 uint32_t opsize;
1522 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
1523 if (VBOX_SUCCESS(rc))
1524 {
1525 pCtx->rip += cpu.opsize;
1526 return rc;
1527 }
1528 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1529 }
1530 }
1531 }
1532 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1533 {
1534 /*
1535 * Handle I/O bitmap?
1536 */
1537 /** @todo We're not supposed to be here with a false guest trap concerning
1538 * I/O access. We can easily handle those in RC. */
1539 DISCPUSTATE cpu;
1540 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1541 if ( VBOX_SUCCESS(rc)
1542 && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1543 {
1544 /*
1545 * We should really check the TSS for the IO bitmap, but it's not like this
1546 * lazy approach really makes things worse.
1547 */
1548 rc = TRPMResetTrap(pVM);
1549 AssertRC(rc);
1550 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1551 }
1552 }
1553
1554#ifdef LOG_ENABLED
1555 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1556 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1557
1558 /* Get guest page information. */
1559 uint64_t fFlags = 0;
1560 RTGCPHYS GCPhys = 0;
1561 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1562 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1563 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1564 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1565 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1566#endif
1567
1568 /*
1569 * #PG has CR2.
1570 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1571 */
1572 if (u8TrapNo == 14 /* #PG */)
1573 pCtx->cr2 = uCR2;
1574
1575 return VINF_EM_RESCHEDULE_REM;
1576}
1577
1578
1579/**
1580 * Handle a ring switch trap.
1581 * Need to do statistics and to install patches. The result is going to REM.
1582 *
1583 * @returns VBox status code suitable for EM.
1584 * @param pVM VM handle.
1585 */
1586int emR3RawRingSwitch(PVM pVM)
1587{
1588 int rc;
1589 DISCPUSTATE Cpu;
1590 PCPUMCTX pCtx = pVM->em.s.pCtx;
1591
1592 /*
1593 * sysenter, syscall & callgate
1594 */
1595 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1596 if (VBOX_SUCCESS(rc))
1597 {
1598 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1599 {
1600 if (pCtx->SysEnter.cs != 0)
1601 {
1602 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1603 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1604 if (VBOX_SUCCESS(rc))
1605 {
1606 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1607 return VINF_EM_RESCHEDULE_RAW;
1608 }
1609 }
1610 }
1611
1612#ifdef VBOX_WITH_STATISTICS
1613 switch (Cpu.pCurInstr->opcode)
1614 {
1615 case OP_SYSENTER:
1616 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysEnter);
1617 break;
1618 case OP_SYSEXIT:
1619 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysExit);
1620 break;
1621 case OP_SYSCALL:
1622 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysCall);
1623 break;
1624 case OP_SYSRET:
1625 STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->StatSysRet);
1626 break;
1627 }
1628#endif
1629 }
1630 else
1631 AssertRC(rc);
1632
1633 /* go to the REM to emulate a single instruction */
1634 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1635}
1636
1637
1638/**
1639 * Handle a trap (\#PF or \#GP) in patch code
1640 *
1641 * @returns VBox status code suitable for EM.
1642 * @param pVM VM handle.
1643 * @param pCtx CPU context
1644 * @param gcret GC return code
1645 */
1646static int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1647{
1648 uint8_t u8TrapNo;
1649 int rc;
1650 TRPMEVENT enmType;
1651 RTGCUINT uErrorCode;
1652 RTGCUINTPTR uCR2;
1653
1654 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1655
1656 if (gcret == VINF_PATM_PATCH_INT3)
1657 {
1658 u8TrapNo = 3;
1659 uCR2 = 0;
1660 uErrorCode = 0;
1661 }
1662 else if (gcret == VINF_PATM_PATCH_TRAP_GP)
1663 {
1664 /* No active trap in this case. Kind of ugly. */
1665 u8TrapNo = X86_XCPT_GP;
1666 uCR2 = 0;
1667 uErrorCode = 0;
1668 }
1669 else
1670 {
1671 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1672 if (VBOX_FAILURE(rc))
1673 {
1674 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1675 return rc;
1676 }
1677 /* Reset the trap as we'll execute the original instruction again. */
1678 TRPMResetTrap(pVM);
1679 }
1680
1681 /*
1682 * Deal with traps inside patch code.
1683 * (This code won't run outside GC.)
1684 */
1685 if (u8TrapNo != 1)
1686 {
1687#ifdef LOG_ENABLED
1688 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1689 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1690
1691 DISCPUSTATE Cpu;
1692 int rc;
1693
1694 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1695 if ( VBOX_SUCCESS(rc)
1696 && Cpu.pCurInstr->opcode == OP_IRET)
1697 {
1698 uint32_t eip, selCS, uEFlags;
1699
1700 /* Iret crashes are bad as we have already changed the flags on the stack */
1701 rc = PGMPhysSimpleReadGCPtr(pVM, &eip, pCtx->esp, 4);
1702 rc |= PGMPhysSimpleReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1703 rc |= PGMPhysSimpleReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1704 if (rc == VINF_SUCCESS)
1705 {
1706 if ( (uEFlags & X86_EFL_VM)
1707 || (selCS & X86_SEL_RPL) == 3)
1708 {
1709 uint32_t selSS, esp;
1710
1711 rc |= PGMPhysSimpleReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1712 rc |= PGMPhysSimpleReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1713
1714 if (uEFlags & X86_EFL_VM)
1715 {
1716 uint32_t selDS, selES, selFS, selGS;
1717 rc = PGMPhysSimpleReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1718 rc |= PGMPhysSimpleReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1719 rc |= PGMPhysSimpleReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1720 rc |= PGMPhysSimpleReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1721 if (rc == VINF_SUCCESS)
1722 {
1723 Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1724 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1725 }
1726 }
1727 else
1728 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1729 }
1730 else
1731 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1732 }
1733 }
1734#endif /* LOG_ENABLED */
1735 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1736 pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1737
1738 RTGCPTR pNewEip;
1739 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1740 switch (rc)
1741 {
1742 /*
1743 * Execute the faulting instruction.
1744 */
1745 case VINF_SUCCESS:
1746 {
1747 /** @todo execute a whole block */
1748 Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1749 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1750 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1751
1752 pCtx->eip = pNewEip;
1753 AssertRelease(pCtx->eip);
1754
1755 if (pCtx->eflags.Bits.u1IF)
1756 {
1757 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1758 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1759 */
1760 if ( u8TrapNo == X86_XCPT_GP
1761 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1762 {
1763 /** @todo move to PATMR3HandleTrap */
1764 Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1765 PATMR3RemovePatch(pVM, pCtx->eip);
1766 }
1767
1768 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1769 /* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
1770
1771 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1772 /* Interrupts are enabled; just go back to the original instruction.
1773 return VINF_SUCCESS; */
1774 }
1775 return VINF_EM_RESCHEDULE_REM;
1776 }
1777
1778 /*
1779 * One instruction.
1780 */
1781 case VINF_PATCH_EMULATE_INSTR:
1782 Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1783 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1784 pCtx->eip = pNewEip;
1785 AssertRelease(pCtx->eip);
1786 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1787
1788 /*
1789 * The patch was disabled, hand it to the REM.
1790 */
1791 case VERR_PATCH_DISABLED:
1792 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1793 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1794 pCtx->eip = pNewEip;
1795 AssertRelease(pCtx->eip);
1796
1797 if (pCtx->eflags.Bits.u1IF)
1798 {
1799 /*
1800 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1801 */
1802 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1803 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1804 }
1805 return VINF_EM_RESCHEDULE_REM;
1806
1807 /* Force continued patch exection; usually due to write monitored stack. */
1808 case VINF_PATCH_CONTINUE:
1809 return VINF_SUCCESS;
1810
1811 /*
1812 * Anything else is *fatal*.
1813 */
1814 default:
1815 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1816 return VERR_INTERNAL_ERROR;
1817 }
1818 }
1819 return VINF_SUCCESS;
1820}
1821
1822
1823/**
1824 * Handle a privileged instruction.
1825 *
1826 * @returns VBox status code suitable for EM.
1827 * @param pVM VM handle.
1828 */
1829int emR3RawPrivileged(PVM pVM)
1830{
1831 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1832 PCPUMCTX pCtx = pVM->em.s.pCtx;
1833
1834 Assert(!pCtx->eflags.Bits.u1VM);
1835
1836 if (PATMIsEnabled(pVM))
1837 {
1838 /*
1839 * Check if in patch code.
1840 */
1841 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1842 {
1843#ifdef LOG_ENABLED
1844 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1845#endif
1846 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1847 return VERR_EM_RAW_PATCH_CONFLICT;
1848 }
1849 if ( (pCtx->ss & X86_SEL_RPL) == 0
1850 && !pCtx->eflags.Bits.u1VM
1851 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1852 {
1853 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1854 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1855 if (VBOX_SUCCESS(rc))
1856 {
1857#ifdef LOG_ENABLED
1858 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1859#endif
1860 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1861 return VINF_SUCCESS;
1862 }
1863 }
1864 }
1865
1866#ifdef LOG_ENABLED
1867 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1868 {
1869 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1870 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1871 }
1872#endif
1873
1874 /*
1875 * Instruction statistics and logging.
1876 */
1877 DISCPUSTATE Cpu;
1878 int rc;
1879
1880 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1881 if (VBOX_SUCCESS(rc))
1882 {
1883#ifdef VBOX_WITH_STATISTICS
1884 PEMSTATS pStats = pVM->em.s.CTX_SUFF(pStats);
1885 switch (Cpu.pCurInstr->opcode)
1886 {
1887 case OP_INVLPG:
1888 STAM_COUNTER_INC(&pStats->StatInvlpg);
1889 break;
1890 case OP_IRET:
1891 STAM_COUNTER_INC(&pStats->StatIret);
1892 break;
1893 case OP_CLI:
1894 STAM_COUNTER_INC(&pStats->StatCli);
1895 emR3RecordCli(pVM, pCtx->rip);
1896 break;
1897 case OP_STI:
1898 STAM_COUNTER_INC(&pStats->StatSti);
1899 break;
1900 case OP_INSB:
1901 case OP_INSWD:
1902 case OP_IN:
1903 case OP_OUTSB:
1904 case OP_OUTSWD:
1905 case OP_OUT:
1906 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1907 break;
1908
1909 case OP_MOV_CR:
1910 if (Cpu.param1.flags & USE_REG_GEN32)
1911 {
1912 //read
1913 Assert(Cpu.param2.flags & USE_REG_CR);
1914 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1915 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1916 }
1917 else
1918 {
1919 //write
1920 Assert(Cpu.param1.flags & USE_REG_CR);
1921 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1922 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1923 }
1924 break;
1925
1926 case OP_MOV_DR:
1927 STAM_COUNTER_INC(&pStats->StatMovDRx);
1928 break;
1929 case OP_LLDT:
1930 STAM_COUNTER_INC(&pStats->StatMovLldt);
1931 break;
1932 case OP_LIDT:
1933 STAM_COUNTER_INC(&pStats->StatMovLidt);
1934 break;
1935 case OP_LGDT:
1936 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1937 break;
1938 case OP_SYSENTER:
1939 STAM_COUNTER_INC(&pStats->StatSysEnter);
1940 break;
1941 case OP_SYSEXIT:
1942 STAM_COUNTER_INC(&pStats->StatSysExit);
1943 break;
1944 case OP_SYSCALL:
1945 STAM_COUNTER_INC(&pStats->StatSysCall);
1946 break;
1947 case OP_SYSRET:
1948 STAM_COUNTER_INC(&pStats->StatSysRet);
1949 break;
1950 case OP_HLT:
1951 STAM_COUNTER_INC(&pStats->StatHlt);
1952 break;
1953 default:
1954 STAM_COUNTER_INC(&pStats->StatMisc);
1955 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1956 break;
1957 }
1958#endif /* VBOX_WITH_STATISTICS */
1959 if ( (pCtx->ss & X86_SEL_RPL) == 0
1960 && !pCtx->eflags.Bits.u1VM
1961 && SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1962 {
1963 uint32_t size;
1964
1965 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1966 switch (Cpu.pCurInstr->opcode)
1967 {
1968 case OP_CLI:
1969 pCtx->eflags.u32 &= ~X86_EFL_IF;
1970 Assert(Cpu.opsize == 1);
1971 pCtx->rip += Cpu.opsize;
1972 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1973 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1974
1975 case OP_STI:
1976 pCtx->eflags.u32 |= X86_EFL_IF;
1977 EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
1978 Assert(Cpu.opsize == 1);
1979 pCtx->rip += Cpu.opsize;
1980 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1981 return VINF_SUCCESS;
1982
1983 case OP_HLT:
1984 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1985 {
1986 PATMTRANSSTATE enmState;
1987 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1988
1989 if (enmState == PATMTRANS_OVERWRITTEN)
1990 {
1991 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1992 Assert(rc == VERR_PATCH_DISABLED);
1993 /* Conflict detected, patch disabled */
1994 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1995
1996 enmState = PATMTRANS_SAFE;
1997 }
1998
1999 /* The translation had better be successful. Otherwise we can't recover. */
2000 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
2001 if (enmState != PATMTRANS_OVERWRITTEN)
2002 pCtx->eip = pOrgInstrGC;
2003 }
2004 /* no break; we could just return VINF_EM_HALT here */
2005
2006 case OP_MOV_CR:
2007 case OP_MOV_DR:
2008#ifdef LOG_ENABLED
2009 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2010 {
2011 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
2012 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
2013 }
2014#endif
2015
2016 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
2017 if (VBOX_SUCCESS(rc))
2018 {
2019 pCtx->rip += Cpu.opsize;
2020 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2021
2022 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
2023 && Cpu.param1.flags == USE_REG_CR /* write */
2024 )
2025 {
2026 /* Deal with CR0 updates inside patch code that force
2027 * us to go to the recompiler.
2028 */
2029 if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
2030 && (pCtx->cr0 & (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE)) != (X86_CR0_WP|X86_CR0_PG|X86_CR0_PE))
2031 {
2032 PATMTRANSSTATE enmState;
2033 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
2034
2035 Assert(pCtx->eflags.Bits.u1IF == 0);
2036 Log(("Force recompiler switch due to cr0 (%VGp) update\n", pCtx->cr0));
2037 if (enmState == PATMTRANS_OVERWRITTEN)
2038 {
2039 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
2040 Assert(rc == VERR_PATCH_DISABLED);
2041 /* Conflict detected, patch disabled */
2042 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->rip));
2043 enmState = PATMTRANS_SAFE;
2044 }
2045 /* The translation had better be successful. Otherwise we can't recover. */
2046 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->rip));
2047 if (enmState != PATMTRANS_OVERWRITTEN)
2048 pCtx->rip = pOrgInstrGC;
2049 }
2050
2051 /* Reschedule is necessary as the execution/paging mode might have changed. */
2052 return VINF_EM_RESCHEDULE;
2053 }
2054 return rc; /* can return VINF_EM_HALT as well. */
2055 }
2056 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
2057 break; /* fall back to the recompiler */
2058 }
2059 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
2060 }
2061 }
2062
2063 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2064 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
2065
2066 return emR3RawExecuteInstruction(pVM, "PRIV");
2067}
2068
2069
2070/**
2071 * Update the forced rawmode execution modifier.
2072 *
2073 * This function is called when we're returning from the raw-mode loop(s). If we're
2074 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2075 * if not in patch code, the flag will be cleared.
2076 *
2077 * We should never interrupt patch code while it's being executed. Cli patches can
2078 * contain big code blocks, but they are always executed with IF=0. Other patches
2079 * replace single instructions and should be atomic.
2080 *
2081 * @returns Updated rc.
2082 *
2083 * @param pVM The VM handle.
2084 * @param pCtx The guest CPU context.
2085 * @param rc The result code.
2086 */
2087DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2088{
2089 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2090 {
2091 /* ignore reschedule attempts. */
2092 switch (rc)
2093 {
2094 case VINF_EM_RESCHEDULE:
2095 case VINF_EM_RESCHEDULE_REM:
2096 rc = VINF_SUCCESS;
2097 break;
2098 }
2099 pVM->em.s.fForceRAW = true;
2100 }
2101 else
2102 pVM->em.s.fForceRAW = false;
2103 return rc;
2104}
2105
2106
2107/**
2108 * Process a subset of the raw-mode return code.
2109 *
2110 * Since we have to share this with raw-mode single stepping, this inline
2111 * function has been created to avoid code duplication.
2112 *
2113 * @returns VINF_SUCCESS if it's ok to continue raw mode.
2114 * @returns VBox status code to return to the EM main loop.
2115 *
2116 * @param pVM The VM handle
2117 * @param rc The return code.
2118 * @param pCtx The guest cpu context.
2119 */
2120DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2121{
2122 switch (rc)
2123 {
2124 /*
2125 * Common & simple ones.
2126 */
2127 case VINF_SUCCESS:
2128 break;
2129 case VINF_EM_RESCHEDULE_RAW:
2130 case VINF_EM_RESCHEDULE_HWACC:
2131 case VINF_EM_RAW_INTERRUPT:
2132 case VINF_EM_RAW_TO_R3:
2133 case VINF_EM_RAW_TIMER_PENDING:
2134 case VINF_EM_PENDING_REQUEST:
2135 rc = VINF_SUCCESS;
2136 break;
2137
2138 /*
2139 * Privileged instruction.
2140 */
2141 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2142 case VINF_PATM_PATCH_TRAP_GP:
2143 rc = emR3RawPrivileged(pVM);
2144 break;
2145
2146 /*
2147 * Got a trap which needs dispatching.
2148 */
2149 case VINF_EM_RAW_GUEST_TRAP:
2150 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2151 {
2152 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2153 rc = VERR_EM_RAW_PATCH_CONFLICT;
2154 break;
2155 }
2156 rc = emR3RawGuestTrap(pVM);
2157 break;
2158
2159 /*
2160 * Trap in patch code.
2161 */
2162 case VINF_PATM_PATCH_TRAP_PF:
2163 case VINF_PATM_PATCH_INT3:
2164 rc = emR3PatchTrap(pVM, pCtx, rc);
2165 break;
2166
2167 case VINF_PATM_DUPLICATE_FUNCTION:
2168 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2169 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2170 AssertRC(rc);
2171 rc = VINF_SUCCESS;
2172 break;
2173
2174 case VINF_PATM_CHECK_PATCH_PAGE:
2175 rc = PATMR3HandleMonitoredPage(pVM);
2176 AssertRC(rc);
2177 rc = VINF_SUCCESS;
2178 break;
2179
2180 /*
2181 * Patch manager.
2182 */
2183 case VERR_EM_RAW_PATCH_CONFLICT:
2184 AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2185 break;
2186
2187#ifdef VBOX_WITH_VMI
2188 /*
2189 * PARAV function.
2190 */
2191 case VINF_EM_RESCHEDULE_PARAV:
2192 rc = PARAVCallFunction(pVM);
2193 break;
2194#endif
2195
2196 /*
2197 * Memory mapped I/O access - attempt to patch the instruction
2198 */
2199 case VINF_PATM_HC_MMIO_PATCH_READ:
2200 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2201 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2202 if (VBOX_FAILURE(rc))
2203 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2204 break;
2205
2206 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2207 AssertFailed(); /* not yet implemented. */
2208 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2209 break;
2210
2211 /*
2212 * Conflict or out of page tables.
2213 *
2214 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2215 * do here is to execute the pending forced actions.
2216 */
2217 case VINF_PGM_SYNC_CR3:
2218 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2219 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2220 rc = VINF_SUCCESS;
2221 break;
2222
2223 /*
2224 * Paging mode change.
2225 */
2226 case VINF_PGM_CHANGE_MODE:
2227 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2228 if (VBOX_SUCCESS(rc))
2229 rc = VINF_EM_RESCHEDULE;
2230 break;
2231
2232 /*
2233 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2234 */
2235 case VINF_CSAM_PENDING_ACTION:
2236 rc = VINF_SUCCESS;
2237 break;
2238
2239 /*
2240 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2241 */
2242 case VINF_EM_RAW_INTERRUPT_PENDING:
2243 case VINF_EM_RAW_RING_SWITCH_INT:
2244 Assert(TRPMHasTrap(pVM));
2245 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2246
2247 if (TRPMHasTrap(pVM))
2248 {
2249 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2250 uint8_t u8Interrupt = TRPMGetTrapNo(pVM);
2251 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2252 {
2253 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2254 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2255 /* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2256 }
2257 }
2258 rc = VINF_EM_RESCHEDULE_REM;
2259 break;
2260
2261 /*
2262 * Other ring switch types.
2263 */
2264 case VINF_EM_RAW_RING_SWITCH:
2265 rc = emR3RawRingSwitch(pVM);
2266 break;
2267
2268 /*
2269 * REMGCNotifyInvalidatePage() failed because of overflow.
2270 */
2271 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2272 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2273 REMR3ReplayInvalidatedPages(pVM);
2274 rc = VINF_SUCCESS;
2275 break;
2276
2277 /*
2278 * I/O Port access - emulate the instruction.
2279 */
2280 case VINF_IOM_HC_IOPORT_READ:
2281 case VINF_IOM_HC_IOPORT_WRITE:
2282 rc = emR3RawExecuteIOInstruction(pVM);
2283 break;
2284
2285 /*
2286 * Memory mapped I/O access - emulate the instruction.
2287 */
2288 case VINF_IOM_HC_MMIO_READ:
2289 case VINF_IOM_HC_MMIO_WRITE:
2290 case VINF_IOM_HC_MMIO_READ_WRITE:
2291 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2292 break;
2293
2294 /*
2295 * Execute instruction.
2296 */
2297 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2298 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2299 break;
2300 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2301 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2302 break;
2303 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2304 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2305 break;
2306 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2307 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2308 break;
2309 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2310 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2311 break;
2312
2313 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2314 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2315 rc = emR3RawPrivileged(pVM);
2316 break;
2317
2318 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2319 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2320 break;
2321
2322 case VINF_EM_RAW_EMULATE_INSTR:
2323 case VINF_PATCH_EMULATE_INSTR:
2324 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2325 break;
2326
2327 /*
2328 * Stale selector and iret traps => REM.
2329 */
2330 case VINF_EM_RAW_STALE_SELECTOR:
2331 case VINF_EM_RAW_IRET_TRAP:
2332 /* We will not go to the recompiler if EIP points to patch code. */
2333 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2334 {
2335 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2336 }
2337 LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2338 rc = VINF_EM_RESCHEDULE_REM;
2339 break;
2340
2341 /*
2342 * Up a level.
2343 */
2344 case VINF_EM_TERMINATE:
2345 case VINF_EM_OFF:
2346 case VINF_EM_RESET:
2347 case VINF_EM_SUSPEND:
2348 case VINF_EM_HALT:
2349 case VINF_EM_RESUME:
2350 case VINF_EM_RESCHEDULE:
2351 case VINF_EM_RESCHEDULE_REM:
2352 break;
2353
2354 /*
2355 * Up a level and invoke the debugger.
2356 */
2357 case VINF_EM_DBG_STEPPED:
2358 case VINF_EM_DBG_BREAKPOINT:
2359 case VINF_EM_DBG_STEP:
2360 case VINF_EM_DBG_HYPER_ASSERTION:
2361 case VINF_EM_DBG_HYPER_BREAKPOINT:
2362 case VINF_EM_DBG_HYPER_STEPPED:
2363 case VINF_EM_DBG_STOP:
2364 break;
2365
2366 /*
2367 * Up a level, dump and debug.
2368 */
2369 case VERR_TRPM_DONT_PANIC:
2370 case VERR_TRPM_PANIC:
2371 break;
2372
2373 case VERR_VMX_INVALID_VMCS_FIELD:
2374 case VERR_VMX_INVALID_VMCS_PTR:
2375 case VERR_VMX_INVALID_VMXON_PTR:
2376 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2377 case VERR_VMX_UNEXPECTED_EXCEPTION:
2378 case VERR_VMX_UNEXPECTED_EXIT_CODE:
2379 case VERR_VMX_INVALID_GUEST_STATE:
2380 HWACCMR3CheckError(pVM, rc);
2381 break;
2382 /*
2383 * Anything which is not known to us means an internal error
2384 * and the termination of the VM!
2385 */
2386 default:
2387 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2388 break;
2389 }
2390 return rc;
2391}
2392
2393
2394/**
2395 * Check for pending raw actions
2396 *
2397 * @returns VBox status code.
2398 * @param pVM The VM to operate on.
2399 */
2400VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2401{
2402 return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2403}
2404
2405
2406/**
2407 * Process raw-mode specific forced actions.
2408 *
2409 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2410 *
2411 * @returns VBox status code.
2412 * Only the normal success/failure stuff, no VINF_EM_*.
2413 * @param pVM The VM handle.
2414 * @param pCtx The guest CPUM register context.
2415 */
2416static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2417{
2418 /*
2419 * Note that the order is *vitally* important!
2420 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2421 */
2422
2423
2424 /*
2425 * Sync selector tables.
2426 */
2427 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2428 {
2429 int rc = SELMR3UpdateFromCPUM(pVM);
2430 if (VBOX_FAILURE(rc))
2431 return rc;
2432 }
2433
2434 /*
2435 * Sync IDT.
2436 */
2437 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2438 {
2439 int rc = TRPMR3SyncIDT(pVM);
2440 if (VBOX_FAILURE(rc))
2441 return rc;
2442 }
2443
2444 /*
2445 * Sync TSS.
2446 */
2447 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2448 {
2449 int rc = SELMR3SyncTSS(pVM);
2450 if (VBOX_FAILURE(rc))
2451 return rc;
2452 }
2453
2454 /*
2455 * Sync page directory.
2456 */
2457 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2458 {
2459 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2460 if (VBOX_FAILURE(rc))
2461 return rc;
2462
2463 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2464
2465 /* Prefetch pages for EIP and ESP */
2466 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2467 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2468 if (rc == VINF_SUCCESS)
2469 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2470 if (rc != VINF_SUCCESS)
2471 {
2472 if (rc != VINF_PGM_SYNC_CR3)
2473 return rc;
2474 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2475 if (VBOX_FAILURE(rc))
2476 return rc;
2477 }
2478 /** @todo maybe prefetch the supervisor stack page as well */
2479 }
2480
2481 /*
2482 * Allocate handy pages (just in case the above actions have consumed some pages).
2483 */
2484 if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2485 {
2486 int rc = PGMR3PhysAllocateHandyPages(pVM);
2487 if (VBOX_FAILURE(rc))
2488 return rc;
2489 }
2490
2491 return VINF_SUCCESS;
2492}
2493
2494
2495/**
2496 * Executes raw code.
2497 *
2498 * This function contains the raw-mode version of the inner
2499 * execution loop (the outer loop being in EMR3ExecuteVM()).
2500 *
2501 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2502 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2503 *
2504 * @param pVM VM handle.
2505 * @param pfFFDone Where to store an indicator telling whether or not
2506 * FFs were done before returning.
2507 */
2508static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2509{
2510 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2511
2512 int rc = VERR_INTERNAL_ERROR;
2513 PCPUMCTX pCtx = pVM->em.s.pCtx;
2514 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2515 pVM->em.s.fForceRAW = false;
2516 *pfFFDone = false;
2517
2518
2519 /*
2520 *
2521 * Spin till we get a forced action or raw mode status code resulting in
2522 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2523 *
2524 */
2525 for (;;)
2526 {
2527 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2528
2529 /*
2530 * Check various preconditions.
2531 */
2532#ifdef VBOX_STRICT
2533 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2534 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2535 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2536 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2537 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2538 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2539 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2540 {
2541 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2542 return VERR_INTERNAL_ERROR;
2543 }
2544#endif /* VBOX_STRICT */
2545
2546 /*
2547 * Process high priority pre-execution raw-mode FFs.
2548 */
2549 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2550 {
2551 rc = emR3RawForcedActions(pVM, pCtx);
2552 if (VBOX_FAILURE(rc))
2553 break;
2554 }
2555
2556 /*
2557 * If we're going to execute ring-0 code, the guest state needs to
2558 * be modified a bit and some of the state components (IF, SS/CS RPL,
2559 * and perhaps EIP) needs to be stored with PATM.
2560 */
2561 rc = CPUMRawEnter(pVM, NULL);
2562 if (rc != VINF_SUCCESS)
2563 {
2564 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2565 break;
2566 }
2567
2568 /*
2569 * Scan code before executing it. Don't bother with user mode or V86 code
2570 */
2571 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2572 && !pCtx->eflags.Bits.u1VM
2573 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2574 {
2575 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2576 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2577 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2578 }
2579
2580#ifdef LOG_ENABLED
2581 /*
2582 * Log important stuff before entering GC.
2583 */
2584 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2585 if (pCtx->eflags.Bits.u1VM)
2586 Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2587 else if ((pCtx->ss & X86_SEL_RPL) == 1)
2588 {
2589 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2590 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2591 }
2592 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2593 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2594#endif /* LOG_ENABLED */
2595
2596
2597
2598 /*
2599 * Execute the code.
2600 */
2601 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2602 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2603 VMMR3Unlock(pVM);
2604 rc = VMMR3RawRunGC(pVM);
2605 VMMR3Lock(pVM);
2606 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2607 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2608
2609 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2610 LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2611
2612
2613
2614 /*
2615 * Restore the real CPU state and deal with high priority post
2616 * execution FFs before doing anything else.
2617 */
2618 rc = CPUMRawLeave(pVM, NULL, rc);
2619 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2620 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2621 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2622
2623#ifdef VBOX_STRICT
2624 /*
2625 * Assert TSS consistency & rc vs patch code.
2626 */
2627 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2628 && EMIsRawRing0Enabled(pVM))
2629 SELMR3CheckTSS(pVM);
2630 switch (rc)
2631 {
2632 case VINF_SUCCESS:
2633 case VINF_EM_RAW_INTERRUPT:
2634 case VINF_PATM_PATCH_TRAP_PF:
2635 case VINF_PATM_PATCH_TRAP_GP:
2636 case VINF_PATM_PATCH_INT3:
2637 case VINF_PATM_CHECK_PATCH_PAGE:
2638 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2639 case VINF_EM_RAW_GUEST_TRAP:
2640 case VINF_EM_RESCHEDULE_RAW:
2641 break;
2642
2643 default:
2644 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2645 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VRv for reason %Vrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2646 break;
2647 }
2648 /*
2649 * Let's go paranoid!
2650 */
2651 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2652 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2653 {
2654 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2655 return VERR_INTERNAL_ERROR;
2656 }
2657#endif /* VBOX_STRICT */
2658
2659 /*
2660 * Process the returned status code.
2661 */
2662 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2663 {
2664 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2665 break;
2666 }
2667 rc = emR3RawHandleRC(pVM, pCtx, rc);
2668 if (rc != VINF_SUCCESS)
2669 {
2670 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2671 if (rc != VINF_SUCCESS)
2672 {
2673 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2674 break;
2675 }
2676 }
2677
2678 /*
2679 * Check and execute forced actions.
2680 */
2681#ifdef VBOX_HIGH_RES_TIMERS_HACK
2682 TMTimerPoll(pVM);
2683#endif
2684 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2685 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2686 {
2687 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
2688
2689 STAM_REL_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2690 rc = emR3ForcedActions(pVM, rc);
2691 STAM_REL_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2692 if ( rc != VINF_SUCCESS
2693 && rc != VINF_EM_RESCHEDULE_RAW)
2694 {
2695 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2696 if (rc != VINF_SUCCESS)
2697 {
2698 *pfFFDone = true;
2699 break;
2700 }
2701 }
2702 }
2703 }
2704
2705 /*
2706 * Return to outer loop.
2707 */
2708#if defined(LOG_ENABLED) && defined(DEBUG)
2709 RTLogFlush(NULL);
2710#endif
2711 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2712 return rc;
2713}
2714
2715
2716/**
2717 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2718 *
2719 * This function contains the raw-mode version of the inner
2720 * execution loop (the outer loop being in EMR3ExecuteVM()).
2721 *
2722 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2723 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2724 *
2725 * @param pVM VM handle.
2726 * @param pfFFDone Where to store an indicator telling whether or not
2727 * FFs were done before returning.
2728 */
2729static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2730{
2731 int rc = VERR_INTERNAL_ERROR;
2732 PCPUMCTX pCtx = pVM->em.s.pCtx;
2733
2734 LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%VGv)\n", pCtx->cs, pCtx->rip));
2735 *pfFFDone = false;
2736
2737 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2738
2739 /*
2740 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2741 */
2742 for (;;)
2743 {
2744 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2745
2746 /*
2747 * Check various preconditions.
2748 */
2749 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2750
2751 /*
2752 * Process high priority pre-execution raw-mode FFs.
2753 */
2754 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2755 {
2756 rc = emR3RawForcedActions(pVM, pCtx);
2757 if (VBOX_FAILURE(rc))
2758 break;
2759 }
2760
2761#ifdef LOG_ENABLED
2762 /*
2763 * Log important stuff before entering GC.
2764 */
2765 if (TRPMHasTrap(pVM))
2766 Log(("Pending hardware interrupt=0x%x cs:eip=%04X:%VGv\n", TRPMGetTrapNo(pVM), pCtx->cs, pCtx->rip));
2767
2768 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2769 if (pCtx->eflags.Bits.u1VM)
2770 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2771 else if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2772 Log(("HWR%d: %04X:%VGv ESP=%VGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2773 else
2774 Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2775#endif /* LOG_ENABLED */
2776
2777 /*
2778 * Execute the code.
2779 */
2780 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2781 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2782 VMMR3Unlock(pVM);
2783 rc = VMMR3HwAccRunGC(pVM);
2784 VMMR3Lock(pVM);
2785 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2786
2787 /*
2788 * Deal with high priority post execution FFs before doing anything else.
2789 */
2790 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2791 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2792 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2793
2794 /*
2795 * Process the returned status code.
2796 */
2797 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2798 break;
2799
2800 rc = emR3RawHandleRC(pVM, pCtx, rc);
2801 if (rc != VINF_SUCCESS)
2802 break;
2803
2804 /*
2805 * Check and execute forced actions.
2806 */
2807#ifdef VBOX_HIGH_RES_TIMERS_HACK
2808 TMTimerPoll(pVM);
2809#endif
2810 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2811 {
2812 rc = emR3ForcedActions(pVM, rc);
2813 if ( rc != VINF_SUCCESS
2814 && rc != VINF_EM_RESCHEDULE_HWACC)
2815 {
2816 *pfFFDone = true;
2817 break;
2818 }
2819 }
2820 }
2821 /*
2822 * Return to outer loop.
2823 */
2824#if defined(LOG_ENABLED) && defined(DEBUG)
2825 RTLogFlush(NULL);
2826#endif
2827 return rc;
2828}
2829
2830
2831/**
2832 * Decides whether to execute RAW, HWACC or REM.
2833 *
2834 * @returns new EM state
2835 * @param pVM The VM.
2836 * @param pCtx The CPU context.
2837 */
2838DECLINLINE(EMSTATE) emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2839{
2840 /*
2841 * When forcing raw-mode execution, things are simple.
2842 */
2843 if (pVM->em.s.fForceRAW)
2844 return EMSTATE_RAW;
2845
2846 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2847 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2848 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2849
2850 X86EFLAGS EFlags = pCtx->eflags;
2851 if (HWACCMIsEnabled(pVM))
2852 {
2853 /* Hardware accelerated raw-mode:
2854 *
2855 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2856 */
2857 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2858 return EMSTATE_HWACC;
2859
2860 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
2861 * off monitoring features essential for raw mode! */
2862 return EMSTATE_REM;
2863 }
2864
2865 /*
2866 * Standard raw-mode:
2867 *
2868 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2869 * or 32 bits protected mode ring 0 code
2870 *
2871 * The tests are ordered by the likelyhood of being true during normal execution.
2872 */
2873 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2874 {
2875 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2876 return EMSTATE_REM;
2877 }
2878
2879#ifndef VBOX_RAW_V86
2880 if (EFlags.u32 & X86_EFL_VM) {
2881 Log2(("raw mode refused: VM_MASK\n"));
2882 return EMSTATE_REM;
2883 }
2884#endif
2885
2886 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2887 uint32_t u32CR0 = pCtx->cr0;
2888 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2889 {
2890 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2891 return EMSTATE_REM;
2892 }
2893
2894 if (pCtx->cr4 & X86_CR4_PAE)
2895 {
2896 uint32_t u32Dummy, u32Features;
2897
2898 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2899 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2900 return EMSTATE_REM;
2901 }
2902
2903 unsigned uSS = pCtx->ss;
2904 if ( pCtx->eflags.Bits.u1VM
2905 || (uSS & X86_SEL_RPL) == 3)
2906 {
2907 if (!EMIsRawRing3Enabled(pVM))
2908 return EMSTATE_REM;
2909
2910 if (!(EFlags.u32 & X86_EFL_IF))
2911 {
2912 Log2(("raw mode refused: IF (RawR3)\n"));
2913 return EMSTATE_REM;
2914 }
2915
2916 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2917 {
2918 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2919 return EMSTATE_REM;
2920 }
2921 }
2922 else
2923 {
2924 if (!EMIsRawRing0Enabled(pVM))
2925 return EMSTATE_REM;
2926
2927 /* Only ring 0 supervisor code. */
2928 if ((uSS & X86_SEL_RPL) != 0)
2929 {
2930 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2931 return EMSTATE_REM;
2932 }
2933
2934 // Let's start with pure 32 bits ring 0 code first
2935 /** @todo What's pure 32-bit mode? flat? */
2936 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2937 || !(pCtx->csHid.Attr.n.u1DefBig))
2938 {
2939 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2940 return EMSTATE_REM;
2941 }
2942
2943 /* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2944 if (!(u32CR0 & X86_CR0_WP))
2945 {
2946 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2947 return EMSTATE_REM;
2948 }
2949
2950 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2951 {
2952 Log2(("raw r0 mode forced: patch code\n"));
2953 return EMSTATE_RAW;
2954 }
2955
2956#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2957 if (!(EFlags.u32 & X86_EFL_IF))
2958 {
2959 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2960 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2961 return EMSTATE_REM;
2962 }
2963#endif
2964
2965 /** @todo still necessary??? */
2966 if (EFlags.Bits.u2IOPL != 0)
2967 {
2968 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2969 return EMSTATE_REM;
2970 }
2971 }
2972
2973 Assert(PGMPhysIsA20Enabled(pVM));
2974 return EMSTATE_RAW;
2975}
2976
2977
2978/**
2979 * Executes all high priority post execution force actions.
2980 *
2981 * @returns rc or a fatal status code.
2982 *
2983 * @param pVM VM handle.
2984 * @param rc The current rc.
2985 */
2986static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2987{
2988 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2989 PDMR3CritSectFF(pVM);
2990
2991 if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2992 CSAMR3DoPendingAction(pVM);
2993
2994 return rc;
2995}
2996
2997
2998/**
2999 * Executes all pending forced actions.
3000 *
3001 * Forced actions can cause execution delays and execution
3002 * rescheduling. The first we deal with using action priority, so
3003 * that for instance pending timers aren't scheduled and ran until
3004 * right before execution. The rescheduling we deal with using
3005 * return codes. The same goes for VM termination, only in that case
3006 * we exit everything.
3007 *
3008 * @returns VBox status code of equal or greater importance/severity than rc.
3009 * The most important ones are: VINF_EM_RESCHEDULE,
3010 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
3011 *
3012 * @param pVM VM handle.
3013 * @param rc The current rc.
3014 *
3015 */
3016static int emR3ForcedActions(PVM pVM, int rc)
3017{
3018 STAM_REL_PROFILE_START(&pVM->em.s.StatForcedActions, a);
3019#ifdef VBOX_STRICT
3020 int rcIrq = VINF_SUCCESS;
3021#endif
3022 int rc2;
3023#define UPDATE_RC() \
3024 do { \
3025 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
3026 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
3027 break; \
3028 if (!rc || rc2 < rc) \
3029 rc = rc2; \
3030 } while (0)
3031
3032 /*
3033 * Post execution chunk first.
3034 */
3035 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
3036 {
3037 /*
3038 * Termination request.
3039 */
3040 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3041 {
3042 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3043 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3044 return VINF_EM_TERMINATE;
3045 }
3046
3047 /*
3048 * Debugger Facility polling.
3049 */
3050 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3051 {
3052 rc2 = DBGFR3VMMForcedAction(pVM);
3053 UPDATE_RC();
3054 }
3055
3056 /*
3057 * Postponed reset request.
3058 */
3059 if (VM_FF_ISSET(pVM, VM_FF_RESET))
3060 {
3061 rc2 = VMR3Reset(pVM);
3062 UPDATE_RC();
3063 VM_FF_CLEAR(pVM, VM_FF_RESET);
3064 }
3065
3066 /*
3067 * CSAM page scanning.
3068 */
3069 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3070 {
3071 PCPUMCTX pCtx = pVM->em.s.pCtx;
3072
3073 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3074 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3075
3076 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3077 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3078 }
3079
3080 /* check that we got them all */
3081 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
3082 }
3083
3084 /*
3085 * Normal priority then.
3086 * (Executed in no particular order.)
3087 */
3088 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3089 {
3090 /*
3091 * PDM Queues are pending.
3092 */
3093 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3094 PDMR3QueueFlushAll(pVM);
3095
3096 /*
3097 * PDM DMA transfers are pending.
3098 */
3099 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3100 PDMR3DmaRun(pVM);
3101
3102 /*
3103 * Requests from other threads.
3104 */
3105 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3106 {
3107 rc2 = VMR3ReqProcessU(pVM->pUVM);
3108 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
3109 {
3110 Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3111 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3112 return rc2;
3113 }
3114 UPDATE_RC();
3115 }
3116
3117 /* Replay the handler notification changes. */
3118 if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3119 REMR3ReplayHandlerNotifications(pVM);
3120
3121 /* check that we got them all */
3122 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY)));
3123 }
3124
3125 /*
3126 * Execute polling function ever so often.
3127 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING "SOON"!
3128 */
3129 static unsigned cLast = 0;
3130 if (!((++cLast) % 4))
3131 PDMR3Poll(pVM);
3132
3133 /*
3134 * High priority pre execution chunk last.
3135 * (Executed in ascending priority order.)
3136 */
3137 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3138 {
3139 /*
3140 * Timers before interrupts.
3141 */
3142 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3143 TMR3TimerQueuesDo(pVM);
3144
3145 /*
3146 * The instruction following an emulated STI should *always* be executed!
3147 */
3148 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3149 {
3150 Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3151 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3152 {
3153 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3154 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3155 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3156 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3157 */
3158 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3159 }
3160 if (HWACCMR3IsActive(pVM))
3161 rc2 = VINF_EM_RESCHEDULE_HWACC;
3162 else
3163 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3164
3165 UPDATE_RC();
3166 }
3167
3168 /*
3169 * Interrupts.
3170 */
3171 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3172 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3173 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3174 && PATMAreInterruptsEnabled(pVM)
3175 && !HWACCMR3IsEventPending(pVM))
3176 {
3177 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3178 {
3179 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3180 /** @todo this really isn't nice, should properly handle this */
3181 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3182#ifdef VBOX_STRICT
3183 rcIrq = rc2;
3184#endif
3185 UPDATE_RC();
3186 }
3187 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3188 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3189 {
3190 rc2 = VINF_EM_RESCHEDULE_REM;
3191 UPDATE_RC();
3192 }
3193 }
3194
3195 /*
3196 * Allocate handy pages.
3197 */
3198 if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3199 {
3200 rc2 = PGMR3PhysAllocateHandyPages(pVM);
3201 UPDATE_RC();
3202 }
3203
3204 /*
3205 * Debugger Facility request.
3206 */
3207 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3208 {
3209 rc2 = DBGFR3VMMForcedAction(pVM);
3210 UPDATE_RC();
3211 }
3212
3213 /*
3214 * Termination request.
3215 */
3216 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3217 {
3218 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3219 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3220 return VINF_EM_TERMINATE;
3221 }
3222
3223#ifdef DEBUG
3224 /*
3225 * Debug, pause the VM.
3226 */
3227 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3228 {
3229 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3230 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3231 return VINF_EM_SUSPEND;
3232 }
3233
3234#endif
3235 /* check that we got them all */
3236 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS | VM_FF_PGM_NEED_HANDY_PAGES)));
3237 }
3238
3239#undef UPDATE_RC
3240 Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3241 STAM_REL_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3242 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3243 return rc;
3244}
3245
3246
3247/**
3248 * Execute VM.
3249 *
3250 * This function is the main loop of the VM. The emulation thread
3251 * calls this function when the VM has been successfully constructed
3252 * and we're ready for executing the VM.
3253 *
3254 * Returning from this function means that the VM is turned off or
3255 * suspended (state already saved) and deconstruction in next in line.
3256 *
3257 * All interaction from other thread are done using forced actions
3258 * and signaling of the wait object.
3259 *
3260 * @returns VBox status code.
3261 * @param pVM The VM to operate on.
3262 */
3263VMMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3264{
3265 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3266 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3267 VM_ASSERT_EMT(pVM);
3268 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3269
3270 VMMR3Lock(pVM);
3271
3272 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3273 if (rc == 0)
3274 {
3275 /*
3276 * Start the virtual time.
3277 */
3278 rc = TMVirtualResume(pVM);
3279 Assert(rc == VINF_SUCCESS);
3280 rc = TMCpuTickResume(pVM);
3281 Assert(rc == VINF_SUCCESS);
3282
3283 /*
3284 * The Outer Main Loop.
3285 */
3286 bool fFFDone = false;
3287 rc = VINF_EM_RESCHEDULE;
3288 pVM->em.s.enmState = EMSTATE_REM;
3289 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3290 for (;;)
3291 {
3292 /*
3293 * Before we can schedule anything (we're here because
3294 * scheduling is required) we must service any pending
3295 * forced actions to avoid any pending action causing
3296 * immediate rescheduling upon entering an inner loop
3297 *
3298 * Do forced actions.
3299 */
3300 if ( !fFFDone
3301 && rc != VINF_EM_TERMINATE
3302 && rc != VINF_EM_OFF
3303 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3304 {
3305 rc = emR3ForcedActions(pVM, rc);
3306 if ( ( rc == VINF_EM_RESCHEDULE_REM
3307 || rc == VINF_EM_RESCHEDULE_HWACC)
3308 && pVM->em.s.fForceRAW)
3309 rc = VINF_EM_RESCHEDULE_RAW;
3310 }
3311 else if (fFFDone)
3312 fFFDone = false;
3313
3314 /*
3315 * Now what to do?
3316 */
3317 Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3318 switch (rc)
3319 {
3320 /*
3321 * Keep doing what we're currently doing.
3322 */
3323 case VINF_SUCCESS:
3324 break;
3325
3326 /*
3327 * Reschedule - to raw-mode execution.
3328 */
3329 case VINF_EM_RESCHEDULE_RAW:
3330 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3331 pVM->em.s.enmState = EMSTATE_RAW;
3332 break;
3333
3334 /*
3335 * Reschedule - to hardware accelerated raw-mode execution.
3336 */
3337 case VINF_EM_RESCHEDULE_HWACC:
3338 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3339 Assert(!pVM->em.s.fForceRAW);
3340 pVM->em.s.enmState = EMSTATE_HWACC;
3341 break;
3342
3343 /*
3344 * Reschedule - to recompiled execution.
3345 */
3346 case VINF_EM_RESCHEDULE_REM:
3347 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3348 pVM->em.s.enmState = EMSTATE_REM;
3349 break;
3350
3351#ifdef VBOX_WITH_VMI
3352 /*
3353 * Reschedule - parav call.
3354 */
3355 case VINF_EM_RESCHEDULE_PARAV:
3356 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVM->em.s.enmState, EMSTATE_PARAV));
3357 pVM->em.s.enmState = EMSTATE_PARAV;
3358 break;
3359#endif
3360
3361 /*
3362 * Resume.
3363 */
3364 case VINF_EM_RESUME:
3365 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3366 /* fall through and get scheduled. */
3367
3368 /*
3369 * Reschedule.
3370 */
3371 case VINF_EM_RESCHEDULE:
3372 {
3373 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3374 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3375 pVM->em.s.enmState = enmState;
3376 break;
3377 }
3378
3379 /*
3380 * Halted.
3381 */
3382 case VINF_EM_HALT:
3383 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3384 pVM->em.s.enmState = EMSTATE_HALTED;
3385 break;
3386
3387 /*
3388 * Suspend.
3389 */
3390 case VINF_EM_SUSPEND:
3391 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3392 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3393 break;
3394
3395 /*
3396 * Reset.
3397 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3398 */
3399 case VINF_EM_RESET:
3400 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3401 pVM->em.s.enmState = EMSTATE_REM;
3402 break;
3403
3404 /*
3405 * Power Off.
3406 */
3407 case VINF_EM_OFF:
3408 pVM->em.s.enmState = EMSTATE_TERMINATING;
3409 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3410 TMVirtualPause(pVM);
3411 TMCpuTickPause(pVM);
3412 VMMR3Unlock(pVM);
3413 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3414 return rc;
3415
3416 /*
3417 * Terminate the VM.
3418 */
3419 case VINF_EM_TERMINATE:
3420 pVM->em.s.enmState = EMSTATE_TERMINATING;
3421 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3422 TMVirtualPause(pVM);
3423 TMCpuTickPause(pVM);
3424 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3425 return rc;
3426
3427 /*
3428 * Guest debug events.
3429 */
3430 case VINF_EM_DBG_STEPPED:
3431 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3432 case VINF_EM_DBG_STOP:
3433 case VINF_EM_DBG_BREAKPOINT:
3434 case VINF_EM_DBG_STEP:
3435 if (pVM->em.s.enmState == EMSTATE_RAW)
3436 {
3437 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3438 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3439 }
3440 else
3441 {
3442 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3443 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3444 }
3445 break;
3446
3447 /*
3448 * Hypervisor debug events.
3449 */
3450 case VINF_EM_DBG_HYPER_STEPPED:
3451 case VINF_EM_DBG_HYPER_BREAKPOINT:
3452 case VINF_EM_DBG_HYPER_ASSERTION:
3453 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3454 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3455 break;
3456
3457 /*
3458 * Any error code showing up here other than the ones we
3459 * know and process above are considered to be FATAL.
3460 *
3461 * Unknown warnings and informational status codes are also
3462 * included in this.
3463 */
3464 default:
3465 if (VBOX_SUCCESS(rc))
3466 {
3467 AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3468 rc = VERR_EM_INTERNAL_ERROR;
3469 }
3470 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3471 Log(("EMR3ExecuteVM returns %d\n", rc));
3472 break;
3473 }
3474
3475
3476 /*
3477 * Any waiters can now be woken up
3478 */
3479 VMMR3Unlock(pVM);
3480 VMMR3Lock(pVM);
3481
3482 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3483 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3484
3485 /*
3486 * Act on the state.
3487 */
3488 switch (pVM->em.s.enmState)
3489 {
3490 /*
3491 * Execute raw.
3492 */
3493 case EMSTATE_RAW:
3494 rc = emR3RawExecute(pVM, &fFFDone);
3495 break;
3496
3497 /*
3498 * Execute hardware accelerated raw.
3499 */
3500 case EMSTATE_HWACC:
3501 rc = emR3HwAccExecute(pVM, &fFFDone);
3502 break;
3503
3504 /*
3505 * Execute recompiled.
3506 */
3507 case EMSTATE_REM:
3508 rc = emR3RemExecute(pVM, &fFFDone);
3509 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3510 break;
3511
3512#ifdef VBOX_WITH_VMI
3513 /*
3514 * Execute PARAV function.
3515 */
3516 case EMSTATE_PARAV:
3517 rc = PARAVCallFunction(pVM);
3518 pVM->em.s.enmState = EMSTATE_REM;
3519 break;
3520#endif
3521
3522 /*
3523 * hlt - execution halted until interrupt.
3524 */
3525 case EMSTATE_HALTED:
3526 {
3527 STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3528 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3529 STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3530 break;
3531 }
3532
3533 /*
3534 * Suspended - return to VM.cpp.
3535 */
3536 case EMSTATE_SUSPENDED:
3537 TMVirtualPause(pVM);
3538 TMCpuTickPause(pVM);
3539 VMMR3Unlock(pVM);
3540 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3541 return VINF_EM_SUSPEND;
3542
3543 /*
3544 * Debugging in the guest.
3545 */
3546 case EMSTATE_DEBUG_GUEST_REM:
3547 case EMSTATE_DEBUG_GUEST_RAW:
3548 TMVirtualPause(pVM);
3549 TMCpuTickPause(pVM);
3550 rc = emR3Debug(pVM, rc);
3551 TMVirtualResume(pVM);
3552 TMCpuTickResume(pVM);
3553 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3554 break;
3555
3556 /*
3557 * Debugging in the hypervisor.
3558 */
3559 case EMSTATE_DEBUG_HYPER:
3560 {
3561 TMVirtualPause(pVM);
3562 TMCpuTickPause(pVM);
3563 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3564
3565 rc = emR3Debug(pVM, rc);
3566 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3567 if (rc != VINF_SUCCESS)
3568 {
3569 /* switch to guru meditation mode */
3570 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3571 VMMR3FatalDump(pVM, rc);
3572 return rc;
3573 }
3574
3575 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3576 TMVirtualResume(pVM);
3577 TMCpuTickResume(pVM);
3578 break;
3579 }
3580
3581 /*
3582 * Guru meditation takes place in the debugger.
3583 */
3584 case EMSTATE_GURU_MEDITATION:
3585 {
3586 TMVirtualPause(pVM);
3587 TMCpuTickPause(pVM);
3588 VMMR3FatalDump(pVM, rc);
3589 emR3Debug(pVM, rc);
3590 VMMR3Unlock(pVM);
3591 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3592 return rc;
3593 }
3594
3595 /*
3596 * The states we don't expect here.
3597 */
3598 case EMSTATE_NONE:
3599 case EMSTATE_TERMINATING:
3600 default:
3601 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3602 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3603 TMVirtualPause(pVM);
3604 TMCpuTickPause(pVM);
3605 VMMR3Unlock(pVM);
3606 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3607 return VERR_EM_INTERNAL_ERROR;
3608 }
3609 } /* The Outer Main Loop */
3610 }
3611 else
3612 {
3613 /*
3614 * Fatal error.
3615 */
3616 LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3617 TMVirtualPause(pVM);
3618 TMCpuTickPause(pVM);
3619 VMMR3FatalDump(pVM, rc);
3620 emR3Debug(pVM, rc);
3621 VMMR3Unlock(pVM);
3622 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3623 /** @todo change the VM state! */
3624 return rc;
3625 }
3626
3627 /* (won't ever get here). */
3628 AssertFailed();
3629}
3630
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