VirtualBox

source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 25414

Last change on this file since 25414 was 23012, checked in by vboxsync, 15 years ago

VMM,Devices,Main: VMR3ReqCall w/ RT_INDEFINITE_WAIT -> VMR3ReqCallWait.
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1/* $Id: DBGFDisas.cpp 23012 2009-09-14 16:38:13Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DBGF
26#include <VBox/dbgf.h>
27#include <VBox/selm.h>
28#include <VBox/mm.h>
29#include <VBox/pgm.h>
30#include <VBox/cpum.h>
31#include "DBGFInternal.h"
32#include <VBox/dis.h>
33#include <VBox/err.h>
34#include <VBox/param.h>
35#include <VBox/vm.h>
36
37#include <VBox/log.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40#include <iprt/alloca.h>
41#include <iprt/ctype.h>
42
43
44/*******************************************************************************
45* Structures and Typedefs *
46*******************************************************************************/
47/**
48 * Structure used when disassembling and instructions in DBGF.
49 * This is used so the reader function can get the stuff it needs.
50 */
51typedef struct
52{
53 /** The core structure. */
54 DISCPUSTATE Cpu;
55 /** The VM handle. */
56 PVM pVM;
57 /** The VMCPU handle. */
58 PVMCPU pVCpu;
59 /** The address space for resolving symbol. */
60 RTDBGAS hAs;
61 /** Pointer to the first byte in the segemnt. */
62 RTGCUINTPTR GCPtrSegBase;
63 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
64 RTGCUINTPTR GCPtrSegEnd;
65 /** The size of the segment minus 1. */
66 RTGCUINTPTR cbSegLimit;
67 /** The guest paging mode. */
68 PGMMODE enmMode;
69 /** Pointer to the current page - R3 Ptr. */
70 void const *pvPageR3;
71 /** Pointer to the current page - GC Ptr. */
72 RTGCPTR pvPageGC;
73 /** Pointer to the next instruction (relative to GCPtrSegBase). */
74 RTGCUINTPTR GCPtrNext;
75 /** The lock information that PGMPhysReleasePageMappingLock needs. */
76 PGMPAGEMAPLOCK PageMapLock;
77 /** Whether the PageMapLock is valid or not. */
78 bool fLocked;
79 /** 64 bits mode or not. */
80 bool f64Bits;
81} DBGFDISASSTATE, *PDBGFDISASSTATE;
82
83
84/*******************************************************************************
85* Internal Functions *
86*******************************************************************************/
87static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t *pDest, uint32_t size, void *pvUserdata);
88
89
90
91/**
92 * Calls the dissassembler with the proper reader functions and such for disa
93 *
94 * @returns VBox status code.
95 * @param pVM VM handle
96 * @param pVCpu VMCPU handle
97 * @param pSelInfo The selector info.
98 * @param enmMode The guest paging mode.
99 * @param GCPtr The GC pointer (selector offset).
100 * @param pState The disas CPU state.
101 */
102static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode, RTGCPTR GCPtr, PDBGFDISASSTATE pState)
103{
104 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
105 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
106 pState->cbSegLimit = pSelInfo->cbLimit;
107 pState->enmMode = enmMode;
108 pState->pvPageGC = 0;
109 pState->pvPageR3 = NULL;
110 pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas*. */
111 ? DBGF_AS_RC_AND_GC_GLOBAL
112 : DBGF_AS_GLOBAL;
113 pState->pVM = pVM;
114 pState->pVCpu = pVCpu;
115 pState->fLocked = false;
116 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
117 uint32_t cbInstr;
118 int rc = DISCoreOneEx(GCPtr,
119 pState->f64Bits
120 ? CPUMODE_64BIT
121 : pSelInfo->u.Raw.Gen.u1DefBig
122 ? CPUMODE_32BIT
123 : CPUMODE_16BIT,
124 dbgfR3DisasInstrRead,
125 &pState->Cpu,
126 &pState->Cpu,
127 &cbInstr);
128 if (RT_SUCCESS(rc))
129 {
130 pState->GCPtrNext = GCPtr + cbInstr;
131 return VINF_SUCCESS;
132 }
133
134 /* cleanup */
135 if (pState->fLocked)
136 {
137 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
138 pState->fLocked = false;
139 }
140 return rc;
141}
142
143
144#if 0
145/**
146 * Calls the dissassembler for disassembling the next instruction.
147 *
148 * @returns VBox status code.
149 * @param pState The disas CPU state.
150 */
151static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
152{
153 uint32_t cbInstr;
154 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
155 if (RT_SUCCESS(rc))
156 {
157 pState->GCPtrNext = GCPtr + cbInstr;
158 return VINF_SUCCESS;
159 }
160 return rc;
161}
162#endif
163
164
165/**
166 * Done with the dissassembler state, free associated resources.
167 *
168 * @param pState The disas CPU state ++.
169 */
170static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
171{
172 if (pState->fLocked)
173 {
174 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
175 pState->fLocked = false;
176 }
177}
178
179
180/**
181 * Instruction reader.
182 *
183 * @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
184 * @param PtrSrc Address to read from.
185 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
186 * @param pu8Dst Where to store the bytes.
187 * @param cbRead Number of bytes to read.
188 * @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
189 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
190 */
191static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, void *pvDisCpu)
192{
193 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
194 Assert(cbRead > 0);
195 for (;;)
196 {
197 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
198
199 /* Need to update the page translation? */
200 if ( !pState->pvPageR3
201 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
202 {
203 int rc = VINF_SUCCESS;
204
205 /* translate the address */
206 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
207 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
208 {
209 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
210 if (!pState->pvPageR3)
211 rc = VERR_INVALID_POINTER;
212 }
213 else
214 {
215 if (pState->fLocked)
216 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
217
218 if (pState->enmMode <= PGMMODE_PROTECTED)
219 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
220 else
221 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
222 pState->fLocked = RT_SUCCESS_NP(rc);
223 }
224 if (RT_FAILURE(rc))
225 {
226 pState->pvPageR3 = NULL;
227 return rc;
228 }
229 }
230
231 /* check the segemnt limit */
232 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
233 return VERR_OUT_OF_SELECTOR_BOUNDS;
234
235 /* calc how much we can read */
236 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
237 if (!pState->f64Bits)
238 {
239 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
240 if (cb > cbSeg && cbSeg)
241 cb = cbSeg;
242 }
243 if (cb > cbRead)
244 cb = cbRead;
245
246 /* read and advance */
247 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
248 cbRead -= cb;
249 if (!cbRead)
250 return VINF_SUCCESS;
251 pu8Dst += cb;
252 PtrSrc += cb;
253 }
254}
255
256
257/**
258 * @copydoc FNDISGETSYMBOL
259 */
260static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
261{
262 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
263 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
264 DBGFADDRESS Addr;
265 RTDBGSYMBOL Sym;
266 RTGCINTPTR off;
267 int rc;
268
269 if ( DIS_FMT_SEL_IS_REG(u32Sel)
270 ? DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS
271 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
272 {
273 rc = DBGFR3AddrFromSelInfoOff(pState->pVM, &Addr, pSelInfo, uAddress);
274 if (RT_SUCCESS(rc))
275 rc = DBGFR3AsSymbolByAddr(pState->pVM, pState->hAs, &Addr, &off, &Sym, NULL /*phMod*/);
276 }
277 else
278 rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
279 if (RT_SUCCESS(rc))
280 {
281 size_t cchName = strlen(Sym.szName);
282 if (cchName >= cchBuf)
283 cchName = cchBuf - 1;
284 memcpy(pszBuf, Sym.szName, cchName);
285 pszBuf[cchName] = '\0';
286
287 *poff = off;
288 }
289
290 return rc;
291}
292
293
294/**
295 * Disassembles the one instruction according to the specified flags and
296 * address, internal worker executing on the EMT of the specified virtual CPU.
297 *
298 * @returns VBox status code.
299 * @param pVM The VM handle.
300 * @param pVCpu The virtual CPU handle.
301 * @param Sel The code selector. This used to determin the 32/16 bit ness and
302 * calculation of the actual instruction address.
303 * @param pGCPtr Pointer to the variable holding the code address
304 * relative to the base of Sel.
305 * @param fFlags Flags controlling where to start and how to format.
306 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
307 * @param pszOutput Output buffer.
308 * @param cchOutput Size of the output buffer.
309 * @param pcbInstr Where to return the size of the instruction.
310 */
311static DECLCALLBACK(int)
312dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, unsigned fFlags,
313 char *pszOutput, uint32_t cchOutput, uint32_t *pcbInstr)
314{
315 VMCPU_ASSERT_EMT(pVCpu);
316 RTGCPTR GCPtr = *pGCPtr;
317
318 /*
319 * Get the Sel and GCPtr if fFlags requests that.
320 */
321 PCCPUMCTXCORE pCtxCore = NULL;
322 CPUMSELREGHID *pHiddenSel = NULL;
323 int rc;
324 if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_CURRENT_HYPER))
325 {
326 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
327 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
328 else
329 pCtxCore = CPUMGetHyperCtxCore(pVCpu);
330 Sel = pCtxCore->cs;
331 pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
332 GCPtr = pCtxCore->rip;
333 }
334
335 /*
336 * Read the selector info - assume no stale selectors and nasty stuff like that.
337 * Since the selector flags in the CPUMCTX structures aren't up to date unless
338 * we recently visited REM, we'll not search for the selector there.
339 */
340 DBGFSELINFO SelInfo;
341 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
342 bool fRealModeAddress = false;
343
344 if ( pHiddenSel
345 && CPUMAreHiddenSelRegsValid(pVM))
346 {
347 SelInfo.Sel = Sel;
348 SelInfo.SelGate = 0;
349 SelInfo.GCPtrBase = pHiddenSel->u64Base;
350 SelInfo.cbLimit = pHiddenSel->u32Limit;
351 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
352 ? DBGFSELINFO_FLAGS_LONG_MODE
353 : enmMode != PGMMODE_REAL && (!pCtxCore || !pCtxCore->eflags.Bits.u1VM)
354 ? DBGFSELINFO_FLAGS_PROT_MODE
355 : DBGFSELINFO_FLAGS_REAL_MODE;
356
357 SelInfo.u.Raw.au32[0] = 0;
358 SelInfo.u.Raw.au32[1] = 0;
359 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
360 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
361 SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
362 SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
363 SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
364 SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
365 SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
366 SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
367 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
368 }
369 else if (Sel == DBGF_SEL_FLAT)
370 {
371 SelInfo.Sel = Sel;
372 SelInfo.SelGate = 0;
373 SelInfo.GCPtrBase = 0;
374 SelInfo.cbLimit = ~0;
375 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
376 ? DBGFSELINFO_FLAGS_LONG_MODE
377 : enmMode != PGMMODE_REAL
378 ? DBGFSELINFO_FLAGS_PROT_MODE
379 : DBGFSELINFO_FLAGS_REAL_MODE;
380 SelInfo.u.Raw.au32[0] = 0;
381 SelInfo.u.Raw.au32[1] = 0;
382 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
383 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
384
385 if (CPUMAreHiddenSelRegsValid(pVM))
386 { /* Assume the current CS defines the execution mode. */
387 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
388 pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
389
390 SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
391 SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
392 SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
393 SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
394 SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
395 SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
396 }
397 else
398 {
399 SelInfo.u.Raw.Gen.u1Present = 1;
400 SelInfo.u.Raw.Gen.u1Granularity = 1;
401 SelInfo.u.Raw.Gen.u1DefBig = 1;
402 SelInfo.u.Raw.Gen.u1DescType = 1;
403 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
404 }
405 }
406 else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
407 && ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
408 || enmMode == PGMMODE_REAL) )
409 { /* V86 mode or real mode - real mode addressing */
410 SelInfo.Sel = Sel;
411 SelInfo.SelGate = 0;
412 SelInfo.GCPtrBase = Sel * 16;
413 SelInfo.cbLimit = ~0;
414 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
415 SelInfo.u.Raw.au32[0] = 0;
416 SelInfo.u.Raw.au32[1] = 0;
417 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
418 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
419 SelInfo.u.Raw.Gen.u1Present = 1;
420 SelInfo.u.Raw.Gen.u1Granularity = 1;
421 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
422 SelInfo.u.Raw.Gen.u1DescType = 1;
423 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
424 fRealModeAddress = true;
425 }
426 else
427 {
428 rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
429 if (RT_FAILURE(rc))
430 {
431 RTStrPrintf(pszOutput, cchOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
432 return rc;
433 }
434 }
435
436 /*
437 * Disassemble it.
438 */
439 DBGFDISASSTATE State;
440 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, &State);
441 if (RT_FAILURE(rc))
442 {
443 RTStrPrintf(pszOutput, cchOutput, "Disas -> %Rrc\n", rc);
444 return rc;
445 }
446
447 /*
448 * Format it.
449 */
450 char szBuf[512];
451 DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
452 DIS_FMT_FLAGS_RELATIVE_BRANCH,
453 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
454 &SelInfo);
455
456 /*
457 * Print it to the user specified buffer.
458 */
459 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
460 {
461 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
462 RTStrPrintf(pszOutput, cchOutput, "%s", szBuf);
463 else if (fRealModeAddress)
464 RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
465 else if (Sel == DBGF_SEL_FLAT)
466 {
467 if (enmMode >= PGMMODE_AMD64)
468 RTStrPrintf(pszOutput, cchOutput, "%RGv %s", GCPtr, szBuf);
469 else
470 RTStrPrintf(pszOutput, cchOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
471 }
472 else
473 {
474 if (enmMode >= PGMMODE_AMD64)
475 RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
476 else
477 RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
478 }
479 }
480 else
481 {
482 uint32_t cbBits = State.Cpu.opsize;
483 uint8_t *pau8Bits = (uint8_t *)alloca(cbBits);
484 rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
485 AssertRC(rc);
486 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
487 RTStrPrintf(pszOutput, cchOutput, "%.*Rhxs%*s %s",
488 cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
489 szBuf);
490 else if (fRealModeAddress)
491 RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %.*Rhxs%*s %s",
492 Sel, (unsigned)GCPtr,
493 cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
494 szBuf);
495 else if (Sel == DBGF_SEL_FLAT)
496 {
497 if (enmMode >= PGMMODE_AMD64)
498 RTStrPrintf(pszOutput, cchOutput, "%RGv %.*Rhxs%*s %s",
499 GCPtr,
500 cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
501 szBuf);
502 else
503 RTStrPrintf(pszOutput, cchOutput, "%08RX32 %.*Rhxs%*s %s",
504 (uint32_t)GCPtr,
505 cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
506 szBuf);
507 }
508 else
509 {
510 if (enmMode >= PGMMODE_AMD64)
511 RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %.*Rhxs%*s %s",
512 Sel, GCPtr,
513 cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
514 szBuf);
515 else
516 RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
517 Sel, (uint32_t)GCPtr,
518 cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
519 szBuf);
520 }
521 }
522
523 if (pcbInstr)
524 *pcbInstr = State.Cpu.opsize;
525
526 dbgfR3DisasInstrDone(&State);
527 return VINF_SUCCESS;
528}
529
530
531/**
532 * Disassembles the one instruction according to the specified flags and address.
533 *
534 * @returns VBox status code.
535 * @param pVM VM handle.
536 * @param idCpu The ID of virtual CPU.
537 * @param Sel The code selector. This used to determin the 32/16 bit ness and
538 * calculation of the actual instruction address.
539 * @param GCPtr The code address relative to the base of Sel.
540 * @param fFlags Flags controlling where to start and how to format.
541 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
542 * @param pszOutput Output buffer.
543 * @param cchOutput Size of the output buffer.
544 * @param pcbInstr Where to return the size of the instruction.
545 *
546 * @remarks May have to switch to the EMT of the virtual CPU in order to do
547 * address conversion.
548 */
549VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags,
550 char *pszOutput, uint32_t cchOutput, uint32_t *pcbInstr)
551{
552 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
553 AssertReturn(idCpu < pVM->cCpus, VERR_INVALID_CPU_ID);
554
555 /*
556 * Optimize the common case where we're called on the EMT of idCpu since
557 * we're using this all the time when logging.
558 */
559 int rc;
560 PVMCPU pVCpu = VMMGetCpu(pVM);
561 if ( pVCpu
562 && pVCpu->idCpu == idCpu)
563 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cchOutput, pcbInstr);
564 else
565 rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
566 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cchOutput, pcbInstr);
567 return rc;
568}
569
570
571/**
572 * Disassembles the current guest context instruction.
573 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
574 *
575 * @returns VBox status code.
576 * @param pVCpu VMCPU handle.
577 * @param pszOutput Output buffer.
578 * @param cchOutput Size of the output buffer.
579 */
580VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cchOutput)
581{
582 *pszOutput = '\0';
583 AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
584 return DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, 0, 0, DBGF_DISAS_FLAGS_CURRENT_GUEST,
585 pszOutput, cchOutput, NULL);
586}
587
588
589/**
590 * Disassembles the current guest context instruction and writes it to the log.
591 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
592 *
593 * @returns VBox status code.
594 * @param pVCpu VMCPU handle.
595 * @param pszPrefix Short prefix string to the dissassembly string. (optional)
596 */
597VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
598{
599 char szBuf[256];
600 szBuf[0] = '\0';
601 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
602 if (RT_FAILURE(rc))
603 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
604 if (pszPrefix && *pszPrefix)
605 RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
606 else
607 RTLogPrintf("%s\n", szBuf);
608 return rc;
609}
610
611
612
613/**
614 * Disassembles the specified guest context instruction and writes it to the log.
615 * Addresses will be attempted resolved to symbols.
616 *
617 * @returns VBox status code.
618 * @param pVM VM handle.
619 * @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
620 * @param Sel The code selector. This used to determin the 32/16 bit-ness and
621 * calculation of the actual instruction address.
622 * @param GCPtr The code address relative to the base of Sel.
623 */
624VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr)
625{
626 char szBuf[256];
627 szBuf[0] = '\0';
628 int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, Sel, GCPtr, 0, &szBuf[0], sizeof(szBuf), NULL);
629 if (RT_FAILURE(rc))
630 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
631 RTLogPrintf("%s\n", szBuf);
632 return rc;
633}
634
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