| 1 | /* $Id: CPUMInternal.h 16113 2009-01-21 09:08:29Z vboxsync $ */
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| 2 | /** @file
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| 3 | * CPUM - Internal header file.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 19 | * additional information or have any questions.
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| 20 | */
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| 21 |
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| 22 | #ifndef ___CPUMInternal_h
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| 23 | #define ___CPUMInternal_h
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| 24 |
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| 25 | #include <VBox/cdefs.h>
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| 26 | #include <VBox/types.h>
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| 27 | #include <VBox/x86.h>
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| 28 |
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| 29 |
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| 30 |
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| 31 | /** @defgroup grp_cpum_int Internals
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| 32 | * @ingroup grp_cpum
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| 33 | * @internal
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| 34 | * @{
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| 35 | */
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| 36 |
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| 37 | /** Flags and types for CPUM fault handlers
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| 38 | * @{ */
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| 39 | /** Type: Load DS */
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| 40 | #define CPUM_HANDLER_DS 1
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| 41 | /** Type: Load ES */
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| 42 | #define CPUM_HANDLER_ES 2
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| 43 | /** Type: Load FS */
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| 44 | #define CPUM_HANDLER_FS 3
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| 45 | /** Type: Load GS */
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| 46 | #define CPUM_HANDLER_GS 4
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| 47 | /** Type: IRET */
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| 48 | #define CPUM_HANDLER_IRET 5
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| 49 | /** Type mask. */
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| 50 | #define CPUM_HANDLER_TYPEMASK 0xff
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| 51 | /** If set EBP points to the CPUMCTXCORE that's being used. */
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| 52 | #define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
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| 53 | /** @} */
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| 54 |
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| 55 |
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| 56 | /** Use flags (CPUM::fUseFlags).
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| 57 | * (Don't forget to sync this with CPUMInternal.mac!)
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| 58 | * @{ */
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| 59 | /** Used the FPU, SSE or such stuff. */
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| 60 | #define CPUM_USED_FPU RT_BIT(0)
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| 61 | /** Used the FPU, SSE or such stuff since last we were in REM.
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| 62 | * REM syncing is clearing this, lazy FPU is setting it. */
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| 63 | #define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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| 64 | /** Host OS is using SYSENTER and we must NULL the CS. */
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| 65 | #define CPUM_USE_SYSENTER RT_BIT(2)
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| 66 | /** Host OS is using SYSENTER and we must NULL the CS. */
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| 67 | #define CPUM_USE_SYSCALL RT_BIT(3)
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| 68 | /** Debug registers are used by host and must be disabled. */
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| 69 | #define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
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| 70 | /** Enabled use of debug registers in guest context. */
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| 71 | #define CPUM_USE_DEBUG_REGS RT_BIT(5)
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| 72 | /** The XMM state was manually restored. (AMD only) */
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| 73 | #define CPUM_MANUAL_XMM_RESTORE RT_BIT(6)
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| 74 | /** Sync the FPU state on entry (32->64 switcher only). */
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| 75 | #define CPUM_SYNC_FPU_STATE RT_BIT(7)
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| 76 | /** Sync the debug state on entry (32->64 switcher only). */
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| 77 | #define CPUM_SYNC_DEBUG_STATE RT_BIT(8)
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| 78 | /** @} */
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| 79 |
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| 80 | /* Sanity check. */
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| 81 | #if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
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| 82 | # error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
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| 83 | #endif
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| 84 |
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| 85 |
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| 86 | /**
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| 87 | * The saved host CPU state.
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| 88 | *
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| 89 | * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
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| 90 | * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
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| 91 | */
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| 92 | typedef struct CPUMHOSTCTX
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| 93 | {
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| 94 | /** FPU state. (16-byte alignment)
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| 95 | * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
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| 96 | X86FXSTATE fpu;
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| 97 |
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| 98 | /** General purpose register, selectors, flags and more
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| 99 | * @{ */
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| 100 | #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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| 101 | /** General purpose register ++
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| 102 | * { */
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| 103 | //uint64_t rax; - scratch
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| 104 | uint64_t rbx;
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| 105 | //uint64_t rcx; - scratch
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| 106 | //uint64_t rdx; - scratch
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| 107 | uint64_t rdi;
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| 108 | uint64_t rsi;
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| 109 | uint64_t rbp;
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| 110 | uint64_t rsp;
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| 111 | //uint64_t r8; - scratch
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| 112 | //uint64_t r9; - scratch
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| 113 | uint64_t r10;
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| 114 | uint64_t r11;
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| 115 | uint64_t r12;
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| 116 | uint64_t r13;
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| 117 | uint64_t r14;
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| 118 | uint64_t r15;
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| 119 | //uint64_t rip; - scratch
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| 120 | uint64_t rflags;
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| 121 | #endif
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| 122 |
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| 123 | #if HC_ARCH_BITS == 32
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| 124 | //uint32_t eax; - scratch
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| 125 | uint32_t ebx;
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| 126 | //uint32_t ecx; - scratch
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| 127 | //uint32_t edx; - scratch
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| 128 | uint32_t edi;
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| 129 | uint32_t esi;
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| 130 | uint32_t ebp;
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| 131 | X86EFLAGS eflags;
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| 132 | //uint32_t eip; - scratch
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| 133 | /* lss pair! */
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| 134 | uint32_t esp;
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| 135 | #endif
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| 136 | /** @} */
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| 137 |
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| 138 | /** Selector registers
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| 139 | * @{ */
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| 140 | RTSEL ss;
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| 141 | RTSEL ssPadding;
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| 142 | RTSEL gs;
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| 143 | RTSEL gsPadding;
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| 144 | RTSEL fs;
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| 145 | RTSEL fsPadding;
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| 146 | RTSEL es;
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| 147 | RTSEL esPadding;
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| 148 | RTSEL ds;
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| 149 | RTSEL dsPadding;
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| 150 | RTSEL cs;
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| 151 | RTSEL csPadding;
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| 152 | /** @} */
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| 153 |
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| 154 | #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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| 155 | /** Control registers.
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| 156 | * @{ */
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| 157 | uint32_t cr0;
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| 158 | //uint32_t cr2; - scratch
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| 159 | uint32_t cr3;
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| 160 | uint32_t cr4;
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| 161 | /** @} */
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| 162 |
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| 163 | /** Debug registers.
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| 164 | * @{ */
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| 165 | uint32_t dr0;
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| 166 | uint32_t dr1;
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| 167 | uint32_t dr2;
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| 168 | uint32_t dr3;
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| 169 | uint32_t dr6;
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| 170 | uint32_t dr7;
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| 171 | /** @} */
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| 172 |
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| 173 | /** Global Descriptor Table register. */
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| 174 | X86XDTR32 gdtr;
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| 175 | uint16_t gdtrPadding;
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| 176 | /** Interrupt Descriptor Table register. */
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| 177 | X86XDTR32 idtr;
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| 178 | uint16_t idtrPadding;
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| 179 | /** The task register. */
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| 180 | RTSEL ldtr;
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| 181 | RTSEL ldtrPadding;
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| 182 | /** The task register. */
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| 183 | RTSEL tr;
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| 184 | RTSEL trPadding;
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| 185 | uint32_t SysEnterPadding;
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| 186 |
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| 187 | /** The sysenter msr registers.
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| 188 | * This member is not used by the hypervisor context. */
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| 189 | CPUMSYSENTER SysEnter;
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| 190 |
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| 191 | /** MSRs
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| 192 | * @{ */
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| 193 | uint64_t efer;
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| 194 | /** @} */
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| 195 |
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| 196 | /* padding to get 64byte aligned size */
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| 197 | uint8_t auPadding[16+32];
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| 198 |
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| 199 | #elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
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| 200 |
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| 201 | /** Control registers.
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| 202 | * @{ */
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| 203 | uint64_t cr0;
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| 204 | //uint64_t cr2; - scratch
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| 205 | uint64_t cr3;
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| 206 | uint64_t cr4;
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| 207 | uint64_t cr8;
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| 208 | /** @} */
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| 209 |
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| 210 | /** Debug registers.
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| 211 | * @{ */
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| 212 | uint64_t dr0;
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| 213 | uint64_t dr1;
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| 214 | uint64_t dr2;
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| 215 | uint64_t dr3;
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| 216 | uint64_t dr6;
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| 217 | uint64_t dr7;
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| 218 | /** @} */
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| 219 |
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| 220 | /** Global Descriptor Table register. */
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| 221 | X86XDTR64 gdtr;
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| 222 | uint16_t gdtrPadding;
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| 223 | /** Interrupt Descriptor Table register. */
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| 224 | X86XDTR64 idtr;
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| 225 | uint16_t idtrPadding;
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| 226 | /** The task register. */
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| 227 | RTSEL ldtr;
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| 228 | RTSEL ldtrPadding;
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| 229 | /** The task register. */
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| 230 | RTSEL tr;
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| 231 | RTSEL trPadding;
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| 232 |
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| 233 | /** MSRs
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| 234 | * @{ */
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| 235 | CPUMSYSENTER SysEnter;
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| 236 | uint64_t FSbase;
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| 237 | uint64_t GSbase;
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| 238 | uint64_t efer;
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| 239 | /** @} */
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| 240 |
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| 241 | /* padding to get 32byte aligned size */
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| 242 | # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
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| 243 | uint8_t auPadding[16];
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| 244 | # else
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| 245 | uint8_t auPadding[8+32];
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| 246 | # endif
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| 247 |
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| 248 | #else
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| 249 | # error HC_ARCH_BITS not defined
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| 250 | #endif
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| 251 | } CPUMHOSTCTX;
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| 252 | /** Pointer to the saved host CPU state. */
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| 253 | typedef CPUMHOSTCTX *PCPUMHOSTCTX;
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| 254 |
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| 255 |
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| 256 | /**
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| 257 | * CPUM Data (part of VM)
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| 258 | */
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| 259 | typedef struct CPUM
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| 260 | {
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| 261 | /**
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| 262 | * Hypervisor context.
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| 263 | * Aligned on a 64-byte boundrary.
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| 264 | */
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| 265 | CPUMCTX Hyper;
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| 266 |
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| 267 | /** Pointer to the current hypervisor core context - R3Ptr. */
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| 268 | R3PTRTYPE(PCPUMCTXCORE) pHyperCoreR3;
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| 269 | /** Pointer to the current hypervisor core context - R0Ptr. */
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| 270 | R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
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| 271 | /** Pointer to the current hypervisor core context - RCPtr. */
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| 272 | RCPTRTYPE(PCPUMCTXCORE) pHyperCoreRC;
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| 273 |
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| 274 | /* Offset from CPUM to CPUMCPU for the first CPU. */
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| 275 | uint32_t ulOffCPUMCPU;
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| 276 |
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| 277 | /** Hidden selector registers state.
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| 278 | * Valid (hw accelerated raw mode) or not (normal raw mode)
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| 279 | */
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| 280 | uint32_t fValidHiddenSelRegs;
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| 281 |
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| 282 | /** Host CPU Features - ECX */
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| 283 | struct
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| 284 | {
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| 285 | /** edx part */
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| 286 | X86CPUIDFEATEDX edx;
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| 287 | /** ecx part */
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| 288 | X86CPUIDFEATECX ecx;
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| 289 | } CPUFeatures;
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| 290 | /** Host extended CPU features. */
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| 291 | struct
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| 292 | {
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| 293 | /** edx part */
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| 294 | uint32_t edx;
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| 295 | /** ecx part */
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| 296 | uint32_t ecx;
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| 297 | } CPUFeaturesExt;
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| 298 |
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| 299 | /* CPU manufacturer. */
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| 300 | CPUMCPUVENDOR enmCPUVendor;
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| 301 |
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| 302 | /** CR4 mask */
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| 303 | struct
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| 304 | {
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| 305 | uint32_t AndMask;
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| 306 | uint32_t OrMask;
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| 307 | } CR4;
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| 308 |
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| 309 | /** Have we entered rawmode? */
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| 310 | bool fRawEntered;
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| 311 | uint8_t abPadding[3 + (HC_ARCH_BITS == 64) * 4];
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| 312 |
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| 313 | /** The standard set of CpuId leafs. */
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| 314 | CPUMCPUID aGuestCpuIdStd[6];
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| 315 | /** The extended set of CpuId leafs. */
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| 316 | CPUMCPUID aGuestCpuIdExt[10];
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| 317 | /** The centaur set of CpuId leafs. */
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| 318 | CPUMCPUID aGuestCpuIdCentaur[4];
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| 319 | /** The default set of CpuId leafs. */
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| 320 | CPUMCPUID GuestCpuIdDef;
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| 321 |
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| 322 | /** Align the next member, and thereby the structure, on a 64-byte boundrary. */
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| 323 | uint8_t abPadding2[HC_ARCH_BITS == 32 ? 60 : 48];
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| 324 |
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| 325 | /**
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| 326 | * Guest context on raw mode entry.
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| 327 | * This a debug feature, see CPUMR3SaveEntryCtx.
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| 328 | */
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| 329 | CPUMCTX GuestEntry;
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| 330 | } CPUM;
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| 331 | /** Pointer to the CPUM instance data residing in the shared VM structure. */
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| 332 | typedef CPUM *PCPUM;
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| 333 |
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| 334 | /**
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| 335 | * CPUM Data (part of VMCPU)
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| 336 | */
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| 337 | typedef struct CPUMCPU
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| 338 | {
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| 339 | /**
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| 340 | * Saved host context. Only valid while inside GC.
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| 341 | * Aligned on a 64-byte boundrary.
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| 342 | */
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| 343 | CPUMHOSTCTX Host;
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| 344 |
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| 345 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 346 | uint8_t aMagic[56];
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| 347 | uint64_t uMagic;
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| 348 | #endif
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| 349 |
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| 350 | /**
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| 351 | * Guest context.
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| 352 | * Aligned on a 64-byte boundrary.
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| 353 | */
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| 354 | CPUMCTX Guest;
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| 355 |
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| 356 | /**
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| 357 | * Guest context - misc MSRs
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| 358 | * Aligned on a 64-byte boundrary.
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| 359 | */
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| 360 | CPUMCTXMSR GuestMsr;
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| 361 |
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| 362 | /** Use flags.
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| 363 | * These flags indicates both what is to be used and what has been used.
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| 364 | */
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| 365 | uint32_t fUseFlags;
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| 366 |
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| 367 | /** Changed flags.
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| 368 | * These flags indicates to REM (and others) which important guest
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| 369 | * registers which has been changed since last time the flags were cleared.
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| 370 | * See the CPUM_CHANGED_* defines for what we keep track of.
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| 371 | */
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| 372 | uint32_t fChanged;
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| 373 |
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| 374 | /* Offset to CPUM. (subtract from the pointer to get to CPUM) */
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| 375 | uint32_t ulOffCPUM;
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| 376 |
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| 377 | /* Temporary storage for the return code of the function called in the 32-64 switcher. */
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| 378 | uint32_t u32RetCode;
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| 379 |
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| 380 | /* Round to 16 byte size.
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| 381 | uint32_t uPadding;
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| 382 | */
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| 383 | } CPUMCPU, *PCPUMCPU;
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| 384 | /** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
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| 385 | typedef CPUMCPU *PCPUMCPU;
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| 386 |
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| 387 | __BEGIN_DECLS
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| 388 |
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| 389 | DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
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| 390 |
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| 391 | #ifdef IN_RING0
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| 392 | DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
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| 393 | DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
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| 394 | DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
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| 395 | DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
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| 396 | DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
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| 397 | DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
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| 398 | DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
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| 399 | DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
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| 400 | DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
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| 401 | DECLASM(uint16_t) cpumR0GetFCW(void);
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| 402 | DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
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| 403 | DECLASM(uint32_t) cpumR0GetMXCSR(void);
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| 404 | DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
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| 405 | DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
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| 406 | #endif
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| 407 |
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| 408 | __END_DECLS
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| 409 |
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| 410 | /** @} */
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| 411 |
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| 412 | #endif
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| 413 |
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