VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 28800

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1/* $Id: CPUM.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers accross world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/cpum.h>
39#include <VBox/cpumdis.h>
40#include <VBox/pgm.h>
41#include <VBox/mm.h>
42#include <VBox/selm.h>
43#include <VBox/dbgf.h>
44#include <VBox/patm.h>
45#include <VBox/hwaccm.h>
46#include <VBox/ssm.h>
47#include "CPUMInternal.h"
48#include <VBox/vm.h>
49
50#include <VBox/param.h>
51#include <VBox/dis.h>
52#include <VBox/err.h>
53#include <VBox/log.h>
54#include <iprt/assert.h>
55#include <iprt/asm.h>
56#include <iprt/string.h>
57#include <iprt/mp.h>
58#include <iprt/cpuset.h>
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/** The current saved state version. */
65#define CPUM_SAVED_STATE_VERSION 11
66/** The saved state version of 3.0 and 3.1 trunk before the teleportation
67 * changes. */
68#define CPUM_SAVED_STATE_VERSION_VER3_0 10
69/** The saved state version for the 2.1 trunk before the MSR changes. */
70#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
71/** The saved state version of 2.0, used for backwards compatibility. */
72#define CPUM_SAVED_STATE_VERSION_VER2_0 8
73/** The saved state version of 1.6, used for backwards compatability. */
74#define CPUM_SAVED_STATE_VERSION_VER1_6 6
75
76
77/*******************************************************************************
78* Structures and Typedefs *
79*******************************************************************************/
80
81/**
82 * What kind of cpu info dump to perform.
83 */
84typedef enum CPUMDUMPTYPE
85{
86 CPUMDUMPTYPE_TERSE,
87 CPUMDUMPTYPE_DEFAULT,
88 CPUMDUMPTYPE_VERBOSE
89} CPUMDUMPTYPE;
90/** Pointer to a cpu info dump type. */
91typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
92
93
94/*******************************************************************************
95* Internal Functions *
96*******************************************************************************/
97static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
98static int cpumR3CpuIdInit(PVM pVM);
99static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
100static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
103static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
104static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110
111
112/**
113 * Initializes the CPUM.
114 *
115 * @returns VBox status code.
116 * @param pVM The VM to operate on.
117 */
118VMMR3DECL(int) CPUMR3Init(PVM pVM)
119{
120 LogFlow(("CPUMR3Init\n"));
121
122 /*
123 * Assert alignment and sizes.
124 */
125 AssertCompileMemberAlignment(VM, cpum.s, 32);
126 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
127 AssertCompileSizeAlignment(CPUMCTX, 64);
128 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
129 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
130 AssertCompileMemberAlignment(VM, cpum, 64);
131 AssertCompileMemberAlignment(VM, aCpus, 64);
132 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
133 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
134
135 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
136 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
137 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
138
139 /* Calculate the offset from CPUMCPU to CPUM. */
140 for (VMCPUID i = 0; i < pVM->cCpus; i++)
141 {
142 PVMCPU pVCpu = &pVM->aCpus[i];
143
144 /*
145 * Setup any fixed pointers and offsets.
146 */
147 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
148 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
149
150 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
151 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
152 }
153
154 /*
155 * Check that the CPU supports the minimum features we require.
156 */
157 if (!ASMHasCpuId())
158 {
159 Log(("The CPU doesn't support CPUID!\n"));
160 return VERR_UNSUPPORTED_CPU;
161 }
162 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
163 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
164
165 /* Setup the CR4 AND and OR masks used in the switcher */
166 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
167 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
168 {
169 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
170 /* No FXSAVE implies no SSE */
171 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
172 pVM->cpum.s.CR4.OrMask = 0;
173 }
174 else
175 {
176 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
177 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
178 }
179
180 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
181 {
182 Log(("The CPU doesn't support MMX!\n"));
183 return VERR_UNSUPPORTED_CPU;
184 }
185 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
186 {
187 Log(("The CPU doesn't support TSC!\n"));
188 return VERR_UNSUPPORTED_CPU;
189 }
190 /* Bogus on AMD? */
191 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
192 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
193
194 /*
195 * Detech the host CPU vendor.
196 * (The guest CPU vendor is re-detected later on.)
197 */
198 uint32_t uEAX, uEBX, uECX, uEDX;
199 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
200 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
201 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
202
203 /*
204 * Setup hypervisor startup values.
205 */
206
207 /*
208 * Register saved state data item.
209 */
210 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
211 NULL, cpumR3LiveExec, NULL,
212 NULL, cpumR3SaveExec, NULL,
213 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
214 if (RT_FAILURE(rc))
215 return rc;
216
217 /*
218 * Register info handlers.
219 */
220 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
221 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
222 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
223 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
224 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
225 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
226
227 /*
228 * Initialize the Guest CPUID state.
229 */
230 rc = cpumR3CpuIdInit(pVM);
231 if (RT_FAILURE(rc))
232 return rc;
233 CPUMR3Reset(pVM);
234 return VINF_SUCCESS;
235}
236
237
238/**
239 * Initializes the per-VCPU CPUM.
240 *
241 * @returns VBox status code.
242 * @param pVM The VM to operate on.
243 */
244VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
245{
246 LogFlow(("CPUMR3InitCPU\n"));
247 return VINF_SUCCESS;
248}
249
250
251/**
252 * Detect the CPU vendor give n the
253 *
254 * @returns The vendor.
255 * @param uEAX EAX from CPUID(0).
256 * @param uEBX EBX from CPUID(0).
257 * @param uECX ECX from CPUID(0).
258 * @param uEDX EDX from CPUID(0).
259 */
260static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
261{
262 if ( uEAX >= 1
263 && uEBX == X86_CPUID_VENDOR_AMD_EBX
264 && uECX == X86_CPUID_VENDOR_AMD_ECX
265 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
266 return CPUMCPUVENDOR_AMD;
267
268 if ( uEAX >= 1
269 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
270 && uECX == X86_CPUID_VENDOR_INTEL_ECX
271 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
272 return CPUMCPUVENDOR_INTEL;
273
274 /** @todo detect the other buggers... */
275 return CPUMCPUVENDOR_UNKNOWN;
276}
277
278
279/**
280 * Fetches overrides for a CPUID leaf.
281 *
282 * @returns VBox status code.
283 * @param pLeaf The leaf to load the overrides into.
284 * @param pCfgNode The CFGM node containing the overrides
285 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
286 * @param iLeaf The CPUID leaf number.
287 */
288static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
289{
290 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
291 if (pLeafNode)
292 {
293 uint32_t u32;
294 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
295 if (RT_SUCCESS(rc))
296 pLeaf->eax = u32;
297 else
298 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
299
300 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
301 if (RT_SUCCESS(rc))
302 pLeaf->ebx = u32;
303 else
304 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
305
306 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
307 if (RT_SUCCESS(rc))
308 pLeaf->ecx = u32;
309 else
310 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
311
312 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
313 if (RT_SUCCESS(rc))
314 pLeaf->edx = u32;
315 else
316 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
317
318 }
319 return VINF_SUCCESS;
320}
321
322
323/**
324 * Load the overrides for a set of CPUID leafs.
325 *
326 * @returns VBox status code.
327 * @param paLeafs The leaf array.
328 * @param cLeafs The number of leafs.
329 * @param uStart The start leaf number.
330 * @param pCfgNode The CFGM node containing the overrides
331 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
332 */
333static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
334{
335 for (uint32_t i = 0; i < cLeafs; i++)
336 {
337 int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
338 if (RT_FAILURE(rc))
339 return rc;
340 }
341
342 return VINF_SUCCESS;
343}
344
345/**
346 * Init a set of host CPUID leafs.
347 *
348 * @returns VBox status code.
349 * @param paLeafs The leaf array.
350 * @param cLeafs The number of leafs.
351 * @param uStart The start leaf number.
352 * @param pCfgNode The /CPUM/HostCPUID/ node.
353 */
354static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
355{
356 /* Using the ECX variant for all of them can't hurt... */
357 for (uint32_t i = 0; i < cLeafs; i++)
358 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
359
360 /* Load CPUID leaf override; we currently don't care if the caller
361 specifies features the host CPU doesn't support. */
362 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
363}
364
365
366/**
367 * Initializes the emulated CPU's cpuid information.
368 *
369 * @returns VBox status code.
370 * @param pVM The VM to operate on.
371 */
372static int cpumR3CpuIdInit(PVM pVM)
373{
374 PCPUM pCPUM = &pVM->cpum.s;
375 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
376 uint32_t i;
377 int rc;
378
379 /*
380 * Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
381 */
382 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
383 * Overrides the host CPUID leaf values used for calculating the guest CPUID
384 * leafs. This can be used to preserve the CPUID values when moving a VM to
385 * a different machine. Another use is restricting (or extending) the
386 * feature set exposed to the guest. */
387 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
388 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
389 AssertRCReturn(rc, rc);
390 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
391 AssertRCReturn(rc, rc);
392 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
393 AssertRCReturn(rc, rc);
394
395 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
396 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
397
398 /*
399 * Only report features we can support.
400 */
401 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
402 | X86_CPUID_FEATURE_EDX_VME
403 | X86_CPUID_FEATURE_EDX_DE
404 | X86_CPUID_FEATURE_EDX_PSE
405 | X86_CPUID_FEATURE_EDX_TSC
406 | X86_CPUID_FEATURE_EDX_MSR
407 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
408 | X86_CPUID_FEATURE_EDX_MCE
409 | X86_CPUID_FEATURE_EDX_CX8
410 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
411 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
412 //| X86_CPUID_FEATURE_EDX_SEP
413 | X86_CPUID_FEATURE_EDX_MTRR
414 | X86_CPUID_FEATURE_EDX_PGE
415 | X86_CPUID_FEATURE_EDX_MCA
416 | X86_CPUID_FEATURE_EDX_CMOV
417 | X86_CPUID_FEATURE_EDX_PAT
418 | X86_CPUID_FEATURE_EDX_PSE36
419 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
420 | X86_CPUID_FEATURE_EDX_CLFSH
421 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
422 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
423 | X86_CPUID_FEATURE_EDX_MMX
424 | X86_CPUID_FEATURE_EDX_FXSR
425 | X86_CPUID_FEATURE_EDX_SSE
426 | X86_CPUID_FEATURE_EDX_SSE2
427 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
428 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
429 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
430 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
431 | 0;
432 pCPUM->aGuestCpuIdStd[1].ecx &= 0
433 | X86_CPUID_FEATURE_ECX_SSE3
434 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
435 | ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
436 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
437 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
438 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
439 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
440 | X86_CPUID_FEATURE_ECX_SSSE3
441 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
442 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
443 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
444 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
445 /* ECX Bit 21 - x2APIC support - not yet. */
446 // | X86_CPUID_FEATURE_ECX_X2APIC
447 /* ECX Bit 23 - POPCNT instruction. */
448 //| X86_CPUID_FEATURE_ECX_POPCNT
449 | 0;
450
451 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
452 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
453 | X86_CPUID_AMD_FEATURE_EDX_VME
454 | X86_CPUID_AMD_FEATURE_EDX_DE
455 | X86_CPUID_AMD_FEATURE_EDX_PSE
456 | X86_CPUID_AMD_FEATURE_EDX_TSC
457 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
458 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
459 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
460 | X86_CPUID_AMD_FEATURE_EDX_CX8
461 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
462 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
463 //| X86_CPUID_AMD_FEATURE_EDX_SEP
464 | X86_CPUID_AMD_FEATURE_EDX_MTRR
465 | X86_CPUID_AMD_FEATURE_EDX_PGE
466 | X86_CPUID_AMD_FEATURE_EDX_MCA
467 | X86_CPUID_AMD_FEATURE_EDX_CMOV
468 | X86_CPUID_AMD_FEATURE_EDX_PAT
469 | X86_CPUID_AMD_FEATURE_EDX_PSE36
470 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
471 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
472 | X86_CPUID_AMD_FEATURE_EDX_MMX
473 | X86_CPUID_AMD_FEATURE_EDX_FXSR
474 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
475 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
476 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
477 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
478 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
479 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
480 | 0;
481 pCPUM->aGuestCpuIdExt[1].ecx &= 0
482 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
483 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
484 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
485 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
486 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
487 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
488 //| X86_CPUID_AMD_FEATURE_ECX_ABM
489 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
490 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
491 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
492 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
493 //| X86_CPUID_AMD_FEATURE_ECX_IBS
494 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
495 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
496 //| X86_CPUID_AMD_FEATURE_ECX_WDT
497 | 0;
498
499 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
500 if (pCPUM->fSyntheticCpu)
501 {
502 const char szVendor[13] = "VirtualBox ";
503 const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
504
505 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
506
507 /* Limit the nr of standard leaves; 5 for monitor/mwait */
508 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
509
510 /* 0: Vendor */
511 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
512 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
513 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
514
515 /* 1.eax: Version information. family : model : stepping */
516 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
517
518 /* Leaves 2 - 4 are Intel only - zero them out */
519 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
520 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
521 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
522
523 /* Leaf 5 = monitor/mwait */
524
525 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
526 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
527 /* AMD only - set to zero. */
528 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
529
530 /* 0x800000001: AMD only; shared feature bits are set dynamically. */
531 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
532
533 /* 0x800000002-4: Processor Name String Identifier. */
534 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
535 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
536 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
537 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
538 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
539 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
540 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
541 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
542 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
543 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
544 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
545 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
546
547 /* 0x800000005-7 - reserved -> zero */
548 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
549 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
550 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
551
552 /* 0x800000008: only the max virtual and physical address size. */
553 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
554 }
555
556 /*
557 * Hide HTT, multicode, SMP, whatever.
558 * (APIC-ID := 0 and #LogCpus := 0)
559 */
560 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
561#ifdef VBOX_WITH_MULTI_CORE
562 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
563 && pVM->cCpus > 1)
564 {
565 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
566 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
567 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
568 }
569#endif
570
571 /* Cpuid 2:
572 * Intel: Cache and TLB information
573 * AMD: Reserved
574 * Safe to expose
575 */
576
577 /* Cpuid 3:
578 * Intel: EAX, EBX - reserved
579 * ECX, EDX - Processor Serial Number if available, otherwise reserved
580 * AMD: Reserved
581 * Safe to expose
582 */
583 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
584 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
585
586 /* Cpuid 4:
587 * Intel: Deterministic Cache Parameters Leaf
588 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
589 * AMD: Reserved
590 * Safe to expose, except for EAX:
591 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
592 * Bits 31-26: Maximum number of processor cores in this physical package**
593 * Note: These SMP values are constant regardless of ECX
594 */
595 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
596 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
597#ifdef VBOX_WITH_MULTI_CORE
598 if ( pVM->cCpus > 1
599 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
600 {
601 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
602 /* One logical processor with possibly multiple cores. */
603 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
604 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
605 }
606#endif
607
608 /* Cpuid 5: Monitor/mwait Leaf
609 * Intel: ECX, EDX - reserved
610 * EAX, EBX - Smallest and largest monitor line size
611 * AMD: EDX - reserved
612 * EAX, EBX - Smallest and largest monitor line size
613 * ECX - extensions (ignored for now)
614 * Safe to expose
615 */
616 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
617 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
618
619 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
620 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
621 * Expose MWAIT extended features to the guest.
622 * For now we expose just MWAIT break on interrupt feature (bit 1)
623 */
624 bool fMWaitExtensions;
625 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
626 if (fMWaitExtensions)
627 {
628 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
629 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
630 it shall be part of our power management virtualization model */
631#if 0
632 /* MWAIT sub C-states */
633 pCPUM->aGuestCpuIdStd[5].edx =
634 (0 << 0) /* 0 in C0 */ |
635 (2 << 4) /* 2 in C1 */ |
636 (2 << 8) /* 2 in C2 */ |
637 (2 << 12) /* 2 in C3 */ |
638 (0 << 16) /* 0 in C4 */
639 ;
640#endif
641 }
642 else
643 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
644
645 /*
646 * Determine the default.
647 *
648 * Intel returns values of the highest standard function, while AMD
649 * returns zeros. VIA on the other hand seems to returning nothing or
650 * perhaps some random garbage, we don't try to duplicate this behavior.
651 */
652 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
653 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
654 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
655
656 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
657 * Safe to pass on to the guest.
658 *
659 * Intel: 0x800000005 reserved
660 * 0x800000006 L2 cache information
661 * AMD: 0x800000005 L1 cache information
662 * 0x800000006 L2/L3 cache information
663 */
664
665 /* Cpuid 0x800000007:
666 * AMD: EAX, EBX, ECX - reserved
667 * EDX: Advanced Power Management Information
668 * Intel: Reserved
669 */
670 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
671 {
672 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
673
674 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
675
676 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
677 {
678 /* Only expose the TSC invariant capability bit to the guest. */
679 pCPUM->aGuestCpuIdExt[7].edx &= 0
680 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
681 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
682 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
683 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
684 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
685 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
686 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
687 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
688#if 1
689 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
690 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
691 */
692#else
693 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
694#endif
695 | 0;
696 }
697 else
698 pCPUM->aGuestCpuIdExt[7].edx = 0;
699 }
700
701 /* Cpuid 0x800000008:
702 * AMD: EBX, EDX - reserved
703 * EAX: Virtual/Physical address Size
704 * ECX: Number of cores + APICIdCoreIdSize
705 * Intel: EAX: Virtual/Physical address Size
706 * EBX, ECX, EDX - reserved
707 */
708 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
709 {
710 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
711 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
712 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
713 * NC (0-7) Number of cores; 0 equals 1 core */
714 pCPUM->aGuestCpuIdExt[8].ecx = 0;
715#ifdef VBOX_WITH_MULTI_CORE
716 if ( pVM->cCpus > 1
717 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
718 {
719 /* Legacy method to determine the number of cores. */
720 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
721 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
722
723 }
724#endif
725 }
726
727 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
728 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
729 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
730 * This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
731 */
732 bool fNt4LeafLimit;
733 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
734 if (fNt4LeafLimit)
735 pCPUM->aGuestCpuIdStd[0].eax = 3;
736
737 /*
738 * Limit it the number of entries and fill the remaining with the defaults.
739 *
740 * The limits are masking off stuff about power saving and similar, this
741 * is perhaps a bit crudely done as there is probably some relatively harmless
742 * info too in these leaves (like words about having a constant TSC).
743 */
744 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
745 pCPUM->aGuestCpuIdStd[0].eax = 5;
746
747 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
748 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
749
750 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
751 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
752 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
753 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
754 : 0;
755 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
756 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
757
758 /*
759 * Centaur stuff (VIA).
760 *
761 * The important part here (we think) is to make sure the 0xc0000000
762 * function returns 0xc0000001. As for the features, we don't currently
763 * let on about any of those... 0xc0000002 seems to be some
764 * temperature/hz/++ stuff, include it as well (static).
765 */
766 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
767 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
768 {
769 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
770 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
771 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
772 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
773 i++)
774 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
775 }
776 else
777 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
778 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
779
780
781 /*
782 * Load CPUID overrides from configuration.
783 * Note: Kind of redundant now, but allows unchanged overrides
784 */
785 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
786 * Overrides the CPUID leaf values. */
787 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
788 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
789 AssertRCReturn(rc, rc);
790 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
791 AssertRCReturn(rc, rc);
792 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
793 AssertRCReturn(rc, rc);
794
795 /*
796 * Check if PAE was explicitely enabled by the user.
797 */
798 bool fEnable;
799 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
800 if (fEnable)
801 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
802
803 /*
804 * Log the cpuid and we're good.
805 */
806 RTCPUSET OnlineSet;
807 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
808 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
809 LogRel(("************************* CPUID dump ************************\n"));
810 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
811 LogRel(("\n"));
812 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
813 LogRel(("******************** End of CPUID dump **********************\n"));
814 return VINF_SUCCESS;
815}
816
817
818
819
820/**
821 * Applies relocations to data and code managed by this
822 * component. This function will be called at init and
823 * whenever the VMM need to relocate it self inside the GC.
824 *
825 * The CPUM will update the addresses used by the switcher.
826 *
827 * @param pVM The VM.
828 */
829VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
830{
831 LogFlow(("CPUMR3Relocate\n"));
832 for (VMCPUID i = 0; i < pVM->cCpus; i++)
833 {
834 /*
835 * Switcher pointers.
836 */
837 PVMCPU pVCpu = &pVM->aCpus[i];
838 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
839 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
840
841 }
842}
843
844
845/**
846 * Apply late CPUM property changes based on the fHWVirtEx setting
847 *
848 * @param pVM The VM to operate on.
849 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
850 */
851VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
852{
853 /*
854 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
855 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
856 * of processors from (cpuid(4).eax >> 26) + 1.
857 *
858 * Note: this code is obsolete, but let's keep it here for reference.
859 * Purpose is valid when we artifically cap the max std id to less than 4.
860 */
861 if (!fHWVirtExEnabled)
862 {
863 Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
864 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
865 }
866}
867
868/**
869 * Terminates the CPUM.
870 *
871 * Termination means cleaning up and freeing all resources,
872 * the VM it self is at this point powered off or suspended.
873 *
874 * @returns VBox status code.
875 * @param pVM The VM to operate on.
876 */
877VMMR3DECL(int) CPUMR3Term(PVM pVM)
878{
879 CPUMR3TermCPU(pVM);
880 return 0;
881}
882
883
884/**
885 * Terminates the per-VCPU CPUM.
886 *
887 * Termination means cleaning up and freeing all resources,
888 * the VM it self is at this point powered off or suspended.
889 *
890 * @returns VBox status code.
891 * @param pVM The VM to operate on.
892 */
893VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
894{
895#ifdef VBOX_WITH_CRASHDUMP_MAGIC
896 for (VMCPUID i = 0; i < pVM->cCpus; i++)
897 {
898 PVMCPU pVCpu = &pVM->aCpus[i];
899 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
900
901 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
902 pVCpu->cpum.s.uMagic = 0;
903 pCtx->dr[5] = 0;
904 }
905#endif
906 return 0;
907}
908
909
910/**
911 * Resets a virtual CPU.
912 *
913 * Used by CPUMR3Reset and CPU hot plugging.
914 *
915 * @param pVCpu The virtual CPU handle.
916 */
917VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
918{
919 /** @todo anything different for VCPU > 0? */
920 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
921
922 /*
923 * Initialize everything to ZERO first.
924 */
925 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
926 memset(pCtx, 0, sizeof(*pCtx));
927 pVCpu->cpum.s.fUseFlags = fUseFlags;
928
929 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
930 pCtx->eip = 0x0000fff0;
931 pCtx->edx = 0x00000600; /* P6 processor */
932 pCtx->eflags.Bits.u1Reserved0 = 1;
933
934 pCtx->cs = 0xf000;
935 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
936 pCtx->csHid.u32Limit = 0x0000ffff;
937 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
938 pCtx->csHid.Attr.n.u1Present = 1;
939 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
940
941 pCtx->dsHid.u32Limit = 0x0000ffff;
942 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
943 pCtx->dsHid.Attr.n.u1Present = 1;
944 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
945
946 pCtx->esHid.u32Limit = 0x0000ffff;
947 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
948 pCtx->esHid.Attr.n.u1Present = 1;
949 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
950
951 pCtx->fsHid.u32Limit = 0x0000ffff;
952 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
953 pCtx->fsHid.Attr.n.u1Present = 1;
954 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
955
956 pCtx->gsHid.u32Limit = 0x0000ffff;
957 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
958 pCtx->gsHid.Attr.n.u1Present = 1;
959 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
960
961 pCtx->ssHid.u32Limit = 0x0000ffff;
962 pCtx->ssHid.Attr.n.u1Present = 1;
963 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
964 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
965
966 pCtx->idtr.cbIdt = 0xffff;
967 pCtx->gdtr.cbGdt = 0xffff;
968
969 pCtx->ldtrHid.u32Limit = 0xffff;
970 pCtx->ldtrHid.Attr.n.u1Present = 1;
971 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
972
973 pCtx->trHid.u32Limit = 0xffff;
974 pCtx->trHid.Attr.n.u1Present = 1;
975 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
976
977 pCtx->dr[6] = X86_DR6_INIT_VAL;
978 pCtx->dr[7] = X86_DR7_INIT_VAL;
979
980 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
981 pCtx->fpu.FCW = 0x37f;
982
983 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
984 pCtx->fpu.MXCSR = 0x1F80;
985
986 /* Init PAT MSR */
987 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
988
989 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
990 * The Intel docs don't mention it.
991 */
992 pCtx->msrEFER = 0;
993}
994
995
996/**
997 * Resets the CPU.
998 *
999 * @returns VINF_SUCCESS.
1000 * @param pVM The VM handle.
1001 */
1002VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1003{
1004 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1005 {
1006 CPUMR3ResetCpu(&pVM->aCpus[i]);
1007
1008#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1009 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1010
1011 /* Magic marker for searching in crash dumps. */
1012 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1013 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1014 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1015#endif
1016 }
1017}
1018
1019
1020/**
1021 * Called both in pass 0 and the final pass.
1022 *
1023 * @param pVM The VM handle.
1024 * @param pSSM The saved state handle.
1025 */
1026static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1027{
1028 /*
1029 * Save all the CPU ID leaves here so we can check them for compatability
1030 * upon loading.
1031 */
1032 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1033 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1034
1035 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1036 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1037
1038 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1039 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1040
1041 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1042
1043 /*
1044 * Save a good portion of the raw CPU IDs as well as they may come in
1045 * handy when validating features for raw mode.
1046 */
1047 CPUMCPUID aRawStd[16];
1048 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1049 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1050 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1051 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1052
1053 CPUMCPUID aRawExt[32];
1054 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1055 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1056 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1057 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1058}
1059
1060
1061/**
1062 * Loads the CPU ID leaves saved by pass 0.
1063 *
1064 * @returns VBox status code.
1065 * @param pVM The VM handle.
1066 * @param pSSM The saved state handle.
1067 * @param uVersion The format version.
1068 */
1069static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1070{
1071 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1072
1073 /*
1074 * Define a bunch of macros for simplifying the code.
1075 */
1076 /* Generic expression + failure message. */
1077#define CPUID_CHECK_RET(expr, fmt) \
1078 do { \
1079 if (!(expr)) \
1080 { \
1081 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadict macros sucks */ \
1082 if (fStrictCpuIdChecks) \
1083 { \
1084 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1085 RTStrFree(pszMsg); \
1086 return rcCpuid; \
1087 } \
1088 LogRel(("CPUM: %s\n", pszMsg)); \
1089 RTStrFree(pszMsg); \
1090 } \
1091 } while (0)
1092#define CPUID_CHECK_WRN(expr, fmt) \
1093 do { \
1094 if (!(expr)) \
1095 LogRel(fmt); \
1096 } while (0)
1097
1098 /* For comparing two values and bitch if they differs. */
1099#define CPUID_CHECK2_RET(what, host, saved) \
1100 do { \
1101 if ((host) != (saved)) \
1102 { \
1103 if (fStrictCpuIdChecks) \
1104 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1105 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1106 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1107 } \
1108 } while (0)
1109#define CPUID_CHECK2_WRN(what, host, saved) \
1110 do { \
1111 if ((host) != (saved)) \
1112 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1113 } while (0)
1114
1115 /* For checking raw cpu features (raw mode). */
1116#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1117 do { \
1118 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1119 { \
1120 if (fStrictCpuIdChecks) \
1121 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1122 N_(#bit " mismatch: host=%d saved=%d"), \
1123 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1124 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1125 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1126 } \
1127 } while (0)
1128#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1129 do { \
1130 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1131 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1132 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1133 } while (0)
1134#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1135
1136 /* For checking guest features. */
1137#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1138 do { \
1139 if ( (aGuestCpuId##set [1].reg & bit) \
1140 && !(aHostRaw##set [1].reg & bit) \
1141 && !(aHostOverride##set [1].reg & bit) \
1142 && !(aGuestOverride##set [1].reg & bit) \
1143 ) \
1144 { \
1145 if (fStrictCpuIdChecks) \
1146 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1147 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1148 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1149 } \
1150 } while (0)
1151#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1152 do { \
1153 if ( (aGuestCpuId##set [1].reg & bit) \
1154 && !(aHostRaw##set [1].reg & bit) \
1155 && !(aHostOverride##set [1].reg & bit) \
1156 && !(aGuestOverride##set [1].reg & bit) \
1157 ) \
1158 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1159 } while (0)
1160#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1161 do { \
1162 if ( (aGuestCpuId##set [1].reg & bit) \
1163 && !(aHostRaw##set [1].reg & bit) \
1164 && !(aHostOverride##set [1].reg & bit) \
1165 && !(aGuestOverride##set [1].reg & bit) \
1166 ) \
1167 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1168 } while (0)
1169#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1170
1171 /* For checking guest features if AMD guest CPU. */
1172#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1173 do { \
1174 if ( (aGuestCpuId##set [1].reg & bit) \
1175 && fGuestAmd \
1176 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1177 && !(aHostOverride##set [1].reg & bit) \
1178 && !(aGuestOverride##set [1].reg & bit) \
1179 ) \
1180 { \
1181 if (fStrictCpuIdChecks) \
1182 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1183 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1184 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1185 } \
1186 } while (0)
1187#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1188 do { \
1189 if ( (aGuestCpuId##set [1].reg & bit) \
1190 && fGuestAmd \
1191 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1192 && !(aHostOverride##set [1].reg & bit) \
1193 && !(aGuestOverride##set [1].reg & bit) \
1194 ) \
1195 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1196 } while (0)
1197#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1198 do { \
1199 if ( (aGuestCpuId##set [1].reg & bit) \
1200 && fGuestAmd \
1201 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1202 && !(aHostOverride##set [1].reg & bit) \
1203 && !(aGuestOverride##set [1].reg & bit) \
1204 ) \
1205 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1206 } while (0)
1207#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1208
1209 /* For checking AMD features which have a corresponding bit in the standard
1210 range. (Intel defines very few bits in the extended feature sets.) */
1211#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1212 do { \
1213 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1214 && !(fHostAmd \
1215 ? aHostRawExt[1].reg & (ExtBit) \
1216 : aHostRawStd[1].reg & (StdBit)) \
1217 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1218 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1219 ) \
1220 { \
1221 if (fStrictCpuIdChecks) \
1222 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1223 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1224 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1225 } \
1226 } while (0)
1227#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1228 do { \
1229 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1230 && !(fHostAmd \
1231 ? aHostRawExt[1].reg & (ExtBit) \
1232 : aHostRawStd[1].reg & (StdBit)) \
1233 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1234 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1235 ) \
1236 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1237 } while (0)
1238#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1239 do { \
1240 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1241 && !(fHostAmd \
1242 ? aHostRawExt[1].reg & (ExtBit) \
1243 : aHostRawStd[1].reg & (StdBit)) \
1244 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1245 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1246 ) \
1247 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1248 } while (0)
1249#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1250
1251 /*
1252 * Load them into stack buffers first.
1253 */
1254 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1255 uint32_t cGuestCpuIdStd;
1256 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1257 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1258 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1259 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1260
1261 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1262 uint32_t cGuestCpuIdExt;
1263 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1264 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1265 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1266 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1267
1268 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1269 uint32_t cGuestCpuIdCentaur;
1270 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1271 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1272 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1273 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1274
1275 CPUMCPUID GuestCpuIdDef;
1276 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1277 AssertRCReturn(rc, rc);
1278
1279 CPUMCPUID aRawStd[16];
1280 uint32_t cRawStd;
1281 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1282 if (cRawStd > RT_ELEMENTS(aRawStd))
1283 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1284 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1285
1286 CPUMCPUID aRawExt[32];
1287 uint32_t cRawExt;
1288 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1289 if (cRawExt > RT_ELEMENTS(aRawExt))
1290 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1291 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1292 AssertRCReturn(rc, rc);
1293
1294 /*
1295 * Note that we support restoring less than the current amount of standard
1296 * leaves because we've been allowed more is newer version of VBox.
1297 *
1298 * So, pad new entries with the default.
1299 */
1300 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1301 aGuestCpuIdStd[i] = GuestCpuIdDef;
1302
1303 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1304 aGuestCpuIdExt[i] = GuestCpuIdDef;
1305
1306 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1307 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1308
1309 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1310 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1311
1312 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1313 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1314
1315 /*
1316 * Get the raw CPU IDs for the current host.
1317 */
1318 CPUMCPUID aHostRawStd[16];
1319 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1320 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1321
1322 CPUMCPUID aHostRawExt[32];
1323 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1324 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1325
1326 /*
1327 * Get the host and guest overrides so we don't reject the state because
1328 * some feature was enabled thru these interfaces.
1329 * Note! We currently only need the feature leafs, so skip rest.
1330 */
1331 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1332 CPUMCPUID aGuestOverrideStd[2];
1333 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1334 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1335
1336 CPUMCPUID aGuestOverrideExt[2];
1337 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1338 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1339
1340 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1341 CPUMCPUID aHostOverrideStd[2];
1342 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1343 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1344
1345 CPUMCPUID aHostOverrideExt[2];
1346 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1347 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1348
1349 /*
1350 * This can be skipped.
1351 */
1352 bool fStrictCpuIdChecks;
1353 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1354
1355
1356
1357 /*
1358 * For raw-mode we'll require that the CPUs are very similar since we don't
1359 * intercept CPUID instructions for user mode applications.
1360 */
1361 if (!HWACCMIsEnabled(pVM))
1362 {
1363 /* CPUID(0) */
1364 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1365 && aHostRawStd[0].ecx == aRawStd[0].ecx
1366 && aHostRawStd[0].edx == aRawStd[0].edx,
1367 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1368 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1369 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1370 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1371 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1372 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1373
1374 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1375
1376 /* CPUID(1).eax */
1377 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1378 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1379 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1380
1381 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1382 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1383 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1384
1385 /* CPUID(1).ecx */
1386 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1387 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1388 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1389 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1390 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1391 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1392 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1393 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1394 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1395 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1396 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1397 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1398 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1399 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1400 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1401 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1402 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1403 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1404 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1405 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1406 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1407 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1408 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1409 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1410 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
1411 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1412 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1413 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1414 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1415 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
1416 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
1417 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /*reserved*/);
1418
1419 /* CPUID(1).edx */
1420 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1421 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1422 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1423 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1424 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1425 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1426 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1427 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1428 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1429 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1430 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
1431 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1432 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1433 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1434 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1435 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1436 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1437 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1438 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1439 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1440 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
1441 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1442 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1443 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1444 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1445 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1446 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1447 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1448 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1449 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1450 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
1451 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1452
1453 /* CPUID(2) - config, mostly about caches. ignore. */
1454 /* CPUID(3) - processor serial number. ignore. */
1455 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1456 /* CPUID(5) - mwait/monitor config. ignore. */
1457 /* CPUID(6) - power management. ignore. */
1458 /* CPUID(7) - ???. ignore. */
1459 /* CPUID(8) - ???. ignore. */
1460 /* CPUID(9) - DCA. ignore for now. */
1461 /* CPUID(a) - PeMo info. ignore for now. */
1462 /* CPUID(b) - topology info - takes ECX as input. ignore. */
1463
1464 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1465 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1466 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1467 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1468 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1469 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1470 {
1471 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1472 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1473 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1474 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1475 }
1476
1477 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
1478 Note! Intel have/is marking many of the fields here as reserved. We
1479 will verify them as if it's an AMD CPU. */
1480 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1481 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1482 (N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1483 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1484 {
1485 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1486 && aHostRawExt[0].ecx == aRawExt[0].ecx
1487 && aHostRawExt[0].edx == aRawExt[0].edx,
1488 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1489 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1490 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1491 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1492
1493 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1494 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1495 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1496 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1497 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1498 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1499
1500 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1501 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1502 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1503 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1504
1505 /* CPUID(0x80000001).ecx */
1506 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1507 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1508 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1509 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1510 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1511 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1512 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1513 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1514 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1515 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1516 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1517 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1518 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1519 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1520 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1521 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1522 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1523 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1524 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1525 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1526 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1527 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1528 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1529 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1530 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1531 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1532 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1533 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1534 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1535 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1536 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1537 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1538
1539 /* CPUID(0x80000001).edx */
1540 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1541 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1542 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1543 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1544 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1545 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1546 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1547 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1548 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1549 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1550 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
1551 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1552 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1553 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1554 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1555 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1556 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1557 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1558 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
1559 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
1560 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1561 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
1562 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1563 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1564 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1565 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1566 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1567 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1568 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
1569 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1570 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1571 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1572
1573 /** @todo verify the rest as well. */
1574 }
1575 }
1576
1577
1578
1579 /*
1580 * Verify that we can support the features already exposed to the guest on
1581 * this host.
1582 *
1583 * Most of the features we're emulating requires intercepting instruction
1584 * and doing it the slow way, so there is no need to warn when they aren't
1585 * present in the host CPU. Thus we use IGN instead of EMU on these.
1586 *
1587 * Trailing comments:
1588 * "EMU" - Possible to emulate, could be lots of work and very slow.
1589 * "EMU?" - Can this be emulated?
1590 */
1591 /* CPUID(1).ecx */
1592 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1593 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1594 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1595 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1596 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1597 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1598 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1599 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1600 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1601 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1602 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1603 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1604 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1605 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1606 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1607 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1608 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1609 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1610 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1611 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1612 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1613 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1614 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1615 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1616 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
1617 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1618 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1619 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1620 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1621 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
1622 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
1623 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /*reserved*/);
1624
1625 /* CPUID(1).edx */
1626 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1627 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1628 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1629 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1630 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1631 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1632 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1633 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1634 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1635 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1636 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
1637 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1638 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1639 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1640 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1641 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1642 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1643 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1644 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1645 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1646 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
1647 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1648 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1649 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1650 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1651 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1652 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1653 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1654 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1655 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1656 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
1657 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1658
1659 /* CPUID(0x80000000). */
1660 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1661 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1662 {
1663 /** @todo deal with no 0x80000001 on the host. */
1664 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1665 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1666
1667 /* CPUID(0x80000001).ecx */
1668 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1669 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1670 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1671 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1672 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1673 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1674 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1675 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1676 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1677 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1678 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1679 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1680 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1681 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1682 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1683 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1684 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1685 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1686 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1687 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1688 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1689 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1690 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1691 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1692 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1693 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1694 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1695 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1696 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1697 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1698 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1699 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1700
1701 /* CPUID(0x80000001).edx */
1702 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1703 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1704 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1705 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1706 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1707 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1708 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1709 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1710 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1711 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1712 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
1713 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1714 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1715 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1716 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1717 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1718 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1719 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1720 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
1721 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
1722 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1723 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
1724 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1725 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1726 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1727 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1728 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1729 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1730 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
1731 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1732 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1733 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1734 }
1735
1736 /*
1737 * We're good, commit the CPU ID leaves.
1738 */
1739 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1740 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1741 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1742 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1743
1744#undef CPUID_CHECK_RET
1745#undef CPUID_CHECK_WRN
1746#undef CPUID_CHECK2_RET
1747#undef CPUID_CHECK2_WRN
1748#undef CPUID_RAW_FEATURE_RET
1749#undef CPUID_RAW_FEATURE_WRN
1750#undef CPUID_RAW_FEATURE_IGN
1751#undef CPUID_GST_FEATURE_RET
1752#undef CPUID_GST_FEATURE_WRN
1753#undef CPUID_GST_FEATURE_EMU
1754#undef CPUID_GST_FEATURE_IGN
1755#undef CPUID_GST_FEATURE2_RET
1756#undef CPUID_GST_FEATURE2_WRN
1757#undef CPUID_GST_FEATURE2_EMU
1758#undef CPUID_GST_FEATURE2_IGN
1759#undef CPUID_GST_AMD_FEATURE_RET
1760#undef CPUID_GST_AMD_FEATURE_WRN
1761#undef CPUID_GST_AMD_FEATURE_EMU
1762#undef CPUID_GST_AMD_FEATURE_IGN
1763
1764 return VINF_SUCCESS;
1765}
1766
1767
1768/**
1769 * Pass 0 live exec callback.
1770 *
1771 * @returns VINF_SSM_DONT_CALL_AGAIN.
1772 * @param pVM The VM handle.
1773 * @param pSSM The saved state handle.
1774 * @param uPass The pass (0).
1775 */
1776static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1777{
1778 AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1779 cpumR3SaveCpuId(pVM, pSSM);
1780 return VINF_SSM_DONT_CALL_AGAIN;
1781}
1782
1783
1784/**
1785 * Execute state save operation.
1786 *
1787 * @returns VBox status code.
1788 * @param pVM VM Handle.
1789 * @param pSSM SSM operation handle.
1790 */
1791static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1792{
1793 /*
1794 * Save.
1795 */
1796 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1797 {
1798 PVMCPU pVCpu = &pVM->aCpus[i];
1799
1800 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1801 }
1802
1803 SSMR3PutU32(pSSM, pVM->cCpus);
1804 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1805 {
1806 PVMCPU pVCpu = &pVM->aCpus[i];
1807
1808 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1809 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1810 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1811 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1812 }
1813
1814 cpumR3SaveCpuId(pVM, pSSM);
1815 return VINF_SUCCESS;
1816}
1817
1818
1819/**
1820 * Load a version 1.6 CPUMCTX structure.
1821 *
1822 * @returns VBox status code.
1823 * @param pVM VM Handle.
1824 * @param pCpumctx16 Version 1.6 CPUMCTX
1825 */
1826static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1827{
1828#define CPUMCTX16_LOADREG(RegName) \
1829 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1830
1831#define CPUMCTX16_LOADDRXREG(RegName) \
1832 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1833
1834#define CPUMCTX16_LOADHIDREG(RegName) \
1835 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1836 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1837 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1838
1839#define CPUMCTX16_LOADSEGREG(RegName) \
1840 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1841 CPUMCTX16_LOADHIDREG(RegName);
1842
1843 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1844
1845 CPUMCTX16_LOADREG(rax);
1846 CPUMCTX16_LOADREG(rbx);
1847 CPUMCTX16_LOADREG(rcx);
1848 CPUMCTX16_LOADREG(rdx);
1849 CPUMCTX16_LOADREG(rdi);
1850 CPUMCTX16_LOADREG(rsi);
1851 CPUMCTX16_LOADREG(rbp);
1852 CPUMCTX16_LOADREG(esp);
1853 CPUMCTX16_LOADREG(rip);
1854 CPUMCTX16_LOADREG(rflags);
1855
1856 CPUMCTX16_LOADSEGREG(cs);
1857 CPUMCTX16_LOADSEGREG(ds);
1858 CPUMCTX16_LOADSEGREG(es);
1859 CPUMCTX16_LOADSEGREG(fs);
1860 CPUMCTX16_LOADSEGREG(gs);
1861 CPUMCTX16_LOADSEGREG(ss);
1862
1863 CPUMCTX16_LOADREG(r8);
1864 CPUMCTX16_LOADREG(r9);
1865 CPUMCTX16_LOADREG(r10);
1866 CPUMCTX16_LOADREG(r11);
1867 CPUMCTX16_LOADREG(r12);
1868 CPUMCTX16_LOADREG(r13);
1869 CPUMCTX16_LOADREG(r14);
1870 CPUMCTX16_LOADREG(r15);
1871
1872 CPUMCTX16_LOADREG(cr0);
1873 CPUMCTX16_LOADREG(cr2);
1874 CPUMCTX16_LOADREG(cr3);
1875 CPUMCTX16_LOADREG(cr4);
1876
1877 CPUMCTX16_LOADDRXREG(0);
1878 CPUMCTX16_LOADDRXREG(1);
1879 CPUMCTX16_LOADDRXREG(2);
1880 CPUMCTX16_LOADDRXREG(3);
1881 CPUMCTX16_LOADDRXREG(4);
1882 CPUMCTX16_LOADDRXREG(5);
1883 CPUMCTX16_LOADDRXREG(6);
1884 CPUMCTX16_LOADDRXREG(7);
1885
1886 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1887 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1888 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1889 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1890
1891 CPUMCTX16_LOADREG(ldtr);
1892 CPUMCTX16_LOADREG(tr);
1893
1894 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1895
1896 CPUMCTX16_LOADREG(msrEFER);
1897 CPUMCTX16_LOADREG(msrSTAR);
1898 CPUMCTX16_LOADREG(msrPAT);
1899 CPUMCTX16_LOADREG(msrLSTAR);
1900 CPUMCTX16_LOADREG(msrCSTAR);
1901 CPUMCTX16_LOADREG(msrSFMASK);
1902 CPUMCTX16_LOADREG(msrKERNELGSBASE);
1903
1904 CPUMCTX16_LOADHIDREG(ldtr);
1905 CPUMCTX16_LOADHIDREG(tr);
1906
1907#undef CPUMCTX16_LOADSEGREG
1908#undef CPUMCTX16_LOADHIDREG
1909#undef CPUMCTX16_LOADDRXREG
1910#undef CPUMCTX16_LOADREG
1911}
1912
1913
1914/**
1915 * @copydoc FNSSMINTLOADPREP
1916 */
1917static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1918{
1919 pVM->cpum.s.fPendingRestore = true;
1920 return VINF_SUCCESS;
1921}
1922
1923
1924/**
1925 * @copydoc FNSSMINTLOADEXEC
1926 */
1927static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1928{
1929 /*
1930 * Validate version.
1931 */
1932 if ( uVersion != CPUM_SAVED_STATE_VERSION
1933 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1934 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1935 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1936 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1937 {
1938 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1939 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1940 }
1941
1942 if (uPass == SSM_PASS_FINAL)
1943 {
1944 /*
1945 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1946 * really old SSM file versions.)
1947 */
1948 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1949 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1950 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1951 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1952
1953 /*
1954 * Restore.
1955 */
1956 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1957 {
1958 PVMCPU pVCpu = &pVM->aCpus[i];
1959 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1960 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1961
1962 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1963 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1964 pVCpu->cpum.s.Hyper.esp = uESP;
1965 }
1966
1967 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1968 {
1969 CPUMCTX_VER1_6 cpumctx16;
1970 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1971 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1972
1973 /* Save the old cpumctx state into the new one. */
1974 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1975
1976 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1977 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1978 }
1979 else
1980 {
1981 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1982 {
1983 uint32_t cCpus;
1984 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1985 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1986 VERR_SSM_UNEXPECTED_DATA);
1987 }
1988 AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1989 || pVM->cCpus == 1,
1990 ("cCpus=%u\n", pVM->cCpus),
1991 VERR_SSM_UNEXPECTED_DATA);
1992
1993 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1994 {
1995 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1996 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1997 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1998 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1999 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2000 }
2001 }
2002 }
2003
2004 pVM->cpum.s.fPendingRestore = false;
2005
2006 /*
2007 * Guest CPUIDs.
2008 */
2009 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2010 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2011
2012 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2013 * actually required. */
2014
2015 /*
2016 * Restore the CPUID leaves.
2017 *
2018 * Note that we support restoring less than the current amount of standard
2019 * leaves because we've been allowed more is newer version of VBox.
2020 */
2021 uint32_t cElements;
2022 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2023 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2024 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2025 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2026
2027 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2028 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2029 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2030 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2031
2032 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2033 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2034 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2035 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2036
2037 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2038
2039 /*
2040 * Check that the basic cpuid id information is unchanged.
2041 */
2042 /** @todo we should check the 64 bits capabilities too! */
2043 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2044 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2045 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2046 uint32_t au32CpuIdSaved[8];
2047 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2048 if (RT_SUCCESS(rc))
2049 {
2050 /* Ignore CPU stepping. */
2051 au32CpuId[4] &= 0xfffffff0;
2052 au32CpuIdSaved[4] &= 0xfffffff0;
2053
2054 /* Ignore APIC ID (AMD specs). */
2055 au32CpuId[5] &= ~0xff000000;
2056 au32CpuIdSaved[5] &= ~0xff000000;
2057
2058 /* Ignore the number of Logical CPUs (AMD specs). */
2059 au32CpuId[5] &= ~0x00ff0000;
2060 au32CpuIdSaved[5] &= ~0x00ff0000;
2061
2062 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2063 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2064 | X86_CPUID_FEATURE_ECX_VMX
2065 | X86_CPUID_FEATURE_ECX_SMX
2066 | X86_CPUID_FEATURE_ECX_EST
2067 | X86_CPUID_FEATURE_ECX_TM2
2068 | X86_CPUID_FEATURE_ECX_CNTXID
2069 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2070 | X86_CPUID_FEATURE_ECX_PDCM
2071 | X86_CPUID_FEATURE_ECX_DCA
2072 | X86_CPUID_FEATURE_ECX_X2APIC
2073 );
2074 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2075 | X86_CPUID_FEATURE_ECX_VMX
2076 | X86_CPUID_FEATURE_ECX_SMX
2077 | X86_CPUID_FEATURE_ECX_EST
2078 | X86_CPUID_FEATURE_ECX_TM2
2079 | X86_CPUID_FEATURE_ECX_CNTXID
2080 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2081 | X86_CPUID_FEATURE_ECX_PDCM
2082 | X86_CPUID_FEATURE_ECX_DCA
2083 | X86_CPUID_FEATURE_ECX_X2APIC
2084 );
2085
2086 /* Make sure we don't forget to update the masks when enabling
2087 * features in the future.
2088 */
2089 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2090 ( X86_CPUID_FEATURE_ECX_DTES64
2091 | X86_CPUID_FEATURE_ECX_VMX
2092 | X86_CPUID_FEATURE_ECX_SMX
2093 | X86_CPUID_FEATURE_ECX_EST
2094 | X86_CPUID_FEATURE_ECX_TM2
2095 | X86_CPUID_FEATURE_ECX_CNTXID
2096 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2097 | X86_CPUID_FEATURE_ECX_PDCM
2098 | X86_CPUID_FEATURE_ECX_DCA
2099 | X86_CPUID_FEATURE_ECX_X2APIC
2100 )));
2101 /* do the compare */
2102 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2103 {
2104 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2105 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2106 "Saved=%.*Rhxs\n"
2107 "Real =%.*Rhxs\n",
2108 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2109 sizeof(au32CpuId), au32CpuId));
2110 else
2111 {
2112 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2113 "Saved=%.*Rhxs\n"
2114 "Real =%.*Rhxs\n",
2115 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2116 sizeof(au32CpuId), au32CpuId));
2117 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2118 }
2119 }
2120 }
2121
2122 return rc;
2123}
2124
2125
2126/**
2127 * @copydoc FNSSMINTLOADPREP
2128 */
2129static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2130{
2131 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2132 return VINF_SUCCESS;
2133
2134 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2135 if (pVM->cpum.s.fPendingRestore)
2136 {
2137 LogRel(("CPUM: Missing state!\n"));
2138 return VERR_INTERNAL_ERROR_2;
2139 }
2140
2141 return VINF_SUCCESS;
2142}
2143
2144
2145/**
2146 * Checks if the CPUM state restore is still pending.
2147 *
2148 * @returns true / false.
2149 * @param pVM The VM handle.
2150 */
2151VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2152{
2153 return pVM->cpum.s.fPendingRestore;
2154}
2155
2156
2157/**
2158 * Formats the EFLAGS value into mnemonics.
2159 *
2160 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2161 * @param efl The EFLAGS value.
2162 */
2163static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2164{
2165 /*
2166 * Format the flags.
2167 */
2168 static const struct
2169 {
2170 const char *pszSet; const char *pszClear; uint32_t fFlag;
2171 } s_aFlags[] =
2172 {
2173 { "vip",NULL, X86_EFL_VIP },
2174 { "vif",NULL, X86_EFL_VIF },
2175 { "ac", NULL, X86_EFL_AC },
2176 { "vm", NULL, X86_EFL_VM },
2177 { "rf", NULL, X86_EFL_RF },
2178 { "nt", NULL, X86_EFL_NT },
2179 { "ov", "nv", X86_EFL_OF },
2180 { "dn", "up", X86_EFL_DF },
2181 { "ei", "di", X86_EFL_IF },
2182 { "tf", NULL, X86_EFL_TF },
2183 { "nt", "pl", X86_EFL_SF },
2184 { "nz", "zr", X86_EFL_ZF },
2185 { "ac", "na", X86_EFL_AF },
2186 { "po", "pe", X86_EFL_PF },
2187 { "cy", "nc", X86_EFL_CF },
2188 };
2189 char *psz = pszEFlags;
2190 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2191 {
2192 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2193 if (pszAdd)
2194 {
2195 strcpy(psz, pszAdd);
2196 psz += strlen(pszAdd);
2197 *psz++ = ' ';
2198 }
2199 }
2200 psz[-1] = '\0';
2201}
2202
2203
2204/**
2205 * Formats a full register dump.
2206 *
2207 * @param pVM VM Handle.
2208 * @param pCtx The context to format.
2209 * @param pCtxCore The context core to format.
2210 * @param pHlp Output functions.
2211 * @param enmType The dump type.
2212 * @param pszPrefix Register name prefix.
2213 */
2214static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2215{
2216 /*
2217 * Format the EFLAGS.
2218 */
2219 uint32_t efl = pCtxCore->eflags.u32;
2220 char szEFlags[80];
2221 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2222
2223 /*
2224 * Format the registers.
2225 */
2226 switch (enmType)
2227 {
2228 case CPUMDUMPTYPE_TERSE:
2229 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2230 pHlp->pfnPrintf(pHlp,
2231 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2232 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2233 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2234 "%sr14=%016RX64 %sr15=%016RX64\n"
2235 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2236 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2237 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2238 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2239 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2240 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2241 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2242 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2243 else
2244 pHlp->pfnPrintf(pHlp,
2245 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2246 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2247 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2248 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2249 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2250 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2251 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2252 break;
2253
2254 case CPUMDUMPTYPE_DEFAULT:
2255 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2256 pHlp->pfnPrintf(pHlp,
2257 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2258 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2259 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2260 "%sr14=%016RX64 %sr15=%016RX64\n"
2261 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2262 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2263 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2264 ,
2265 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2266 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2267 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2268 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2269 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2270 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2271 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2272 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2273 else
2274 pHlp->pfnPrintf(pHlp,
2275 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2276 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2277 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2278 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2279 ,
2280 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2281 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2282 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2283 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2284 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2285 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2286 break;
2287
2288 case CPUMDUMPTYPE_VERBOSE:
2289 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2290 pHlp->pfnPrintf(pHlp,
2291 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2292 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2293 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2294 "%sr14=%016RX64 %sr15=%016RX64\n"
2295 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2296 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2297 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2298 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2299 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2300 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2301 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2302 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2303 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2304 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2305 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2306 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2307 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2308 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2309 ,
2310 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2311 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2312 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2313 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2314 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2315 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2316 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2317 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2318 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2319 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2320 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2321 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2322 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2323 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2324 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2325 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2326 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2327 else
2328 pHlp->pfnPrintf(pHlp,
2329 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2330 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2331 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2332 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2333 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2334 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2335 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2336 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2337 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2338 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2339 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2340 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2341 ,
2342 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2343 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2344 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2345 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2346 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2347 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2348 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2349 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2350 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2351 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2352 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2353 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2354
2355 pHlp->pfnPrintf(pHlp,
2356 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2357 "%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2358 ,
2359 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2360 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2361 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2362 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2363 );
2364 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2365 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2366 {
2367 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2368 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2369 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2370 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2371 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2372 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2373 /** @todo This isn't entirenly correct and needs more work! */
2374 pHlp->pfnPrintf(pHlp,
2375 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2376 pszPrefix, iST, pszPrefix, iFPR,
2377 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2378 uTag, chSign, iInteger, u64Fraction, uExponent);
2379 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2380 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2381 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2382 else
2383 pHlp->pfnPrintf(pHlp, "\n");
2384 }
2385 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2386 pHlp->pfnPrintf(pHlp,
2387 iXMM & 1
2388 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2389 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2390 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2391 pCtx->fpu.aXMM[iXMM].au32[3],
2392 pCtx->fpu.aXMM[iXMM].au32[2],
2393 pCtx->fpu.aXMM[iXMM].au32[1],
2394 pCtx->fpu.aXMM[iXMM].au32[0]);
2395 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2396 if (pCtx->fpu.au32RsrvdRest[i])
2397 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2398 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2399
2400 pHlp->pfnPrintf(pHlp,
2401 "%sEFER =%016RX64\n"
2402 "%sPAT =%016RX64\n"
2403 "%sSTAR =%016RX64\n"
2404 "%sCSTAR =%016RX64\n"
2405 "%sLSTAR =%016RX64\n"
2406 "%sSFMASK =%016RX64\n"
2407 "%sKERNELGSBASE =%016RX64\n",
2408 pszPrefix, pCtx->msrEFER,
2409 pszPrefix, pCtx->msrPAT,
2410 pszPrefix, pCtx->msrSTAR,
2411 pszPrefix, pCtx->msrCSTAR,
2412 pszPrefix, pCtx->msrLSTAR,
2413 pszPrefix, pCtx->msrSFMASK,
2414 pszPrefix, pCtx->msrKERNELGSBASE);
2415 break;
2416 }
2417}
2418
2419
2420/**
2421 * Display all cpu states and any other cpum info.
2422 *
2423 * @param pVM VM Handle.
2424 * @param pHlp The info helper functions.
2425 * @param pszArgs Arguments, ignored.
2426 */
2427static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2428{
2429 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2430 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2431 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2432 cpumR3InfoHost(pVM, pHlp, pszArgs);
2433}
2434
2435
2436/**
2437 * Parses the info argument.
2438 *
2439 * The argument starts with 'verbose', 'terse' or 'default' and then
2440 * continues with the comment string.
2441 *
2442 * @param pszArgs The pointer to the argument string.
2443 * @param penmType Where to store the dump type request.
2444 * @param ppszComment Where to store the pointer to the comment string.
2445 */
2446static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
2447{
2448 if (!pszArgs)
2449 {
2450 *penmType = CPUMDUMPTYPE_DEFAULT;
2451 *ppszComment = "";
2452 }
2453 else
2454 {
2455 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2456 {
2457 pszArgs += 5;
2458 *penmType = CPUMDUMPTYPE_VERBOSE;
2459 }
2460 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2461 {
2462 pszArgs += 5;
2463 *penmType = CPUMDUMPTYPE_TERSE;
2464 }
2465 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2466 {
2467 pszArgs += 7;
2468 *penmType = CPUMDUMPTYPE_DEFAULT;
2469 }
2470 else
2471 *penmType = CPUMDUMPTYPE_DEFAULT;
2472 *ppszComment = RTStrStripL(pszArgs);
2473 }
2474}
2475
2476
2477/**
2478 * Display the guest cpu state.
2479 *
2480 * @param pVM VM Handle.
2481 * @param pHlp The info helper functions.
2482 * @param pszArgs Arguments, ignored.
2483 */
2484static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2485{
2486 CPUMDUMPTYPE enmType;
2487 const char *pszComment;
2488 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2489
2490 /* @todo SMP support! */
2491 PVMCPU pVCpu = VMMGetCpu(pVM);
2492 if (!pVCpu)
2493 pVCpu = &pVM->aCpus[0];
2494
2495 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2496
2497 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2498 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2499}
2500
2501
2502/**
2503 * Display the current guest instruction
2504 *
2505 * @param pVM VM Handle.
2506 * @param pHlp The info helper functions.
2507 * @param pszArgs Arguments, ignored.
2508 */
2509static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2510{
2511 char szInstruction[256];
2512 /* @todo SMP support! */
2513 PVMCPU pVCpu = VMMGetCpu(pVM);
2514 if (!pVCpu)
2515 pVCpu = &pVM->aCpus[0];
2516
2517 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2518 if (RT_SUCCESS(rc))
2519 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2520}
2521
2522
2523/**
2524 * Display the hypervisor cpu state.
2525 *
2526 * @param pVM VM Handle.
2527 * @param pHlp The info helper functions.
2528 * @param pszArgs Arguments, ignored.
2529 */
2530static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2531{
2532 CPUMDUMPTYPE enmType;
2533 const char *pszComment;
2534 /* @todo SMP */
2535 PVMCPU pVCpu = &pVM->aCpus[0];
2536
2537 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2538 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2539 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2540 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2541}
2542
2543
2544/**
2545 * Display the host cpu state.
2546 *
2547 * @param pVM VM Handle.
2548 * @param pHlp The info helper functions.
2549 * @param pszArgs Arguments, ignored.
2550 */
2551static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2552{
2553 CPUMDUMPTYPE enmType;
2554 const char *pszComment;
2555 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2556 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2557
2558 /*
2559 * Format the EFLAGS.
2560 */
2561 /* @todo SMP */
2562 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2563#if HC_ARCH_BITS == 32
2564 uint32_t efl = pCtx->eflags.u32;
2565#else
2566 uint64_t efl = pCtx->rflags;
2567#endif
2568 char szEFlags[80];
2569 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2570
2571 /*
2572 * Format the registers.
2573 */
2574#if HC_ARCH_BITS == 32
2575# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2576 if (!(pCtx->efer & MSR_K6_EFER_LMA))
2577# endif
2578 {
2579 pHlp->pfnPrintf(pHlp,
2580 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2581 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2582 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2583 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2584 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2585 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2586 ,
2587 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2588 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2589 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2590 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2591 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2592 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2593 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2594 }
2595# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2596 else
2597# endif
2598#endif
2599#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2600 {
2601 pHlp->pfnPrintf(pHlp,
2602 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2603 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2604 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2605 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2606 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2607 "r14=%016RX64 r15=%016RX64\n"
2608 "iopl=%d %31s\n"
2609 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2610 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2611 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2612 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2613 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2614 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2615 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2616 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2617 ,
2618 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2619 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2620 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2621 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2622 pCtx->r11, pCtx->r12, pCtx->r13,
2623 pCtx->r14, pCtx->r15,
2624 X86_EFL_GET_IOPL(efl), szEFlags,
2625 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2626 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2627 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2628 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2629 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2630 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2631 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2632 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2633 }
2634#endif
2635}
2636
2637
2638/**
2639 * Get L1 cache / TLS associativity.
2640 */
2641static const char *getCacheAss(unsigned u, char *pszBuf)
2642{
2643 if (u == 0)
2644 return "res0 ";
2645 if (u == 1)
2646 return "direct";
2647 if (u >= 256)
2648 return "???";
2649
2650 RTStrPrintf(pszBuf, 16, "%d way", u);
2651 return pszBuf;
2652}
2653
2654
2655/**
2656 * Get L2 cache soociativity.
2657 */
2658const char *getL2CacheAss(unsigned u)
2659{
2660 switch (u)
2661 {
2662 case 0: return "off ";
2663 case 1: return "direct";
2664 case 2: return "2 way ";
2665 case 3: return "res3 ";
2666 case 4: return "4 way ";
2667 case 5: return "res5 ";
2668 case 6: return "8 way "; case 7: return "res7 ";
2669 case 8: return "16 way";
2670 case 9: return "res9 ";
2671 case 10: return "res10 ";
2672 case 11: return "res11 ";
2673 case 12: return "res12 ";
2674 case 13: return "res13 ";
2675 case 14: return "res14 ";
2676 case 15: return "fully ";
2677 default:
2678 return "????";
2679 }
2680}
2681
2682
2683/**
2684 * Display the guest CpuId leaves.
2685 *
2686 * @param pVM VM Handle.
2687 * @param pHlp The info helper functions.
2688 * @param pszArgs "terse", "default" or "verbose".
2689 */
2690static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2691{
2692 /*
2693 * Parse the argument.
2694 */
2695 unsigned iVerbosity = 1;
2696 if (pszArgs)
2697 {
2698 pszArgs = RTStrStripL(pszArgs);
2699 if (!strcmp(pszArgs, "terse"))
2700 iVerbosity--;
2701 else if (!strcmp(pszArgs, "verbose"))
2702 iVerbosity++;
2703 }
2704
2705 /*
2706 * Start cracking.
2707 */
2708 CPUMCPUID Host;
2709 CPUMCPUID Guest;
2710 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2711
2712 pHlp->pfnPrintf(pHlp,
2713 " RAW Standard CPUIDs\n"
2714 " Function eax ebx ecx edx\n");
2715 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2716 {
2717 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2718 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2719
2720 pHlp->pfnPrintf(pHlp,
2721 "Gst: %08x %08x %08x %08x %08x%s\n"
2722 "Hst: %08x %08x %08x %08x\n",
2723 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2724 i <= cStdMax ? "" : "*",
2725 Host.eax, Host.ebx, Host.ecx, Host.edx);
2726 }
2727
2728 /*
2729 * If verbose, decode it.
2730 */
2731 if (iVerbosity)
2732 {
2733 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2734 pHlp->pfnPrintf(pHlp,
2735 "Name: %.04s%.04s%.04s\n"
2736 "Supports: 0-%x\n",
2737 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2738 }
2739
2740 /*
2741 * Get Features.
2742 */
2743 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2744 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2745 pVM->cpum.s.aGuestCpuIdStd[0].edx);
2746 if (cStdMax >= 1 && iVerbosity)
2747 {
2748 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2749 uint32_t uEAX = Guest.eax;
2750
2751 pHlp->pfnPrintf(pHlp,
2752 "Family: %d \tExtended: %d \tEffective: %d\n"
2753 "Model: %d \tExtended: %d \tEffective: %d\n"
2754 "Stepping: %d\n"
2755 "Type: %d\n"
2756 "APIC ID: %#04x\n"
2757 "Logical CPUs: %d\n"
2758 "CLFLUSH Size: %d\n"
2759 "Brand ID: %#04x\n",
2760 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2761 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2762 ASMGetCpuStepping(uEAX),
2763 (uEAX >> 12) & 3,
2764 (Guest.ebx >> 24) & 0xff,
2765 (Guest.ebx >> 16) & 0xff,
2766 (Guest.ebx >> 8) & 0xff,
2767 (Guest.ebx >> 0) & 0xff);
2768 if (iVerbosity == 1)
2769 {
2770 uint32_t uEDX = Guest.edx;
2771 pHlp->pfnPrintf(pHlp, "Features EDX: ");
2772 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2773 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2774 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2775 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2776 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2777 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2778 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2779 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2780 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2781 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2782 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2783 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2784 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2785 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2786 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2787 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2788 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2789 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2790 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2791 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2792 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2793 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2794 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2795 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2796 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2797 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2798 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2799 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2800 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2801 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2802 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2803 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2804 pHlp->pfnPrintf(pHlp, "\n");
2805
2806 uint32_t uECX = Guest.ecx;
2807 pHlp->pfnPrintf(pHlp, "Features ECX: ");
2808 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2809 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2810 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2811 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2812 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2813 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2814 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2815 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2816 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2817 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2818 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2819 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2820 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2821 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2822 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2823 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2824 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2825 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2826 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2827 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2828 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2829 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2830 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2831 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2832 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2833 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2834 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2835 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2836 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2837 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2838 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2839 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2840 pHlp->pfnPrintf(pHlp, "\n");
2841 }
2842 else
2843 {
2844 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2845
2846 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2847 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2848 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2849 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2850
2851 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2852 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2853 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2854 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2855 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2856 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2857 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2858 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2859 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2860 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2861 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2862 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2863 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2864 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2865 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2866 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2867 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2868 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2869 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2870 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2871 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2872 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2873 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2874 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2875 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2876 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2877 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2878 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2879 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2880 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2881 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2882 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2883 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2884
2885 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2886 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2887 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2888 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2889 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2890 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2891 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2892 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2893 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2894 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2895 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2896 pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2897 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2898 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2899 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2900 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2901 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2902 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2903 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2904 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2905 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2906 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2907 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2908 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2909 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2910 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2911 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2912 }
2913 }
2914 if (cStdMax >= 2 && iVerbosity)
2915 {
2916 /** @todo */
2917 }
2918
2919 /*
2920 * Extended.
2921 * Implemented after AMD specs.
2922 */
2923 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2924
2925 pHlp->pfnPrintf(pHlp,
2926 "\n"
2927 " RAW Extended CPUIDs\n"
2928 " Function eax ebx ecx edx\n");
2929 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2930 {
2931 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2932 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2933
2934 pHlp->pfnPrintf(pHlp,
2935 "Gst: %08x %08x %08x %08x %08x%s\n"
2936 "Hst: %08x %08x %08x %08x\n",
2937 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2938 i <= cExtMax ? "" : "*",
2939 Host.eax, Host.ebx, Host.ecx, Host.edx);
2940 }
2941
2942 /*
2943 * Understandable output
2944 */
2945 if (iVerbosity)
2946 {
2947 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2948 pHlp->pfnPrintf(pHlp,
2949 "Ext Name: %.4s%.4s%.4s\n"
2950 "Ext Supports: 0x80000000-%#010x\n",
2951 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2952 }
2953
2954 if (iVerbosity && cExtMax >= 1)
2955 {
2956 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2957 uint32_t uEAX = Guest.eax;
2958 pHlp->pfnPrintf(pHlp,
2959 "Family: %d \tExtended: %d \tEffective: %d\n"
2960 "Model: %d \tExtended: %d \tEffective: %d\n"
2961 "Stepping: %d\n"
2962 "Brand ID: %#05x\n",
2963 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2964 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2965 ASMGetCpuStepping(uEAX),
2966 Guest.ebx & 0xfff);
2967
2968 if (iVerbosity == 1)
2969 {
2970 uint32_t uEDX = Guest.edx;
2971 pHlp->pfnPrintf(pHlp, "Features EDX: ");
2972 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2973 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2974 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2975 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2976 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2977 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2978 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2979 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2980 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2981 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2982 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2983 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2984 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2985 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2986 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2987 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2988 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2989 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2990 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2991 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2992 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2993 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2994 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2995 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2996 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2997 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2998 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2999 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3000 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3001 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3002 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3003 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3004 pHlp->pfnPrintf(pHlp, "\n");
3005
3006 uint32_t uECX = Guest.ecx;
3007 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3008 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3009 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3010 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3011 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3012 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3013 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3014 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3015 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3016 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3017 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3018 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3019 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3020 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3021 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3022 for (unsigned iBit = 5; iBit < 32; iBit++)
3023 if (uECX & RT_BIT(iBit))
3024 pHlp->pfnPrintf(pHlp, " %d", iBit);
3025 pHlp->pfnPrintf(pHlp, "\n");
3026 }
3027 else
3028 {
3029 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3030
3031 uint32_t uEdxGst = Guest.edx;
3032 uint32_t uEdxHst = Host.edx;
3033 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3034 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3035 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3036 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3037 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3038 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3039 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3040 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3041 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3042 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3043 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3044 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3045 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3046 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3047 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3048 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3049 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3050 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3051 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3052 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3053 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3054 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3055 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3056 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3057 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3058 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3059 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3060 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3061 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3062 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3063 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3064 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3065 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3066
3067 uint32_t uEcxGst = Guest.ecx;
3068 uint32_t uEcxHst = Host.ecx;
3069 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3070 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3071 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3072 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3073 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3074 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3075 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3076 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3077 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3078 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3079 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3080 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3081 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3082 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3083 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3084 }
3085 }
3086
3087 if (iVerbosity && cExtMax >= 2)
3088 {
3089 char szString[4*4*3+1] = {0};
3090 uint32_t *pu32 = (uint32_t *)szString;
3091 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3092 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3093 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3094 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3095 if (cExtMax >= 3)
3096 {
3097 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3098 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3099 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3100 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3101 }
3102 if (cExtMax >= 4)
3103 {
3104 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3105 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3106 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3107 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3108 }
3109 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3110 }
3111
3112 if (iVerbosity && cExtMax >= 5)
3113 {
3114 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3115 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3116 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3117 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3118 char sz1[32];
3119 char sz2[32];
3120
3121 pHlp->pfnPrintf(pHlp,
3122 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3123 "TLB 2/4M Data: %s %3d entries\n",
3124 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3125 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3126 pHlp->pfnPrintf(pHlp,
3127 "TLB 4K Instr/Uni: %s %3d entries\n"
3128 "TLB 4K Data: %s %3d entries\n",
3129 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3130 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3131 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3132 "L1 Instr Cache Lines Per Tag: %d\n"
3133 "L1 Instr Cache Associativity: %s\n"
3134 "L1 Instr Cache Size: %d KB\n",
3135 (uEDX >> 0) & 0xff,
3136 (uEDX >> 8) & 0xff,
3137 getCacheAss((uEDX >> 16) & 0xff, sz1),
3138 (uEDX >> 24) & 0xff);
3139 pHlp->pfnPrintf(pHlp,
3140 "L1 Data Cache Line Size: %d bytes\n"
3141 "L1 Data Cache Lines Per Tag: %d\n"
3142 "L1 Data Cache Associativity: %s\n"
3143 "L1 Data Cache Size: %d KB\n",
3144 (uECX >> 0) & 0xff,
3145 (uECX >> 8) & 0xff,
3146 getCacheAss((uECX >> 16) & 0xff, sz1),
3147 (uECX >> 24) & 0xff);
3148 }
3149
3150 if (iVerbosity && cExtMax >= 6)
3151 {
3152 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3153 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3154 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3155
3156 pHlp->pfnPrintf(pHlp,
3157 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3158 "L2 TLB 2/4M Data: %s %4d entries\n",
3159 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3160 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3161 pHlp->pfnPrintf(pHlp,
3162 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3163 "L2 TLB 4K Data: %s %4d entries\n",
3164 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3165 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3166 pHlp->pfnPrintf(pHlp,
3167 "L2 Cache Line Size: %d bytes\n"
3168 "L2 Cache Lines Per Tag: %d\n"
3169 "L2 Cache Associativity: %s\n"
3170 "L2 Cache Size: %d KB\n",
3171 (uEDX >> 0) & 0xff,
3172 (uEDX >> 8) & 0xf,
3173 getL2CacheAss((uEDX >> 12) & 0xf),
3174 (uEDX >> 16) & 0xffff);
3175 }
3176
3177 if (iVerbosity && cExtMax >= 7)
3178 {
3179 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3180
3181 pHlp->pfnPrintf(pHlp, "APM Features: ");
3182 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3183 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3184 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3185 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3186 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3187 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3188 for (unsigned iBit = 6; iBit < 32; iBit++)
3189 if (uEDX & RT_BIT(iBit))
3190 pHlp->pfnPrintf(pHlp, " %d", iBit);
3191 pHlp->pfnPrintf(pHlp, "\n");
3192 }
3193
3194 if (iVerbosity && cExtMax >= 8)
3195 {
3196 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3197 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3198
3199 pHlp->pfnPrintf(pHlp,
3200 "Physical Address Width: %d bits\n"
3201 "Virtual Address Width: %d bits\n",
3202 (uEAX >> 0) & 0xff,
3203 (uEAX >> 8) & 0xff);
3204 pHlp->pfnPrintf(pHlp,
3205 "Physical Core Count: %d\n",
3206 (uECX >> 0) & 0xff);
3207 }
3208
3209
3210 /*
3211 * Centaur.
3212 */
3213 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3214
3215 pHlp->pfnPrintf(pHlp,
3216 "\n"
3217 " RAW Centaur CPUIDs\n"
3218 " Function eax ebx ecx edx\n");
3219 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3220 {
3221 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3222 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3223
3224 pHlp->pfnPrintf(pHlp,
3225 "Gst: %08x %08x %08x %08x %08x%s\n"
3226 "Hst: %08x %08x %08x %08x\n",
3227 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3228 i <= cCentaurMax ? "" : "*",
3229 Host.eax, Host.ebx, Host.ecx, Host.edx);
3230 }
3231
3232 /*
3233 * Understandable output
3234 */
3235 if (iVerbosity)
3236 {
3237 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3238 pHlp->pfnPrintf(pHlp,
3239 "Centaur Supports: 0xc0000000-%#010x\n",
3240 Guest.eax);
3241 }
3242
3243 if (iVerbosity && cCentaurMax >= 1)
3244 {
3245 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3246 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3247 uint32_t uEdxHst = Host.edx;
3248
3249 if (iVerbosity == 1)
3250 {
3251 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3252 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3253 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3254 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3255 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3256 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3257 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3258 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3259 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3260 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3261 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3262 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3263 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3264 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3265 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3266 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3267 for (unsigned iBit = 14; iBit < 32; iBit++)
3268 if (uEdxGst & RT_BIT(iBit))
3269 pHlp->pfnPrintf(pHlp, " %d", iBit);
3270 pHlp->pfnPrintf(pHlp, "\n");
3271 }
3272 else
3273 {
3274 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3275 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3276 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3277 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3278 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3279 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3280 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3281 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3282 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3283 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3284 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3285 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3286 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3287 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3288 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3289 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3290 for (unsigned iBit = 14; iBit < 32; iBit++)
3291 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3292 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3293 pHlp->pfnPrintf(pHlp, "\n");
3294 }
3295 }
3296}
3297
3298
3299/**
3300 * Structure used when disassembling and instructions in DBGF.
3301 * This is used so the reader function can get the stuff it needs.
3302 */
3303typedef struct CPUMDISASSTATE
3304{
3305 /** Pointer to the CPU structure. */
3306 PDISCPUSTATE pCpu;
3307 /** The VM handle. */
3308 PVM pVM;
3309 /** The VMCPU handle. */
3310 PVMCPU pVCpu;
3311 /** Pointer to the first byte in the segemnt. */
3312 RTGCUINTPTR GCPtrSegBase;
3313 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3314 RTGCUINTPTR GCPtrSegEnd;
3315 /** The size of the segment minus 1. */
3316 RTGCUINTPTR cbSegLimit;
3317 /** Pointer to the current page - R3 Ptr. */
3318 void const *pvPageR3;
3319 /** Pointer to the current page - GC Ptr. */
3320 RTGCPTR pvPageGC;
3321 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3322 PGMPAGEMAPLOCK PageMapLock;
3323 /** Whether the PageMapLock is valid or not. */
3324 bool fLocked;
3325 /** 64 bits mode or not. */
3326 bool f64Bits;
3327} CPUMDISASSTATE, *PCPUMDISASSTATE;
3328
3329
3330/**
3331 * Instruction reader.
3332 *
3333 * @returns VBox status code.
3334 * @param PtrSrc Address to read from.
3335 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3336 * @param pu8Dst Where to store the bytes.
3337 * @param cbRead Number of bytes to read.
3338 * @param uDisCpu Pointer to the disassembler cpu state.
3339 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
3340 */
3341static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
3342{
3343 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3344 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3345 Assert(cbRead > 0);
3346 for (;;)
3347 {
3348 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3349
3350 /* Need to update the page translation? */
3351 if ( !pState->pvPageR3
3352 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3353 {
3354 int rc = VINF_SUCCESS;
3355
3356 /* translate the address */
3357 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3358 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3359 && !HWACCMIsEnabled(pState->pVM))
3360 {
3361 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3362 if (!pState->pvPageR3)
3363 rc = VERR_INVALID_POINTER;
3364 }
3365 else
3366 {
3367 /* Release mapping lock previously acquired. */
3368 if (pState->fLocked)
3369 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3370 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3371 pState->fLocked = RT_SUCCESS_NP(rc);
3372 }
3373 if (RT_FAILURE(rc))
3374 {
3375 pState->pvPageR3 = NULL;
3376 return rc;
3377 }
3378 }
3379
3380 /* check the segemnt limit */
3381 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3382 return VERR_OUT_OF_SELECTOR_BOUNDS;
3383
3384 /* calc how much we can read */
3385 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3386 if (!pState->f64Bits)
3387 {
3388 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3389 if (cb > cbSeg && cbSeg)
3390 cb = cbSeg;
3391 }
3392 if (cb > cbRead)
3393 cb = cbRead;
3394
3395 /* read and advance */
3396 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3397 cbRead -= cb;
3398 if (!cbRead)
3399 return VINF_SUCCESS;
3400 pu8Dst += cb;
3401 PtrSrc += cb;
3402 }
3403}
3404
3405
3406/**
3407 * Disassemble an instruction and return the information in the provided structure.
3408 *
3409 * @returns VBox status code.
3410 * @param pVM VM Handle
3411 * @param pVCpu VMCPU Handle
3412 * @param pCtx CPU context
3413 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
3414 * @param pCpu Disassembly state
3415 * @param pszPrefix String prefix for logging (debug only)
3416 *
3417 */
3418VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3419{
3420 CPUMDISASSTATE State;
3421 int rc;
3422
3423 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3424 State.pCpu = pCpu;
3425 State.pvPageGC = 0;
3426 State.pvPageR3 = NULL;
3427 State.pVM = pVM;
3428 State.pVCpu = pVCpu;
3429 State.fLocked = false;
3430 State.f64Bits = false;
3431
3432 /*
3433 * Get selector information.
3434 */
3435 if ( (pCtx->cr0 & X86_CR0_PE)
3436 && pCtx->eflags.Bits.u1VM == 0)
3437 {
3438 if (CPUMAreHiddenSelRegsValid(pVM))
3439 {
3440 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3441 State.GCPtrSegBase = pCtx->csHid.u64Base;
3442 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3443 State.cbSegLimit = pCtx->csHid.u32Limit;
3444 pCpu->mode = (State.f64Bits)
3445 ? CPUMODE_64BIT
3446 : pCtx->csHid.Attr.n.u1DefBig
3447 ? CPUMODE_32BIT
3448 : CPUMODE_16BIT;
3449 }
3450 else
3451 {
3452 DBGFSELINFO SelInfo;
3453
3454 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3455 if (RT_FAILURE(rc))
3456 {
3457 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3458 return rc;
3459 }
3460
3461 /*
3462 * Validate the selector.
3463 */
3464 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3465 if (RT_FAILURE(rc))
3466 {
3467 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3468 return rc;
3469 }
3470 State.GCPtrSegBase = SelInfo.GCPtrBase;
3471 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3472 State.cbSegLimit = SelInfo.cbLimit;
3473 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3474 }
3475 }
3476 else
3477 {
3478 /* real or V86 mode */
3479 pCpu->mode = CPUMODE_16BIT;
3480 State.GCPtrSegBase = pCtx->cs * 16;
3481 State.GCPtrSegEnd = 0xFFFFFFFF;
3482 State.cbSegLimit = 0xFFFFFFFF;
3483 }
3484
3485 /*
3486 * Disassemble the instruction.
3487 */
3488 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3489 pCpu->apvUserData[0] = &State;
3490
3491 uint32_t cbInstr;
3492#ifndef LOG_ENABLED
3493 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3494 if (RT_SUCCESS(rc))
3495 {
3496#else
3497 char szOutput[160];
3498 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3499 if (RT_SUCCESS(rc))
3500 {
3501 /* log it */
3502 if (pszPrefix)
3503 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3504 else
3505 Log(("%s", szOutput));
3506#endif
3507 rc = VINF_SUCCESS;
3508 }
3509 else
3510 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3511
3512 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
3513 if (State.fLocked)
3514 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3515
3516 return rc;
3517}
3518
3519#ifdef DEBUG
3520
3521/**
3522 * Disassemble an instruction and dump it to the log
3523 *
3524 * @returns VBox status code.
3525 * @param pVM VM Handle
3526 * @param pVCpu VMCPU Handle
3527 * @param pCtx CPU context
3528 * @param pc GC instruction pointer
3529 * @param pszPrefix String prefix for logging
3530 *
3531 * @deprecated Use DBGFR3DisasInstrCurrentLog().
3532 */
3533VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3534{
3535 DISCPUSTATE Cpu;
3536 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3537}
3538
3539
3540/**
3541 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
3542 *
3543 * @internal
3544 */
3545VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3546{
3547 /** @todo SMP support!! */
3548 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3549}
3550
3551#endif /* DEBUG */
3552
3553/**
3554 * API for controlling a few of the CPU features found in CR4.
3555 *
3556 * Currently only X86_CR4_TSD is accepted as input.
3557 *
3558 * @returns VBox status code.
3559 *
3560 * @param pVM The VM handle.
3561 * @param fOr The CR4 OR mask.
3562 * @param fAnd The CR4 AND mask.
3563 */
3564VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3565{
3566 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3567 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3568
3569 pVM->cpum.s.CR4.OrMask &= fAnd;
3570 pVM->cpum.s.CR4.OrMask |= fOr;
3571
3572 return VINF_SUCCESS;
3573}
3574
3575
3576/**
3577 * Gets a pointer to the array of standard CPUID leaves.
3578 *
3579 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3580 *
3581 * @returns Pointer to the standard CPUID leaves (read-only).
3582 * @param pVM The VM handle.
3583 * @remark Intended for PATM.
3584 */
3585VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3586{
3587 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3588}
3589
3590
3591/**
3592 * Gets a pointer to the array of extended CPUID leaves.
3593 *
3594 * CPUMGetGuestCpuIdExtMax() give the size of the array.
3595 *
3596 * @returns Pointer to the extended CPUID leaves (read-only).
3597 * @param pVM The VM handle.
3598 * @remark Intended for PATM.
3599 */
3600VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3601{
3602 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3603}
3604
3605
3606/**
3607 * Gets a pointer to the array of centaur CPUID leaves.
3608 *
3609 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3610 *
3611 * @returns Pointer to the centaur CPUID leaves (read-only).
3612 * @param pVM The VM handle.
3613 * @remark Intended for PATM.
3614 */
3615VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3616{
3617 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3618}
3619
3620
3621/**
3622 * Gets a pointer to the default CPUID leaf.
3623 *
3624 * @returns Pointer to the default CPUID leaf (read-only).
3625 * @param pVM The VM handle.
3626 * @remark Intended for PATM.
3627 */
3628VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3629{
3630 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3631}
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