1 | ; $Id: ASMCpuIdExSlow.asm 98103 2023-01-17 14:15:46Z vboxsync $
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2 | ;; @file
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3 | ; IPRT - ASMCpuIdExSlow().
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4 | ;
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5 |
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6 | ;
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7 | ; Copyright (C) 2012-2023 Oracle and/or its affiliates.
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8 | ;
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9 | ; This file is part of VirtualBox base platform packages, as
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10 | ; available from https://www.virtualbox.org.
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11 | ;
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12 | ; This program is free software; you can redistribute it and/or
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13 | ; modify it under the terms of the GNU General Public License
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14 | ; as published by the Free Software Foundation, in version 3 of the
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15 | ; License.
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16 | ;
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17 | ; This program is distributed in the hope that it will be useful, but
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18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | ; General Public License for more details.
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21 | ;
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22 | ; You should have received a copy of the GNU General Public License
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23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | ;
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25 | ; The contents of this file may alternatively be used under the terms
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26 | ; of the Common Development and Distribution License Version 1.0
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27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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28 | ; in the VirtualBox distribution, in which case the provisions of the
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29 | ; CDDL are applicable instead of those of the GPL.
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30 | ;
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31 | ; You may elect to license modified versions of this file under the
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32 | ; terms and conditions of either the GPL or the CDDL or both.
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33 | ;
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34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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35 | ;
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36 |
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37 | ;*******************************************************************************
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38 | ;* Header Files *
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39 | ;*******************************************************************************
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40 | %include "iprt/asmdefs.mac"
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41 |
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42 | BEGINCODE
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43 |
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44 | ;;
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45 | ; CPUID with EAX and ECX inputs, returning ALL output registers.
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46 | ;
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47 | ; @param uOperator x86:ebp+8 gcc:rdi msc:rcx
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48 | ; @param uInitEBX x86:ebp+c gcc:rsi msc:rdx
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49 | ; @param uInitECX x86:ebp+10 gcc:rdx msc:r8
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50 | ; @param uInitEDX x86:ebp+14 gcc:rcx msc:r9
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51 | ; @param pvEAX x86:ebp+18 gcc:r8 msc:rbp+30h
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52 | ; @param pvEBX x86:ebp+1c gcc:r9 msc:rbp+38h
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53 | ; @param pvECX x86:ebp+20 gcc:rbp+10h msc:rbp+40h
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54 | ; @param pvEDX x86:ebp+24 gcc:rbp+18h msc:rbp+48h
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55 | ;
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56 | ; @returns EAX
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57 | ;
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58 | RT_BEGINPROC ASMCpuIdExSlow
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59 | push xBP
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60 | mov xBP, xSP
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61 | push xBX
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62 | %if ARCH_BITS == 32
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63 | push edi
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64 | %elif ARCH_BITS == 16
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65 | push di
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66 | push es
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67 | %endif
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68 |
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69 | %ifdef ASM_CALL64_MSC
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70 | %if ARCH_BITS != 64
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71 | %error ARCH_BITS mismatch?
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72 | %endif
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73 | mov eax, ecx
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74 | mov ebx, edx
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75 | mov ecx, r8d
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76 | mov edx, r9d
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77 | mov r8, [rbp + 30h]
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78 | mov r9, [rbp + 38h]
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79 | mov r10, [rbp + 40h]
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80 | mov r11, [rbp + 48h]
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81 | %elifdef ASM_CALL64_GCC
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82 | mov eax, edi
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83 | mov ebx, esi
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84 | xchg ecx, edx
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85 | mov r10, [rbp + 10h]
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86 | mov r11, [rbp + 18h]
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87 | %elif ARCH_BITS == 32
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88 | mov eax, [xBP + 08h]
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89 | mov ebx, [xBP + 0ch]
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90 | mov ecx, [xBP + 10h]
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91 | mov edx, [xBP + 14h]
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92 | mov edi, [xBP + 18h]
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93 | %elif ARCH_BITS == 16
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94 | mov eax, [xBP + 08h - 4]
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95 | mov ebx, [xBP + 0ch - 4]
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96 | mov ecx, [xBP + 10h - 4]
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97 | mov edx, [xBP + 14h - 4]
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98 | %else
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99 | %error unsupported arch
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100 | %endif
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101 |
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102 | cpuid
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103 |
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104 | %ifdef RT_ARCH_AMD64
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105 | test r8, r8
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106 | jz .store_ebx
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107 | mov [r8], eax
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108 | %elif ARCH_BITS == 32
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109 | test edi, edi
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110 | jz .store_ebx
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111 | mov [edi], eax
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112 | %else
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113 | cmp dword [bp + 18h - 4], 0
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114 | je .store_ebx
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115 | les di, [bp + 18h - 4]
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116 | mov [es:di], eax
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117 | %endif
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118 | .store_ebx:
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119 |
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120 | %ifdef RT_ARCH_AMD64
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121 | test r9, r9
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122 | jz .store_ecx
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123 | mov [r9], ebx
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124 | %elif ARCH_BITS == 32
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125 | mov edi, [ebp + 1ch]
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126 | test edi, edi
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127 | jz .store_ecx
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128 | mov [edi], ebx
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129 | %else
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130 | cmp dword [bp + 1ch - 4], 0
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131 | je .store_ecx
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132 | les di, [bp + 1ch - 4]
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133 | mov [es:di], ebx
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134 | %endif
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135 | .store_ecx:
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136 |
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137 | %ifdef RT_ARCH_AMD64
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138 | test r10, r10
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139 | jz .store_edx
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140 | mov [r10], ecx
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141 | %elif ARCH_BITS == 32
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142 | mov edi, [ebp + 20h]
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143 | test edi, edi
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144 | jz .store_edx
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145 | mov [edi], ecx
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146 | %else
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147 | cmp dword [bp + 20h - 4], 0
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148 | je .store_edx
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149 | les di, [bp + 20h - 4]
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150 | mov [es:di], ecx
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151 | %endif
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152 | .store_edx:
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153 |
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154 | %ifdef RT_ARCH_AMD64
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155 | test r11, r11
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156 | jz .done
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157 | mov [r11], edx
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158 | %elif ARCH_BITS == 32
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159 | mov edi, [ebp + 24h]
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160 | test edi, edi
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161 | jz .done
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162 | mov [edi], edx
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163 | %else
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164 | cmp dword [bp + 24h - 4], 0
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165 | je .done
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166 | les di, [bp + 24h - 4]
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167 | mov [es:di], edx
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168 | %endif
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169 | .done:
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170 |
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171 | %if ARCH_BITS == 32
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172 | pop edi
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173 | %elif ARCH_BITS == 16
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174 | pop es
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175 | pop di
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176 | %endif
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177 | pop xBX
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178 | leave
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179 | ret
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180 | ENDPROC ASMCpuIdExSlow
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181 |
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