VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigX86.cpp@ 103415

Last change on this file since 103415 was 103091, checked in by vboxsync, 11 months ago

Main,FE/VBoxManage,FE/VirtualBox,ValidationKit: Allow setting the primary VM execution engine to make it easier to force particular engine for testing, bugref:10583 [scm]

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 85.2 KB
Line 
1/* $Id: ConsoleImplConfigX86.cpp 103091 2024-01-26 16:38:30Z vboxsync $ */
2/** @file
3 * VBox Console COM Class implementation - VM Configuration Bits.
4 *
5 * @remark We've split out the code that the 64-bit VC++ v8 compiler finds
6 * problematic to optimize so we can disable optimizations and later,
7 * perhaps, find a real solution for it (like rewriting the code and
8 * to stop resemble a tonne of spaghetti).
9 */
10
11/*
12 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
13 *
14 * This file is part of VirtualBox base platform packages, as
15 * available from https://www.virtualbox.org.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation, in version 3 of the
20 * License.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, see <https://www.gnu.org/licenses>.
29 *
30 * SPDX-License-Identifier: GPL-3.0-only
31 */
32
33
34/*********************************************************************************************************************************
35* Header Files *
36*********************************************************************************************************************************/
37#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
38#include "LoggingNew.h"
39
40#include "ConsoleImpl.h"
41#include "DisplayImpl.h"
42#include "NvramStoreImpl.h"
43#include "PlatformImpl.h"
44#include "VMMDev.h"
45#include "Global.h"
46#ifdef VBOX_WITH_PCI_PASSTHROUGH
47# include "PCIRawDevImpl.h"
48#endif
49
50// generated header
51#include "SchemaDefs.h"
52
53#include "AutoCaller.h"
54
55#include <iprt/base64.h>
56#include <iprt/buildconfig.h>
57#include <iprt/ctype.h>
58#include <iprt/dir.h>
59#include <iprt/file.h>
60#include <iprt/param.h>
61#include <iprt/path.h>
62#include <iprt/string.h>
63#include <iprt/system.h>
64#if 0 /* enable to play with lots of memory. */
65# include <iprt/env.h>
66#endif
67#include <iprt/stream.h>
68
69#include <iprt/http.h>
70#include <iprt/socket.h>
71#include <iprt/uri.h>
72
73#include <VBox/vmm/vmmr3vtable.h>
74#include <VBox/vmm/vmapi.h>
75#include <VBox/err.h>
76#include <VBox/param.h>
77#include <VBox/settings.h> /* For MachineConfigFile::getHostDefaultAudioDriver(). */
78#include <VBox/vmm/pdmapi.h> /* For PDMR3DriverAttach/PDMR3DriverDetach. */
79#include <VBox/vmm/pdmusb.h> /* For PDMR3UsbCreateEmulatedDevice. */
80#include <VBox/vmm/pdmdev.h> /* For PDMAPICMODE enum. */
81#include <VBox/vmm/pdmstorageifs.h>
82#include <VBox/vmm/gcm.h>
83#include <VBox/version.h>
84
85#include <VBox/com/com.h>
86#include <VBox/com/string.h>
87#include <VBox/com/array.h>
88
89#include "NetworkServiceRunner.h"
90#include "BusAssignmentManager.h"
91#ifdef VBOX_WITH_EXTPACK
92# include "ExtPackManagerImpl.h"
93#endif
94
95
96/*********************************************************************************************************************************
97* Internal Functions *
98*********************************************************************************************************************************/
99
100/* Darwin compile kludge */
101#undef PVM
102
103/**
104 * @throws HRESULT on extra data retrival error.
105 */
106static int getSmcDeviceKey(IVirtualBox *pVirtualBox, IMachine *pMachine, Utf8Str *pStrKey, bool *pfGetKeyFromRealSMC)
107{
108 *pfGetKeyFromRealSMC = false;
109
110 /*
111 * The extra data takes precedence (if non-zero).
112 */
113 GetExtraDataBoth(pVirtualBox, pMachine, "VBoxInternal2/SmcDeviceKey", pStrKey);
114 if (pStrKey->isNotEmpty())
115 return VINF_SUCCESS;
116
117#ifdef RT_OS_DARWIN
118
119 /*
120 * Work done in EFI/DevSmc
121 */
122 *pfGetKeyFromRealSMC = true;
123 int vrc = VINF_SUCCESS;
124
125#else
126 /*
127 * Is it apple hardware in bootcamp?
128 */
129 /** @todo implement + test RTSYSDMISTR_MANUFACTURER on all hosts.
130 * Currently falling back on the product name. */
131 char szManufacturer[256];
132 szManufacturer[0] = '\0';
133 RTSystemQueryDmiString(RTSYSDMISTR_MANUFACTURER, szManufacturer, sizeof(szManufacturer));
134 if (szManufacturer[0] != '\0')
135 {
136 if ( !strcmp(szManufacturer, "Apple Computer, Inc.")
137 || !strcmp(szManufacturer, "Apple Inc.")
138 )
139 *pfGetKeyFromRealSMC = true;
140 }
141 else
142 {
143 char szProdName[256];
144 szProdName[0] = '\0';
145 RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME, szProdName, sizeof(szProdName));
146 if ( ( !strncmp(szProdName, RT_STR_TUPLE("Mac"))
147 || !strncmp(szProdName, RT_STR_TUPLE("iMac"))
148 || !strncmp(szProdName, RT_STR_TUPLE("Xserve"))
149 )
150 && !strchr(szProdName, ' ') /* no spaces */
151 && RT_C_IS_DIGIT(szProdName[strlen(szProdName) - 1]) /* version number */
152 )
153 *pfGetKeyFromRealSMC = true;
154 }
155
156 int vrc = VINF_SUCCESS;
157#endif
158
159 return vrc;
160}
161
162
163/*
164 * VC++ 8 / amd64 has some serious trouble with the next functions.
165 * As a temporary measure, we'll drop global optimizations.
166 */
167#if defined(_MSC_VER) && defined(RT_ARCH_AMD64)
168# if _MSC_VER >= RT_MSC_VER_VC80 && _MSC_VER < RT_MSC_VER_VC100
169# pragma optimize("g", off)
170# endif
171#endif
172
173/** Helper that finds out the next HBA port used
174 */
175static LONG GetNextUsedPort(LONG aPortUsed[30], LONG lBaseVal, uint32_t u32Size)
176{
177 LONG lNextPortUsed = 30;
178 for (size_t j = 0; j < u32Size; ++j)
179 {
180 if ( aPortUsed[j] > lBaseVal
181 && aPortUsed[j] <= lNextPortUsed)
182 lNextPortUsed = aPortUsed[j];
183 }
184 return lNextPortUsed;
185}
186
187#define MAX_BIOS_LUN_COUNT 4
188
189int Console::SetBiosDiskInfo(ComPtr<IMachine> pMachine, PCFGMNODE pCfg, PCFGMNODE pBiosCfg,
190 Bstr controllerName, const char * const s_apszBiosConfig[4])
191{
192 RT_NOREF(pCfg);
193 HRESULT hrc;
194#define MAX_DEVICES 30
195#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
196#define VRC() AssertLogRelMsgReturn(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), vrc)
197
198 LONG lPortLUN[MAX_BIOS_LUN_COUNT];
199 LONG lPortUsed[MAX_DEVICES];
200 uint32_t u32HDCount = 0;
201
202 /* init to max value */
203 lPortLUN[0] = MAX_DEVICES;
204
205 com::SafeIfaceArray<IMediumAttachment> atts;
206 hrc = pMachine->GetMediumAttachmentsOfController(controllerName.raw(),
207 ComSafeArrayAsOutParam(atts)); H();
208 size_t uNumAttachments = atts.size();
209 if (uNumAttachments > MAX_DEVICES)
210 {
211 LogRel(("Number of Attachments > Max=%d.\n", uNumAttachments));
212 uNumAttachments = MAX_DEVICES;
213 }
214
215 /* Find the relevant ports/IDs, i.e the ones to which a HD is attached. */
216 for (size_t j = 0; j < uNumAttachments; ++j)
217 {
218 IMediumAttachment *pMediumAtt = atts[j];
219 LONG lPortNum = 0;
220 hrc = pMediumAtt->COMGETTER(Port)(&lPortNum); H();
221 if (SUCCEEDED(hrc))
222 {
223 DeviceType_T lType;
224 hrc = pMediumAtt->COMGETTER(Type)(&lType); H();
225 if (SUCCEEDED(hrc) && lType == DeviceType_HardDisk)
226 {
227 /* find min port number used for HD */
228 if (lPortNum < lPortLUN[0])
229 lPortLUN[0] = lPortNum;
230 lPortUsed[u32HDCount++] = lPortNum;
231 LogFlowFunc(("HD port Count=%d\n", u32HDCount));
232 }
233 }
234 }
235
236
237 /* Pick only the top 4 used HD Ports as CMOS doesn't have space
238 * to save details for all 30 ports
239 */
240 uint32_t u32MaxPortCount = MAX_BIOS_LUN_COUNT;
241 if (u32HDCount < MAX_BIOS_LUN_COUNT)
242 u32MaxPortCount = u32HDCount;
243 for (size_t j = 1; j < u32MaxPortCount; j++)
244 lPortLUN[j] = GetNextUsedPort(lPortUsed, lPortLUN[j-1], u32HDCount);
245 if (pBiosCfg)
246 {
247 for (size_t j = 0; j < u32MaxPortCount; j++)
248 {
249 InsertConfigInteger(pBiosCfg, s_apszBiosConfig[j], lPortLUN[j]);
250 LogFlowFunc(("Top %d HBA ports = %s, %d\n", j, s_apszBiosConfig[j], lPortLUN[j]));
251 }
252 }
253 return VINF_SUCCESS;
254}
255
256#ifdef VBOX_WITH_PCI_PASSTHROUGH
257HRESULT Console::i_attachRawPCIDevices(PUVM pUVM, BusAssignmentManager *pBusMgr, PCFGMNODE pDevices)
258{
259# ifndef VBOX_WITH_EXTPACK
260 RT_NOREF(pUVM);
261# endif
262 HRESULT hrc = S_OK;
263 PCFGMNODE pInst, pCfg, pLunL0, pLunL1;
264
265 SafeIfaceArray<IPCIDeviceAttachment> assignments;
266 ComPtr<IMachine> aMachine = i_machine();
267
268 hrc = aMachine->COMGETTER(PCIDeviceAssignments)(ComSafeArrayAsOutParam(assignments));
269 if ( hrc != S_OK
270 || assignments.size() < 1)
271 return hrc;
272
273 /*
274 * PCI passthrough is only available if the proper ExtPack is installed.
275 *
276 * Note. Configuring PCI passthrough here and providing messages about
277 * the missing extpack isn't exactly clean, but it is a necessary evil
278 * to patch over legacy compatability issues introduced by the new
279 * distribution model.
280 */
281# ifdef VBOX_WITH_EXTPACK
282 static const char *s_pszPCIRawExtPackName = "Oracle VM VirtualBox Extension Pack";
283 if (!mptrExtPackManager->i_isExtPackUsable(s_pszPCIRawExtPackName))
284 /* Always fatal! */
285 return pVMM->pfnVMR3SetError(pUVM, VERR_NOT_FOUND, RT_SRC_POS,
286 N_("Implementation of the PCI passthrough framework not found!\n"
287 "The VM cannot be started. To fix this problem, either "
288 "install the '%s' or disable PCI passthrough via VBoxManage"),
289 s_pszPCIRawExtPackName);
290# endif
291
292 /* Now actually add devices */
293 PCFGMNODE pPCIDevs = NULL;
294
295 if (assignments.size() > 0)
296 {
297 InsertConfigNode(pDevices, "pciraw", &pPCIDevs);
298
299 PCFGMNODE pRoot = CFGMR3GetParent(pDevices); Assert(pRoot);
300
301 /* Tell PGM to tell GPCIRaw about guest mappings. */
302 CFGMR3InsertNode(pRoot, "PGM", NULL);
303 InsertConfigInteger(CFGMR3GetChild(pRoot, "PGM"), "PciPassThrough", 1);
304
305 /*
306 * Currently, using IOMMU needed for PCI passthrough
307 * requires RAM preallocation.
308 */
309 /** @todo check if we can lift this requirement */
310 CFGMR3RemoveValue(pRoot, "RamPreAlloc");
311 InsertConfigInteger(pRoot, "RamPreAlloc", 1);
312 }
313
314 for (size_t iDev = 0; iDev < assignments.size(); iDev++)
315 {
316 ComPtr<IPCIDeviceAttachment> const assignment = assignments[iDev];
317
318 LONG host;
319 hrc = assignment->COMGETTER(HostAddress)(&host); H();
320 LONG guest;
321 hrc = assignment->COMGETTER(GuestAddress)(&guest); H();
322 Bstr bstrDevName;
323 hrc = assignment->COMGETTER(Name)(bstrDevName.asOutParam()); H();
324
325 InsertConfigNodeF(pPCIDevs, &pInst, "%d", iDev);
326 InsertConfigInteger(pInst, "Trusted", 1);
327
328 PCIBusAddress HostPCIAddress(host);
329 Assert(HostPCIAddress.valid());
330 InsertConfigNode(pInst, "Config", &pCfg);
331 InsertConfigString(pCfg, "DeviceName", bstrDevName);
332
333 InsertConfigInteger(pCfg, "DetachHostDriver", 1);
334 InsertConfigInteger(pCfg, "HostPCIBusNo", HostPCIAddress.miBus);
335 InsertConfigInteger(pCfg, "HostPCIDeviceNo", HostPCIAddress.miDevice);
336 InsertConfigInteger(pCfg, "HostPCIFunctionNo", HostPCIAddress.miFn);
337
338 PCIBusAddress GuestPCIAddress(guest);
339 Assert(GuestPCIAddress.valid());
340 hrc = pBusMgr->assignHostPCIDevice("pciraw", pInst, HostPCIAddress, GuestPCIAddress, true);
341 if (hrc != S_OK)
342 return hrc;
343
344 InsertConfigInteger(pCfg, "GuestPCIBusNo", GuestPCIAddress.miBus);
345 InsertConfigInteger(pCfg, "GuestPCIDeviceNo", GuestPCIAddress.miDevice);
346 InsertConfigInteger(pCfg, "GuestPCIFunctionNo", GuestPCIAddress.miFn);
347
348 /* the driver */
349 InsertConfigNode(pInst, "LUN#0", &pLunL0);
350 InsertConfigString(pLunL0, "Driver", "pciraw");
351 InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
352
353 /* the Main driver */
354 InsertConfigString(pLunL1, "Driver", "MainPciRaw");
355 InsertConfigNode(pLunL1, "Config", &pCfg);
356 PCIRawDev *pMainDev = new PCIRawDev(this);
357# error This is not allowed any more
358 InsertConfigInteger(pCfg, "Object", (uintptr_t)pMainDev);
359 }
360
361 return hrc;
362}
363#endif
364
365
366/**
367 * Worker for configConstructor.
368 *
369 * @return VBox status code.
370 * @param pUVM The user mode VM handle.
371 * @param pVM The cross context VM handle.
372 * @param pVMM The VMM vtable.
373 * @param pAlock The automatic lock instance. This is for when we have
374 * to leave it in order to avoid deadlocks (ext packs and
375 * more).
376 */
377int Console::i_configConstructorX86(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
378{
379 RT_NOREF(pVM /* when everything is disabled */);
380 ComPtr<IMachine> pMachine = i_machine();
381
382 int vrc;
383 HRESULT hrc;
384 Utf8Str strTmp;
385 Bstr bstr;
386
387#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
388
389 /*
390 * Get necessary objects and frequently used parameters.
391 */
392 ComPtr<IVirtualBox> virtualBox;
393 hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
394
395 ComPtr<IHost> host;
396 hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
397
398 ComPtr<ISystemProperties> systemProperties;
399 hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
400
401 ComPtr<IFirmwareSettings> firmwareSettings;
402 hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
403
404 ComPtr<INvramStore> nvramStore;
405 hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
406
407 hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
408 RTUUID HardwareUuid;
409 vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
410 AssertRCReturn(vrc, vrc);
411
412 ULONG cRamMBs;
413 hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
414#if 0 /* enable to play with lots of memory. */
415 if (RTEnvExist("VBOX_RAM_SIZE"))
416 cRamMBs = RTStrToUInt64(RTEnvGet("VBOX_RAM_SIZE"));
417#endif
418 uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
419 uint32_t cbRamHole = MM_RAM_HOLE_SIZE_DEFAULT;
420 uint64_t uMcfgBase = 0;
421 uint32_t cbMcfgLength = 0;
422
423 ParavirtProvider_T enmParavirtProvider;
424 hrc = pMachine->GetEffectiveParavirtProvider(&enmParavirtProvider); H();
425
426 Bstr strParavirtDebug;
427 hrc = pMachine->COMGETTER(ParavirtDebug)(strParavirtDebug.asOutParam()); H();
428
429 BOOL fIOAPIC;
430 uint32_t uIoApicPciAddress = NIL_PCIBDF;
431 hrc = firmwareSettings->COMGETTER(IOAPICEnabled)(&fIOAPIC); H();
432
433 ComPtr<IPlatform> platform;
434 pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
435
436 ChipsetType_T chipsetType;
437 hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
438 if (chipsetType == ChipsetType_ICH9)
439 {
440 /* We'd better have 0x10000000 region, to cover 256 buses but this put
441 * too much load on hypervisor heap. Linux 4.8 currently complains with
442 * ``acpi PNP0A03:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f]
443 * only partially covers this bridge'' */
444 cbMcfgLength = 0x4000000; //0x10000000;
445 cbRamHole += cbMcfgLength;
446 uMcfgBase = _4G - cbRamHole;
447 }
448
449 /* Get the CPU profile name. */
450 Bstr bstrCpuProfile;
451 hrc = pMachine->COMGETTER(CPUProfile)(bstrCpuProfile.asOutParam()); H();
452
453 /* Get the X86 platform object. */
454 ComPtr<IPlatformX86> platformX86;
455 hrc = platform->COMGETTER(X86)(platformX86.asOutParam()); H();
456
457 /* Check if long mode is enabled. */
458 BOOL fIsGuest64Bit;
459 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_LongMode, &fIsGuest64Bit); H();
460
461 /*
462 * Figure out the IOMMU config.
463 */
464#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
465 IommuType_T enmIommuType;
466 hrc = platform->COMGETTER(IommuType)(&enmIommuType); H();
467
468 /* Resolve 'automatic' type to an Intel or AMD IOMMU based on the host CPU. */
469 if (enmIommuType == IommuType_Automatic)
470 {
471 if ( bstrCpuProfile.startsWith("AMD")
472 || bstrCpuProfile.startsWith("Quad-Core AMD")
473 || bstrCpuProfile.startsWith("Hygon"))
474 enmIommuType = IommuType_AMD;
475 else if (bstrCpuProfile.startsWith("Intel"))
476 {
477 if ( bstrCpuProfile.equals("Intel 8086")
478 || bstrCpuProfile.equals("Intel 80186")
479 || bstrCpuProfile.equals("Intel 80286")
480 || bstrCpuProfile.equals("Intel 80386")
481 || bstrCpuProfile.equals("Intel 80486"))
482 enmIommuType = IommuType_None;
483 else
484 enmIommuType = IommuType_Intel;
485 }
486# if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
487 else if (ASMIsAmdCpu())
488 enmIommuType = IommuType_AMD;
489 else if (ASMIsIntelCpu())
490 enmIommuType = IommuType_Intel;
491# endif
492 else
493 {
494 /** @todo Should we handle other CPUs like Shanghai, VIA etc. here? */
495 LogRel(("WARNING! Unrecognized CPU type, IOMMU disabled.\n"));
496 enmIommuType = IommuType_None;
497 }
498 }
499
500 if (enmIommuType == IommuType_AMD)
501 {
502# ifdef VBOX_WITH_IOMMU_AMD
503 /*
504 * Reserve the specific PCI address of the "SB I/O APIC" when using
505 * an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
506 */
507 uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
508# else
509 LogRel(("WARNING! AMD IOMMU not supported, IOMMU disabled.\n"));
510 enmIommuType = IommuType_None;
511# endif
512 }
513
514 if (enmIommuType == IommuType_Intel)
515 {
516# ifdef VBOX_WITH_IOMMU_INTEL
517 /*
518 * Reserve a unique PCI address for the I/O APIC when using
519 * an Intel IOMMU. For convenience we use the same address as
520 * we do on AMD, see @bugref{9967#c13}.
521 */
522 uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
523# else
524 LogRel(("WARNING! Intel IOMMU not supported, IOMMU disabled.\n"));
525 enmIommuType = IommuType_None;
526# endif
527 }
528
529 if ( enmIommuType == IommuType_AMD
530 || enmIommuType == IommuType_Intel)
531 {
532 if (chipsetType != ChipsetType_ICH9)
533 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
534 N_("IOMMU uses MSIs which requires the ICH9 chipset implementation."));
535 if (!fIOAPIC)
536 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
537 N_("IOMMU requires an I/O APIC for remapping interrupts."));
538 }
539#else
540 IommuType_T const enmIommuType = IommuType_None;
541#endif
542
543 /* Instantiate the bus assignment manager. */
544 Assert(enmIommuType != IommuType_Automatic);
545 BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, enmIommuType);
546
547 ULONG cCpus = 1;
548 hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
549
550 ULONG ulCpuExecutionCap = 100;
551 hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
552
553 VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
554 hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
555
556 LogRel(("Guest architecture: x86\n"));
557
558 Bstr osTypeId;
559 hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
560 LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
561
562 APICMode_T apicMode;
563 hrc = firmwareSettings->COMGETTER(APICMode)(&apicMode); H();
564 uint32_t uFwAPIC;
565 switch (apicMode)
566 {
567 case APICMode_Disabled:
568 uFwAPIC = 0;
569 break;
570 case APICMode_APIC:
571 uFwAPIC = 1;
572 break;
573 case APICMode_X2APIC:
574 uFwAPIC = 2;
575 break;
576 default:
577 AssertMsgFailed(("Invalid APICMode=%d\n", apicMode));
578 uFwAPIC = 1;
579 break;
580 }
581
582 ComPtr<IGuestOSType> pGuestOSType;
583 virtualBox->GetGuestOSType(osTypeId.raw(), pGuestOSType.asOutParam());
584
585 BOOL fOsXGuest = FALSE;
586 BOOL fWinGuest = FALSE;
587 BOOL fOs2Guest = FALSE;
588 BOOL fW9xGuest = FALSE;
589 BOOL fDosGuest = FALSE;
590 if (pGuestOSType.isNotNull())
591 {
592 Bstr guestTypeFamilyId;
593 hrc = pGuestOSType->COMGETTER(FamilyId)(guestTypeFamilyId.asOutParam()); H();
594 fOsXGuest = guestTypeFamilyId == Bstr("MacOS");
595 fWinGuest = guestTypeFamilyId == Bstr("Windows");
596 fOs2Guest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("OS2"));
597 fW9xGuest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("Windows9")); /* Does not include Windows Me. */
598 fDosGuest = osTypeId.equals(GUEST_OS_ID_STR_X86("DOS")) || osTypeId.equals(GUEST_OS_ID_STR_X86("Windows31"));
599 }
600
601 ComPtr<IPlatformProperties> platformProperties;
602 virtualBox->GetPlatformProperties(PlatformArchitecture_x86, platformProperties.asOutParam());
603
604 /*
605 * Get root node first.
606 * This is the only node in the tree.
607 */
608 PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
609 Assert(pRoot);
610
611 // catching throws from InsertConfigString and friends.
612 try
613 {
614
615 /*
616 * Set the root (and VMM) level values.
617 */
618 hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
619 InsertConfigString(pRoot, "Name", bstr);
620 InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
621 InsertConfigInteger(pRoot, "RamSize", cbRam);
622 InsertConfigInteger(pRoot, "RamHoleSize", cbRamHole);
623 InsertConfigInteger(pRoot, "NumCPUs", cCpus);
624 InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
625 InsertConfigInteger(pRoot, "TimerMillies", 10);
626
627 BOOL fPageFusion = FALSE;
628 hrc = pMachine->COMGETTER(PageFusionEnabled)(&fPageFusion); H();
629 InsertConfigInteger(pRoot, "PageFusionAllowed", fPageFusion); /* boolean */
630
631 /* Not necessary, but makes sure this setting ends up in the release log. */
632 ULONG ulBalloonSize = 0;
633 hrc = pMachine->COMGETTER(MemoryBalloonSize)(&ulBalloonSize); H();
634 InsertConfigInteger(pRoot, "MemBalloonSize", ulBalloonSize);
635
636 /*
637 * EM values (before CPUM as it may need to set IemExecutesAll).
638 */
639 PCFGMNODE pEM;
640 InsertConfigNode(pRoot, "EM", &pEM);
641
642 /* Triple fault behavior. */
643 BOOL fTripleFaultReset = false;
644 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_TripleFaultReset, &fTripleFaultReset); H();
645 InsertConfigInteger(pEM, "TripleFaultReset", fTripleFaultReset);
646
647 /*
648 * CPUM values.
649 */
650 PCFGMNODE pCPUM;
651 InsertConfigNode(pRoot, "CPUM", &pCPUM);
652 PCFGMNODE pIsaExts;
653 InsertConfigNode(pCPUM, "IsaExts", &pIsaExts);
654
655 /* Host CPUID leaf overrides. */
656 for (uint32_t iOrdinal = 0; iOrdinal < _4K; iOrdinal++)
657 {
658 ULONG uLeaf, uSubLeaf, uEax, uEbx, uEcx, uEdx;
659 hrc = platformX86->GetCPUIDLeafByOrdinal(iOrdinal, &uLeaf, &uSubLeaf, &uEax, &uEbx, &uEcx, &uEdx);
660 if (hrc == E_INVALIDARG)
661 break;
662 H();
663 PCFGMNODE pLeaf;
664 InsertConfigNode(pCPUM, Utf8StrFmt("HostCPUID/%RX32", uLeaf).c_str(), &pLeaf);
665 /** @todo Figure out how to tell the VMM about uSubLeaf */
666 InsertConfigInteger(pLeaf, "eax", uEax);
667 InsertConfigInteger(pLeaf, "ebx", uEbx);
668 InsertConfigInteger(pLeaf, "ecx", uEcx);
669 InsertConfigInteger(pLeaf, "edx", uEdx);
670 }
671
672 /* We must limit CPUID count for Windows NT 4, as otherwise it stops
673 with error 0x3e (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED). */
674 if (osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4"))
675 {
676 LogRel(("Limiting CPUID leaf count for NT4 guests\n"));
677 InsertConfigInteger(pCPUM, "NT4LeafLimit", true);
678 }
679
680 if (fOsXGuest)
681 {
682 /* Expose extended MWAIT features to Mac OS X guests. */
683 LogRel(("Using MWAIT extensions\n"));
684 InsertConfigInteger(pIsaExts, "MWaitExtensions", true);
685
686 /* Fake the CPU family/model so the guest works. This is partly
687 because older mac releases really doesn't work on newer cpus,
688 and partly because mac os x expects more from systems with newer
689 cpus (MSRs, power features, whatever). */
690 uint32_t uMaxIntelFamilyModelStep = UINT32_MAX;
691 if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS")
692 || osTypeId == GUEST_OS_ID_STR_X64("MacOS"))
693 uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482. */
694 else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS106")
695 || osTypeId == GUEST_OS_ID_STR_X64("MacOS106"))
696 uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */
697 else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS107")
698 || osTypeId == GUEST_OS_ID_STR_X64("MacOS107"))
699 uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */ /** @todo figure out
700 what is required here. */
701 else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS108")
702 || osTypeId == GUEST_OS_ID_STR_X64("MacOS108"))
703 uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */ /** @todo figure out
704 what is required here. */
705 else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS109")
706 || osTypeId == GUEST_OS_ID_STR_X64("MacOS109"))
707 uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */ /** @todo figure
708 out what is required here. */
709 if (uMaxIntelFamilyModelStep != UINT32_MAX)
710 InsertConfigInteger(pCPUM, "MaxIntelFamilyModelStep", uMaxIntelFamilyModelStep);
711 }
712
713 /* CPU Portability level, */
714 ULONG uCpuIdPortabilityLevel = 0;
715 hrc = pMachine->COMGETTER(CPUIDPortabilityLevel)(&uCpuIdPortabilityLevel); H();
716 InsertConfigInteger(pCPUM, "PortableCpuIdLevel", uCpuIdPortabilityLevel);
717
718 /* Physical Address Extension (PAE) */
719 BOOL fEnablePAE = false;
720 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_PAE, &fEnablePAE); H();
721 fEnablePAE |= fIsGuest64Bit;
722 InsertConfigInteger(pRoot, "EnablePAE", fEnablePAE);
723
724 /* 64-bit guests (long mode) */
725 InsertConfigInteger(pCPUM, "Enable64bit", fIsGuest64Bit);
726
727 /* APIC/X2APIC configuration */
728 BOOL fEnableAPIC = true;
729 BOOL fEnableX2APIC = true;
730 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_APIC, &fEnableAPIC); H();
731 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_X2APIC, &fEnableX2APIC); H();
732 if (fEnableX2APIC)
733 Assert(fEnableAPIC);
734
735 /* CPUM profile name. */
736 InsertConfigString(pCPUM, "GuestCpuName", bstrCpuProfile);
737
738 /*
739 * Temporary(?) hack to make sure we emulate the ancient 16-bit CPUs
740 * correctly. There are way too many #UDs we'll miss using VT-x,
741 * raw-mode or qemu for the 186 and 286, while we'll get undefined opcodes
742 * dead wrong on 8086 (see http://www.os2museum.com/wp/undocumented-8086-opcodes/).
743 */
744 if ( bstrCpuProfile.equals("Intel 80386") /* just for now */
745 || bstrCpuProfile.equals("Intel 80286")
746 || bstrCpuProfile.equals("Intel 80186")
747 || bstrCpuProfile.equals("Nec V20")
748 || bstrCpuProfile.equals("Intel 8086") )
749 {
750 InsertConfigInteger(pEM, "IemExecutesAll", true);
751 if (!bstrCpuProfile.equals("Intel 80386"))
752 {
753 fEnableAPIC = false;
754 fIOAPIC = false;
755 }
756 fEnableX2APIC = false;
757 }
758
759 /* Adjust firmware APIC handling to stay within the VCPU limits. */
760 if (uFwAPIC == 2 && !fEnableX2APIC)
761 {
762 if (fEnableAPIC)
763 uFwAPIC = 1;
764 else
765 uFwAPIC = 0;
766 LogRel(("Limiting the firmware APIC level from x2APIC to %s\n", fEnableAPIC ? "APIC" : "Disabled"));
767 }
768 else if (uFwAPIC == 1 && !fEnableAPIC)
769 {
770 uFwAPIC = 0;
771 LogRel(("Limiting the firmware APIC level from APIC to Disabled\n"));
772 }
773
774 /* Speculation Control. */
775 BOOL fSpecCtrl = FALSE;
776 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrl, &fSpecCtrl); H();
777 InsertConfigInteger(pCPUM, "SpecCtrl", fSpecCtrl);
778
779 /* Nested VT-x / AMD-V. */
780 BOOL fNestedHWVirt = FALSE;
781 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_HWVirt, &fNestedHWVirt); H();
782 InsertConfigInteger(pCPUM, "NestedHWVirt", fNestedHWVirt ? true : false);
783
784 /*
785 * Hardware virtualization extensions.
786 */
787 /* Sanitize valid/useful APIC combinations, see @bugref{8868}. */
788 if (!fEnableAPIC)
789 {
790 if (fIsGuest64Bit)
791 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
792 N_("Cannot disable the APIC for a 64-bit guest."));
793 if (cCpus > 1)
794 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
795 N_("Cannot disable the APIC for an SMP guest."));
796 if (fIOAPIC)
797 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
798 N_("Cannot disable the APIC when the I/O APIC is present."));
799 }
800
801 BOOL fHMEnabled;
802 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Enabled, &fHMEnabled); H();
803 if (cCpus > 1 && !fHMEnabled)
804 {
805 LogRel(("Forced fHMEnabled to TRUE by SMP guest.\n"));
806 fHMEnabled = TRUE;
807 }
808
809 BOOL fHMForced;
810 fHMEnabled = fHMForced = TRUE;
811 LogRel(("fHMForced=true - No raw-mode support in this build!\n"));
812 if (!fHMForced) /* No need to query if already forced above. */
813 {
814 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Force, &fHMForced); H();
815 if (fHMForced)
816 LogRel(("fHMForced=true - HWVirtExPropertyType_Force\n"));
817 }
818 InsertConfigInteger(pRoot, "HMEnabled", fHMEnabled);
819
820 /* /HM/xyz */
821 PCFGMNODE pHM;
822 InsertConfigNode(pRoot, "HM", &pHM);
823 InsertConfigInteger(pHM, "HMForced", fHMForced);
824 if (fHMEnabled)
825 {
826 /* Indicate whether 64-bit guests are supported or not. */
827 InsertConfigInteger(pHM, "64bitEnabled", fIsGuest64Bit);
828
829 /** @todo Not exactly pretty to check strings; VBOXOSTYPE would be better,
830 but that requires quite a bit of API change in Main. */
831 if ( fIOAPIC
832 && ( osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4")
833 || osTypeId == GUEST_OS_ID_STR_X86("Windows2000")
834 || osTypeId == GUEST_OS_ID_STR_X86("WindowsXP")
835 || osTypeId == GUEST_OS_ID_STR_X86("Windows2003")))
836 {
837 /* Only allow TPR patching for NT, Win2k, XP and Windows Server 2003. (32 bits mode)
838 * We may want to consider adding more guest OSes (Solaris) later on.
839 */
840 InsertConfigInteger(pHM, "TPRPatchingEnabled", 1);
841 }
842 }
843
844 /*
845 * Set VM execution engine.
846 */
847 /** @todo r=aeichner Maybe provide a better VMM API for this instead of the different CFGM knobs. */
848 LogRel(("Using execution engine %u\n", enmExecEngine));
849 switch (enmExecEngine)
850 {
851 case VMExecutionEngine_HwVirt:
852 InsertConfigInteger(pEM, "IemExecutesAll", 0);
853 InsertConfigInteger(pEM, "IemRecompiled", 0);
854 InsertConfigInteger(pHM, "UseNEMInstead", 0);
855 InsertConfigInteger(pHM, "FallbackToNEM", 0);
856 InsertConfigInteger(pHM, "FallbackToIEM", 0);
857 break;
858 case VMExecutionEngine_NativeApi:
859 InsertConfigInteger(pEM, "IemExecutesAll", 0);
860 InsertConfigInteger(pEM, "IemRecompiled", 0);
861 InsertConfigInteger(pHM, "UseNEMInstead", 1);
862 InsertConfigInteger(pHM, "FallbackToNEM", 1);
863 InsertConfigInteger(pHM, "FallbackToIEM", 0);
864 break;
865 case VMExecutionEngine_Interpreter:
866 case VMExecutionEngine_Recompiler:
867 InsertConfigInteger(pEM, "IemExecutesAll", 1);
868 InsertConfigInteger(pEM, "IemRecompiled", enmExecEngine == VMExecutionEngine_Recompiler);
869 InsertConfigInteger(pHM, "UseNEMInstead", 0);
870 InsertConfigInteger(pHM, "FallbackToNEM", 0);
871 InsertConfigInteger(pHM, "FallbackToIEM", 1);
872 break;
873 case VMExecutionEngine_Default:
874 break; /* Nothing to do, let VMM decide. */
875 default:
876 AssertLogRelFailed();
877 }
878
879 /* HWVirtEx exclusive mode */
880 BOOL fHMExclusive = true;
881 hrc = platformProperties->COMGETTER(ExclusiveHwVirt)(&fHMExclusive); H();
882 InsertConfigInteger(pHM, "Exclusive", fHMExclusive);
883
884 /* Nested paging (VT-x/AMD-V) */
885 BOOL fEnableNestedPaging = false;
886 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_NestedPaging, &fEnableNestedPaging); H();
887 InsertConfigInteger(pHM, "EnableNestedPaging", fEnableNestedPaging);
888
889 /* Large pages; requires nested paging */
890 BOOL fEnableLargePages = false;
891 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_LargePages, &fEnableLargePages); H();
892 InsertConfigInteger(pHM, "EnableLargePages", fEnableLargePages);
893
894 /* VPID (VT-x) */
895 BOOL fEnableVPID = false;
896 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_VPID, &fEnableVPID); H();
897 InsertConfigInteger(pHM, "EnableVPID", fEnableVPID);
898
899 /* Unrestricted execution aka UX (VT-x) */
900 BOOL fEnableUX = false;
901 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UnrestrictedExecution, &fEnableUX); H();
902 InsertConfigInteger(pHM, "EnableUX", fEnableUX);
903
904 /* Virtualized VMSAVE/VMLOAD (AMD-V) */
905 BOOL fVirtVmsaveVmload = true;
906 hrc = host->GetProcessorFeature(ProcessorFeature_VirtVmsaveVmload, &fVirtVmsaveVmload); H();
907 InsertConfigInteger(pHM, "SvmVirtVmsaveVmload", fVirtVmsaveVmload);
908
909 /* Indirect branch prediction boundraries. */
910 BOOL fIBPBOnVMExit = false;
911 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMExit, &fIBPBOnVMExit); H();
912 InsertConfigInteger(pHM, "IBPBOnVMExit", fIBPBOnVMExit);
913
914 BOOL fIBPBOnVMEntry = false;
915 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMEntry, &fIBPBOnVMEntry); H();
916 InsertConfigInteger(pHM, "IBPBOnVMEntry", fIBPBOnVMEntry);
917
918 BOOL fSpecCtrlByHost = false;
919 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrlByHost, &fSpecCtrlByHost); H();
920 InsertConfigInteger(pHM, "SpecCtrlByHost", fSpecCtrlByHost);
921
922 BOOL fL1DFlushOnSched = true;
923 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnEMTScheduling, &fL1DFlushOnSched); H();
924 InsertConfigInteger(pHM, "L1DFlushOnSched", fL1DFlushOnSched);
925
926 BOOL fL1DFlushOnVMEntry = false;
927 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnVMEntry, &fL1DFlushOnVMEntry); H();
928 InsertConfigInteger(pHM, "L1DFlushOnVMEntry", fL1DFlushOnVMEntry);
929
930 BOOL fMDSClearOnSched = true;
931 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnEMTScheduling, &fMDSClearOnSched); H();
932 InsertConfigInteger(pHM, "MDSClearOnSched", fMDSClearOnSched);
933
934 BOOL fMDSClearOnVMEntry = false;
935 hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnVMEntry, &fMDSClearOnVMEntry); H();
936 InsertConfigInteger(pHM, "MDSClearOnVMEntry", fMDSClearOnVMEntry);
937
938 /* Reset overwrite. */
939 mfTurnResetIntoPowerOff = GetExtraDataBoth(virtualBox, pMachine,
940 "VBoxInternal2/TurnResetIntoPowerOff", &strTmp)->equals("1");
941 if (mfTurnResetIntoPowerOff)
942 InsertConfigInteger(pRoot, "PowerOffInsteadOfReset", 1);
943
944 /** @todo This is a bit redundant but in order to avoid forcing setting version bumps later on
945 * and don't magically change behavior of old VMs we have to keep this for now. As soon as the user sets
946 * the execution to anything else than Default the execution engine setting takes precedence.
947 */
948 if (enmExecEngine == VMExecutionEngine_Default)
949 {
950 /* Use NEM rather than HM. */
951 BOOL fUseNativeApi = false;
952 hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UseNativeApi, &fUseNativeApi); H();
953 InsertConfigInteger(pHM, "UseNEMInstead", fUseNativeApi);
954 }
955
956 /* Enable workaround for missing TLB flush for OS/2 guests, see ticketref:20625. */
957 if (fOs2Guest)
958 InsertConfigInteger(pHM, "MissingOS2TlbFlushWorkaround", 1);
959
960 /*
961 * NEM
962 */
963 PCFGMNODE pNEM;
964 InsertConfigNode(pRoot, "NEM", &pNEM);
965 InsertConfigInteger(pNEM, "Allow64BitGuests", fIsGuest64Bit);
966
967 /*
968 * Paravirt. provider.
969 */
970 PCFGMNODE pParavirtNode;
971 InsertConfigNode(pRoot, "GIM", &pParavirtNode);
972 const char *pcszParavirtProvider;
973 bool fGimDeviceNeeded = true;
974 switch (enmParavirtProvider)
975 {
976 case ParavirtProvider_None:
977 pcszParavirtProvider = "None";
978 fGimDeviceNeeded = false;
979 break;
980
981 case ParavirtProvider_Minimal:
982 pcszParavirtProvider = "Minimal";
983 break;
984
985 case ParavirtProvider_HyperV:
986 pcszParavirtProvider = "HyperV";
987 break;
988
989 case ParavirtProvider_KVM:
990 pcszParavirtProvider = "KVM";
991 break;
992
993 default:
994 AssertMsgFailed(("Invalid enmParavirtProvider=%d\n", enmParavirtProvider));
995 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, N_("Invalid paravirt. provider '%d'"),
996 enmParavirtProvider);
997 }
998 InsertConfigString(pParavirtNode, "Provider", pcszParavirtProvider);
999
1000 /*
1001 * Parse paravirt. debug options.
1002 */
1003 bool fGimDebug = false;
1004 com::Utf8Str strGimDebugAddress = "127.0.0.1";
1005 uint32_t uGimDebugPort = 50000;
1006 if (strParavirtDebug.isNotEmpty())
1007 {
1008 /* Hyper-V debug options. */
1009 if (enmParavirtProvider == ParavirtProvider_HyperV)
1010 {
1011 bool fGimHvDebug = false;
1012 com::Utf8Str strGimHvVendor;
1013 bool fGimHvVsIf = false;
1014 bool fGimHvHypercallIf = false;
1015
1016 size_t uPos = 0;
1017 com::Utf8Str strDebugOptions = strParavirtDebug;
1018 com::Utf8Str strKey;
1019 com::Utf8Str strVal;
1020 while ((uPos = strDebugOptions.parseKeyValue(strKey, strVal, uPos)) != com::Utf8Str::npos)
1021 {
1022 if (strKey == "enabled")
1023 {
1024 if (strVal.toUInt32() == 1)
1025 {
1026 /* Apply defaults.
1027 The defaults are documented in the user manual,
1028 changes need to be reflected accordingly. */
1029 fGimHvDebug = true;
1030 strGimHvVendor = "Microsoft Hv";
1031 fGimHvVsIf = true;
1032 fGimHvHypercallIf = false;
1033 }
1034 /* else: ignore, i.e. don't assert below with 'enabled=0'. */
1035 }
1036 else if (strKey == "address")
1037 strGimDebugAddress = strVal;
1038 else if (strKey == "port")
1039 uGimDebugPort = strVal.toUInt32();
1040 else if (strKey == "vendor")
1041 strGimHvVendor = strVal;
1042 else if (strKey == "vsinterface")
1043 fGimHvVsIf = RT_BOOL(strVal.toUInt32());
1044 else if (strKey == "hypercallinterface")
1045 fGimHvHypercallIf = RT_BOOL(strVal.toUInt32());
1046 else
1047 {
1048 AssertMsgFailed(("Unrecognized Hyper-V debug option '%s'\n", strKey.c_str()));
1049 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1050 N_("Unrecognized Hyper-V debug option '%s' in '%s'"), strKey.c_str(),
1051 strDebugOptions.c_str());
1052 }
1053 }
1054
1055 /* Update HyperV CFGM node with active debug options. */
1056 if (fGimHvDebug)
1057 {
1058 PCFGMNODE pHvNode;
1059 InsertConfigNode(pParavirtNode, "HyperV", &pHvNode);
1060 InsertConfigString(pHvNode, "VendorID", strGimHvVendor);
1061 InsertConfigInteger(pHvNode, "VSInterface", fGimHvVsIf ? 1 : 0);
1062 InsertConfigInteger(pHvNode, "HypercallDebugInterface", fGimHvHypercallIf ? 1 : 0);
1063 fGimDebug = true;
1064 }
1065 }
1066 }
1067
1068 /*
1069 * Guest Compatibility Manager.
1070 */
1071 PCFGMNODE pGcmNode;
1072 uint32_t u32FixerSet = 0;
1073 InsertConfigNode(pRoot, "GCM", &pGcmNode);
1074 /* OS/2 and Win9x guests can run DOS apps so they get
1075 * the DOS specific fixes as well.
1076 */
1077 if (fOs2Guest)
1078 u32FixerSet = GCMFIXER_DBZ_DOS | GCMFIXER_DBZ_OS2;
1079 else if (fW9xGuest)
1080 u32FixerSet = GCMFIXER_DBZ_DOS | GCMFIXER_DBZ_WIN9X;
1081 else if (fDosGuest)
1082 u32FixerSet = GCMFIXER_DBZ_DOS;
1083 InsertConfigInteger(pGcmNode, "FixerSet", u32FixerSet);
1084
1085
1086 /*
1087 * MM values.
1088 */
1089 PCFGMNODE pMM;
1090 InsertConfigNode(pRoot, "MM", &pMM);
1091 InsertConfigInteger(pMM, "CanUseLargerHeap", chipsetType == ChipsetType_ICH9);
1092
1093 /*
1094 * PDM config.
1095 * Load drivers in VBoxC.[so|dll]
1096 */
1097 vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
1098
1099 /*
1100 * Devices
1101 */
1102 PCFGMNODE pDevices = NULL; /* /Devices */
1103 PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
1104 PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
1105 PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
1106 PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
1107 PCFGMNODE pLunL1 = NULL; /* /Devices/Dev/0/LUN#0/AttachedDriver/ */
1108 PCFGMNODE pBiosCfg = NULL; /* /Devices/pcbios/0/Config/ */
1109 PCFGMNODE pNetBootCfg = NULL; /* /Devices/pcbios/0/Config/NetBoot/ */
1110
1111 InsertConfigNode(pRoot, "Devices", &pDevices);
1112
1113 /*
1114 * GIM Device
1115 */
1116 if (fGimDeviceNeeded)
1117 {
1118 InsertConfigNode(pDevices, "GIMDev", &pDev);
1119 InsertConfigNode(pDev, "0", &pInst);
1120 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1121 //InsertConfigNode(pInst, "Config", &pCfg);
1122
1123 if (fGimDebug)
1124 {
1125 InsertConfigNode(pInst, "LUN#998", &pLunL0);
1126 InsertConfigString(pLunL0, "Driver", "UDP");
1127 InsertConfigNode(pLunL0, "Config", &pLunL1);
1128 InsertConfigString(pLunL1, "ServerAddress", strGimDebugAddress);
1129 InsertConfigInteger(pLunL1, "ServerPort", uGimDebugPort);
1130 }
1131 }
1132
1133 /*
1134 * PC Arch.
1135 */
1136 InsertConfigNode(pDevices, "pcarch", &pDev);
1137 InsertConfigNode(pDev, "0", &pInst);
1138 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1139 InsertConfigNode(pInst, "Config", &pCfg);
1140
1141 /*
1142 * The time offset
1143 */
1144 LONG64 timeOffset;
1145 hrc = firmwareSettings->COMGETTER(TimeOffset)(&timeOffset); H();
1146 PCFGMNODE pTMNode;
1147 InsertConfigNode(pRoot, "TM", &pTMNode);
1148 InsertConfigInteger(pTMNode, "UTCOffset", timeOffset * 1000000);
1149
1150 /*
1151 * DMA
1152 */
1153 InsertConfigNode(pDevices, "8237A", &pDev);
1154 InsertConfigNode(pDev, "0", &pInst);
1155 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1156
1157 /*
1158 * PCI buses.
1159 */
1160 uint32_t uIocPCIAddress, uHbcPCIAddress;
1161 switch (chipsetType)
1162 {
1163 default:
1164 AssertFailed();
1165 RT_FALL_THRU();
1166 case ChipsetType_PIIX3:
1167 /* Create the base for adding bridges on demand */
1168 InsertConfigNode(pDevices, "pcibridge", NULL);
1169
1170 InsertConfigNode(pDevices, "pci", &pDev);
1171 uHbcPCIAddress = (0x0 << 16) | 0;
1172 uIocPCIAddress = (0x1 << 16) | 0; // ISA controller
1173 break;
1174 case ChipsetType_ICH9:
1175 /* Create the base for adding bridges on demand */
1176 InsertConfigNode(pDevices, "ich9pcibridge", NULL);
1177
1178 InsertConfigNode(pDevices, "ich9pci", &pDev);
1179 uHbcPCIAddress = (0x1e << 16) | 0;
1180 uIocPCIAddress = (0x1f << 16) | 0; // LPC controller
1181 break;
1182 }
1183 InsertConfigNode(pDev, "0", &pInst);
1184 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1185 InsertConfigNode(pInst, "Config", &pCfg);
1186 InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1187 if (chipsetType == ChipsetType_ICH9)
1188 {
1189 /* Provide MCFG info */
1190 InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1191 InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1192
1193#ifdef VBOX_WITH_PCI_PASSTHROUGH
1194 /* Add PCI passthrough devices */
1195 hrc = i_attachRawPCIDevices(pUVM, pBusMgr, pDevices); H();
1196#endif
1197
1198 if (enmIommuType == IommuType_AMD)
1199 {
1200 /* AMD IOMMU. */
1201 InsertConfigNode(pDevices, "iommu-amd", &pDev);
1202 InsertConfigNode(pDev, "0", &pInst);
1203 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1204 InsertConfigNode(pInst, "Config", &pCfg);
1205 hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst); H();
1206
1207 /* The AMD IOMMU device needs to know which PCI slot it's in, see @bugref{9654#c104}. */
1208 {
1209 PCIBusAddress Address;
1210 if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1211 {
1212 uint32_t const u32IommuAddress = (Address.miDevice << 16) | Address.miFn;
1213 InsertConfigInteger(pCfg, "PCIAddress", u32IommuAddress);
1214 }
1215 else
1216 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1217 N_("Failed to find PCI address of the assigned IOMMU device!"));
1218 }
1219
1220 PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1221 hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg */, PCIAddr, true /*fGuestAddressRequired*/); H();
1222 }
1223 else if (enmIommuType == IommuType_Intel)
1224 {
1225 /* Intel IOMMU. */
1226 InsertConfigNode(pDevices, "iommu-intel", &pDev);
1227 InsertConfigNode(pDev, "0", &pInst);
1228 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1229 InsertConfigNode(pInst, "Config", &pCfg);
1230 hrc = pBusMgr->assignPCIDevice("iommu-intel", pInst); H();
1231
1232 PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1233 hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg */, PCIAddr, true /*fGuestAddressRequired*/); H();
1234 }
1235 }
1236
1237 /*
1238 * Enable the following devices: HPET, SMC and LPC on MacOS X guests or on ICH9 chipset
1239 */
1240
1241 /*
1242 * High Precision Event Timer (HPET)
1243 */
1244 BOOL fHPETEnabled;
1245 /* Other guests may wish to use HPET too, but MacOS X not functional without it */
1246 hrc = platformX86->COMGETTER(HPETEnabled)(&fHPETEnabled); H();
1247 /* so always enable HPET in extended profile */
1248 fHPETEnabled |= fOsXGuest;
1249 /* HPET is always present on ICH9 */
1250 fHPETEnabled |= (chipsetType == ChipsetType_ICH9);
1251 if (fHPETEnabled)
1252 {
1253 InsertConfigNode(pDevices, "hpet", &pDev);
1254 InsertConfigNode(pDev, "0", &pInst);
1255 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1256 InsertConfigNode(pInst, "Config", &pCfg);
1257 InsertConfigInteger(pCfg, "ICH9", (chipsetType == ChipsetType_ICH9) ? 1 : 0); /* boolean */
1258 }
1259
1260 /*
1261 * System Management Controller (SMC)
1262 */
1263 BOOL fSmcEnabled;
1264 fSmcEnabled = fOsXGuest;
1265 if (fSmcEnabled)
1266 {
1267 InsertConfigNode(pDevices, "smc", &pDev);
1268 InsertConfigNode(pDev, "0", &pInst);
1269 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1270 InsertConfigNode(pInst, "Config", &pCfg);
1271
1272 bool fGetKeyFromRealSMC;
1273 Utf8Str strKey;
1274 vrc = getSmcDeviceKey(virtualBox, pMachine, &strKey, &fGetKeyFromRealSMC);
1275 AssertRCReturn(vrc, vrc);
1276
1277 if (!fGetKeyFromRealSMC)
1278 InsertConfigString(pCfg, "DeviceKey", strKey);
1279 InsertConfigInteger(pCfg, "GetKeyFromRealSMC", fGetKeyFromRealSMC);
1280 }
1281
1282 /*
1283 * Low Pin Count (LPC) bus
1284 */
1285 BOOL fLpcEnabled;
1286 /** @todo implement appropriate getter */
1287 fLpcEnabled = fOsXGuest || (chipsetType == ChipsetType_ICH9);
1288 if (fLpcEnabled)
1289 {
1290 InsertConfigNode(pDevices, "lpc", &pDev);
1291 InsertConfigNode(pDev, "0", &pInst);
1292 hrc = pBusMgr->assignPCIDevice("lpc", pInst); H();
1293 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1294 }
1295
1296 BOOL fShowRtc;
1297 fShowRtc = fOsXGuest || (chipsetType == ChipsetType_ICH9);
1298
1299 /*
1300 * PS/2 keyboard & mouse.
1301 */
1302 InsertConfigNode(pDevices, "pckbd", &pDev);
1303 InsertConfigNode(pDev, "0", &pInst);
1304 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1305 InsertConfigNode(pInst, "Config", &pCfg);
1306
1307 KeyboardHIDType_T aKbdHID;
1308 hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
1309 if (aKbdHID != KeyboardHIDType_None)
1310 {
1311 InsertConfigNode(pInst, "LUN#0", &pLunL0);
1312 InsertConfigString(pLunL0, "Driver", "KeyboardQueue");
1313 InsertConfigNode(pLunL0, "Config", &pCfg);
1314 InsertConfigInteger(pCfg, "QueueSize", 64);
1315
1316 InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1317 InsertConfigString(pLunL1, "Driver", "MainKeyboard");
1318 }
1319
1320 PointingHIDType_T aPointingHID;
1321 hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
1322 if (aPointingHID != PointingHIDType_None)
1323 {
1324 InsertConfigNode(pInst, "LUN#1", &pLunL0);
1325 InsertConfigString(pLunL0, "Driver", "MouseQueue");
1326 InsertConfigNode(pLunL0, "Config", &pCfg);
1327 InsertConfigInteger(pCfg, "QueueSize", 128);
1328
1329 InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1330 InsertConfigString(pLunL1, "Driver", "MainMouse");
1331 }
1332
1333 /*
1334 * i8254 Programmable Interval Timer And Dummy Speaker
1335 */
1336 InsertConfigNode(pDevices, "i8254", &pDev);
1337 InsertConfigNode(pDev, "0", &pInst);
1338 InsertConfigNode(pInst, "Config", &pCfg);
1339#ifdef DEBUG
1340 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1341#endif
1342
1343 /*
1344 * i8259 Programmable Interrupt Controller.
1345 */
1346 InsertConfigNode(pDevices, "i8259", &pDev);
1347 InsertConfigNode(pDev, "0", &pInst);
1348 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1349 InsertConfigNode(pInst, "Config", &pCfg);
1350
1351 /*
1352 * Advanced Programmable Interrupt Controller.
1353 * SMP: Each CPU has a LAPIC, but we have a single device representing all LAPICs states,
1354 * thus only single insert
1355 */
1356 if (fEnableAPIC)
1357 {
1358 InsertConfigNode(pDevices, "apic", &pDev);
1359 InsertConfigNode(pDev, "0", &pInst);
1360 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1361 InsertConfigNode(pInst, "Config", &pCfg);
1362 InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1363 PDMAPICMODE enmAPICMode = PDMAPICMODE_APIC;
1364 if (fEnableX2APIC)
1365 enmAPICMode = PDMAPICMODE_X2APIC;
1366 else if (!fEnableAPIC)
1367 enmAPICMode = PDMAPICMODE_NONE;
1368 InsertConfigInteger(pCfg, "Mode", enmAPICMode);
1369 InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1370
1371 if (fIOAPIC)
1372 {
1373 /*
1374 * I/O Advanced Programmable Interrupt Controller.
1375 */
1376 InsertConfigNode(pDevices, "ioapic", &pDev);
1377 InsertConfigNode(pDev, "0", &pInst);
1378 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1379 InsertConfigNode(pInst, "Config", &pCfg);
1380 InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1381 if (enmIommuType == IommuType_AMD)
1382 InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1383 else if (enmIommuType == IommuType_Intel)
1384 {
1385 InsertConfigString(pCfg, "ChipType", "DMAR");
1386 InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1387 }
1388 }
1389 }
1390
1391 /*
1392 * RTC MC146818.
1393 */
1394 InsertConfigNode(pDevices, "mc146818", &pDev);
1395 InsertConfigNode(pDev, "0", &pInst);
1396 InsertConfigNode(pInst, "Config", &pCfg);
1397 BOOL fRTCUseUTC;
1398 hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
1399 InsertConfigInteger(pCfg, "UseUTC", fRTCUseUTC ? 1 : 0);
1400
1401 /*
1402 * VGA.
1403 */
1404 ComPtr<IGraphicsAdapter> pGraphicsAdapter;
1405 hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
1406 GraphicsControllerType_T enmGraphicsController;
1407 hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
1408 switch (enmGraphicsController)
1409 {
1410 case GraphicsControllerType_Null:
1411 break;
1412#ifdef VBOX_WITH_VMSVGA
1413 case GraphicsControllerType_VMSVGA:
1414 InsertConfigInteger(pHM, "LovelyMesaDrvWorkaround", 1); /* hits someone else logging backdoor. */
1415 InsertConfigInteger(pNEM, "LovelyMesaDrvWorkaround", 1); /* hits someone else logging backdoor. */
1416 RT_FALL_THROUGH();
1417 case GraphicsControllerType_VBoxSVGA:
1418#endif
1419 case GraphicsControllerType_VBoxVGA:
1420 vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine, pGraphicsAdapter, firmwareSettings);
1421 if (FAILED(vrc))
1422 return vrc;
1423 break;
1424 default:
1425 AssertMsgFailed(("Invalid graphicsController=%d\n", enmGraphicsController));
1426 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1427 N_("Invalid graphics controller type '%d'"), enmGraphicsController);
1428 }
1429
1430 /*
1431 * Firmware.
1432 */
1433 FirmwareType_T eFwType = FirmwareType_BIOS;
1434 hrc = firmwareSettings->COMGETTER(FirmwareType)(&eFwType); H();
1435
1436#ifdef VBOX_WITH_EFI
1437 BOOL fEfiEnabled = (eFwType >= FirmwareType_EFI) && (eFwType <= FirmwareType_EFIDUAL);
1438#else
1439 BOOL fEfiEnabled = false;
1440#endif
1441 if (!fEfiEnabled)
1442 {
1443 /*
1444 * PC Bios.
1445 */
1446 InsertConfigNode(pDevices, "pcbios", &pDev);
1447 InsertConfigNode(pDev, "0", &pInst);
1448 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1449 InsertConfigNode(pInst, "Config", &pBiosCfg);
1450 InsertConfigInteger(pBiosCfg, "NumCPUs", cCpus);
1451 InsertConfigString(pBiosCfg, "HardDiskDevice", "piix3ide");
1452 InsertConfigString(pBiosCfg, "FloppyDevice", "i82078");
1453 InsertConfigInteger(pBiosCfg, "IOAPIC", fIOAPIC);
1454 InsertConfigInteger(pBiosCfg, "APIC", uFwAPIC);
1455 BOOL fPXEDebug;
1456 hrc = firmwareSettings->COMGETTER(PXEDebugEnabled)(&fPXEDebug); H();
1457 InsertConfigInteger(pBiosCfg, "PXEDebug", fPXEDebug);
1458 InsertConfigBytes(pBiosCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1459 BOOL fUuidLe;
1460 hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1461 InsertConfigInteger(pBiosCfg, "UuidLe", fUuidLe);
1462 BOOL fAutoSerialNumGen;
1463 hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1464 if (fAutoSerialNumGen)
1465 InsertConfigString(pBiosCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1466 InsertConfigNode(pBiosCfg, "NetBoot", &pNetBootCfg);
1467 InsertConfigInteger(pBiosCfg, "McfgBase", uMcfgBase);
1468 InsertConfigInteger(pBiosCfg, "McfgLength", cbMcfgLength);
1469
1470 AssertMsgReturn(SchemaDefs::MaxBootPosition <= 9, ("Too many boot devices %d\n", SchemaDefs::MaxBootPosition),
1471 VERR_INVALID_PARAMETER);
1472
1473 for (ULONG pos = 1; pos <= SchemaDefs::MaxBootPosition; ++pos)
1474 {
1475 DeviceType_T enmBootDevice;
1476 hrc = pMachine->GetBootOrder(pos, &enmBootDevice); H();
1477
1478 char szParamName[] = "BootDeviceX";
1479 szParamName[sizeof(szParamName) - 2] = (char)(pos - 1 + '0');
1480
1481 const char *pszBootDevice;
1482 switch (enmBootDevice)
1483 {
1484 case DeviceType_Null:
1485 pszBootDevice = "NONE";
1486 break;
1487 case DeviceType_HardDisk:
1488 pszBootDevice = "IDE";
1489 break;
1490 case DeviceType_DVD:
1491 pszBootDevice = "DVD";
1492 break;
1493 case DeviceType_Floppy:
1494 pszBootDevice = "FLOPPY";
1495 break;
1496 case DeviceType_Network:
1497 pszBootDevice = "LAN";
1498 break;
1499 default:
1500 AssertMsgFailed(("Invalid enmBootDevice=%d\n", enmBootDevice));
1501 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1502 N_("Invalid boot device '%d'"), enmBootDevice);
1503 }
1504 InsertConfigString(pBiosCfg, szParamName, pszBootDevice);
1505 }
1506
1507 /** @todo @bugref{7145}: We might want to enable this by default for new VMs. For now,
1508 * this is required for Windows 2012 guests. */
1509 if (osTypeId == GUEST_OS_ID_STR_X64("Windows2012"))
1510 InsertConfigInteger(pBiosCfg, "DmiExposeMemoryTable", 1); /* boolean */
1511 }
1512 else
1513 {
1514 /* Autodetect firmware type, basing on guest type */
1515 if (eFwType == FirmwareType_EFI)
1516 eFwType = fIsGuest64Bit ? FirmwareType_EFI64 : FirmwareType_EFI32;
1517 bool const f64BitEntry = eFwType == FirmwareType_EFI64;
1518
1519 Assert(eFwType == FirmwareType_EFI64 || eFwType == FirmwareType_EFI32 || eFwType == FirmwareType_EFIDUAL);
1520#ifdef VBOX_WITH_EFI_IN_DD2
1521 const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "VBoxEFIDual.fd"
1522 : eFwType == FirmwareType_EFI32 ? "VBoxEFI32.fd"
1523 : "VBoxEFI64.fd";
1524#else
1525 Utf8Str efiRomFile;
1526 vrc = findEfiRom(virtualBox, PlatformArchitecture_x86, eFwType, &efiRomFile);
1527 AssertRCReturn(vrc, vrc);
1528 const char *pszEfiRomFile = efiRomFile.c_str();
1529#endif
1530
1531 /* Get boot args */
1532 Utf8Str bootArgs;
1533 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiBootArgs", &bootArgs);
1534
1535 /* Get device props */
1536 Utf8Str deviceProps;
1537 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiDeviceProps", &deviceProps);
1538
1539 /* Get NVRAM file name */
1540 Utf8Str strNvram = mptrNvramStore->i_getNonVolatileStorageFile();
1541
1542 BOOL fUuidLe;
1543 hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1544
1545 BOOL fAutoSerialNumGen;
1546 hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1547
1548 /* Get graphics mode settings */
1549 uint32_t u32GraphicsMode = UINT32_MAX;
1550 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsMode", &strTmp);
1551 if (strTmp.isEmpty())
1552 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGopMode", &strTmp);
1553 if (!strTmp.isEmpty())
1554 u32GraphicsMode = strTmp.toUInt32();
1555
1556 /* Get graphics resolution settings, with some sanity checking */
1557 Utf8Str strResolution;
1558 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsResolution", &strResolution);
1559 if (!strResolution.isEmpty())
1560 {
1561 size_t pos = strResolution.find("x");
1562 if (pos != strResolution.npos)
1563 {
1564 Utf8Str strH, strV;
1565 strH.assignEx(strResolution, 0, pos);
1566 strV.assignEx(strResolution, pos+1, strResolution.length()-pos-1);
1567 uint32_t u32H = strH.toUInt32();
1568 uint32_t u32V = strV.toUInt32();
1569 if (u32H == 0 || u32V == 0)
1570 strResolution.setNull();
1571 }
1572 else
1573 strResolution.setNull();
1574 }
1575 else
1576 {
1577 uint32_t u32H = 0;
1578 uint32_t u32V = 0;
1579 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiHorizontalResolution", &strTmp);
1580 if (strTmp.isEmpty())
1581 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaHorizontalResolution", &strTmp);
1582 if (!strTmp.isEmpty())
1583 u32H = strTmp.toUInt32();
1584
1585 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiVerticalResolution", &strTmp);
1586 if (strTmp.isEmpty())
1587 GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaVerticalResolution", &strTmp);
1588 if (!strTmp.isEmpty())
1589 u32V = strTmp.toUInt32();
1590 if (u32H != 0 && u32V != 0)
1591 strResolution = Utf8StrFmt("%ux%u", u32H, u32V);
1592 }
1593
1594 /*
1595 * EFI subtree.
1596 */
1597 InsertConfigNode(pDevices, "efi", &pDev);
1598 InsertConfigNode(pDev, "0", &pInst);
1599 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1600 InsertConfigNode(pInst, "Config", &pCfg);
1601 InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1602 InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1603 InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1604 InsertConfigString(pCfg, "EfiRom", pszEfiRomFile);
1605 InsertConfigString(pCfg, "BootArgs", bootArgs);
1606 InsertConfigString(pCfg, "DeviceProps", deviceProps);
1607 InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1608 InsertConfigInteger(pCfg, "APIC", uFwAPIC);
1609 InsertConfigBytes(pCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1610 InsertConfigInteger(pCfg, "UuidLe", fUuidLe);
1611 if (fAutoSerialNumGen)
1612 InsertConfigString(pCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1613 InsertConfigInteger(pCfg, "64BitEntry", f64BitEntry); /* boolean */
1614 InsertConfigString(pCfg, "NvramFile", strNvram);
1615 if (u32GraphicsMode != UINT32_MAX)
1616 InsertConfigInteger(pCfg, "GraphicsMode", u32GraphicsMode);
1617 if (!strResolution.isEmpty())
1618 InsertConfigString(pCfg, "GraphicsResolution", strResolution);
1619
1620 /* For OS X guests we'll force passing host's DMI info to the guest */
1621 if (fOsXGuest)
1622 {
1623 InsertConfigInteger(pCfg, "DmiUseHostInfo", 1);
1624 InsertConfigInteger(pCfg, "DmiExposeMemoryTable", 1);
1625 }
1626
1627 /* Attach the NVRAM storage driver. */
1628 InsertConfigNode(pInst, "LUN#0", &pLunL0);
1629 InsertConfigString(pLunL0, "Driver", "NvramStore");
1630 }
1631
1632 /*
1633 * The USB Controllers.
1634 */
1635 PCFGMNODE pUsbDevices = NULL;
1636 vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, aKbdHID, aPointingHID, &pUsbDevices);
1637
1638 /*
1639 * Storage controllers.
1640 */
1641 bool fFdcEnabled = false;
1642 vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
1643 pDevices, pUsbDevices, pBiosCfg, &fFdcEnabled); VRC();
1644
1645 /*
1646 * Network adapters
1647 */
1648 std::list<BootNic> llBootNics;
1649 vrc = i_configNetworkCtrls(pMachine, platformProperties, chipsetType, pBusMgr,
1650 pVMM, pUVM, pDevices, llBootNics); VRC();
1651
1652 /*
1653 * Build network boot information and transfer it to the BIOS.
1654 */
1655 if (pNetBootCfg && !llBootNics.empty()) /* NetBoot node doesn't exist for EFI! */
1656 {
1657 llBootNics.sort(); /* Sort the list by boot priority. */
1658
1659 char achBootIdx[] = "0";
1660 unsigned uBootIdx = 0;
1661
1662 for (std::list<BootNic>::iterator it = llBootNics.begin(); it != llBootNics.end(); ++it)
1663 {
1664 /* A NIC with priority 0 is only used if it's first in the list. */
1665 if (it->mBootPrio == 0 && uBootIdx != 0)
1666 break;
1667
1668 PCFGMNODE pNetBtDevCfg;
1669 achBootIdx[0] = (char)('0' + uBootIdx++); /* Boot device order. */
1670 InsertConfigNode(pNetBootCfg, achBootIdx, &pNetBtDevCfg);
1671 InsertConfigInteger(pNetBtDevCfg, "NIC", it->mInstance);
1672 InsertConfigInteger(pNetBtDevCfg, "PCIBusNo", it->mPCIAddress.miBus);
1673 InsertConfigInteger(pNetBtDevCfg, "PCIDeviceNo", it->mPCIAddress.miDevice);
1674 InsertConfigInteger(pNetBtDevCfg, "PCIFunctionNo", it->mPCIAddress.miFn);
1675 }
1676 }
1677
1678 /*
1679 * Serial (UART) Ports
1680 */
1681 /* serial enabled mask to be passed to dev ACPI */
1682 uint16_t auSerialIoPortBase[SchemaDefs::SerialPortCount] = {0};
1683 uint8_t auSerialIrq[SchemaDefs::SerialPortCount] = {0};
1684 InsertConfigNode(pDevices, "serial", &pDev);
1685 for (ULONG ulInstance = 0; ulInstance < SchemaDefs::SerialPortCount; ++ulInstance)
1686 {
1687 ComPtr<ISerialPort> serialPort;
1688 hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
1689 BOOL fEnabledSerPort = FALSE;
1690 if (serialPort)
1691 {
1692 hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
1693 }
1694 if (!fEnabledSerPort)
1695 {
1696 m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
1697 continue;
1698 }
1699
1700 InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1701 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1702 InsertConfigNode(pInst, "Config", &pCfg);
1703
1704 ULONG ulIRQ;
1705 hrc = serialPort->COMGETTER(IRQ)(&ulIRQ); H();
1706 InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1707 auSerialIrq[ulInstance] = (uint8_t)ulIRQ;
1708
1709 ULONG ulIOBase;
1710 hrc = serialPort->COMGETTER(IOAddress)(&ulIOBase); H();
1711 InsertConfigInteger(pCfg, "IOAddress", ulIOBase);
1712 auSerialIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1713
1714 BOOL fServer;
1715 hrc = serialPort->COMGETTER(Server)(&fServer); H();
1716 hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
1717 UartType_T eUartType;
1718 const char *pszUartType;
1719 hrc = serialPort->COMGETTER(UartType)(&eUartType); H();
1720 switch (eUartType)
1721 {
1722 case UartType_U16450: pszUartType = "16450"; break;
1723 case UartType_U16750: pszUartType = "16750"; break;
1724 default: AssertFailed(); RT_FALL_THRU();
1725 case UartType_U16550A: pszUartType = "16550A"; break;
1726 }
1727 InsertConfigString(pCfg, "UartType", pszUartType);
1728
1729 PortMode_T eHostMode;
1730 hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
1731
1732 m_aeSerialPortMode[ulInstance] = eHostMode;
1733 if (eHostMode != PortMode_Disconnected)
1734 {
1735 vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
1736 if (RT_FAILURE(vrc))
1737 return vrc;
1738 }
1739 }
1740
1741 /*
1742 * Parallel (LPT) Ports
1743 */
1744 /* parallel enabled mask to be passed to dev ACPI */
1745 uint16_t auParallelIoPortBase[SchemaDefs::ParallelPortCount] = {0};
1746 uint8_t auParallelIrq[SchemaDefs::ParallelPortCount] = {0};
1747 InsertConfigNode(pDevices, "parallel", &pDev);
1748 for (ULONG ulInstance = 0; ulInstance < SchemaDefs::ParallelPortCount; ++ulInstance)
1749 {
1750 ComPtr<IParallelPort> parallelPort;
1751 hrc = pMachine->GetParallelPort(ulInstance, parallelPort.asOutParam()); H();
1752 BOOL fEnabledParPort = FALSE;
1753 if (parallelPort)
1754 {
1755 hrc = parallelPort->COMGETTER(Enabled)(&fEnabledParPort); H();
1756 }
1757 if (!fEnabledParPort)
1758 continue;
1759
1760 InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1761 InsertConfigNode(pInst, "Config", &pCfg);
1762
1763 ULONG ulIRQ;
1764 hrc = parallelPort->COMGETTER(IRQ)(&ulIRQ); H();
1765 InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1766 auParallelIrq[ulInstance] = (uint8_t)ulIRQ;
1767 ULONG ulIOBase;
1768 hrc = parallelPort->COMGETTER(IOBase)(&ulIOBase); H();
1769 InsertConfigInteger(pCfg, "IOBase", ulIOBase);
1770 auParallelIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1771
1772 hrc = parallelPort->COMGETTER(Path)(bstr.asOutParam()); H();
1773 if (!bstr.isEmpty())
1774 {
1775 InsertConfigNode(pInst, "LUN#0", &pLunL0);
1776 InsertConfigString(pLunL0, "Driver", "HostParallel");
1777 InsertConfigNode(pLunL0, "Config", &pLunL1);
1778 InsertConfigString(pLunL1, "DevicePath", bstr);
1779 }
1780 }
1781
1782 vrc = i_configVmmDev(pMachine, pBusMgr, pDevices); VRC();
1783
1784 /*
1785 * Audio configuration.
1786 */
1787 bool fAudioEnabled = false;
1788 vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
1789 fOsXGuest, &fAudioEnabled); VRC();
1790
1791#if defined(VBOX_WITH_TPM)
1792 /*
1793 * Configure the Trusted Platform Module.
1794 */
1795 ComObjPtr<ITrustedPlatformModule> ptrTpm;
1796 TpmType_T enmTpmType = TpmType_None;
1797
1798 hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
1799 hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
1800 if (enmTpmType != TpmType_None)
1801 {
1802 InsertConfigNode(pDevices, "tpm", &pDev);
1803 InsertConfigNode(pDev, "0", &pInst);
1804 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1805 InsertConfigNode(pInst, "Config", &pCfg);
1806 InsertConfigNode(pInst, "LUN#0", &pLunL0);
1807
1808 switch (enmTpmType)
1809 {
1810 case TpmType_v1_2:
1811 case TpmType_v2_0:
1812 InsertConfigString(pLunL0, "Driver", "TpmEmuTpms");
1813 InsertConfigNode(pLunL0, "Config", &pCfg);
1814 InsertConfigInteger(pCfg, "TpmVersion", enmTpmType == TpmType_v1_2 ? 1 : 2);
1815 InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1816 InsertConfigString(pLunL1, "Driver", "NvramStore");
1817 break;
1818 case TpmType_Host:
1819#if defined(RT_OS_LINUX) || defined(RT_OS_WINDOWS)
1820 InsertConfigString(pLunL0, "Driver", "TpmHost");
1821 InsertConfigNode(pLunL0, "Config", &pCfg);
1822#endif
1823 break;
1824 case TpmType_Swtpm:
1825 hrc = ptrTpm->COMGETTER(Location)(bstr.asOutParam()); H();
1826 InsertConfigString(pLunL0, "Driver", "TpmEmu");
1827 InsertConfigNode(pLunL0, "Config", &pCfg);
1828 InsertConfigString(pCfg, "Location", bstr);
1829 break;
1830 default:
1831 AssertFailedBreak();
1832 }
1833 }
1834#endif
1835
1836 /*
1837 * ACPI
1838 */
1839 BOOL fACPI;
1840 hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
1841 if (fACPI)
1842 {
1843 /* Always show the CPU leafs when we have multiple VCPUs or when the IO-APIC is enabled.
1844 * The Windows SMP kernel needs a CPU leaf or else its idle loop will burn cpu cycles; the
1845 * intelppm driver refuses to register an idle state handler.
1846 * Always show CPU leafs for OS X guests. */
1847 BOOL fShowCpu = fOsXGuest;
1848 if (cCpus > 1 || fIOAPIC)
1849 fShowCpu = true;
1850
1851 BOOL fCpuHotPlug;
1852 hrc = pMachine->COMGETTER(CPUHotPlugEnabled)(&fCpuHotPlug); H();
1853
1854 InsertConfigNode(pDevices, "acpi", &pDev);
1855 InsertConfigNode(pDev, "0", &pInst);
1856 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1857 InsertConfigNode(pInst, "Config", &pCfg);
1858 hrc = pBusMgr->assignPCIDevice("acpi", pInst); H();
1859
1860 InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1861
1862 InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1863 InsertConfigInteger(pCfg, "FdcEnabled", fFdcEnabled);
1864 InsertConfigInteger(pCfg, "HpetEnabled", fHPETEnabled);
1865 InsertConfigInteger(pCfg, "SmcEnabled", fSmcEnabled);
1866 InsertConfigInteger(pCfg, "ShowRtc", fShowRtc);
1867 if (fOsXGuest && !llBootNics.empty())
1868 {
1869 BootNic aNic = llBootNics.front();
1870 uint32_t u32NicPCIAddr = (aNic.mPCIAddress.miDevice << 16) | aNic.mPCIAddress.miFn;
1871 InsertConfigInteger(pCfg, "NicPciAddress", u32NicPCIAddr);
1872 }
1873 if (fOsXGuest && fAudioEnabled)
1874 {
1875 PCIBusAddress Address;
1876 if (pBusMgr->findPCIAddress("hda", 0, Address))
1877 {
1878 uint32_t u32AudioPCIAddr = (Address.miDevice << 16) | Address.miFn;
1879 InsertConfigInteger(pCfg, "AudioPciAddress", u32AudioPCIAddr);
1880 }
1881 }
1882 if (fOsXGuest)
1883 {
1884 PCIBusAddress Address;
1885 if (pBusMgr->findPCIAddress("nvme", 0, Address))
1886 {
1887 uint32_t u32NvmePCIAddr = (Address.miDevice << 16) | Address.miFn;
1888 InsertConfigInteger(pCfg, "NvmePciAddress", u32NvmePCIAddr);
1889 }
1890 }
1891 if (enmIommuType == IommuType_AMD)
1892 {
1893 PCIBusAddress Address;
1894 if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1895 {
1896 uint32_t u32IommuAddress = (Address.miDevice << 16) | Address.miFn;
1897 InsertConfigInteger(pCfg, "IommuAmdEnabled", true);
1898 InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1899 if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1900 {
1901 uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) | Address.miFn;
1902 InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1903 }
1904 else
1905 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1906 N_("AMD IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1907 }
1908 }
1909 else if (enmIommuType == IommuType_Intel)
1910 {
1911 PCIBusAddress Address;
1912 if (pBusMgr->findPCIAddress("iommu-intel", 0, Address))
1913 {
1914 uint32_t u32IommuAddress = (Address.miDevice << 16) | Address.miFn;
1915 InsertConfigInteger(pCfg, "IommuIntelEnabled", true);
1916 InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1917 if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1918 {
1919 uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) | Address.miFn;
1920 InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1921 }
1922 else
1923 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1924 N_("Intel IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1925 }
1926 }
1927
1928 InsertConfigInteger(pCfg, "IocPciAddress", uIocPCIAddress);
1929 if (chipsetType == ChipsetType_ICH9)
1930 {
1931 InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1932 InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1933 /* 64-bit prefetch window root resource: Only for ICH9 and if PAE or Long Mode is enabled (@bugref{5454}). */
1934 if (fIsGuest64Bit || fEnablePAE)
1935 InsertConfigInteger(pCfg, "PciPref64Enabled", 1);
1936 }
1937 InsertConfigInteger(pCfg, "HostBusPciAddress", uHbcPCIAddress);
1938 InsertConfigInteger(pCfg, "ShowCpu", fShowCpu);
1939 InsertConfigInteger(pCfg, "CpuHotPlug", fCpuHotPlug);
1940
1941 InsertConfigInteger(pCfg, "Serial0IoPortBase", auSerialIoPortBase[0]);
1942 InsertConfigInteger(pCfg, "Serial0Irq", auSerialIrq[0]);
1943
1944 InsertConfigInteger(pCfg, "Serial1IoPortBase", auSerialIoPortBase[1]);
1945 InsertConfigInteger(pCfg, "Serial1Irq", auSerialIrq[1]);
1946
1947 if (auSerialIoPortBase[2])
1948 {
1949 InsertConfigInteger(pCfg, "Serial2IoPortBase", auSerialIoPortBase[2]);
1950 InsertConfigInteger(pCfg, "Serial2Irq", auSerialIrq[2]);
1951 }
1952
1953 if (auSerialIoPortBase[3])
1954 {
1955 InsertConfigInteger(pCfg, "Serial3IoPortBase", auSerialIoPortBase[3]);
1956 InsertConfigInteger(pCfg, "Serial3Irq", auSerialIrq[3]);
1957 }
1958
1959 InsertConfigInteger(pCfg, "Parallel0IoPortBase", auParallelIoPortBase[0]);
1960 InsertConfigInteger(pCfg, "Parallel0Irq", auParallelIrq[0]);
1961
1962 InsertConfigInteger(pCfg, "Parallel1IoPortBase", auParallelIoPortBase[1]);
1963 InsertConfigInteger(pCfg, "Parallel1Irq", auParallelIrq[1]);
1964
1965#if defined(VBOX_WITH_TPM)
1966 switch (enmTpmType)
1967 {
1968 case TpmType_v1_2:
1969 InsertConfigString(pCfg, "TpmMode", "tis1.2");
1970 break;
1971 case TpmType_v2_0:
1972 InsertConfigString(pCfg, "TpmMode", "fifo2.0");
1973 break;
1974 /** @todo Host and swtpm. */
1975 default:
1976 break;
1977 }
1978#endif
1979
1980 InsertConfigNode(pInst, "LUN#0", &pLunL0);
1981 InsertConfigString(pLunL0, "Driver", "ACPIHost");
1982 InsertConfigNode(pLunL0, "Config", &pCfg);
1983
1984 /* Attach the dummy CPU drivers */
1985 for (ULONG iCpuCurr = 1; iCpuCurr < cCpus; iCpuCurr++)
1986 {
1987 BOOL fCpuAttached = true;
1988
1989 if (fCpuHotPlug)
1990 {
1991 hrc = pMachine->GetCPUStatus(iCpuCurr, &fCpuAttached); H();
1992 }
1993
1994 if (fCpuAttached)
1995 {
1996 InsertConfigNode(pInst, Utf8StrFmt("LUN#%u", iCpuCurr).c_str(), &pLunL0);
1997 InsertConfigString(pLunL0, "Driver", "ACPICpu");
1998 InsertConfigNode(pLunL0, "Config", &pCfg);
1999 }
2000 }
2001 }
2002
2003 /*
2004 * Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
2005 */
2006 vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
2007 }
2008 catch (ConfigError &x)
2009 {
2010 // InsertConfig threw something:
2011 pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
2012 return x.m_vrc;
2013 }
2014 catch (HRESULT hrcXcpt)
2015 {
2016 AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
2017 }
2018
2019#ifdef VBOX_WITH_EXTPACK
2020 /*
2021 * Call the extension pack hooks if everything went well thus far.
2022 */
2023 if (RT_SUCCESS(vrc))
2024 {
2025 pAlock->release();
2026 vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
2027 pAlock->acquire();
2028 }
2029#endif
2030
2031 /*
2032 * Apply the CFGM overlay.
2033 */
2034 if (RT_SUCCESS(vrc))
2035 vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
2036
2037 /*
2038 * Dump all extradata API settings tweaks, both global and per VM.
2039 */
2040 if (RT_SUCCESS(vrc))
2041 vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
2042
2043#undef H
2044
2045 pAlock->release(); /* Avoid triggering the lock order inversion check. */
2046
2047 /*
2048 * Register VM state change handler.
2049 */
2050 int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
2051 AssertRC(vrc2);
2052 if (RT_SUCCESS(vrc))
2053 vrc = vrc2;
2054
2055 /*
2056 * Register VM runtime error handler.
2057 */
2058 vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
2059 AssertRC(vrc2);
2060 if (RT_SUCCESS(vrc))
2061 vrc = vrc2;
2062
2063 pAlock->acquire();
2064
2065 LogFlowFunc(("vrc = %Rrc\n", vrc));
2066 LogFlowFuncLeave();
2067
2068 return vrc;
2069}
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette