VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 102493

Last change on this file since 102493 was 101622, checked in by vboxsync, 14 months ago

Main/src-client/ConsoleImpl: Preliminary code to hook up the power button requests to the GPIO interface for an ARM guest, bugref:10538 [scm]
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1/* $Id: ConsoleImplConfigArmV8.cpp 101622 2023-10-27 13:05:01Z vboxsync $ */
2/** @file
3 * VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33#include "LoggingNew.h"
34
35#include "ConsoleImpl.h"
36#include "ResourceStoreImpl.h"
37#include "Global.h"
38#include "VMMDev.h"
39
40// generated header
41#include "SchemaDefs.h"
42
43#include "AutoCaller.h"
44
45#include <iprt/buildconfig.h>
46#include <iprt/ctype.h>
47#include <iprt/dir.h>
48#include <iprt/fdt.h>
49#include <iprt/file.h>
50#include <iprt/param.h>
51#include <iprt/path.h>
52#include <iprt/string.h>
53#include <iprt/system.h>
54#if 0 /* enable to play with lots of memory. */
55# include <iprt/env.h>
56#endif
57#include <iprt/stream.h>
58
59#include <iprt/formats/arm-psci.h>
60
61#include <VBox/vmm/vmmr3vtable.h>
62#include <VBox/vmm/vmapi.h>
63#include <VBox/err.h>
64#include <VBox/param.h>
65#include <VBox/version.h>
66#include <VBox/platforms/vbox-armv8.h>
67
68#include "BusAssignmentManager.h"
69#ifdef VBOX_WITH_EXTPACK
70# include "ExtPackManagerImpl.h"
71#endif
72
73
74/*********************************************************************************************************************************
75* Internal Functions *
76*********************************************************************************************************************************/
77
78/* Darwin compile kludge */
79#undef PVM
80
81#ifdef VBOX_WITH_VIRT_ARMV8
82/**
83 * Worker for configConstructor.
84 *
85 * @return VBox status code.
86 * @param pUVM The user mode VM handle.
87 * @param pVM The cross context VM handle.
88 * @param pVMM The VMM vtable.
89 * @param pAlock The automatic lock instance. This is for when we have
90 * to leave it in order to avoid deadlocks (ext packs and
91 * more).
92 *
93 * @todo This is a big hack at the moment and provides a static VM config to work with, will be adjusted later
94 * on to adhere to the VM config when sorting out the API bits.
95 */
96int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
97{
98 RT_NOREF(pVM /* when everything is disabled */);
99 ComPtr<IMachine> pMachine = i_machine();
100
101 HRESULT hrc;
102 Utf8Str strTmp;
103 Bstr bstr;
104
105 RTFDT hFdt = NIL_RTFDT;
106 int vrc = RTFdtCreateEmpty(&hFdt);
107 AssertRCReturn(vrc, vrc);
108
109#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
110#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
111
112 /** @todo Find a way to figure it out before CPUM is set up, can't use CPUMGetGuestAddrWidths() and on macOS we need
113 * access to Hypervisor.framework to query the ID registers (Linux can in theory parse /proc/cpuinfo, no idea for Windows). */
114 RTGCPHYS GCPhysTopOfAddrSpace = RT_BIT_64(36);
115
116 /*
117 * Get necessary objects and frequently used parameters.
118 */
119 ComPtr<IVirtualBox> virtualBox;
120 hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
121
122 ComPtr<IHost> host;
123 hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
124
125 PlatformArchitecture_T platformArchHost;
126 hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
127
128 ComPtr<ISystemProperties> systemProperties;
129 hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
130
131 ComPtr<IFirmwareSettings> firmwareSettings;
132 hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
133
134 ComPtr<INvramStore> nvramStore;
135 hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
136
137 hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
138 RTUUID HardwareUuid;
139 vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
140 AssertRCReturn(vrc, vrc);
141
142 ULONG cRamMBs;
143 hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
144 uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
145
146 ComPtr<IPlatform> platform;
147 hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
148
149 /* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
150#if 1 /* For now we only support running ARM VMs on ARM hosts. */
151 PlatformArchitecture_T platformArchMachine;
152 hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
153 if (platformArchMachine != platformArchHost)
154 return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
155 N_("VM platform architecture (%s) not supported on this host (%s)."),
156 Global::stringifyPlatformArchitecture(platformArchMachine),
157 Global::stringifyPlatformArchitecture(platformArchHost));
158#endif
159
160 ComPtr<IPlatformProperties> pPlatformProperties;
161 hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
162
163 ChipsetType_T chipsetType;
164 hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
165
166 ULONG cCpus = 1;
167 hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
168 Assert(cCpus);
169
170 ULONG ulCpuExecutionCap = 100;
171 hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
172
173 LogRel(("Guest architecture: ARM\n"));
174
175 Bstr osTypeId;
176 hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
177 LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
178
179 BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
180
181 /*
182 * Get root node first.
183 * This is the only node in the tree.
184 */
185 PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
186 Assert(pRoot);
187
188 // catching throws from InsertConfigString and friends.
189 try
190 {
191
192 /*
193 * Set the root (and VMM) level values.
194 */
195 hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
196 InsertConfigString(pRoot, "Name", bstr);
197 InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
198 InsertConfigInteger(pRoot, "NumCPUs", cCpus);
199 InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
200 InsertConfigInteger(pRoot, "TimerMillies", 10);
201
202 /*
203 * NEM
204 */
205 PCFGMNODE pNEM;
206 InsertConfigNode(pRoot, "NEM", &pNEM);
207
208 uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
209 Assert(idPHandleIntCtrl != UINT32_MAX);
210 uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
211 Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
212 uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
213 Assert(idPHandleAbpPClk != UINT32_MAX);
214 uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
215 Assert(idPHandleGpio != UINT32_MAX);
216
217 uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
218 for (uint32_t i = 0; i < cCpus; i++)
219 {
220 aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
221 Assert(aidPHandleCpus[i] != UINT32_MAX);
222 }
223
224 vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
225 vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
226 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
227 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
228 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
229
230 /* Configure the Power State Coordination Interface. */
231 vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
232 vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
233 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
234 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
235 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
236 vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
237 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
238 "arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
239 vrc = RTFdtNodeFinalize(hFdt); VRC();
240
241 /* Configure the timer and clock. */
242 InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
243 vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
244 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
245 0x01, 0x0d, 0x104,
246 0x01, 0x0e, 0x104,
247 0x01, 0x0b, 0x104,
248 0x01, 0x0a, 0x104); VRC();
249 vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
250 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
251 vrc = RTFdtNodeFinalize(hFdt);
252
253 vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
254 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
255 vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
256 vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24 * 1000 * 1000); VRC();
257 vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
258 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
259 vrc = RTFdtNodeFinalize(hFdt);
260
261 /*
262 * MM values.
263 */
264 PCFGMNODE pMM;
265 InsertConfigNode(pRoot, "MM", &pMM);
266
267 /*
268 * Memory setup.
269 */
270 PCFGMNODE pMem = NULL;
271 InsertConfigNode(pMM, "MemRegions", &pMem);
272
273 PCFGMNODE pMemRegion = NULL;
274 InsertConfigNode(pMem, "Conventional", &pMemRegion);
275 InsertConfigInteger(pMemRegion, "GCPhysStart", 0x40000000);
276 InsertConfigInteger(pMemRegion, "Size", cbRam);
277
278 vrc = RTFdtNodeAddF(hFdt, "memory@%RX32", 0x40000000); VRC();
279 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, 0x40000000, cbRam); VRC();
280 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
281 vrc = RTFdtNodeFinalize(hFdt); VRC();
282
283 /* Configure the CPUs in the system, only one socket and cluster at the moment. */
284 vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
285 vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
286 vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
287
288 vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
289 vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
290
291 for (uint32_t i = 0; i < cCpus; i++)
292 {
293 vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
294 vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
295 vrc = RTFdtNodeFinalize(hFdt); VRC();
296 }
297
298 vrc = RTFdtNodeFinalize(hFdt); VRC();
299 vrc = RTFdtNodeFinalize(hFdt); VRC();
300
301 for (uint32_t i = 0; i < cCpus; i++)
302 {
303 vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
304 vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
305 vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
306 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
307 vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
308 if (cCpus > 1)
309 {
310 vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
311 }
312 vrc = RTFdtNodeFinalize(hFdt); VRC();
313 }
314
315 vrc = RTFdtNodeFinalize(hFdt); VRC();
316
317
318 /*
319 * PDM config.
320 * Load drivers in VBoxC.[so|dll]
321 */
322 vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
323
324
325 /*
326 * VGA.
327 */
328 ComPtr<IGraphicsAdapter> pGraphicsAdapter;
329 hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
330 GraphicsControllerType_T enmGraphicsController;
331 hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
332
333 /*
334 * Devices
335 */
336 PCFGMNODE pDevices = NULL; /* /Devices */
337 PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
338 PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
339 PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
340 PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
341
342 InsertConfigNode(pRoot, "Devices", &pDevices);
343
344 InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
345
346 InsertConfigNode(pDevices, "platform", &pDev);
347 InsertConfigNode(pDev, "0", &pInst);
348 InsertConfigNode(pInst, "Config", &pCfg);
349 InsertConfigNode(pInst, "LUN#0", &pLunL0);
350 InsertConfigString(pLunL0, "Driver", "ResourceStore");
351
352 /* Add the resources. */
353 PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
354 PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
355 InsertConfigString(pCfg, "ResourceNamespace", "resources");
356 InsertConfigNode(pCfg, "Resources", &pResources);
357 InsertConfigNode(pResources, "EfiRom", &pRes);
358 InsertConfigInteger(pRes, "RegisterAsRom", 1);
359 InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
360
361 /** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
362 /*
363 * Firmware.
364 */
365 FirmwareType_T eFwType = FirmwareType_EFI64;
366#ifdef VBOX_WITH_EFI_IN_DD2
367 const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
368 : eFwType == FirmwareType_EFI32 ? "VBoxEFIAArch32.fd"
369 : "VBoxEFIAArch64.fd";
370 const char *pszKey = "ResourceId";
371#else
372 Utf8Str efiRomFile;
373 vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
374 AssertRCReturn(vrc, vrc);
375 const char *pszEfiRomFile = efiRomFile.c_str();
376 const char *pszKey = "Filename";
377#endif
378 InsertConfigString(pRes, pszKey, pszEfiRomFile);
379
380 InsertConfigNode(pResources, "ArmV8Desc", &pRes);
381 InsertConfigInteger(pRes, "RegisterAsRom", 1);
382 InsertConfigInteger(pRes, "GCPhysLoadAddress", UINT64_MAX); /* End of physical address space. */
383 InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
384
385 /*
386 * Configure the interrupt controller.
387 */
388 InsertConfigNode(pDevices, "gic", &pDev);
389 InsertConfigNode(pDev, "0", &pInst);
390 InsertConfigInteger(pInst, "Trusted", 1);
391 InsertConfigNode(pInst, "Config", &pCfg);
392 InsertConfigInteger(pCfg, "DistributorMmioBase", 0x08000000);
393 InsertConfigInteger(pCfg, "RedistributorMmioBase", 0x080a0000);
394
395 vrc = RTFdtNodeAddF(hFdt, "intc@%RX32", 0x08000000); VRC();
396 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
397 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
398 0x08000000, 0x10000, /* Distributor */
399 0x080a0000, 0xf60000); /* Re-Distributor */ VRC();
400 vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
401 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
402 vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
403 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
404 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
405 vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
406 vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
407
408#if 0
409 vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
410 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
411 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
412 vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
413 vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
414 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
415 vrc = RTFdtNodeFinalize(hFdt); VRC();
416#endif
417
418 vrc = RTFdtNodeFinalize(hFdt); VRC();
419
420 if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
421 {
422 InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
423 InsertConfigNode(pDev, "0", &pInst);
424 InsertConfigNode(pInst, "Config", &pCfg);
425 InsertConfigInteger(pCfg, "MmioSize", 4096);
426 InsertConfigInteger(pCfg, "MmioBase", 0x09020000);
427 InsertConfigInteger(pCfg, "DmaEnabled", 1);
428 InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
429 InsertConfigNode(pInst, "LUN#0", &pLunL0);
430 InsertConfigString(pLunL0, "Driver", "MainDisplay");
431
432 vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RX32", 0x09020000); VRC();
433 vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
434 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, 0x09020000, 0x18); VRC();
435 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
436 vrc = RTFdtNodeFinalize(hFdt); VRC();
437 }
438
439 InsertConfigNode(pDevices, "flash-cfi", &pDev);
440 InsertConfigNode(pDev, "0", &pInst);
441 InsertConfigNode(pInst, "Config", &pCfg);
442 InsertConfigInteger(pCfg, "BaseAddress", 64 * _1M);
443 InsertConfigInteger(pCfg, "Size", 768 * _1K);
444 InsertConfigString(pCfg, "FlashFile", "nvram");
445 /* Attach the NVRAM storage driver. */
446 InsertConfigNode(pInst, "LUN#0", &pLunL0);
447 InsertConfigString(pLunL0, "Driver", "NvramStore");
448
449 vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
450 vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
451 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
452 0, 0x04000000, /* First region (EFI). */
453 0x04000000, 0x04000000); /* Second region (NVRAM). */ VRC();
454 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
455 vrc = RTFdtNodeFinalize(hFdt); VRC();
456
457 InsertConfigNode(pDevices, "arm-pl011", &pDev);
458 for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
459 {
460 ComPtr<ISerialPort> serialPort;
461 hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
462 BOOL fEnabledSerPort = FALSE;
463 if (serialPort)
464 {
465 hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
466 }
467 if (!fEnabledSerPort)
468 {
469 m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
470 continue;
471 }
472
473 InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
474 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
475 InsertConfigNode(pInst, "Config", &pCfg);
476
477 InsertConfigInteger(pCfg, "Irq", 1);
478 InsertConfigInteger(pCfg, "MmioBase", 0x09000000);
479
480 vrc = RTFdtNodeAddF(hFdt, "pl011@%RX32", 0x09000000); VRC();
481 vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
482 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
483 idPHandleAbpPClk, idPHandleAbpPClk); VRC();
484 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x01, 0x04); VRC();
485 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, 0x09000000, _4K); VRC();
486 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
487 "arm,pl011", "arm,primecell"); VRC();
488 vrc = RTFdtNodeFinalize(hFdt); VRC();
489
490 BOOL fServer;
491 hrc = serialPort->COMGETTER(Server)(&fServer); H();
492 hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
493
494 PortMode_T eHostMode;
495 hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
496
497 m_aeSerialPortMode[ulInstance] = eHostMode;
498 if (eHostMode != PortMode_Disconnected)
499 {
500 vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
501 if (RT_FAILURE(vrc))
502 return vrc;
503 }
504 }
505
506 BOOL fRTCUseUTC;
507 hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
508
509 InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
510 InsertConfigNode(pDev, "0", &pInst);
511 InsertConfigNode(pInst, "Config", &pCfg);
512 InsertConfigInteger(pCfg, "Irq", 2);
513 InsertConfigInteger(pCfg, "MmioBase", 0x09010000);
514 InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
515
516 vrc = RTFdtNodeAddF(hFdt, "pl032@%RX32", 0x09010000); VRC();
517 vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
518 vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
519 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x02, 0x04); VRC();
520 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x09010000, 0, 0x1000); VRC();
521 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
522 "arm,pl031", "arm,primecell"); VRC();
523 vrc = RTFdtNodeFinalize(hFdt); VRC();
524
525 /* Configure gpio keys. */
526 InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
527 InsertConfigNode(pDev, "0", &pInst);
528 InsertConfigNode(pInst, "Config", &pCfg);
529 InsertConfigInteger(pCfg, "Irq", 7);
530 InsertConfigInteger(pCfg, "MmioBase", 0x09030000);
531 vrc = RTFdtNodeAddF(hFdt, "pl061@%RX32", 0x09030000); VRC();
532 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
533 vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
534 vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
535 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, 0x07, 0x04); VRC();
536 vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
537 vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
538 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
539 "arm,pl061", "arm,primecell"); VRC();
540 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, 0x09030000, _4K); VRC();
541 vrc = RTFdtNodeFinalize(hFdt); VRC();
542
543 InsertConfigNode(pInst, "LUN#0", &pLunL0);
544 InsertConfigString(pLunL0, "Driver", "GpioButton");
545 InsertConfigNode(pLunL0, "Config", &pCfg);
546 InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
547 InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
548
549 vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
550 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
551
552 vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
553 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
554 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
555 vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
556 vrc = RTFdtNodeFinalize(hFdt); VRC();
557
558 vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
559 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
560 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
561 vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
562 vrc = RTFdtNodeFinalize(hFdt);
563
564 vrc = RTFdtNodeFinalize(hFdt); VRC();
565
566 uint32_t aPinIrqs[] = { 3, 4, 5, 6 };
567 InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
568 InsertConfigNode(pDev, "0", &pInst);
569 InsertConfigNode(pInst, "Config", &pCfg);
570 InsertConfigInteger(pCfg, "MmioEcamBase", 0x3f000000);
571 InsertConfigInteger(pCfg, "MmioEcamLength", 0x01000000);
572 InsertConfigInteger(pCfg, "MmioPioBase", 0x3eff0000);
573 InsertConfigInteger(pCfg, "MmioPioSize", 0x0000ffff);
574 InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
575 InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
576 InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
577 InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
578 vrc = RTFdtNodeAddF(hFdt, "pcie@%RX32", 0x10000000); VRC();
579 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
580
581 uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
582 uint32_t *pau32IrqCell = &aIrqCells[0];
583 uint32_t iIrqPinSwizzle = 0;
584
585 for (uint32_t i = 0; i < 32; i++)
586 {
587 for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
588 {
589 pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
590 pau32IrqCell[1] = 0;
591 pau32IrqCell[2] = 0;
592 pau32IrqCell[3] = iIrqPin + 1;
593 pau32IrqCell[4] = idPHandleIntCtrl;
594 pau32IrqCell[5] = 0;
595 pau32IrqCell[6] = 0;
596 pau32IrqCell[7] = 0;
597 pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
598 pau32IrqCell[9] = 0x04;
599 pau32IrqCell += 10;
600 }
601
602 iIrqPinSwizzle++;
603 }
604
605 vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]);
606 vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
607 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 14,
608 0x1000000, 0, 0, 0, 0x3eff0000, 0, 0x10000,
609 0x2000000, 0, 0x10000000, 0, 0x10000000, 0,
610 0x2eff0000); VRC();
611 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, 0x3f000000, 0x1000000); VRC();
612 /** @todo msi-map */
613 vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
614 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
615 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
616 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
617 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
618 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
619 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
620 vrc = RTFdtNodeFinalize(hFdt); VRC();
621
622 /*
623 * VMSVGA compliant graphics controller.
624 */
625 if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
626 && enmGraphicsController != GraphicsControllerType_Null)
627 {
628 vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
629 pGraphicsAdapter, firmwareSettings,
630 true /*fForceVmSvga3*/, false /*fExposeLegacyVga*/); VRC();
631 }
632
633 /*
634 * The USB Controllers and input devices.
635 */
636#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
637 KeyboardHIDType_T aKbdHID;
638 hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
639#endif
640
641 PointingHIDType_T aPointingHID;
642 hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
643
644 PCFGMNODE pUsbDevices = NULL;
645 vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
646
647 /*
648 * Storage controllers.
649 */
650 bool fFdcEnabled = false;
651 vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
652 pDevices, pUsbDevices, NULL /*pBiosCfg*/, &fFdcEnabled); VRC();
653
654 /*
655 * Network adapters
656 */
657 std::list<BootNic> llBootNics;
658 vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
659 pVMM, pUVM, pDevices, llBootNics); VRC();
660
661 /*
662 * The VMM device.
663 */
664 vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /*fMmioReq*/); VRC();
665
666 /*
667 * Audio configuration.
668 */
669 bool fAudioEnabled = false;
670 vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
671 false /*fOsXGuest*/, &fAudioEnabled); VRC();
672 }
673 catch (ConfigError &x)
674 {
675 RTFdtDestroy(hFdt);
676
677 // InsertConfig threw something:
678 pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
679 return x.m_vrc;
680 }
681 catch (HRESULT hrcXcpt)
682 {
683 RTFdtDestroy(hFdt);
684 AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
685 }
686
687#ifdef VBOX_WITH_EXTPACK
688 /*
689 * Call the extension pack hooks if everything went well thus far.
690 */
691 if (RT_SUCCESS(vrc))
692 {
693 pAlock->release();
694 vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
695 pAlock->acquire();
696 }
697#endif
698
699#if 0
700 vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
701 vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
702 vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
703 vrc = RTFdtNodeFinalize(hFdt);
704#endif
705
706 /* Finalize the FDT and add it to the resource store. */
707 vrc = RTFdtFinalize(hFdt);
708 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
709
710 RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
711 vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /*cbEstimate*/, &hVfsFileDesc);
712 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
713 RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
714 AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
715
716 /* Initialize the VBox platform descriptor. */
717 VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
718
719 vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /*fFlags*/, hVfsIosDesc, NULL /*pErrInfo*/);
720 if (RT_SUCCESS(vrc))
721 vrc = RTVfsFileQuerySize(hVfsFileDesc, &ArmV8Platform.cbFdt);
722 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
723
724 vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(ArmV8Platform.cbFdt, _64K) - ArmV8Platform.cbFdt));
725 AssertRCReturn(vrc, vrc);
726
727 ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
728 ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
729 ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
730 ArmV8Platform.fFlags = 0;
731 ArmV8Platform.u64PhysAddrRamBase = UINT64_C(0x40000000);
732 ArmV8Platform.cbRamBase = cbRam;
733 ArmV8Platform.u64OffBackFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
734 ArmV8Platform.cbFdt = RT_ALIGN_64(ArmV8Platform.cbFdt, _64K);
735 ArmV8Platform.u64OffBackAcpiXsdp = 0;
736 ArmV8Platform.cbAcpiXsdp = 0;
737 ArmV8Platform.u64OffBackUefiRom = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform);
738 ArmV8Platform.cbUefiRom = _64M; /** @todo Fixed reservation but the ROM region is usually much smaller. */
739 ArmV8Platform.u64OffBackMmio = GCPhysTopOfAddrSpace - sizeof(ArmV8Platform) - 0x08000000; /** @todo Start of generic MMIO area containing the GIC,UART,RTC, etc. Will be changed soon */
740 ArmV8Platform.cbMmio = _128M;
741
742 /* Add the VBox platform descriptor to the resource store. */
743 vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /*fBlocking*/, NULL /*pcbWritten*/);
744 RTVfsIoStrmRelease(hVfsIosDesc);
745 vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
746 RTVfsFileRelease(hVfsFileDesc);
747 AssertRCReturn(vrc, vrc);
748
749 /* Dump the DTB for debugging purposes if requested. */
750 Bstr DtbDumpVal;
751 hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
752 DtbDumpVal.asOutParam());
753 if ( hrc == S_OK
754 && DtbDumpVal.isNotEmpty())
755 {
756 vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /*fFlags*/, Utf8Str(DtbDumpVal).c_str(), NULL /*pErrInfo*/);
757 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
758 }
759
760
761 /*
762 * Apply the CFGM overlay.
763 */
764 if (RT_SUCCESS(vrc))
765 vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
766
767 /*
768 * Dump all extradata API settings tweaks, both global and per VM.
769 */
770 if (RT_SUCCESS(vrc))
771 vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
772
773#undef H
774
775 pAlock->release(); /* Avoid triggering the lock order inversion check. */
776
777 /*
778 * Register VM state change handler.
779 */
780 int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
781 AssertRC(vrc2);
782 if (RT_SUCCESS(vrc))
783 vrc = vrc2;
784
785 /*
786 * Register VM runtime error handler.
787 */
788 vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
789 AssertRC(vrc2);
790 if (RT_SUCCESS(vrc))
791 vrc = vrc2;
792
793 pAlock->acquire();
794
795 LogFlowFunc(("vrc = %Rrc\n", vrc));
796 LogFlowFuncLeave();
797
798 return vrc;
799}
800#endif /* !VBOX_WITH_VIRT_ARMV8 */
801
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