VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 67981

Last change on this file since 67981 was 64281, checked in by vboxsync, 8 years ago

IPRT,SUP: Major vboxdrv and GIP version change; more flexible processor group handling on Windows.
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File size: 15.3 KB
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1/* $Id: tstGIP-2.cpp 64281 2016-10-15 16:46:29Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28/*********************************************************************************************************************************
29* Header Files *
30*********************************************************************************************************************************/
31#include <VBox/sup.h>
32#include <VBox/err.h>
33#include <VBox/param.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36#include <iprt/alloc.h>
37#include <iprt/thread.h>
38#include <iprt/stream.h>
39#include <iprt/string.h>
40#include <iprt/initterm.h>
41#include <iprt/getopt.h>
42#include <iprt/x86.h>
43
44
45/**
46 * Entry point.
47 */
48extern "C" DECLEXPORT(int) TrustedMain(int argc, char **argv)
49{
50 RTR3InitExe(argc, &argv, 0);
51
52 /*
53 * Parse args
54 */
55 static const RTGETOPTDEF g_aOptions[] =
56 {
57 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
58 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
59 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
60 { "--spin", 's', RTGETOPT_REQ_NOTHING },
61 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
62 * CpuHz deviation in a separate column. */
63 { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
64 * implies updating GIP CpuHz even when invariant) */
65 };
66
67 bool fHex = true;
68 bool fSpin = false;
69 bool fCompat = true;
70 bool fTestMode = true;
71 int ch;
72 uint32_t cIterations = 40;
73 uint64_t uCpuHzRef = UINT64_MAX;
74 RTGETOPTUNION ValueUnion;
75 RTGETOPTSTATE GetState;
76 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
77 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
78 {
79 switch (ch)
80 {
81 case 'i':
82 cIterations = ValueUnion.u32;
83 break;
84
85 case 'd':
86 fHex = false;
87 break;
88
89 case 'h':
90 fHex = true;
91 break;
92
93 case 's':
94 fSpin = true;
95 break;
96
97 case 'r':
98 uCpuHzRef = ValueUnion.u64;
99 break;
100
101 case 't':
102 fTestMode = false;
103 break;
104
105 default:
106 return RTGetOptPrintError(ch, &ValueUnion);
107 }
108 }
109
110 /*
111 * Init
112 */
113 PSUPDRVSESSION pSession = NIL_RTR0PTR;
114 int rc = SUPR3Init(&pSession);
115 if (RT_SUCCESS(rc))
116 {
117 if (g_pSUPGlobalInfoPage)
118 {
119 uint64_t uCpuHzOverallDeviation = 0;
120 uint32_t cCpuHzNotCompat = 0;
121 int64_t iCpuHzMaxDeviation = 0;
122 int32_t cCpuHzOverallDevCnt = 0;
123 uint32_t cCpuHzChecked = 0;
124
125 /* Pick current CpuHz as the reference if none was specified. */
126 if (uCpuHzRef == UINT64_MAX)
127 uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
128
129 if ( fTestMode
130 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
131 SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
132
133 RTPrintf("tstGIP-2: u32Mode=%d (%s) fTestMode=%RTbool u32Version=%#x fGetGipCpu=%#RX32\n",
134 g_pSUPGlobalInfoPage->u32Mode,
135 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
136 fTestMode,
137 g_pSUPGlobalInfoPage->u32Version,
138 g_pSUPGlobalInfoPage->fGetGipCpu);
139 RTPrintf("tstGIP-2: cCpus=%d cPossibleCpus=%d cPossibleCpuGroups=%d cPresentCpus=%d cOnlineCpus=%d idCpuMax=%#x\n",
140 g_pSUPGlobalInfoPage->cCpus,
141 g_pSUPGlobalInfoPage->cPossibleCpus,
142 g_pSUPGlobalInfoPage->cPossibleCpuGroups,
143 g_pSUPGlobalInfoPage->cPresentCpus,
144 g_pSUPGlobalInfoPage->cOnlineCpus,
145 g_pSUPGlobalInfoPage->idCpuMax);
146 RTPrintf("tstGIP-2: u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64\n",
147 g_pSUPGlobalInfoPage->u32UpdateHz,
148 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
149 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
150 g_pSUPGlobalInfoPage->u64CpuHz,
151 uCpuHzRef);
152 for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
153 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState != SUPGIPCPUSTATE_INVALID)
154 {
155 SUPGIPCPU const *pGipCpu = &g_pSUPGlobalInfoPage->aCPUs[iCpu];
156 RTPrintf("tstGIP-2: aCPU[%u]: enmState=%d iCpuSet=%u idCpu=%#010x iCpuGroup=%u iCpuGroupMember=%u idApic=%#x\n",
157 iCpu, pGipCpu->enmState, pGipCpu->iCpuSet, pGipCpu->idCpu, pGipCpu->iCpuGroup,
158 pGipCpu->iCpuGroupMember, pGipCpu->idApic);
159 }
160
161 RTPrintf(fHex
162 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
163 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
164 uCpuHzRef ? " CpuHz deviation Compat " : "");
165 static SUPGIPCPU s_aaCPUs[2][256];
166 for (uint32_t i = 0; i < cIterations; i++)
167 {
168 /* Copy the data. */
169 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
170
171 /* Display it & find something to spin on. */
172 uint32_t u32TransactionId = 0;
173 uint32_t volatile *pu32TransactionId = NULL;
174 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
175 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
176 {
177 char szCpuHzDeviation[32];
178 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
179 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
180 if (uCpuHzRef)
181 {
182 /* Only CPU 0 is updated for invariant & sync modes, see supdrvGipUpdate(). */
183 if ( iCpu == 0
184 || g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_ASYNC_TSC)
185 {
186 /* Wait until the history validation code takes effect. */
187 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
188 {
189 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
190 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
191 bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /*fRelax*/);
192 if (uCpuHzDeviation <= 999999999)
193 {
194 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
195 iCpuHzMaxDeviation = iCpuHzDeviation;
196 uCpuHzOverallDeviation += uCpuHzDeviation;
197 cCpuHzOverallDevCnt++;
198 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
199 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
200 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
201 }
202 else
203 {
204 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s %RTbool ", "?",
205 fCurHzCompat);
206 }
207
208 if (!fCurHzCompat)
209 ++cCpuHzNotCompat;
210 fCompat &= fCurHzCompat;
211 ++cCpuHzChecked;
212 }
213 else
214 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "priming");
215 }
216 else
217 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "");
218 }
219 else
220 szCpuHzDeviation[0] = '\0';
221 RTPrintf(fHex
222 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
223 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
224 i, iCpu,
225 pCpu->u64NanoTS,
226 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
227 pCpu->u64TSC,
228 pCpu->u32UpdateIntervalTSC,
229 pCpu->iTSCHistoryHead,
230 pCpu->u32TransactionId,
231 pCpu->u64CpuHz,
232 szCpuHzDeviation,
233 pCpu->au32TSCHistory[0],
234 pCpu->au32TSCHistory[1],
235 pCpu->au32TSCHistory[2],
236 pCpu->au32TSCHistory[3],
237 pCpu->au32TSCHistory[4],
238 pCpu->au32TSCHistory[5],
239 pCpu->au32TSCHistory[6],
240 pCpu->au32TSCHistory[7],
241 pCpu->cErrors);
242 if (!pu32TransactionId)
243 {
244 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
245 u32TransactionId = pCpu->u32TransactionId;
246 }
247 }
248
249 /* Wait a bit / spin. */
250 if (!fSpin)
251 RTThreadSleep(9);
252 else
253 {
254 if (pu32TransactionId)
255 {
256 uint32_t uTmp;
257 while ( u32TransactionId == (uTmp = *pu32TransactionId)
258 || (uTmp & 1))
259 ASMNopPause();
260 }
261 else
262 RTThreadSleep(1);
263 }
264 }
265
266 /*
267 * Display TSC deltas.
268 *
269 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
270 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
271 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
272 */
273 RTPrintf("tstGIP-2: TSC deltas:\n");
274 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
275 for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
276 {
277 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
278 if (iCpu != UINT16_MAX)
279 {
280 RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
281 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
282 }
283 }
284
285 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
286 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
287 RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
288
289 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
290 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
291 if (uCpuHzRef)
292 {
293 if (cCpuHzOverallDevCnt)
294 {
295 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
296 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
297 uPct / 1000, (uPct % 1000) / 10);
298
299 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
300 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
301 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
302 }
303 else
304 {
305 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
306 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
307 }
308
309 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz - %s GIP)\n", fCompat,
310 cCpuHzNotCompat, cCpuHzChecked, uCpuHzRef, SUPGetGIPModeName(g_pSUPGlobalInfoPage));
311
312 if ( !fCompat
313 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
314 rc = -1;
315 }
316
317 /* Disable GIP test mode. */
318 if (fTestMode)
319 SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
320 }
321 else
322 {
323 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
324 rc = -1;
325 }
326
327 SUPR3Term(false /*fForced*/);
328 }
329 else
330 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
331 return !!rc;
332}
333
334#if !defined(VBOX_WITH_HARDENING) || !defined(RT_OS_WINDOWS)
335/**
336 * Main entry point.
337 */
338int main(int argc, char **argv)
339{
340 return TrustedMain(argc, argv);
341}
342#endif
343
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