VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 53351

Last change on this file since 53351 was 53351, checked in by vboxsync, 11 years ago

tstGIP-2: print the deviation of CpuHz to a reference value in a separate column
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File size: 9.1 KB
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1/* $Id: tstGIP-2.cpp 53351 2014-11-19 14:05:55Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2014 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27/*******************************************************************************
28* Header Files *
29*******************************************************************************/
30#include <VBox/sup.h>
31#include <VBox/err.h>
32#include <VBox/param.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/alloc.h>
36#include <iprt/thread.h>
37#include <iprt/stream.h>
38#include <iprt/string.h>
39#include <iprt/initterm.h>
40#include <iprt/getopt.h>
41
42
43int main(int argc, char **argv)
44{
45 RTR3InitExe(argc, &argv, 0);
46
47 /*
48 * Parse args
49 */
50 static const RTGETOPTDEF g_aOptions[] =
51 {
52 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
53 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
54 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
55 { "--spin", 's', RTGETOPT_REQ_NOTHING },
56 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
57 * CpuHz deviation in a separate column. */
58 };
59
60 uint32_t cIterations = 40;
61 bool fHex = true;
62 bool fSpin = false;
63 int ch;
64 uint64_t uCpuHzRef = 0;
65 RTGETOPTUNION ValueUnion;
66 RTGETOPTSTATE GetState;
67 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
68 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
69 {
70 switch (ch)
71 {
72 case 'i':
73 cIterations = ValueUnion.u32;
74 break;
75
76 case 'd':
77 fHex = false;
78 break;
79
80 case 'h':
81 fHex = true;
82 break;
83
84 case 's':
85 fSpin = true;
86 break;
87
88 case 'r':
89 uCpuHzRef = ValueUnion.u64;
90 break;
91
92 default:
93 return RTGetOptPrintError(ch, &ValueUnion);
94 }
95 }
96
97 /*
98 * Init
99 */
100 PSUPDRVSESSION pSession = NIL_RTR0PTR;
101 int rc = SUPR3Init(&pSession);
102 if (RT_SUCCESS(rc))
103 {
104 if (g_pSUPGlobalInfoPage)
105 {
106 RTPrintf("tstGIP-2: cCpus=%d u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 u32Mode=%d (%s) u32Version=%#x\n",
107 g_pSUPGlobalInfoPage->cCpus,
108 g_pSUPGlobalInfoPage->u32UpdateHz,
109 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
110 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
111 g_pSUPGlobalInfoPage->u64CpuHz,
112 g_pSUPGlobalInfoPage->u32Mode,
113 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
114 g_pSUPGlobalInfoPage->u32Version);
115 RTPrintf(fHex
116 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
117 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
118 uCpuHzRef ? " CpuHzDev " : "");
119 static SUPGIPCPU s_aaCPUs[2][256];
120 for (uint32_t i = 0; i < cIterations; i++)
121 {
122 /* copy the data */
123 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
124
125 /* display it & find something to spin on. */
126 uint32_t u32TransactionId = 0;
127 uint32_t volatile *pu32TransactionId = NULL;
128 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
129 if ( g_pSUPGlobalInfoPage->aCPUs[iCpu].u64CpuHz > 0
130 && g_pSUPGlobalInfoPage->aCPUs[iCpu].u64CpuHz != _4G + 1)
131 {
132 char szCpuHzDeviation[32];
133 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
134 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
135 if (uCpuHzRef)
136 {
137 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
138 if (RT_ABS(iCpuHzDeviation) > 999999999)
139 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10s ", "?");
140 else
141 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64 ", iCpuHzDeviation);
142 }
143 else
144 szCpuHzDeviation[0] = '\0';
145 RTPrintf(fHex
146 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
147 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
148 i, iCpu,
149 pCpu->u64NanoTS,
150 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
151 pCpu->u64TSC,
152 pCpu->u32UpdateIntervalTSC,
153 pCpu->iTSCHistoryHead,
154 pCpu->u32TransactionId,
155 pCpu->u64CpuHz,
156 szCpuHzDeviation,
157 pCpu->au32TSCHistory[0],
158 pCpu->au32TSCHistory[1],
159 pCpu->au32TSCHistory[2],
160 pCpu->au32TSCHistory[3],
161 pCpu->au32TSCHistory[4],
162 pCpu->au32TSCHistory[5],
163 pCpu->au32TSCHistory[6],
164 pCpu->au32TSCHistory[7],
165 pCpu->cErrors);
166 if (!pu32TransactionId)
167 {
168 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
169 u32TransactionId = pCpu->u32TransactionId;
170 }
171 }
172
173 /* wait a bit / spin */
174 if (!fSpin)
175 RTThreadSleep(9);
176 else
177 {
178 if (pu32TransactionId)
179 {
180 while (u32TransactionId == *pu32TransactionId)
181 ASMNopPause();
182 }
183 else
184 RTThreadSleep(1);
185 }
186 }
187
188 /*
189 * Display TSC deltas.
190 *
191 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
192 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
193 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
194 */
195 RTPrintf("tstGIP-2: TSC deltas:\n");
196 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
197 for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
198 {
199 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
200 if (iCpu != UINT16_MAX)
201 {
202 RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
203 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
204 }
205 }
206
207 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
208 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
209 RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
210 }
211 else
212 {
213 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
214 rc = -1;
215 }
216
217 SUPR3Term(false /*fForced*/);
218 }
219 else
220 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
221 return !!rc;
222}
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