1 | /* $Id: tstGIP-2.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
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2 | /** @file
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3 | * SUP Testcase - Global Info Page interface (ring 3).
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * The contents of this file may alternatively be used under the terms
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26 | * of the Common Development and Distribution License Version 1.0
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27 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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28 | * in the VirtualBox distribution, in which case the provisions of the
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29 | * CDDL are applicable instead of those of the GPL.
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30 | *
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31 | * You may elect to license modified versions of this file under the
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32 | * terms and conditions of either the GPL or the CDDL or both.
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33 | *
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34 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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35 | */
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36 |
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37 |
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38 | /*********************************************************************************************************************************
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39 | * Header Files *
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40 | *********************************************************************************************************************************/
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41 | #include <VBox/sup.h>
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42 | #include <iprt/errcore.h>
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43 | #include <VBox/param.h>
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44 | #include <iprt/asm.h>
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45 | #include <iprt/assert.h>
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46 | #include <iprt/alloc.h>
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47 | #include <iprt/thread.h>
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48 | #include <iprt/stream.h>
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49 | #include <iprt/string.h>
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50 | #include <iprt/initterm.h>
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51 | #include <iprt/getopt.h>
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52 | #include <iprt/x86.h>
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53 |
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54 |
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55 | /**
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56 | * Entry point.
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57 | */
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58 | extern "C" DECLEXPORT(int) TrustedMain(int argc, char **argv)
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59 | {
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60 | RTR3InitExe(argc, &argv, 0);
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61 |
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62 | /*
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63 | * Parse args
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64 | */
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65 | static const RTGETOPTDEF g_aOptions[] =
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66 | {
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67 | { "--iterations", 'i', RTGETOPT_REQ_INT32 },
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68 | { "--hex", 'h', RTGETOPT_REQ_NOTHING },
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69 | { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
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70 | { "--spin", 's', RTGETOPT_REQ_NOTHING },
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71 | { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
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72 | * CpuHz deviation in a separate column. */
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73 | { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
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74 | * implies updating GIP CpuHz even when invariant) */
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75 | };
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76 |
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77 | bool fHex = true;
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78 | bool fSpin = false;
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79 | bool fCompat = true;
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80 | bool fTestMode = true;
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81 | int ch;
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82 | uint32_t cIterations = 40;
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83 | uint64_t uCpuHzRef = UINT64_MAX;
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84 | RTGETOPTUNION ValueUnion;
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85 | RTGETOPTSTATE GetState;
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86 | RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
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87 | while ((ch = RTGetOpt(&GetState, &ValueUnion)))
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88 | {
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89 | switch (ch)
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90 | {
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91 | case 'i':
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92 | cIterations = ValueUnion.u32;
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93 | break;
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94 |
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95 | case 'd':
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96 | fHex = false;
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97 | break;
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98 |
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99 | case 'h':
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100 | fHex = true;
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101 | break;
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102 |
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103 | case 's':
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104 | fSpin = true;
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105 | break;
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106 |
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107 | case 'r':
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108 | uCpuHzRef = ValueUnion.u64;
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109 | break;
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110 |
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111 | case 't':
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112 | fTestMode = false;
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113 | break;
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114 |
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115 | default:
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116 | return RTGetOptPrintError(ch, &ValueUnion);
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117 | }
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118 | }
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119 |
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120 | /*
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121 | * Init
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122 | */
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123 | PSUPDRVSESSION pSession = NIL_RTR0PTR;
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124 | int rc = SUPR3Init(&pSession);
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125 | if (RT_SUCCESS(rc))
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126 | {
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127 | if (g_pSUPGlobalInfoPage)
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128 | {
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129 | uint64_t uCpuHzOverallDeviation = 0;
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130 | uint32_t cCpuHzNotCompat = 0;
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131 | int64_t iCpuHzMaxDeviation = 0;
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132 | int32_t cCpuHzOverallDevCnt = 0;
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133 | uint32_t cCpuHzChecked = 0;
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134 |
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135 | /* Pick current CpuHz as the reference if none was specified. */
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136 | if (uCpuHzRef == UINT64_MAX)
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137 | uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
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138 |
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139 | if ( fTestMode
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140 | && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
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141 | SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
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142 |
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143 | RTPrintf("tstGIP-2: u32Mode=%d (%s) fTestMode=%RTbool u32Version=%#x fGetGipCpu=%#RX32 cPages=%#RX32\n",
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144 | g_pSUPGlobalInfoPage->u32Mode,
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145 | SUPGetGIPModeName(g_pSUPGlobalInfoPage),
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146 | fTestMode,
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147 | g_pSUPGlobalInfoPage->u32Version,
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148 | g_pSUPGlobalInfoPage->fGetGipCpu,
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149 | g_pSUPGlobalInfoPage->cPages);
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150 | RTPrintf("tstGIP-2: cCpus=%d cPossibleCpus=%d cPossibleCpuGroups=%d cPresentCpus=%d cOnlineCpus=%d idCpuMax=%#x\n",
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151 | g_pSUPGlobalInfoPage->cCpus,
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152 | g_pSUPGlobalInfoPage->cPossibleCpus,
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153 | g_pSUPGlobalInfoPage->cPossibleCpuGroups,
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154 | g_pSUPGlobalInfoPage->cPresentCpus,
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155 | g_pSUPGlobalInfoPage->cOnlineCpus,
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156 | g_pSUPGlobalInfoPage->idCpuMax);
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157 | RTPrintf("tstGIP-2: u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64\n",
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158 | g_pSUPGlobalInfoPage->u32UpdateHz,
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159 | g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
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160 | g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
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161 | g_pSUPGlobalInfoPage->u64CpuHz,
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162 | uCpuHzRef);
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163 | for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
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164 | if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState != SUPGIPCPUSTATE_INVALID)
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165 | {
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166 | SUPGIPCPU const *pGipCpu = &g_pSUPGlobalInfoPage->aCPUs[iCpu];
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167 | RTPrintf("tstGIP-2: aCPU[%3u]: enmState=%d iCpuSet=%-3u idCpu=%#010x iCpuGroup=%-2u iCpuGroupMember=%-3u idApic=%#06x\n",
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168 | iCpu, pGipCpu->enmState, pGipCpu->iCpuSet, pGipCpu->idCpu, pGipCpu->iCpuGroup,
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169 | pGipCpu->iCpuGroupMember, pGipCpu->idApic);
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170 | }
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171 |
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172 | RTPrintf(fHex
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173 | ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
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174 | : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
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175 | uCpuHzRef ? " CpuHz deviation Compat " : "");
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176 | static SUPGIPCPU s_aaCPUs[2][RTCPUSET_MAX_CPUS];
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177 | for (uint32_t i = 0; i < cIterations; i++)
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178 | {
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179 | /* Copy the data. */
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180 | memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
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181 |
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182 | /* Display it & find something to spin on. */
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183 | uint32_t u32TransactionId = 0;
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184 | uint32_t volatile *pu32TransactionId = NULL;
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185 | for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
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186 | if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
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187 | {
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188 | char szCpuHzDeviation[32];
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189 | PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
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190 | PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
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191 | if (uCpuHzRef)
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192 | {
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193 | /* Only CPU 0 is updated for invariant & sync modes, see supdrvGipUpdate(). */
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194 | if ( iCpu == 0
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195 | || g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_ASYNC_TSC)
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196 | {
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197 | /* Wait until the history validation code takes effect. */
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198 | if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
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199 | {
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200 | int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
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201 | uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
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202 | bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /*fRelax*/);
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203 | if (uCpuHzDeviation <= 999999999)
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204 | {
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205 | if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
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206 | iCpuHzMaxDeviation = iCpuHzDeviation;
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207 | uCpuHzOverallDeviation += uCpuHzDeviation;
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208 | cCpuHzOverallDevCnt++;
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209 | uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
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210 | RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
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211 | iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
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212 | }
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213 | else
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214 | {
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215 | RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s %RTbool ", "?",
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216 | fCurHzCompat);
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217 | }
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218 |
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219 | if (!fCurHzCompat)
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220 | ++cCpuHzNotCompat;
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221 | fCompat &= fCurHzCompat;
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222 | ++cCpuHzChecked;
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223 | }
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224 | else
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225 | RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "priming");
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226 | }
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227 | else
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228 | RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "");
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229 | }
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230 | else
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231 | szCpuHzDeviation[0] = '\0';
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232 | RTPrintf(fHex
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233 | ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
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234 | : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
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235 | i, iCpu,
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236 | pCpu->u64NanoTS,
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237 | i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
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238 | pCpu->u64TSC,
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239 | pCpu->u32UpdateIntervalTSC,
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240 | pCpu->iTSCHistoryHead,
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241 | pCpu->u32TransactionId,
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242 | pCpu->u64CpuHz,
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243 | szCpuHzDeviation,
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244 | pCpu->au32TSCHistory[0],
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245 | pCpu->au32TSCHistory[1],
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246 | pCpu->au32TSCHistory[2],
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247 | pCpu->au32TSCHistory[3],
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248 | pCpu->au32TSCHistory[4],
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249 | pCpu->au32TSCHistory[5],
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250 | pCpu->au32TSCHistory[6],
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251 | pCpu->au32TSCHistory[7],
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252 | pCpu->cErrors);
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253 | if (!pu32TransactionId)
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254 | {
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255 | pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
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256 | u32TransactionId = pCpu->u32TransactionId;
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257 | }
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258 | }
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259 |
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260 | /* Wait a bit / spin. */
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261 | if (!fSpin)
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262 | RTThreadSleep(9);
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263 | else
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264 | {
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265 | if (pu32TransactionId)
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266 | {
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267 | uint32_t uTmp;
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268 | while ( u32TransactionId == (uTmp = *pu32TransactionId)
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269 | || (uTmp & 1))
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270 | ASMNopPause();
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271 | }
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272 | else
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273 | RTThreadSleep(1);
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274 | }
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275 | }
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276 |
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277 | /*
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278 | * Display TSC deltas.
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279 | *
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280 | * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
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281 | * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
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282 | * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
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283 | */
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284 | RTPrintf("tstGIP-2: TSC deltas:\n");
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285 | RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
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286 | for (uint32_t i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
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287 | {
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288 | uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
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289 | if (iCpu != UINT16_MAX)
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290 | RTPrintf("tstGIP-2: %#7x: %6lld (grp=%#04x mbr=%#05x set=%d cpu=%#05x)\n",
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291 | g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic, g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta,
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292 | g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroup, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroupMember,
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293 | g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuSet, iCpu);
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294 | }
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295 |
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296 | for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
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297 | if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
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298 | RTPrintf("tstGIP-2: offline: %6lld (grp=%#04x mbr=%#05x set=%d cpu=%#05x)\n",
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299 | g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroup,
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300 | g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroupMember, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuSet, iCpu);
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301 |
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302 | RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
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303 | g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
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304 | if (uCpuHzRef)
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305 | {
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306 | if (cCpuHzOverallDevCnt)
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307 | {
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308 | uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
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309 | RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
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310 | uPct / 1000, (uPct % 1000) / 10);
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311 |
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312 | uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
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313 | RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
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314 | uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
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315 | }
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316 | else
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317 | {
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318 | RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
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319 | RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
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320 | }
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321 |
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322 | RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz - %s GIP)\n", fCompat,
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323 | cCpuHzNotCompat, cCpuHzChecked, uCpuHzRef, SUPGetGIPModeName(g_pSUPGlobalInfoPage));
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324 |
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325 | if ( !fCompat
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326 | && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
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327 | rc = -1;
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328 | }
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329 |
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330 | /* Disable GIP test mode. */
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331 | if (fTestMode)
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332 | SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
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333 | }
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334 | else
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335 | {
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336 | RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
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337 | rc = -1;
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338 | }
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339 |
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340 | SUPR3Term(false /*fForced*/);
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341 | }
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342 | else
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343 | RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
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344 | return !!rc;
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345 | }
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346 |
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347 | #if !defined(VBOX_WITH_HARDENING) || !defined(RT_OS_WINDOWS)
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348 | /**
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349 | * Main entry point.
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350 | */
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351 | int main(int argc, char **argv)
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352 | {
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353 | return TrustedMain(argc, argv);
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354 | }
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355 | #endif
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356 |
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