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source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp

Last change on this file was 98103, checked in by vboxsync, 17 months ago

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[22077]1/* $Id: tstGIP-2.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
[1]2/** @file
[22077]3 * SUP Testcase - Global Info Page interface (ring 3).
[1]4 */
5
6/*
[98103]7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
[1]8 *
[96407]9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
[5999]11 *
[96407]12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
[5999]25 * The contents of this file may alternatively be used under the terms
26 * of the Common Development and Distribution License Version 1.0
[96407]27 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28 * in the VirtualBox distribution, in which case the provisions of the
[5999]29 * CDDL are applicable instead of those of the GPL.
30 *
31 * You may elect to license modified versions of this file under the
32 * terms and conditions of either the GPL or the CDDL or both.
[96407]33 *
34 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
[1]35 */
36
[57358]37
38/*********************************************************************************************************************************
39* Header Files *
40*********************************************************************************************************************************/
[1]41#include <VBox/sup.h>
[76474]42#include <iprt/errcore.h>
[1]43#include <VBox/param.h>
44#include <iprt/asm.h>
45#include <iprt/assert.h>
46#include <iprt/alloc.h>
47#include <iprt/thread.h>
48#include <iprt/stream.h>
[9961]49#include <iprt/string.h>
[9469]50#include <iprt/initterm.h>
51#include <iprt/getopt.h>
[53430]52#include <iprt/x86.h>
[1]53
[57351]54
55/**
56 * Entry point.
57 */
58extern "C" DECLEXPORT(int) TrustedMain(int argc, char **argv)
[1]59{
[38636]60 RTR3InitExe(argc, &argv, 0);
[1]61
62 /*
[9469]63 * Parse args
64 */
[17091]65 static const RTGETOPTDEF g_aOptions[] =
[9469]66 {
[33595]67 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
[9961]68 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
69 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
[53351]70 { "--spin", 's', RTGETOPT_REQ_NOTHING },
71 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
72 * CpuHz deviation in a separate column. */
[57218]73 { "--notestmode", 't', RTGETOPT_REQ_NOTHING } /* don't run GIP in test-mode (atm, test-mode
74 * implies updating GIP CpuHz even when invariant) */
[9469]75 };
76
[57349]77 bool fHex = true;
78 bool fSpin = false;
79 bool fCompat = true;
80 bool fTestMode = true;
81 int ch;
82 uint32_t cIterations = 40;
83 uint64_t uCpuHzRef = UINT64_MAX;
[17091]84 RTGETOPTUNION ValueUnion;
85 RTGETOPTSTATE GetState;
[26517]86 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
[17091]87 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
[9469]88 {
89 switch (ch)
90 {
91 case 'i':
92 cIterations = ValueUnion.u32;
93 break;
94
[9961]95 case 'd':
96 fHex = false;
97 break;
98
99 case 'h':
100 fHex = true;
101 break;
102
103 case 's':
104 fSpin = true;
105 break;
106
[53351]107 case 'r':
108 uCpuHzRef = ValueUnion.u64;
109 break;
110
[57218]111 case 't':
112 fTestMode = false;
113 break;
114
[9469]115 default:
[26517]116 return RTGetOptPrintError(ch, &ValueUnion);
[9469]117 }
118 }
119
120 /*
[1]121 * Init
122 */
[1841]123 PSUPDRVSESSION pSession = NIL_RTR0PTR;
[11794]124 int rc = SUPR3Init(&pSession);
[13835]125 if (RT_SUCCESS(rc))
[1]126 {
127 if (g_pSUPGlobalInfoPage)
128 {
[57349]129 uint64_t uCpuHzOverallDeviation = 0;
130 uint32_t cCpuHzNotCompat = 0;
131 int64_t iCpuHzMaxDeviation = 0;
132 int32_t cCpuHzOverallDevCnt = 0;
133 uint32_t cCpuHzChecked = 0;
134
[57218]135 /* Pick current CpuHz as the reference if none was specified. */
136 if (uCpuHzRef == UINT64_MAX)
137 uCpuHzRef = SUPGetCpuHzFromGip(g_pSUPGlobalInfoPage);
138
139 if ( fTestMode
140 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
141 SUPR3GipSetFlags(SUPGIP_FLAGS_TESTING_ENABLE, UINT32_MAX);
142
[81096]143 RTPrintf("tstGIP-2: u32Mode=%d (%s) fTestMode=%RTbool u32Version=%#x fGetGipCpu=%#RX32 cPages=%#RX32\n",
[64255]144 g_pSUPGlobalInfoPage->u32Mode,
145 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
146 fTestMode,
147 g_pSUPGlobalInfoPage->u32Version,
[81096]148 g_pSUPGlobalInfoPage->fGetGipCpu,
149 g_pSUPGlobalInfoPage->cPages);
[64281]150 RTPrintf("tstGIP-2: cCpus=%d cPossibleCpus=%d cPossibleCpuGroups=%d cPresentCpus=%d cOnlineCpus=%d idCpuMax=%#x\n",
[45399]151 g_pSUPGlobalInfoPage->cCpus,
[64255]152 g_pSUPGlobalInfoPage->cPossibleCpus,
153 g_pSUPGlobalInfoPage->cPossibleCpuGroups,
154 g_pSUPGlobalInfoPage->cPresentCpus,
[64281]155 g_pSUPGlobalInfoPage->cOnlineCpus,
156 g_pSUPGlobalInfoPage->idCpuMax);
[64255]157 RTPrintf("tstGIP-2: u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64\n",
[1]158 g_pSUPGlobalInfoPage->u32UpdateHz,
159 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
[9469]160 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
[53269]161 g_pSUPGlobalInfoPage->u64CpuHz,
[64255]162 uCpuHzRef);
[64281]163 for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
164 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState != SUPGIPCPUSTATE_INVALID)
165 {
166 SUPGIPCPU const *pGipCpu = &g_pSUPGlobalInfoPage->aCPUs[iCpu];
[81106]167 RTPrintf("tstGIP-2: aCPU[%3u]: enmState=%d iCpuSet=%-3u idCpu=%#010x iCpuGroup=%-2u iCpuGroupMember=%-3u idApic=%#06x\n",
[64281]168 iCpu, pGipCpu->enmState, pGipCpu->iCpuSet, pGipCpu->idCpu, pGipCpu->iCpuGroup,
169 pGipCpu->iCpuGroupMember, pGipCpu->idApic);
170 }
[64255]171
[9961]172 RTPrintf(fHex
[53351]173 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
174 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
[57060]175 uCpuHzRef ? " CpuHz deviation Compat " : "");
[81106]176 static SUPGIPCPU s_aaCPUs[2][RTCPUSET_MAX_CPUS];
[9478]177 for (uint32_t i = 0; i < cIterations; i++)
[1]178 {
[57349]179 /* Copy the data. */
[45399]180 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
[9961]181
[57349]182 /* Display it & find something to spin on. */
[9961]183 uint32_t u32TransactionId = 0;
184 uint32_t volatile *pu32TransactionId = NULL;
[45399]185 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
[54352]186 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
[11794]187 {
[53351]188 char szCpuHzDeviation[32];
[9961]189 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
190 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
[53351]191 if (uCpuHzRef)
192 {
[57349]193 /* Only CPU 0 is updated for invariant & sync modes, see supdrvGipUpdate(). */
194 if ( iCpu == 0
195 || g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_ASYNC_TSC)
[53352]196 {
[53430]197 /* Wait until the history validation code takes effect. */
198 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
[53358]199 {
[57349]200 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
201 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
202 bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /*fRelax*/);
203 if (uCpuHzDeviation <= 999999999)
204 {
205 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
206 iCpuHzMaxDeviation = iCpuHzDeviation;
207 uCpuHzOverallDeviation += uCpuHzDeviation;
208 cCpuHzOverallDevCnt++;
209 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
210 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
211 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
212 }
213 else
214 {
215 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s %RTbool ", "?",
216 fCurHzCompat);
217 }
218
219 if (!fCurHzCompat)
220 ++cCpuHzNotCompat;
221 fCompat &= fCurHzCompat;
222 ++cCpuHzChecked;
[53358]223 }
[57349]224 else
225 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "priming");
[53352]226 }
[57349]227 else
228 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%25s ", "");
[53351]229 }
230 else
231 szCpuHzDeviation[0] = '\0';
[9961]232 RTPrintf(fHex
[53351]233 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
234 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
[2369]235 i, iCpu,
[9961]236 pCpu->u64NanoTS,
237 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
238 pCpu->u64TSC,
239 pCpu->u32UpdateIntervalTSC,
240 pCpu->iTSCHistoryHead,
241 pCpu->u32TransactionId,
242 pCpu->u64CpuHz,
[53351]243 szCpuHzDeviation,
[9961]244 pCpu->au32TSCHistory[0],
245 pCpu->au32TSCHistory[1],
246 pCpu->au32TSCHistory[2],
247 pCpu->au32TSCHistory[3],
248 pCpu->au32TSCHistory[4],
249 pCpu->au32TSCHistory[5],
250 pCpu->au32TSCHistory[6],
251 pCpu->au32TSCHistory[7],
252 pCpu->cErrors);
253 if (!pu32TransactionId)
254 {
255 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
256 u32TransactionId = pCpu->u32TransactionId;
257 }
258 }
259
[57349]260 /* Wait a bit / spin. */
[9961]261 if (!fSpin)
262 RTThreadSleep(9);
263 else
[53069]264 {
265 if (pu32TransactionId)
266 {
[53455]267 uint32_t uTmp;
268 while ( u32TransactionId == (uTmp = *pu32TransactionId)
269 || (uTmp & 1))
[53069]270 ASMNopPause();
271 }
272 else
273 RTThreadSleep(1);
274 }
[1]275 }
[52618]276
[53026]277 /*
278 * Display TSC deltas.
279 *
280 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
281 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
282 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
283 */
[52618]284 RTPrintf("tstGIP-2: TSC deltas:\n");
[53026]285 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
[81106]286 for (uint32_t i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
[52871]287 {
288 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
289 if (iCpu != UINT16_MAX)
[81106]290 RTPrintf("tstGIP-2: %#7x: %6lld (grp=%#04x mbr=%#05x set=%d cpu=%#05x)\n",
291 g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic, g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta,
292 g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroup, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroupMember,
293 g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuSet, iCpu);
[52871]294 }
[53026]295
[81106]296 for (uint32_t iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
[53026]297 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
[81106]298 RTPrintf("tstGIP-2: offline: %6lld (grp=%#04x mbr=%#05x set=%d cpu=%#05x)\n",
299 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroup,
300 g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuGroupMember, g_pSUPGlobalInfoPage->aCPUs[iCpu].iCpuSet, iCpu);
[53358]301
[54252]302 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
303 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
[57349]304 if (uCpuHzRef)
[53356]305 {
[57349]306 if (cCpuHzOverallDevCnt)
307 {
308 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
309 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
310 uPct / 1000, (uPct % 1000) / 10);
[54252]311
[57349]312 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
313 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
314 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
315 }
316 else
317 {
318 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
319 RTPrintf("tstGIP-2: Average CpuHz deviation: ??.??\n");
320 }
[57060]321
[57349]322 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz - %s GIP)\n", fCompat,
323 cCpuHzNotCompat, cCpuHzChecked, uCpuHzRef, SUPGetGIPModeName(g_pSUPGlobalInfoPage));
[57218]324
325 if ( !fCompat
326 && g_pSUPGlobalInfoPage->u32Mode == SUPGIPMODE_INVARIANT_TSC)
327 rc = -1;
[53356]328 }
[57218]329
330 /* Disable GIP test mode. */
331 if (fTestMode)
332 SUPR3GipSetFlags(0, ~SUPGIP_FLAGS_TESTING_ENABLE);
[1]333 }
334 else
335 {
336 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
337 rc = -1;
338 }
339
[20864]340 SUPR3Term(false /*fForced*/);
[1]341 }
342 else
[13837]343 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
[1]344 return !!rc;
345}
[53430]346
[57354]347#if !defined(VBOX_WITH_HARDENING) || !defined(RT_OS_WINDOWS)
[57351]348/**
349 * Main entry point.
350 */
351int main(int argc, char **argv)
352{
353 return TrustedMain(argc, argv);
354}
[57354]355#endif
[57351]356
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