VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/SUPLibAll.cpp@ 87235

Last change on this file since 87235 was 87235, checked in by vboxsync, 4 years ago

SUP,IPRT: Adjustments for bugref:9898.

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1/* $Id: SUPLibAll.cpp 87235 2021-01-13 12:41:05Z vboxsync $ */
2/** @file
3 * VirtualBox Support Library - All Contexts Code.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27
28/*********************************************************************************************************************************
29* Header Files *
30*********************************************************************************************************************************/
31#include <VBox/sup.h>
32#ifdef IN_RC
33# include <VBox/vmm/vm.h>
34# include <VBox/vmm/vmm.h>
35#endif
36#ifdef IN_RING0
37# include <iprt/mp.h>
38#endif
39#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
40# include <iprt/asm-amd64-x86.h>
41#endif
42#include <iprt/errcore.h>
43
44
45#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
46/**
47 * The slow case for SUPReadTsc where we need to apply deltas.
48 *
49 * Must only be called when deltas are applicable, so please do not call it
50 * directly.
51 *
52 * @returns TSC with delta applied.
53 * @param pGip Pointer to the GIP.
54 *
55 * @remarks May be called with interrupts disabled in ring-0! This is why the
56 * ring-0 code doesn't attempt to figure the delta.
57 *
58 * @internal
59 */
60SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
61{
62 uint64_t uTsc;
63 uint16_t iGipCpu;
64 AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
65 AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
66 Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
67
68 /*
69 * Read the TSC and get the corresponding aCPUs index.
70 */
71#ifdef IN_RING3
72 if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
73 {
74 /* RDTSCP gives us all we need, no loops/cli. */
75 uint32_t iCpuSet;
76 uTsc = ASMReadTscWithAux(&iCpuSet);
77 iCpuSet &= RTCPUSET_MAX_CPUS - 1;
78 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
79 }
80 else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
81 {
82 /* Storing the IDTR is normally very quick, but we need to loop. */
83 uint32_t cTries = 0;
84 for (;;)
85 {
86 uint16_t cbLim = ASMGetIdtrLimit();
87 uTsc = ASMReadTSC();
88 if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
89 {
90 uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
91 iCpuSet &= RTCPUSET_MAX_CPUS - 1;
92 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
93 break;
94 }
95 if (cTries >= 16)
96 {
97 iGipCpu = UINT16_MAX;
98 break;
99 }
100 cTries++;
101 }
102 }
103 else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
104 {
105 /* Get APIC ID / 0x1b via the slow CPUID instruction, requires looping. */
106 uint32_t cTries = 0;
107 for (;;)
108 {
109 uint32_t idApic = ASMGetApicIdExt0B();
110 uTsc = ASMReadTSC();
111 if (RT_LIKELY(ASMGetApicIdExt0B() == idApic))
112 {
113 iGipCpu = pGip->aiCpuFromApicId[idApic];
114 break;
115 }
116 if (cTries >= 16)
117 {
118 iGipCpu = UINT16_MAX;
119 break;
120 }
121 cTries++;
122 }
123 }
124 else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
125 {
126 /* Get APIC ID / 0x8000001e via the slow CPUID instruction, requires looping. */
127 uint32_t cTries = 0;
128 for (;;)
129 {
130 uint32_t idApic = ASMGetApicIdExt8000001E();
131 uTsc = ASMReadTSC();
132 if (RT_LIKELY(ASMGetApicIdExt8000001E() == idApic))
133 {
134 iGipCpu = pGip->aiCpuFromApicId[idApic];
135 break;
136 }
137 if (cTries >= 16)
138 {
139 iGipCpu = UINT16_MAX;
140 break;
141 }
142 cTries++;
143 }
144 }
145 else
146 {
147 /* Get APIC ID via the slow CPUID instruction, requires looping. */
148 uint32_t cTries = 0;
149 for (;;)
150 {
151 uint8_t idApic = ASMGetApicId();
152 uTsc = ASMReadTSC();
153 if (RT_LIKELY(ASMGetApicId() == idApic))
154 {
155 iGipCpu = pGip->aiCpuFromApicId[idApic];
156 break;
157 }
158 if (cTries >= 16)
159 {
160 iGipCpu = UINT16_MAX;
161 break;
162 }
163 cTries++;
164 }
165 }
166#elif defined(IN_RING0)
167 /* Ring-0: Use use RTMpCpuId(), no loops. */
168 RTCCUINTREG uFlags = ASMIntDisableFlags();
169 int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
170 if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
171 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
172 else
173 iGipCpu = UINT16_MAX;
174 uTsc = ASMReadTSC();
175 ASMSetFlags(uFlags);
176
177# elif defined(IN_RC)
178 /* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
179 RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
180 uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
181 if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
182 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
183 else
184 iGipCpu = UINT16_MAX;
185 uTsc = ASMReadTSC();
186 ASMSetFlags(uFlags);
187#else
188# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
189#endif
190
191 /*
192 * If the delta is valid, apply it.
193 */
194 if (RT_LIKELY(iGipCpu < pGip->cCpus))
195 {
196 int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
197 if (RT_LIKELY(iTscDelta != INT64_MAX))
198 return uTsc - iTscDelta;
199
200# ifdef IN_RING3
201 /*
202 * The delta needs calculating, call supdrv to get the TSC.
203 */
204 int rc = SUPR3ReadTsc(&uTsc, NULL);
205 if (RT_SUCCESS(rc))
206 return uTsc;
207 AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
208 uTsc = ASMReadTSC();
209# endif /* IN_RING3 */
210 }
211
212 /*
213 * This shouldn't happen, especially not in ring-3 and raw-mode context.
214 * But if it does, return something that's half useful.
215 */
216 AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
217 return uTsc;
218}
219#endif /* RT_ARCH_AMD64 || RT_ARCH_X86 */
220
221
222/**
223 * Internal worker for getting the GIP CPU array index for the calling CPU.
224 *
225 * @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
226 * @param pGip The GIP.
227 */
228DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
229{
230 uint16_t iGipCpu;
231#ifdef IN_RING3
232# if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
233 if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
234 {
235 /* Storing the IDTR is normally very fast. */
236 uint16_t cbLim = ASMGetIdtrLimit();
237 uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
238 iCpuSet &= RTCPUSET_MAX_CPUS - 1;
239 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
240 }
241 else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
242 {
243 /* RDTSCP gives us what need need and more. */
244 uint32_t iCpuSet;
245 ASMReadTscWithAux(&iCpuSet);
246 iCpuSet &= RTCPUSET_MAX_CPUS - 1;
247 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
248 }
249 else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
250 {
251 /* Get APIC ID via the slow CPUID/0000000B instruction. */
252 uint32_t idApic = ASMGetApicIdExt0B();
253 iGipCpu = pGip->aiCpuFromApicId[idApic];
254 }
255 else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
256 {
257 /* Get APIC ID via the slow CPUID/8000001E instruction. */
258 uint32_t idApic = ASMGetApicIdExt8000001E();
259 iGipCpu = pGip->aiCpuFromApicId[idApic];
260 }
261 else
262 {
263 /* Get APIC ID via the slow CPUID instruction. */
264 uint8_t idApic = ASMGetApicId();
265 iGipCpu = pGip->aiCpuFromApicId[idApic];
266 }
267
268# else
269 int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
270 if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
271 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
272 else
273 iGipCpu = UINT16_MAX;
274# endif
275
276#elif defined(IN_RING0)
277 /* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
278 RTCCUINTREG uFlags = ASMIntDisableFlags();
279 int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
280 if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
281 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
282 else
283 iGipCpu = UINT16_MAX;
284 ASMSetFlags(uFlags);
285
286# elif defined(IN_RC)
287 /* Raw-mode context: We can get the host CPU set index via VMCPU. */
288 uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
289 if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
290 iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
291 else
292 iGipCpu = UINT16_MAX;
293
294#else
295# error "IN_RING3, IN_RC or IN_RING0 must be defined!"
296#endif
297 return iGipCpu;
298}
299
300
301/**
302 * Slow path in SUPGetTscDelta, don't call directly.
303 *
304 * @returns See SUPGetTscDelta.
305 * @param pGip The GIP.
306 * @internal
307 */
308SUPDECL(int64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
309{
310 uint16_t iGipCpu = supGetGipCpuIndex(pGip);
311 if (RT_LIKELY(iGipCpu < pGip->cCpus))
312 {
313 int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
314 if (iTscDelta != INT64_MAX)
315 return iTscDelta;
316 }
317 AssertFailed();
318 return 0;
319}
320
321
322/**
323 * Slow path in SUPGetCpuHzFromGip, don't call directly.
324 *
325 * @returns See SUPGetCpuHzFromGip.
326 * @param pGip The GIP.
327 * @internal
328 */
329SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
330{
331 uint16_t iGipCpu = supGetGipCpuIndex(pGip);
332 if (RT_LIKELY(iGipCpu < pGip->cCpus))
333 return pGip->aCPUs[iGipCpu].u64CpuHz;
334 AssertFailed();
335 return pGip->u64CpuHz;
336}
337
338
339
340/**
341 * Worker for SUPIsTscFreqCompatible().
342 *
343 * @returns true if it's compatible, false otherwise.
344 * @param uBaseCpuHz The reference CPU frequency of the system.
345 * @param uCpuHz The CPU frequency to compare with the base.
346 * @param fRelax Whether to use a more relaxed threshold (like
347 * for when running in a virtualized environment).
348 *
349 * @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
350 * to be used by tstGIP-2 or the like.
351 */
352SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
353{
354 if (uBaseCpuHz != uCpuHz)
355 {
356 /* Arbitrary tolerance threshold, tweak later if required, perhaps
357 more tolerance on lower frequencies and less tolerance on higher. */
358 uint16_t uFact = !fRelax ? 666 /* 0.15% */ : 125 /* 0.8% */;
359 uint64_t uThr = uBaseCpuHz / uFact;
360 uint64_t uLo = uBaseCpuHz - uThr;
361 uint64_t uHi = uBaseCpuHz + uThr;
362 if ( uCpuHz < uLo
363 || uCpuHz > uHi)
364 return false;
365 }
366 return true;
367}
368
369
370/**
371 * Checks if the provided TSC frequency is close enough to the computed TSC
372 * frequency of the host.
373 *
374 * @returns true if it's compatible, false otherwise.
375 * @param uCpuHz The TSC frequency to check.
376 * @param puGipCpuHz Where to store the GIP TSC frequency used
377 * during the compatibility test - optional.
378 * @param fRelax Whether to use a more relaxed threshold (like
379 * for when running in a virtualized environment).
380 */
381SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
382{
383 PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
384 bool fCompat = false;
385 uint64_t uGipCpuHz = 0;
386 if ( pGip
387 && pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
388 {
389 uGipCpuHz = pGip->u64CpuHz;
390 fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
391 }
392 if (puGipCpuHz)
393 *puGipCpuHz = uGipCpuHz;
394 return fCompat;
395}
396
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