1 | /* $Id: SUPLibAll.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
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2 | /** @file
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3 | * VirtualBox Support Library - All Contexts Code.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2020 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * The contents of this file may alternatively be used under the terms
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18 | * of the Common Development and Distribution License Version 1.0
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19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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20 | * VirtualBox OSE distribution, in which case the provisions of the
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21 | * CDDL are applicable instead of those of the GPL.
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22 | *
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23 | * You may elect to license modified versions of this file under the
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24 | * terms and conditions of either the GPL or the CDDL or both.
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25 | */
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26 |
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27 |
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28 | /*********************************************************************************************************************************
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29 | * Header Files *
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30 | *********************************************************************************************************************************/
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31 | #include <VBox/sup.h>
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32 | #ifdef IN_RC
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33 | # include <VBox/vmm/vm.h>
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34 | # include <VBox/vmm/vmm.h>
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35 | #endif
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36 | #ifdef IN_RING0
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37 | # include <iprt/mp.h>
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38 | #endif
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39 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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40 | # include <iprt/asm-amd64-x86.h>
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41 | #endif
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42 | #include <iprt/errcore.h>
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43 |
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44 |
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45 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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46 |
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47 | /**
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48 | * The slow case for SUPReadTsc where we need to apply deltas.
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49 | *
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50 | * Must only be called when deltas are applicable, so please do not call it
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51 | * directly.
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52 | *
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53 | * @returns TSC with delta applied.
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54 | * @param pGip Pointer to the GIP.
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55 | *
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56 | * @remarks May be called with interrupts disabled in ring-0! This is why the
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57 | * ring-0 code doesn't attempt to figure the delta.
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58 | *
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59 | * @internal
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60 | */
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61 | SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
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62 | {
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63 | uint64_t uTsc;
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64 | uint16_t iGipCpu;
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65 | AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
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66 | AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
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67 | Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
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68 |
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69 | /*
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70 | * Read the TSC and get the corresponding aCPUs index.
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71 | */
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72 | #ifdef IN_RING3
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73 | if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
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74 | {
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75 | /* RDTSCP gives us all we need, no loops/cli. */
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76 | uint32_t iCpuSet;
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77 | uTsc = ASMReadTscWithAux(&iCpuSet);
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78 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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79 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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80 | }
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81 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
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82 | {
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83 | /* Storing the IDTR is normally very quick, but we need to loop. */
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84 | uint32_t cTries = 0;
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85 | for (;;)
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86 | {
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87 | uint16_t cbLim = ASMGetIdtrLimit();
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88 | uTsc = ASMReadTSC();
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89 | if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
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90 | {
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91 | uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
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92 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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93 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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94 | break;
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95 | }
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96 | if (cTries >= 16)
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97 | {
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98 | iGipCpu = UINT16_MAX;
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99 | break;
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100 | }
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101 | cTries++;
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102 | }
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103 | }
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104 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
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105 | {
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106 | /* Get APIC ID / 0x1b via the slow CPUID instruction, requires looping. */
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107 | uint32_t cTries = 0;
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108 | for (;;)
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109 | {
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110 | uint32_t idApic = ASMGetApicIdExt0B();
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111 | uTsc = ASMReadTSC();
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112 | if (RT_LIKELY(ASMGetApicIdExt0B() == idApic))
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113 | {
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114 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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115 | break;
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116 | }
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117 | if (cTries >= 16)
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118 | {
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119 | iGipCpu = UINT16_MAX;
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120 | break;
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121 | }
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122 | cTries++;
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123 | }
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124 | }
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125 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
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126 | {
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127 | /* Get APIC ID / 0x8000001e via the slow CPUID instruction, requires looping. */
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128 | uint32_t cTries = 0;
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129 | for (;;)
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130 | {
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131 | uint32_t idApic = ASMGetApicIdExt8000001E();
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132 | uTsc = ASMReadTSC();
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133 | if (RT_LIKELY(ASMGetApicIdExt8000001E() == idApic))
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134 | {
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135 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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136 | break;
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137 | }
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138 | if (cTries >= 16)
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139 | {
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140 | iGipCpu = UINT16_MAX;
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141 | break;
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142 | }
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143 | cTries++;
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144 | }
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145 | }
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146 | else
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147 | {
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148 | /* Get APIC ID via the slow CPUID instruction, requires looping. */
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149 | uint32_t cTries = 0;
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150 | for (;;)
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151 | {
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152 | uint8_t idApic = ASMGetApicId();
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153 | uTsc = ASMReadTSC();
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154 | if (RT_LIKELY(ASMGetApicId() == idApic))
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155 | {
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156 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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157 | break;
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158 | }
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159 | if (cTries >= 16)
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160 | {
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161 | iGipCpu = UINT16_MAX;
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162 | break;
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163 | }
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164 | cTries++;
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165 | }
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166 | }
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167 | #elif defined(IN_RING0)
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168 | /* Ring-0: Use use RTMpCpuId(), no loops. */
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169 | RTCCUINTREG uFlags = ASMIntDisableFlags();
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170 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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171 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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172 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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173 | else
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174 | iGipCpu = UINT16_MAX;
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175 | uTsc = ASMReadTSC();
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176 | ASMSetFlags(uFlags);
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177 |
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178 | # elif defined(IN_RC)
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179 | /* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
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180 | RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
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181 | uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
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182 | if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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183 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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184 | else
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185 | iGipCpu = UINT16_MAX;
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186 | uTsc = ASMReadTSC();
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187 | ASMSetFlags(uFlags);
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188 | #else
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189 | # error "IN_RING3, IN_RC or IN_RING0 must be defined!"
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190 | #endif
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191 |
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192 | /*
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193 | * If the delta is valid, apply it.
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194 | */
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195 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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196 | {
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197 | int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
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198 | if (RT_LIKELY(iTscDelta != INT64_MAX))
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199 | return uTsc - iTscDelta;
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200 |
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201 | # ifdef IN_RING3
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202 | /*
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203 | * The delta needs calculating, call supdrv to get the TSC.
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204 | */
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205 | int rc = SUPR3ReadTsc(&uTsc, NULL);
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206 | if (RT_SUCCESS(rc))
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207 | return uTsc;
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208 | AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
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209 | uTsc = ASMReadTSC();
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210 | # endif /* IN_RING3 */
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211 | }
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212 |
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213 | /*
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214 | * This shouldn't happen, especially not in ring-3 and raw-mode context.
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215 | * But if it does, return something that's half useful.
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216 | */
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217 | AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
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218 | return uTsc;
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219 | }
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220 |
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221 |
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222 | /**
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223 | * Internal worker for getting the GIP CPU array index for the calling CPU.
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224 | *
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225 | * @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
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226 | * @param pGip The GIP.
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227 | */
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228 | DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
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229 | {
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230 | uint16_t iGipCpu;
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231 | #ifdef IN_RING3
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232 | if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
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233 | {
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234 | /* Storing the IDTR is normally very fast. */
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235 | uint16_t cbLim = ASMGetIdtrLimit();
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236 | uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
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237 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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238 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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239 | }
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240 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
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241 | {
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242 | /* RDTSCP gives us what need need and more. */
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243 | uint32_t iCpuSet;
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244 | ASMReadTscWithAux(&iCpuSet);
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245 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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246 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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247 | }
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248 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_0B)
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249 | {
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250 | /* Get APIC ID via the slow CPUID/0000000B instruction. */
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251 | uint32_t idApic = ASMGetApicIdExt0B();
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252 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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253 | }
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254 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_APIC_ID_EXT_8000001E)
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255 | {
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256 | /* Get APIC ID via the slow CPUID/8000001E instruction. */
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257 | uint32_t idApic = ASMGetApicIdExt8000001E();
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258 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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259 | }
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260 | else
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261 | {
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262 | /* Get APIC ID via the slow CPUID instruction. */
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263 | uint8_t idApic = ASMGetApicId();
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264 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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265 | }
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266 | #elif defined(IN_RING0)
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267 | /* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
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268 | RTCCUINTREG uFlags = ASMIntDisableFlags();
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269 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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270 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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271 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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272 | else
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273 | iGipCpu = UINT16_MAX;
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274 | ASMSetFlags(uFlags);
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275 |
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276 | # elif defined(IN_RC)
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277 | /* Raw-mode context: We can get the host CPU set index via VMCPU. */
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278 | uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
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279 | if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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280 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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281 | else
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282 | iGipCpu = UINT16_MAX;
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283 | #else
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284 | # error "IN_RING3, IN_RC or IN_RING0 must be defined!"
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285 | #endif
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286 | return iGipCpu;
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287 | }
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288 |
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289 |
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290 | /**
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291 | * Slow path in SUPGetTscDelta, don't call directly.
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292 | *
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293 | * @returns See SUPGetTscDelta.
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294 | * @param pGip The GIP.
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295 | * @internal
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296 | */
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297 | SUPDECL(uint64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
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298 | {
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299 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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300 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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301 | {
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302 | int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
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303 | if (iTscDelta != INT64_MAX)
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304 | return iTscDelta;
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305 | }
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306 | AssertFailed();
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307 | return 0;
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308 | }
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309 |
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310 |
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311 | /**
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312 | * Slow path in SUPGetCpuHzFromGip, don't call directly.
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313 | *
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314 | * @returns See SUPGetCpuHzFromGip.
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315 | * @param pGip The GIP.
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316 | * @internal
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317 | */
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318 | SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
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319 | {
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320 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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321 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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322 | return pGip->aCPUs[iGipCpu].u64CpuHz;
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323 | AssertFailed();
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324 | return pGip->u64CpuHz;
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325 | }
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326 |
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327 |
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328 | /**
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329 | * Worker for SUPIsTscFreqCompatible().
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330 | *
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331 | * @returns true if it's compatible, false otherwise.
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332 | * @param uBaseCpuHz The reference CPU frequency of the system.
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333 | * @param uCpuHz The CPU frequency to compare with the base.
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334 | * @param fRelax Whether to use a more relaxed threshold (like
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335 | * for when running in a virtualized environment).
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336 | *
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337 | * @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
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338 | * to be used by tstGIP-2 or the like.
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339 | */
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340 | SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
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341 | {
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342 | if (uBaseCpuHz != uCpuHz)
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343 | {
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344 | /* Arbitrary tolerance threshold, tweak later if required, perhaps
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345 | more tolerance on lower frequencies and less tolerance on higher. */
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346 | uint16_t uFact = !fRelax ? 666 /* 0.15% */ : 125 /* 0.8% */;
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347 | uint64_t uThr = uBaseCpuHz / uFact;
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348 | uint64_t uLo = uBaseCpuHz - uThr;
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349 | uint64_t uHi = uBaseCpuHz + uThr;
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350 | if ( uCpuHz < uLo
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351 | || uCpuHz > uHi)
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352 | return false;
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353 | }
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354 | return true;
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355 | }
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356 |
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357 |
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358 | /**
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359 | * Checks if the provided TSC frequency is close enough to the computed TSC
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360 | * frequency of the host.
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361 | *
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362 | * @returns true if it's compatible, false otherwise.
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363 | * @param uCpuHz The TSC frequency to check.
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364 | * @param puGipCpuHz Where to store the GIP TSC frequency used
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365 | * during the compatibility test - optional.
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366 | * @param fRelax Whether to use a more relaxed threshold (like
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367 | * for when running in a virtualized environment).
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368 | */
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369 | SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
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370 | {
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371 | PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
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372 | bool fCompat = false;
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373 | uint64_t uGipCpuHz = 0;
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374 | if ( pGip
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375 | && pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
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376 | {
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377 | uGipCpuHz = pGip->u64CpuHz;
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378 | fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
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379 | }
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380 | if (puGipCpuHz)
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381 | *puGipCpuHz = uGipCpuHz;
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382 | return fCompat;
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383 | }
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384 |
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385 | #endif /* RT_ARCH_AMD64 || RT_ARCH_X86 */
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386 |
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