[54224] | 1 | /* $Id: SUPLibAll.cpp 62490 2016-07-22 18:41:49Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VirtualBox Support Library - All Contexts Code.
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| 4 | */
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| 5 |
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| 6 | /*
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[62490] | 7 | * Copyright (C) 2006-2016 Oracle Corporation
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[54224] | 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * The contents of this file may alternatively be used under the terms
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| 18 | * of the Common Development and Distribution License Version 1.0
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| 19 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | * VirtualBox OSE distribution, in which case the provisions of the
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| 21 | * CDDL are applicable instead of those of the GPL.
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| 22 | *
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| 23 | * You may elect to license modified versions of this file under the
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| 24 | * terms and conditions of either the GPL or the CDDL or both.
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| 25 | */
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| 26 |
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[57358] | 27 |
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| 28 | /*********************************************************************************************************************************
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| 29 | * Header Files *
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| 30 | *********************************************************************************************************************************/
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[54224] | 31 | #include <VBox/sup.h>
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[54257] | 32 | #ifdef IN_RC
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| 33 | # include <VBox/vmm/vm.h>
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| 34 | # include <VBox/vmm/vmm.h>
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| 35 | #endif
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[54224] | 36 | #ifdef IN_RING0
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| 37 | # include <iprt/mp.h>
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| 38 | #endif
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| 39 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 40 | # include <iprt/asm-amd64-x86.h>
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| 41 | #endif
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| 42 |
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| 43 |
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| 44 | #if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
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| 45 |
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| 46 | /**
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| 47 | * The slow case for SUPReadTsc where we need to apply deltas.
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| 48 | *
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| 49 | * Must only be called when deltas are applicable, so please do not call it
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| 50 | * directly.
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| 51 | *
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| 52 | * @returns TSC with delta applied.
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[54308] | 53 | * @param pGip Pointer to the GIP.
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[54224] | 54 | *
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| 55 | * @remarks May be called with interrupts disabled in ring-0! This is why the
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| 56 | * ring-0 code doesn't attempt to figure the delta.
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| 57 | *
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| 58 | * @internal
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| 59 | */
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[54335] | 60 | SUPDECL(uint64_t) SUPReadTscWithDelta(PSUPGLOBALINFOPAGE pGip)
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[54224] | 61 | {
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[54257] | 62 | uint64_t uTsc;
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| 63 | uint16_t iGipCpu;
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| 64 | AssertCompile(RT_IS_POWER_OF_TWO(RTCPUSET_MAX_CPUS));
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| 65 | AssertCompile(RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx) >= RTCPUSET_MAX_CPUS);
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[54308] | 66 | Assert(pGip->enmUseTscDelta > SUPGIPUSETSCDELTA_PRACTICALLY_ZERO);
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[54224] | 67 |
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| 68 | /*
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[54257] | 69 | * Read the TSC and get the corresponding aCPUs index.
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[54224] | 70 | */
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[54308] | 71 | #ifdef IN_RING3
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[54257] | 72 | if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
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[54224] | 73 | {
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[54257] | 74 | /* RDTSCP gives us all we need, no loops/cli. */
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| 75 | uint32_t iCpuSet;
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| 76 | uTsc = ASMReadTscWithAux(&iCpuSet);
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| 77 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 78 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 79 | }
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| 80 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
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| 81 | {
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| 82 | /* Storing the IDTR is normally very quick, but we need to loop. */
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| 83 | uint32_t cTries = 0;
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| 84 | for (;;)
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[54224] | 85 | {
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[54257] | 86 | uint16_t cbLim = ASMGetIdtrLimit();
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| 87 | uTsc = ASMReadTSC();
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| 88 | if (RT_LIKELY(ASMGetIdtrLimit() == cbLim))
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| 89 | {
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| 90 | uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
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| 91 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 92 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 93 | break;
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| 94 | }
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| 95 | if (cTries >= 16)
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| 96 | {
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| 97 | iGipCpu = UINT16_MAX;
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| 98 | break;
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| 99 | }
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| 100 | cTries++;
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| 101 | }
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| 102 | }
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| 103 | else
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| 104 | {
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[54308] | 105 | /* Get APIC ID via the slow CPUID instruction, requires looping. */
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[54257] | 106 | uint32_t cTries = 0;
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| 107 | for (;;)
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| 108 | {
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| 109 | uint8_t idApic = ASMGetApicId();
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| 110 | uTsc = ASMReadTSC();
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| 111 | if (RT_LIKELY(ASMGetApicId() == idApic))
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| 112 | {
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| 113 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 114 | break;
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| 115 | }
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| 116 | if (cTries >= 16)
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| 117 | {
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| 118 | iGipCpu = UINT16_MAX;
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| 119 | break;
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| 120 | }
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| 121 | cTries++;
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| 122 | }
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[54308] | 123 | }
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| 124 | #elif defined(IN_RING0)
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| 125 | /* Ring-0: Use use RTMpCpuId(), no loops. */
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| 126 | RTCCUINTREG uFlags = ASMIntDisableFlags();
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| 127 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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| 128 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 129 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 130 | else
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| 131 | iGipCpu = UINT16_MAX;
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| 132 | uTsc = ASMReadTSC();
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| 133 | ASMSetFlags(uFlags);
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[54224] | 134 |
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[54257] | 135 | # elif defined(IN_RC)
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[54308] | 136 | /* Raw-mode context: We can get the host CPU set index via VMCPU, no loops. */
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| 137 | RTCCUINTREG uFlags = ASMIntDisableFlags(); /* Are already disable, but play safe. */
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| 138 | uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
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| 139 | if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 140 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 141 | else
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| 142 | iGipCpu = UINT16_MAX;
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| 143 | uTsc = ASMReadTSC();
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| 144 | ASMSetFlags(uFlags);
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| 145 | #else
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| 146 | # error "IN_RING3, IN_RC or IN_RING0 must be defined!"
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| 147 | #endif
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[54257] | 148 |
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[54224] | 149 | /*
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[54257] | 150 | * If the delta is valid, apply it.
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[54224] | 151 | */
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[54257] | 152 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 153 | {
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| 154 | int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
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| 155 | if (RT_LIKELY(iTscDelta != INT64_MAX))
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[55246] | 156 | return uTsc - iTscDelta;
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[54224] | 157 |
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[54257] | 158 | # ifdef IN_RING3
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| 159 | /*
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| 160 | * The delta needs calculating, call supdrv to get the TSC.
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| 161 | */
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| 162 | int rc = SUPR3ReadTsc(&uTsc, NULL);
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| 163 | if (RT_SUCCESS(rc))
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| 164 | return uTsc;
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| 165 | AssertMsgFailed(("SUPR3ReadTsc -> %Rrc\n", rc));
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| 166 | uTsc = ASMReadTSC();
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| 167 | # endif /* IN_RING3 */
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| 168 | }
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| 169 |
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[54224] | 170 | /*
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[54257] | 171 | * This shouldn't happen, especially not in ring-3 and raw-mode context.
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| 172 | * But if it does, return something that's half useful.
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[54224] | 173 | */
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[54257] | 174 | AssertMsgFailed(("iGipCpu=%d (%#x) cCpus=%d fGetGipCpu=%#x\n", iGipCpu, iGipCpu, pGip->cCpus, pGip->fGetGipCpu));
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[54224] | 175 | return uTsc;
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| 176 | }
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| 177 |
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[54308] | 178 |
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| 179 | /**
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| 180 | * Internal worker for getting the GIP CPU array index for the calling CPU.
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| 181 | *
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| 182 | * @returns Index into SUPGLOBALINFOPAGE::aCPUs or UINT16_MAX.
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| 183 | * @param pGip The GIP.
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| 184 | */
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| 185 | DECLINLINE(uint16_t) supGetGipCpuIndex(PSUPGLOBALINFOPAGE pGip)
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| 186 | {
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| 187 | uint16_t iGipCpu;
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| 188 | #ifdef IN_RING3
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| 189 | if (pGip->fGetGipCpu & SUPGIPGETCPU_IDTR_LIMIT_MASK_MAX_SET_CPUS)
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| 190 | {
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| 191 | /* Storing the IDTR is normally very fast. */
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| 192 | uint16_t cbLim = ASMGetIdtrLimit();
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| 193 | uint16_t iCpuSet = cbLim - 256 * (ARCH_BITS == 64 ? 16 : 8);
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| 194 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 195 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 196 | }
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| 197 | else if (pGip->fGetGipCpu & SUPGIPGETCPU_RDTSCP_MASK_MAX_SET_CPUS)
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| 198 | {
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| 199 | /* RDTSCP gives us what need need and more. */
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| 200 | uint32_t iCpuSet;
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| 201 | ASMReadTscWithAux(&iCpuSet);
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| 202 | iCpuSet &= RTCPUSET_MAX_CPUS - 1;
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| 203 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 204 | }
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| 205 | else
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| 206 | {
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| 207 | /* Get APIC ID via the slow CPUID instruction. */
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| 208 | uint8_t idApic = ASMGetApicId();
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| 209 | iGipCpu = pGip->aiCpuFromApicId[idApic];
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| 210 | }
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| 211 | #elif defined(IN_RING0)
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| 212 | /* Ring-0: Use use RTMpCpuId() (disables cli to avoid host OS assertions about unsafe CPU number usage). */
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| 213 | RTCCUINTREG uFlags = ASMIntDisableFlags();
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| 214 | int iCpuSet = RTMpCpuIdToSetIndex(RTMpCpuId());
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| 215 | if (RT_LIKELY((unsigned)iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 216 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 217 | else
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| 218 | iGipCpu = UINT16_MAX;
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| 219 | ASMSetFlags(uFlags);
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| 220 |
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| 221 | # elif defined(IN_RC)
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| 222 | /* Raw-mode context: We can get the host CPU set index via VMCPU. */
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| 223 | uint32_t iCpuSet = VMMGetCpu(&g_VM)->iHostCpuSet;
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| 224 | if (RT_LIKELY(iCpuSet < RT_ELEMENTS(pGip->aiCpuFromCpuSetIdx)))
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| 225 | iGipCpu = pGip->aiCpuFromCpuSetIdx[iCpuSet];
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| 226 | else
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| 227 | iGipCpu = UINT16_MAX;
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| 228 | #else
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| 229 | # error "IN_RING3, IN_RC or IN_RING0 must be defined!"
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| 230 | #endif
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| 231 | return iGipCpu;
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| 232 | }
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| 233 |
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| 234 |
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| 235 | /**
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| 236 | * Slow path in SUPGetTscDelta, don't call directly.
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| 237 | *
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| 238 | * @returns See SUPGetTscDelta.
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| 239 | * @param pGip The GIP.
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| 240 | * @internal
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| 241 | */
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| 242 | SUPDECL(uint64_t) SUPGetTscDeltaSlow(PSUPGLOBALINFOPAGE pGip)
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| 243 | {
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| 244 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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| 245 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 246 | {
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| 247 | int64_t iTscDelta = pGip->aCPUs[iGipCpu].i64TSCDelta;
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| 248 | if (iTscDelta != INT64_MAX)
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| 249 | return iTscDelta;
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| 250 | }
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| 251 | AssertFailed();
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| 252 | return 0;
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| 253 | }
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| 254 |
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| 255 |
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| 256 | /**
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| 257 | * Slow path in SUPGetCpuHzFromGip, don't call directly.
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| 258 | *
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| 259 | * @returns See SUPGetCpuHzFromGip.
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| 260 | * @param pGip The GIP.
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| 261 | * @internal
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| 262 | */
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| 263 | SUPDECL(uint64_t) SUPGetCpuHzFromGipForAsyncMode(PSUPGLOBALINFOPAGE pGip)
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| 264 | {
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| 265 | uint16_t iGipCpu = supGetGipCpuIndex(pGip);
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| 266 | if (RT_LIKELY(iGipCpu < pGip->cCpus))
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| 267 | return pGip->aCPUs[iGipCpu].u64CpuHz;
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| 268 | AssertFailed();
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| 269 | return pGip->u64CpuHz;
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| 270 | }
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| 271 |
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| 272 |
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[57090] | 273 | /**
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| 274 | * Worker for SUPIsTscFreqCompatible().
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| 275 | *
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| 276 | * @returns true if it's compatible, false otherwise.
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| 277 | * @param uBaseCpuHz The reference CPU frequency of the system.
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| 278 | * @param uCpuHz The CPU frequency to compare with the base.
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| 279 | * @param fRelax Whether to use a more relaxed threshold (like
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| 280 | * for when running in a virtualized environment).
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| 281 | *
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| 282 | * @remarks Don't use directly, use SUPIsTscFreqCompatible() instead. This is
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| 283 | * to be used by tstGIP-2 or the like.
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| 284 | */
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| 285 | SUPDECL(bool) SUPIsTscFreqCompatibleEx(uint64_t uBaseCpuHz, uint64_t uCpuHz, bool fRelax)
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| 286 | {
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| 287 | if (uBaseCpuHz != uCpuHz)
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| 288 | {
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| 289 | /* Arbitrary tolerance threshold, tweak later if required, perhaps
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| 290 | more tolerance on lower frequencies and less tolerance on higher. */
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[57218] | 291 | uint16_t uFact = !fRelax ? 666 /* 0.15% */ : 125 /* 0.8% */;
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| 292 | uint64_t uThr = uBaseCpuHz / uFact;
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| 293 | uint64_t uLo = uBaseCpuHz - uThr;
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| 294 | uint64_t uHi = uBaseCpuHz + uThr;
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[57090] | 295 | if ( uCpuHz < uLo
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| 296 | || uCpuHz > uHi)
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| 297 | return false;
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| 298 | }
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| 299 | return true;
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| 300 | }
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| 301 |
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| 302 |
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| 303 | /**
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| 304 | * Checks if the provided TSC frequency is close enough to the computed TSC
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| 305 | * frequency of the host.
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| 306 | *
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| 307 | * @returns true if it's compatible, false otherwise.
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| 308 | * @param uCpuHz The TSC frequency to check.
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| 309 | * @param puGipCpuHz Where to store the GIP TSC frequency used
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| 310 | * during the compatibility test - optional.
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| 311 | * @param fRelax Whether to use a more relaxed threshold (like
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| 312 | * for when running in a virtualized environment).
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| 313 | */
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| 314 | SUPDECL(bool) SUPIsTscFreqCompatible(uint64_t uCpuHz, uint64_t *puGipCpuHz, bool fRelax)
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| 315 | {
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| 316 | PSUPGLOBALINFOPAGE pGip = g_pSUPGlobalInfoPage;
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[57097] | 317 | bool fCompat = false;
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| 318 | uint64_t uGipCpuHz = 0;
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[57090] | 319 | if ( pGip
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| 320 | && pGip->u32Mode != SUPGIPMODE_ASYNC_TSC)
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| 321 | {
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[57097] | 322 | uGipCpuHz = pGip->u64CpuHz;
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| 323 | fCompat = SUPIsTscFreqCompatibleEx(uGipCpuHz, uCpuHz, fRelax);
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[57090] | 324 | }
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[57097] | 325 | if (puGipCpuHz)
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| 326 | *puGipCpuHz = uGipCpuHz;
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| 327 | return fCompat;
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[57090] | 328 | }
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| 329 |
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[54224] | 330 | #endif /* RT_ARCH_AMD64 || RT_ARCH_X86 */
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| 331 |
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