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DisasmTables-armv8-a64.cpp

Last change on this file was 100046, checked in by vboxsync, 12 months ago
Disassembler: Some updates to the ARMv8 disassembler lying around, bugref:10394
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1	/* $Id: DisasmTables-armv8-a64.cpp 100046 2023-06-01 18:57:29Z vboxsync $ */
2	/** @file
3	* VBox disassembler - Tables for ARMv8 A64.
4	*/
5
6	/*
7	* Copyright (C) 2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#include <VBox/dis.h>
33	#include <VBox/disopcode-armv8.h>
34	#include "DisasmInternal-armv8.h"
35
36
37	/*********************************************************************************************************************************
38	* Global Variables *
39	*********************************************************************************************************************************/
40
41	#define DIS_ARMV8_OP(a_fMask, a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \
42	{ a_fMask, a_fValue, OP(a_szOpcode, 0, 0, 0, a_uOpcode, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, a_fOpType) }
43
44	#ifndef DIS_CORE_ONLY
45	static char g_szInvalidOpcode[] = "Invalid Opcode";
46	#endif
47
48	#define INVALID_OPCODE \
49	DIS_ARMV8_OP(0xffffffff, 0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)
50
51
52	/* Invalid opcode */
53	DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] =
54	{
55	OP(g_szInvalidOpcode, 0, 0, 0, OP_ARMV8_INVALID, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, DISOPTYPE_INVALID)
56	};
57
58
59	/* UDF */
60	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_aArmV8A64InsnRsvd)
61	DIS_ARMV8_OP(0xffff0000, 0x00000000, "udf %I" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID)
62	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_aArmV8A64InsnRsvd, 0 /fClass/,
63	kDisArmV8OpcDecodeNop, 0xffff0000, 16)
64	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 0, 16),
65	DIS_ARMV8_INSN_PARAM_NONE,
66	DIS_ARMV8_INSN_PARAM_NONE,
67	DIS_ARMV8_INSN_PARAM_NONE
68	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
69
70
71	/* ADR/ADRP */
72	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Adr)
73	DIS_ARMV8_OP(0x9f000000, 0x10000000, "adr %X,%I" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS),
74	DIS_ARMV8_OP(0x9f000000, 0x90000000, "adrp %X,%I" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS)
75	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Adr, DISARMV8INSNCLASS_F_FORCED_64BIT,
76	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31)
77	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
78	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmAdr, 0, 0),
79	DIS_ARMV8_INSN_PARAM_NONE,
80	DIS_ARMV8_INSN_PARAM_NONE
81	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
82
83
84	/* ADD/ADDS/SUB/SUBS */
85	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64AddSubImm)
86	DIS_ARMV8_OP(0x7f800000, 0x11000000, "add %X,%X,%I" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS),
87	DIS_ARMV8_OP(0x7f800000, 0x31000000, "adds %X,%X,%I" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS),
88	DIS_ARMV8_OP(0x7f800000, 0x51000000, "sub %X,%X,%I" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS),
89	DIS_ARMV8_OP(0x7f800000, 0x71000000, "subs %X,%X,%I" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS),
90	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64AddSubImm, DISARMV8INSNCLASS_F_SF,
91	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
92	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
93	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5),
94	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 10, 12),
95	DIS_ARMV8_INSN_PARAM_NONE
96	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
97
98
99	/* AND/ORR/EOR/ANDS */
100	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64LogicalImm)
101	DIS_ARMV8_OP(0x7f800000, 0x12000000, "and %X,%X,%I" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS),
102	DIS_ARMV8_OP(0x7f800000, 0x32000000, "orr %X,%X,%I" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS),
103	DIS_ARMV8_OP(0x7f800000, 0x52000000, "eor %X,%X,%I" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS),
104	DIS_ARMV8_OP(0x7f800000, 0x72000000, "ands %X,%X,%I" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS),
105	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LogicalImm, DISARMV8INSNCLASS_F_SF,
106	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
107	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
108	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 6),
109	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13),
110	DIS_ARMV8_INSN_PARAM_NONE
111	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
112
113
114	/* MOVN/MOVZ/MOVK */
115	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64MoveWide)
116	DIS_ARMV8_OP(0x7f800000, 0x12800000, "movn %X,%I LSL %I", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS),
117	INVALID_OPCODE,
118	DIS_ARMV8_OP(0x7f800000, 0x52800000, "movz %X,%I LSL %I" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS),
119	DIS_ARMV8_OP(0x7f800000, 0x72800000, "movk %X,%I LSL %I" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS),
120	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64MoveWide, DISARMV8INSNCLASS_F_SF,
121	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
122	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
123	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16),
124	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseHw, 21, 2),
125	DIS_ARMV8_INSN_PARAM_NONE
126	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
127
128
129	/* SBFM/BFM/UBFM */
130	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Bitfield)
131	DIS_ARMV8_OP(0x7f800000, 0x13000000, "sbfm %X,%X,%I", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS),
132	DIS_ARMV8_OP(0x7f800000, 0x33000000, "bfm %X,%X,%I", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS),
133	DIS_ARMV8_OP(0x7f800000, 0x23000000, "ubfm %X,%X,%I", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),
134	INVALID_OPCODE,
135	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Bitfield, DISARMV8INSNCLASS_F_SF \| DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT,
136	kDisArmV8OpcDecodeNop, RT_BIT_32(29) \| RT_BIT_32(30), 29)
137	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
138	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5),
139	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13),
140	DIS_ARMV8_INSN_PARAM_NONE
141	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
142
143
144	/*
145	* C4.1.65 of the ARMv8 architecture reference manual has the following table for the
146	* data processing (immediate) instruction classes:
147	*
148	* Bit 25 24 23
149	* +-------------------------------------------
150	* 0 0 x PC-rel. addressing.
151	* 0 1 0 Add/subtract (immediate)
152	* 0 1 1 Add/subtract (immediate, with tags)
153	* 1 0 0 Logical (immediate)
154	* 1 0 1 Move wide (immediate)
155	* 1 1 0 Bitfield
156	* 1 1 1 Extract
157	*/
158	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_aArmV8A64InsnDataProcessingImm)
159	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Adr),
160	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Adr),
161	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64AddSubImm),
162	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo Add/subtract immediate with tags. */
163	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64LogicalImm),
164	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64MoveWide),
165	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Bitfield),
166	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo Extract */
167	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_aArmV8A64InsnDataProcessingImm, RT_BIT_32(23) \| RT_BIT_32(24) \| RT_BIT_32(25), 23);
168
169
170	/* B.cond/BC.cond */
171	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CondBr)
172	DIS_ARMV8_OP(0xff000010, 0x54000000, "b.%C %J", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
173	DIS_ARMV8_OP(0xff000010, 0x54000010, "bc.%C %J" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW \| DISOPTYPE_RELATIVE_CONTROLFLOW \| DISOPTYPE_COND_CONTROLFLOW),
174	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CondBr, 0 /fClass/,
175	kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4)
176	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCond, 0, 4),
177	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19),
178	DIS_ARMV8_INSN_PARAM_NONE,
179	DIS_ARMV8_INSN_PARAM_NONE
180	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
181
182
183	/* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */
184	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Excp)
185	DIS_ARMV8_OP(0xffe0001f, 0xd4000001, "svc %I", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
186	DIS_ARMV8_OP(0xffe0001f, 0xd4000002, "hvc %I", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
187	DIS_ARMV8_OP(0xffe0001f, 0xd4000003, "smc %I", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT \| DISOPTYPE_PRIVILEGED),
188	DIS_ARMV8_OP(0xffe0001f, 0xd4200000, "brk %I", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
189	DIS_ARMV8_OP(0xffe0001f, 0xd4400000, "hlt %I", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
190	DIS_ARMV8_OP(0xffe0001f, 0xd4600000, "tcancel %I", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT), /* FEAT_TME */
191	DIS_ARMV8_OP(0xffe0001f, 0xd4a00001, "dcps1 %I", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
192	DIS_ARMV8_OP(0xffe0001f, 0xd4a00002, "dcps2 %I", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
193	DIS_ARMV8_OP(0xffe0001f, 0xd4a00003, "dcps3 %I", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW \| DISOPTYPE_INTERRUPT),
194	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Excp, 0 /fClass/,
195	kDisArmV8OpcDecodeLookup, 0xffe0001f, 0)
196	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16),
197	DIS_ARMV8_INSN_PARAM_NONE,
198	DIS_ARMV8_INSN_PARAM_NONE,
199	DIS_ARMV8_INSN_PARAM_NONE
200	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
201
202
203	/* WFET/WFIT */
204	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysReg)
205	DIS_ARMV8_OP(0xffffffe0, 0xd5031000, "wfet %X", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
206	DIS_ARMV8_OP(0xffffffe0, 0x54000010, "wfit %X" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */
207	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysReg, DISARMV8INSNCLASS_F_FORCED_64BIT,
208	kDisArmV8OpcDecodeNop, 0xfe0, 5)
209	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
210	DIS_ARMV8_INSN_PARAM_NONE,
211	DIS_ARMV8_INSN_PARAM_NONE,
212	DIS_ARMV8_INSN_PARAM_NONE
213	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
214
215
216	/* Various hint instructions */
217	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Hints)
218	DIS_ARMV8_OP(0xffffffff, 0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS),
219	DIS_ARMV8_OP(0xffffffff, 0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS),
220	DIS_ARMV8_OP(0xffffffff, 0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS),
221	DIS_ARMV8_OP(0xffffffff, 0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS),
222	DIS_ARMV8_OP(0xffffffff, 0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS),
223	DIS_ARMV8_OP(0xffffffff, 0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS),
224	DIS_ARMV8_OP(0xffffffff, 0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */
225	DIS_ARMV8_OP(0xffffffff, 0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */
226	/** @todo */
227	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Hints, 0 /fClass/,
228	kDisArmV8OpcDecodeNop, 0xfe0, 5)
229	DIS_ARMV8_INSN_PARAM_NONE,
230	DIS_ARMV8_INSN_PARAM_NONE,
231	DIS_ARMV8_INSN_PARAM_NONE,
232	DIS_ARMV8_INSN_PARAM_NONE
233	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
234
235
236	/* CLREX */
237	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Clrex)
238	DIS_ARMV8_OP(0xfffff0ff, 0xd503305f, "clrex %I", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS),
239	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Clrex, 0 /fClass/,
240	kDisArmV8OpcDecodeNop, 0, 0)
241	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4),
242	DIS_ARMV8_INSN_PARAM_NONE,
243	DIS_ARMV8_INSN_PARAM_NONE,
244	DIS_ARMV8_INSN_PARAM_NONE
245	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
246
247
248	/* Barrier instructions, we divide these instructions further based on the op2 field. */
249	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DecodeBarriers)
250	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
251	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
252	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Clrex), /* CLREX */
253	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */
254	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */
255	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DMB */
256	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */
257	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */
258	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DecodeBarriers, RT_BIT_32(5) \| RT_BIT_32(6) \| RT_BIT_32(7), 5);
259
260
261	/* MSR (and potentially CFINV,XAFLAG,AXFLAG) */
262	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64PState)
263	DIS_ARMV8_OP(0xfffff0ff, 0xd503305f, "msr %P, %I", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED),
264	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64PState, 0 /fClass/,
265	kDisArmV8OpcDecodeNop, 0, 0)
266	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParsePState, 0, 0), /* This is special for the MSR instruction. */
267	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4), /* CRm field encodes the immediate value */
268	DIS_ARMV8_INSN_PARAM_NONE,
269	DIS_ARMV8_INSN_PARAM_NONE
270	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
271
272
273	/* TSTART/TTEST */
274	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysResult)
275	DIS_ARMV8_OP(0xfffffffe, 0xd5233060, "tstart %X", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED), /* FEAT_TME */
276	DIS_ARMV8_OP(0xfffffffe, 0xd5233160, "ttest %X", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */
277	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysResult, DISARMV8INSNCLASS_F_FORCED_64BIT,
278	kDisArmV8OpcDecodeNop, RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11), 8)
279	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
280	DIS_ARMV8_INSN_PARAM_NONE,
281	DIS_ARMV8_INSN_PARAM_NONE,
282	DIS_ARMV8_INSN_PARAM_NONE
283	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
284
285
286	/* SYS */
287	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Sys)
288	DIS_ARMV8_OP(0xfff80000, 0xd5080000, "sys %I, %Cn, %Cm, %I, %X", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS),
289	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Sys, DISARMV8INSNCLASS_F_FORCED_64BIT,
290	kDisArmV8OpcDecodeNop, 0, 0)
291	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3),
292	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8),
293	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3),
294	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5)
295	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
296
297
298	/* SYSL */
299	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysL)
300	DIS_ARMV8_OP(0xfff80000, 0xd5280000, "sysl %X, %I, %Cn, %Cm, %I", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS),
301	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysL, DISARMV8INSNCLASS_F_FORCED_64BIT,
302	kDisArmV8OpcDecodeNop, 0, 0)
303	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
304	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3),
305	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8),
306	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3)
307	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
308
309
310	/* MSR */
311	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Msr)
312	DIS_ARMV8_OP(0xfff00000, 0xd5080000, "msr %S, %X", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED),
313	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Msr, DISARMV8INSNCLASS_F_FORCED_64BIT,
314	kDisArmV8OpcDecodeNop, 0, 0)
315	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15),
316	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
317	DIS_ARMV8_INSN_PARAM_NONE,
318	DIS_ARMV8_INSN_PARAM_NONE
319	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
320
321
322	/* MRS */
323	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Mrs)
324	DIS_ARMV8_OP(0xfff00000, 0xd5280000, "mrs %X, %S", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS \| DISOPTYPE_PRIVILEGED),
325	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Mrs, DISARMV8INSNCLASS_F_FORCED_64BIT,
326	kDisArmV8OpcDecodeNop, 0, 0)
327	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
328	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15),
329	DIS_ARMV8_INSN_PARAM_NONE,
330	DIS_ARMV8_INSN_PARAM_NONE
331	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
332
333
334	/* Unconditional branch (register) instructions, we divide these instructions further based on the opc field. */
335	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64UncondBrReg)
336	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
337	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
338	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
339	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
340	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
341	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
342	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
343	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
344	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
345	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
346	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
347	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
348	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
349	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
350	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
351	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY
352	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64UncondBrReg, RT_BIT_32(21) \| RT_BIT_32(22) \| RT_BIT_32(23) \| RT_BIT_32(24), 21);
353
354
355	/* B/BL */
356	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64UncondBrImm)
357	DIS_ARMV8_OP(0xfc000000, 0x14000000, "b %J", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
358	DIS_ARMV8_OP(0xfc000000, 0x94000000, "bl %J", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
359	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64UncondBrImm, 0 /fClass/,
360	kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31)
361	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 0, 26),
362	DIS_ARMV8_INSN_PARAM_NONE,
363	DIS_ARMV8_INSN_PARAM_NONE,
364	DIS_ARMV8_INSN_PARAM_NONE
365	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
366
367
368	/* CBZ/CBNZ */
369	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CmpBrImm)
370	DIS_ARMV8_OP(0x7f000000, 0x34000000, "cbz %X, %J", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
371	DIS_ARMV8_OP(0x7f000000, 0x35000000, "cbnz %X, %J", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
372	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CmpBrImm, DISARMV8INSNCLASS_F_SF,
373	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24)
374	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
375	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19),
376	DIS_ARMV8_INSN_PARAM_NONE,
377	DIS_ARMV8_INSN_PARAM_NONE
378	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
379
380
381	/* TBZ/TBNZ */
382	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64TestBrImm)
383	DIS_ARMV8_OP(0x7f000000, 0x36000000, "tbz %X, %I, %J", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
384	DIS_ARMV8_OP(0x7f000000, 0x37000000, "tbnz %X, %I, %J", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS \| DISOPTYPE_CONTROLFLOW),
385	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64TestBrImm, DISARMV8INSNCLASS_F_SF,
386	kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24)
387	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5),
388	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 19, 5),
389	DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 14),
390	DIS_ARMV8_INSN_PARAM_NONE
391	DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END;
392
393
394	DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(g_ArmV8A64BrExcpSys)
395	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30), g_ArmV8A64CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */
396	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) \| RT_BIT_32(28) \| RT_BIT_32(30) \| RT_BIT_32(31), g_ArmV8A64Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */
397	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, g_ArmV8A64SysReg), /* op0: 110, op1: 01000000110001, op2: -. */
398	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, g_ArmV8A64Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */
399	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, g_ArmV8A64DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */
400	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, g_ArmV8A64PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */
401	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, g_ArmV8A64SysResult), /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */
402	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5080000, g_ArmV8A64Sys), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
403	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff80000, 0xd5280000, g_ArmV8A64SysL), /* op0: 110, op1: 0100x01xxxxxxx, op2: - (we include the L field of the next stage here to differentiate between SYS/SYSL as they have a different string representation). */
404	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5100000, g_ArmV8A64Msr), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
405	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff00000, 0xd5300000, g_ArmV8A64Mrs), /* op0: 110, op1: 0100x1xxxxxxxx, op2: - (we include the L field of the next stage here to differentiate between MSR/MRS as they have a different string representation). */
406	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe1f0000, 0xd61f0000, g_ArmV8A64UncondBrReg), /* op0: 110, op1: 1xxxxxxxxxxxxx, op2: - (we include the op2 field from the next stage here as it should be always 11111). */
407	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7c000000, 0x14000000, g_ArmV8A64UncondBrImm), /* op0: x00, op1: xxxxxxxxxxxxxx, op2: -. */
408	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x34000000, g_ArmV8A64CmpBrImm), /* op0: x01, op1: 0xxxxxxxxxxxxx, op2: -. */
409	DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0x7e000000, 0x36000000, g_ArmV8A64TestBrImm), /* op0: x01, op1: 1xxxxxxxxxxxxx, op2: -. */
410	DIS_ARMV8_DECODE_TBL_DEFINE_END(g_ArmV8A64BrExcpSys);
411
412
413	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64LogicalAddSubReg)
414	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Logical (shifted register) */
415	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Add/subtract (shifted/extended register) */
416	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64LogicalAddSubReg, RT_BIT_32(24), 24);
417
418
419	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DataProcReg)
420	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,
421	DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DataProcReg, RT_BIT_32(24), 24);
422
423
424	/*
425	* C4.1 of the ARMv8 architecture reference manual has the following table for the
426	* topmost decoding level (Level 0 in our terms), x means don't care:
427	*
428	* Bit 28 27 26 25
429	* +-------------------------------------------
430	* 0 0 0 0 Reserved or SME encoding (depends on bit 31).
431	* 0 0 0 1 UNALLOC
432	* 0 0 1 0 SVE encodings
433	* 0 0 1 1 UNALLOC
434	* 1 0 0 x Data processing immediate
435	* 1 0 1 x Branch, exception generation and system instructions
436	* x 1 x 0 Loads and stores
437	* x 1 0 1 Data processing - register
438	* x 1 1 1 Data processing - SIMD and floating point
439	*
440	* In order to save us some fiddling with the don't care bits we blow up the lookup table
441	* which gives us 16 possible values (4 bits) we can use as an index into the decoder
442	* lookup table for the next level:
443	* Bit 28 27 26 25
444	* +-------------------------------------------
445	* 0 0 0 0 0 Reserved or SME encoding (depends on bit 31).
446	* 1 0 0 0 1 UNALLOC
447	* 2 0 0 1 0 SVE encodings
448	* 3 0 0 1 1 UNALLOC
449	* 4 0 1 0 0 Loads and stores
450	* 5 0 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
451	* 6 0 1 1 0 Loads and stores
452	* 7 0 1 1 1 Data processing - SIMD and floating point
453	* 8 1 0 0 0 Data processing immediate
454	* 9 1 0 0 1 Data processing immediate
455	* 10 1 0 1 0 Branch, exception generation and system instructions
456	* 11 1 0 1 1 Branch, exception generation and system instructions
457	* 12 1 1 0 0 Loads and stores
458	* 13 1 1 0 1 Data processing - register (using op1 (bit 28) from the next stage to differentiate further already)
459	* 14 1 1 1 0 Loads and stores
460	* 15 1 1 1 1 Data processing - SIMD and floating point
461	*/
462	DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DecodeL0)
463	DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnRsvd), /* Reserved class or SME encoding (@todo). */
464	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
465	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo SVE */
466	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Unallocated */
467	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */
468	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64LogicalAddSubReg), /* Data processing (register) (see op1 in C4.1.68). */
469	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores */
470	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Data processing (SIMD & FP) */
471	DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnDataProcessingImm), /* Data processing (immediate). */
472	DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnDataProcessingImm), /* Data processing (immediate). */
473	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64BrExcpSys), /* Branches / Exception generation and system instructions. */
474	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64BrExcpSys), /* Branches / Exception generation and system instructions. */
475	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores. */
476	DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64DataProcReg), /* Data processing (register) (see op1 in C4.1.68). */
477	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Load/Stores. */
478	DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /* Data processing (SIMD & FP). */
479	DIS_ARMV8_DECODE_MAP_DEFINE_END_NON_STATIC(g_ArmV8A64DecodeL0, RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28), 25);

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source: vbox/trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

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