VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 67981

Last change on this file since 67981 was 65654, checked in by vboxsync, 7 years ago

gcc 7: Disassembler: fall thru
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1/* $Id: DisasmFormatYasm.cpp 65654 2017-02-07 11:56:47Z vboxsync $ */
2/** @file
3 * VBox Disassembler - Yasm(/Nasm) Style Formatter.
4 */
5
6/*
7 * Copyright (C) 2008-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include <VBox/dis.h>
23#include "DisasmInternal.h"
24#include <iprt/string.h>
25#include <iprt/assert.h>
26#include <iprt/ctype.h>
27
28
29/*********************************************************************************************************************************
30* Global Variables *
31*********************************************************************************************************************************/
32static const char g_szSpaces[] =
33" ";
34static const char g_aszYasmRegGen8[20][5] =
35{
36 "al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37};
38static const char g_aszYasmRegGen16[16][5] =
39{
40 "ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41};
42#if 0 /* unused */
43static const char g_aszYasmRegGen1616[8][6] =
44{
45 "bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
46};
47#endif
48static const char g_aszYasmRegGen32[16][5] =
49{
50 "eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
51};
52static const char g_aszYasmRegGen64[16][4] =
53{
54 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
55};
56static const char g_aszYasmRegSeg[6][3] =
57{
58 "es", "cs", "ss", "ds", "fs", "gs"
59};
60static const char g_aszYasmRegFP[8][4] =
61{
62 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
63};
64static const char g_aszYasmRegMMX[8][4] =
65{
66 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
67};
68static const char g_aszYasmRegXMM[16][6] =
69{
70 "xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
71};
72static const char g_aszYasmRegYMM[16][6] =
73{
74 "ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
75};
76static const char g_aszYasmRegCRx[16][5] =
77{
78 "cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
79};
80static const char g_aszYasmRegDRx[16][5] =
81{
82 "dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
83};
84static const char g_aszYasmRegTRx[16][5] =
85{
86 "tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
87};
88
89
90
91/**
92 * Gets the base register name for the given parameter.
93 *
94 * @returns Pointer to the register name.
95 * @param pDis The disassembler state.
96 * @param pParam The parameter.
97 * @param pcchReg Where to store the length of the name.
98 */
99static const char *disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
100{
101 RT_NOREF_PV(pDis);
102
103 switch (pParam->fUse & ( DISUSE_REG_GEN8 | DISUSE_REG_GEN16 | DISUSE_REG_GEN32 | DISUSE_REG_GEN64
104 | DISUSE_REG_FP | DISUSE_REG_MMX | DISUSE_REG_XMM | DISUSE_REG_YMM
105 | DISUSE_REG_CR | DISUSE_REG_DBG | DISUSE_REG_SEG | DISUSE_REG_TEST))
106
107 {
108 case DISUSE_REG_GEN8:
109 {
110 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
111 const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
112 *pcchReg = 2 + !!psz[2] + !!psz[3];
113 return psz;
114 }
115
116 case DISUSE_REG_GEN16:
117 {
118 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
119 const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
120 *pcchReg = 2 + !!psz[2] + !!psz[3];
121 return psz;
122 }
123
124 // VSIB
125 case DISUSE_REG_XMM | DISUSE_REG_GEN32:
126 case DISUSE_REG_YMM | DISUSE_REG_GEN32:
127 case DISUSE_REG_GEN32:
128 {
129 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
130 const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
131 *pcchReg = 2 + !!psz[2] + !!psz[3];
132 return psz;
133 }
134
135 // VSIB
136 case DISUSE_REG_XMM | DISUSE_REG_GEN64:
137 case DISUSE_REG_YMM | DISUSE_REG_GEN64:
138 case DISUSE_REG_GEN64:
139 {
140 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
141 const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
142 *pcchReg = 2 + !!psz[2] + !!psz[3];
143 return psz;
144 }
145
146 case DISUSE_REG_FP:
147 {
148 Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
149 const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
150 *pcchReg = 3;
151 return psz;
152 }
153
154 case DISUSE_REG_MMX:
155 {
156 Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
157 const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
158 *pcchReg = 3;
159 return psz;
160 }
161
162 case DISUSE_REG_XMM:
163 {
164 Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
165 const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
166 *pcchReg = 4 + !!psz[4];
167 return psz;
168 }
169
170 case DISUSE_REG_YMM:
171 {
172 Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
173 const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
174 *pcchReg = 4 + !!psz[4];
175 return psz;
176 }
177
178 case DISUSE_REG_CR:
179 {
180 Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
181 const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
182 *pcchReg = 3;
183 return psz;
184 }
185
186 case DISUSE_REG_DBG:
187 {
188 Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
189 const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
190 *pcchReg = 3;
191 return psz;
192 }
193
194 case DISUSE_REG_SEG:
195 {
196 Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
197 const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
198 *pcchReg = 2;
199 return psz;
200 }
201
202 case DISUSE_REG_TEST:
203 {
204 Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
205 const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
206 *pcchReg = 3;
207 return psz;
208 }
209
210 default:
211 AssertMsgFailed(("%#x\n", pParam->fUse));
212 *pcchReg = 3;
213 return "r??";
214 }
215}
216
217
218/**
219 * Gets the index register name for the given parameter.
220 *
221 * @returns The index register name.
222 * @param pDis The disassembler state.
223 * @param pParam The parameter.
224 * @param pcchReg Where to store the length of the name.
225 */
226static const char *disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
227{
228 if (pParam->fUse & DISUSE_REG_XMM)
229 {
230 Assert(pParam->Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
231 const char *psz = g_aszYasmRegXMM[pParam->Index.idxXmmReg];
232 *pcchReg = 4 + !!psz[4];
233 return psz;
234 }
235 else if (pParam->fUse & DISUSE_REG_YMM)
236 {
237 Assert(pParam->Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
238 const char *psz = g_aszYasmRegYMM[pParam->Index.idxYmmReg];
239 *pcchReg = 4 + !!psz[4];
240 return psz;
241
242 }
243 else
244 switch (pDis->uAddrMode)
245 {
246 case DISCPUMODE_16BIT:
247 {
248 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
249 const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
250 *pcchReg = 2 + !!psz[2] + !!psz[3];
251 return psz;
252 }
253
254 case DISCPUMODE_32BIT:
255 {
256 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
257 const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
258 *pcchReg = 2 + !!psz[2] + !!psz[3];
259 return psz;
260 }
261
262 case DISCPUMODE_64BIT:
263 {
264 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
265 const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
266 *pcchReg = 2 + !!psz[2] + !!psz[3];
267 return psz;
268 }
269
270 default:
271 AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
272 *pcchReg = 3;
273 return "r??";
274 }
275}
276
277
278/**
279 * Formats the current instruction in Yasm (/ Nasm) style.
280 *
281 *
282 * @returns The number of output characters. If this is >= cchBuf, then the content
283 * of pszBuf will be truncated.
284 * @param pDis Pointer to the disassembler state.
285 * @param pszBuf The output buffer.
286 * @param cchBuf The size of the output buffer.
287 * @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
288 * @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
289 * @param pvUser User argument for pfnGetSymbol.
290 */
291DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
292 PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
293{
294/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
295 /*
296 * Input validation and massaging.
297 */
298 AssertPtr(pDis);
299 AssertPtrNull(pszBuf);
300 Assert(pszBuf || !cchBuf);
301 AssertPtrNull(pfnGetSymbol);
302 AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
303 if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
304 fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) | DIS_FMT_FLAGS_ADDR_RIGHT;
305 if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
306 fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) | DIS_FMT_FLAGS_BYTES_RIGHT;
307
308 PCDISOPCODE const pOp = pDis->pCurInstr;
309
310 /*
311 * Output macros
312 */
313 char *pszDst = pszBuf;
314 size_t cchDst = cchBuf;
315 size_t cchOutput = 0;
316#define PUT_C(ch) \
317 do { \
318 cchOutput++; \
319 if (cchDst > 1) \
320 { \
321 cchDst--; \
322 *pszDst++ = (ch); \
323 } \
324 } while (0)
325#define PUT_STR(pszSrc, cchSrc) \
326 do { \
327 cchOutput += (cchSrc); \
328 if (cchDst > (cchSrc)) \
329 { \
330 memcpy(pszDst, (pszSrc), (cchSrc)); \
331 pszDst += (cchSrc); \
332 cchDst -= (cchSrc); \
333 } \
334 else if (cchDst > 1) \
335 { \
336 memcpy(pszDst, (pszSrc), cchDst - 1); \
337 pszDst += cchDst - 1; \
338 cchDst = 1; \
339 } \
340 } while (0)
341#define PUT_SZ(sz) \
342 PUT_STR((sz), sizeof(sz) - 1)
343#define PUT_SZ_STRICT(szStrict, szRelaxed) \
344 do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
345#define PUT_PSZ(psz) \
346 do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
347#define PUT_NUM(cch, fmt, num) \
348 do { \
349 cchOutput += (cch); \
350 if (cchDst > 1) \
351 { \
352 const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
353 pszDst += cchTmp; \
354 cchDst -= cchTmp; \
355 Assert(cchTmp == (cch) || cchDst == 1); \
356 } \
357 } while (0)
358/** @todo add two flags for choosing between %X / %x and h / 0x. */
359#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
360#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
361#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
362#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
363
364#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
365 do { \
366 if ((stype)(num) >= 0) \
367 { \
368 PUT_C('+'); \
369 PUT_NUM(cch, fmt, (utype)(num)); \
370 } \
371 else \
372 { \
373 PUT_C('-'); \
374 PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
375 } \
376 } while (0)
377#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
378#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
379#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
380#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
381
382#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
383 do { \
384 if (RT_SUCCESS(a_rcSym)) \
385 { \
386 PUT_SZ(a_szStart); \
387 PUT_PSZ(szSymbol); \
388 if (off != 0) \
389 { \
390 if ((int8_t)off == off) \
391 PUT_NUM_S8(off); \
392 else if ((int16_t)off == off) \
393 PUT_NUM_S16(off); \
394 else if ((int32_t)off == off) \
395 PUT_NUM_S32(off); \
396 else \
397 PUT_NUM_S64(off); \
398 } \
399 PUT_C(a_chEnd); \
400 } \
401 } while (0)
402
403#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
404 do { \
405 if (pfnGetSymbol) \
406 { \
407 int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
408 PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
409 } \
410 } while (0)
411
412
413 /*
414 * The address?
415 */
416 if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
417 {
418#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
419 if (pDis->uInstrAddr >= _4G)
420 PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
421#endif
422 PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
423 PUT_C(' ');
424 }
425
426 /*
427 * The opcode bytes?
428 */
429 if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
430 {
431 size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
432 cchOutput += cchTmp;
433 if (cchDst > 1)
434 {
435 if (cchTmp <= cchDst)
436 {
437 cchDst -= cchTmp;
438 pszDst += cchTmp;
439 }
440 else
441 {
442 pszDst += cchDst - 1;
443 cchDst = 1;
444 }
445 }
446
447 /* Some padding to align the instruction. */
448 size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
449 + !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
450 + 2;
451 cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
452 PUT_STR(g_szSpaces, cchPadding);
453 }
454
455
456 /*
457 * Filter out invalid opcodes first as they need special
458 * treatment. UD2 is an exception and should be handled normally.
459 */
460 size_t const offInstruction = cchOutput;
461 if ( pOp->uOpcode == OP_INVALID
462 || ( pOp->uOpcode == OP_ILLUD2
463 && (pDis->fPrefix & DISPREFIX_LOCK)))
464 PUT_SZ("Illegal opcode");
465 else
466 {
467 /*
468 * Prefixes
469 */
470 if (pDis->fPrefix & DISPREFIX_LOCK)
471 PUT_SZ("lock ");
472 if (pDis->fPrefix & DISPREFIX_REP)
473 PUT_SZ("rep ");
474 else if(pDis->fPrefix & DISPREFIX_REPNE)
475 PUT_SZ("repne ");
476
477 /*
478 * Adjust the format string to the correct mnemonic
479 * or to avoid things the assembler cannot handle correctly.
480 */
481 char szTmpFmt[48];
482 const char *pszFmt = pOp->pszOpcode;
483 bool fIgnoresOpSize = false;
484 bool fMayNeedAddrSize = false;
485 switch (pOp->uOpcode)
486 {
487 case OP_JECXZ:
488 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
489 break;
490 case OP_PUSHF:
491 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
492 break;
493 case OP_POPF:
494 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
495 break;
496 case OP_PUSHA:
497 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
498 break;
499 case OP_POPA:
500 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
501 break;
502 case OP_INSB:
503 pszFmt = "insb";
504 fIgnoresOpSize = fMayNeedAddrSize = true;
505 break;
506 case OP_INSWD:
507 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
508 fMayNeedAddrSize = true;
509 break;
510 case OP_OUTSB:
511 pszFmt = "outsb";
512 fIgnoresOpSize = fMayNeedAddrSize = true;
513 break;
514 case OP_OUTSWD:
515 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
516 fMayNeedAddrSize = true;
517 break;
518 case OP_MOVSB:
519 pszFmt = "movsb";
520 fIgnoresOpSize = fMayNeedAddrSize = true;
521 break;
522 case OP_MOVSWD:
523 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
524 fMayNeedAddrSize = true;
525 break;
526 case OP_CMPSB:
527 pszFmt = "cmpsb";
528 fIgnoresOpSize = fMayNeedAddrSize = true;
529 break;
530 case OP_CMPWD:
531 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
532 fMayNeedAddrSize = true;
533 break;
534 case OP_SCASB:
535 pszFmt = "scasb";
536 fIgnoresOpSize = fMayNeedAddrSize = true;
537 break;
538 case OP_SCASWD:
539 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
540 fMayNeedAddrSize = true;
541 break;
542 case OP_LODSB:
543 pszFmt = "lodsb";
544 fIgnoresOpSize = fMayNeedAddrSize = true;
545 break;
546 case OP_LODSWD:
547 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
548 fMayNeedAddrSize = true;
549 break;
550 case OP_STOSB:
551 pszFmt = "stosb";
552 fIgnoresOpSize = fMayNeedAddrSize = true;
553 break;
554 case OP_STOSWD:
555 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
556 fMayNeedAddrSize = true;
557 break;
558 case OP_CBW:
559 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
560 break;
561 case OP_CWD:
562 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
563 break;
564 case OP_SHL:
565 Assert(pszFmt[3] == '/');
566 pszFmt += 4;
567 break;
568 case OP_XLAT:
569 pszFmt = "xlatb";
570 break;
571 case OP_INT3:
572 pszFmt = "int3";
573 break;
574
575 /*
576 * Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
577 */
578 case OP_NOP:
579 if (pDis->bOpCode == 0x90)
580 /* fine, fine */;
581 else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
582 pszFmt = "prefetch %Eb";
583 else if (pDis->bOpCode == 0x1f)
584 {
585 Assert(pDis->cbInstr >= 3);
586 PUT_SZ("db 00fh, 01fh,");
587 PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
588 for (unsigned i = 3; i < pDis->cbInstr; i++)
589 {
590 PUT_C(',');
591 PUT_NUM_8(0x90); /// @todo fixme.
592 }
593 pszFmt = "";
594 }
595 break;
596
597 default:
598 /* ST(X) -> stX (floating point) */
599 if (*pszFmt == 'f' && strchr(pszFmt, '('))
600 {
601 char *pszFmtDst = szTmpFmt;
602 char ch;
603 do
604 {
605 ch = *pszFmt++;
606 if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
607 {
608 *pszFmtDst++ = 's';
609 *pszFmtDst++ = 't';
610 pszFmt += 2;
611 ch = *pszFmt;
612 Assert(pszFmt[1] == ')');
613 pszFmt += 2;
614 *pszFmtDst++ = ch;
615 }
616 else
617 *pszFmtDst++ = ch;
618 } while (ch != '\0');
619 pszFmt = szTmpFmt;
620 }
621 if (strchr ("#@&", *pszFmt))
622 {
623 const char *pszDelim = strchr(pszFmt, '/');
624 const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
625 if (pszDelim != NULL)
626 {
627 char *pszFmtDst = szTmpFmt;
628 if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
629 if ( (*pszFmt == '#' && pDis->bVexWFlag)
630 || (*pszFmt == '@' && !VEXREG_IS256B(pDis->bVexDestReg))
631 || (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
632 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
633 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
634 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
635 {
636 strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
637 pszFmtDst += pszDelim - pszFmt - 1;
638 }
639 else
640 {
641 strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
642 pszFmtDst += pszSpace - pszDelim - 1;
643 }
644 strcpy (pszFmtDst, pszSpace);
645 pszFmt = szTmpFmt;
646 }
647 }
648 break;
649
650 /*
651 * Horrible hacks.
652 */
653 case OP_FLD:
654 if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
655 *(int *)&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
656 break;
657 case OP_LAR: /* hack w -> v, probably not correct. */
658 *(int *)&pDis->Param2.fParam &= ~0x1f;
659 *(int *)&pDis->Param2.fParam |= OP_PARM_v;
660 break;
661 }
662
663 /*
664 * Add operand size and address prefixes for outsb, movsb, etc.
665 */
666 if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
667 {
668 if (fIgnoresOpSize && (pDis->fPrefix & DISPREFIX_OPSIZE) )
669 {
670 if (pDis->uCpuMode == DISCPUMODE_16BIT)
671 PUT_SZ("o32 ");
672 else
673 PUT_SZ("o16 ");
674 }
675 if (fMayNeedAddrSize && (pDis->fPrefix & DISPREFIX_ADDRSIZE) )
676 {
677 if (pDis->uCpuMode == DISCPUMODE_16BIT)
678 PUT_SZ("a32 ");
679 else
680 PUT_SZ("a16 ");
681 }
682 }
683
684 /*
685 * Formatting context and associated macros.
686 */
687 PCDISOPPARAM pParam = &pDis->Param1;
688 int iParam = 1;
689
690#define PUT_FAR() \
691 do { \
692 if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
693 && pOp->uOpcode != OP_LDS /* table bugs? */ \
694 && pOp->uOpcode != OP_LES \
695 && pOp->uOpcode != OP_LFS \
696 && pOp->uOpcode != OP_LGS \
697 && pOp->uOpcode != OP_LSS ) \
698 PUT_SZ("far "); \
699 } while (0)
700 /** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
701 /** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
702#define PUT_SIZE_OVERRIDE() \
703 do { \
704 switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
705 { \
706 case OP_PARM_v: \
707 case OP_PARM_y: \
708 switch (pDis->uOpMode) \
709 { \
710 case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->fParam) != OP_PARM_y) PUT_SZ("word "); break; \
711 case DISCPUMODE_32BIT: \
712 if (pDis->pCurInstr->uOpcode != OP_GATHER || pDis->bVexWFlag) { PUT_SZ("dword "); break; } \
713 /* fall thru */ \
714 case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
715 default: break; \
716 } \
717 break; \
718 case OP_PARM_b: PUT_SZ("byte "); break; \
719 case OP_PARM_w: \
720 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
721 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
722 { \
723 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("dword "); \
724 else PUT_SZ("word "); \
725 } \
726 break; \
727 case OP_PARM_d: \
728 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
729 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
730 { \
731 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("qword "); \
732 else PUT_SZ("dword "); \
733 } \
734 break; \
735 case OP_PARM_q: \
736 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
737 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
738 { \
739 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("oword "); \
740 else PUT_SZ("qword "); \
741 } \
742 break; \
743 case OP_PARM_ps: \
744 case OP_PARM_pd: \
745 case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword "); break; } /* fall thru */ \
746 case OP_PARM_ss: \
747 case OP_PARM_sd: \
748 case OP_PARM_dq: PUT_SZ("oword "); break; \
749 case OP_PARM_qq: PUT_SZ("yword "); break; \
750 case OP_PARM_p: break; /* see PUT_FAR */ \
751 case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
752 case OP_PARM_z: break; \
753 case OP_PARM_NONE: \
754 if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
755 && ((pParam->fUse & DISUSE_REG_FP) || pOp->uOpcode == OP_FLD)) \
756 PUT_SZ("tword "); \
757 break; \
758 default: break; /*no pointer type specified/necessary*/ \
759 } \
760 } while (0)
761 static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
762#define PUT_SEGMENT_OVERRIDE() \
763 do { \
764 if (pDis->fPrefix & DISPREFIX_SEG) \
765 PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
766 } while (0)
767
768
769 /*
770 * Segment prefixing for instructions that doesn't do memory access.
771 */
772 if ( (pDis->fPrefix & DISPREFIX_SEG)
773 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
774 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
775 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
776 {
777 PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
778 PUT_C(' ');
779 }
780
781
782 /*
783 * The formatting loop.
784 */
785 RTINTPTR off;
786 char szSymbol[128];
787 char ch;
788 while ((ch = *pszFmt++) != '\0')
789 {
790 if (ch == '%')
791 {
792 ch = *pszFmt++;
793 switch (ch)
794 {
795 /*
796 * ModRM - Register only.
797 */
798 case 'C': /* Control register (ParseModRM / UseModRM). */
799 case 'D': /* Debug register (ParseModRM / UseModRM). */
800 case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
801 case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
802 case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
803 case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
804 case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
805 case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
806 case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
807 {
808 pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
809 Assert(!(pParam->fUse & (DISUSE_INDEX | DISUSE_SCALE) /* No SIB here... */));
810 Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)));
811
812 size_t cchReg;
813 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
814 PUT_STR(pszReg, cchReg);
815 break;
816 }
817
818 /*
819 * ModRM - Register or memory.
820 */
821 case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
822 case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
823 case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
824 case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
825 case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
826 {
827 pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
828
829 PUT_FAR();
830 uint32_t const fUse = pParam->fUse;
831 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
832 {
833 /* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
834 while the register variants deals with 16, 32 & 64 in the normal fashion. */
835 if ( pParam->fParam != OP_PARM_Ev
836 || pOp->uOpcode != OP_MOV
837 || ( pOp->fParam1 != OP_PARM_Sw
838 && pOp->fParam2 != OP_PARM_Sw))
839 PUT_SIZE_OVERRIDE();
840 PUT_C('[');
841 }
842 if ( (fFlags & DIS_FMT_FLAGS_STRICT)
843 && (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)))
844 {
845 if ( (fUse & DISUSE_DISPLACEMENT8)
846 && !pParam->uDisp.i8)
847 PUT_SZ("byte ");
848 else if ( (fUse & DISUSE_DISPLACEMENT16)
849 && (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
850 PUT_SZ("word ");
851 else if ( (fUse & DISUSE_DISPLACEMENT32)
852 && (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
853 PUT_SZ("dword ");
854 else if ( (fUse & DISUSE_DISPLACEMENT64)
855 && (pDis->SIB.Bits.Base != 5 || pDis->ModRM.Bits.Mod != 0)
856 && (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
857 PUT_SZ("qword ");
858 }
859 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
860 PUT_SEGMENT_OVERRIDE();
861
862 bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
863 || ( (fUse & ( DISUSE_REG_GEN8
864 | DISUSE_REG_GEN16
865 | DISUSE_REG_GEN32
866 | DISUSE_REG_GEN64
867 | DISUSE_REG_FP
868 | DISUSE_REG_MMX
869 | DISUSE_REG_XMM
870 | DISUSE_REG_YMM
871 | DISUSE_REG_CR
872 | DISUSE_REG_DBG
873 | DISUSE_REG_SEG
874 | DISUSE_REG_TEST ))
875 && !DISUSE_IS_EFFECTIVE_ADDR(fUse));
876 if (fBase)
877 {
878 size_t cchReg;
879 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
880 PUT_STR(pszReg, cchReg);
881 }
882
883 if (fUse & DISUSE_INDEX)
884 {
885 if (fBase)
886 PUT_C('+');
887
888 size_t cchReg;
889 const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
890 PUT_STR(pszReg, cchReg);
891
892 if (fUse & DISUSE_SCALE)
893 {
894 PUT_C('*');
895 PUT_C('0' + pParam->uScale);
896 }
897 }
898 else
899 Assert(!(fUse & DISUSE_SCALE));
900
901 int64_t off2 = 0;
902 if (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))
903 {
904 if (fUse & DISUSE_DISPLACEMENT8)
905 off2 = pParam->uDisp.i8;
906 else if (fUse & DISUSE_DISPLACEMENT16)
907 off2 = pParam->uDisp.i16;
908 else if (fUse & (DISUSE_DISPLACEMENT32 | DISUSE_RIPDISPLACEMENT32))
909 off2 = pParam->uDisp.i32;
910 else if (fUse & DISUSE_DISPLACEMENT64)
911 off2 = pParam->uDisp.i64;
912 else
913 {
914 AssertFailed();
915 off2 = 0;
916 }
917
918 int64_t off3 = off2;
919 if (fBase || (fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)))
920 {
921 PUT_C(off3 >= 0 ? '+' : '-');
922 if (off3 < 0)
923 off3 = -off3;
924 }
925 if (fUse & DISUSE_DISPLACEMENT8)
926 PUT_NUM_8( off3);
927 else if (fUse & DISUSE_DISPLACEMENT16)
928 PUT_NUM_16(off3);
929 else if (fUse & DISUSE_DISPLACEMENT32)
930 PUT_NUM_32(off3);
931 else if (fUse & DISUSE_DISPLACEMENT64)
932 PUT_NUM_64(off3);
933 else
934 {
935 PUT_NUM_32(off3);
936 PUT_SZ(" wrt rip (");
937 off2 += pDis->uInstrAddr + pDis->cbInstr;
938 PUT_NUM_64(off2);
939 if (pfnGetSymbol)
940 PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
941 ? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
942 : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
943 pDis->uAddrMode == DISCPUMODE_64BIT
944 ? (uint64_t)off2
945 : pDis->uAddrMode == DISCPUMODE_32BIT
946 ? (uint32_t)off2
947 : (uint16_t)off2,
948 " = ",
949 ')');
950 else
951 PUT_C(')');
952 }
953 }
954
955 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
956 {
957 if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
958 PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
959 ? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
960 : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
961 pDis->uAddrMode == DISCPUMODE_64BIT
962 ? (uint64_t)off2
963 : pDis->uAddrMode == DISCPUMODE_32BIT
964 ? (uint32_t)off2
965 : (uint16_t)off2,
966 " (=",
967 ')');
968 PUT_C(']');
969 }
970 break;
971 }
972
973 case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
974 AssertFailed();
975 break;
976
977 case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
978 Assert(*pszFmt == 'b' || *pszFmt == 'v' || *pszFmt == 'w' || *pszFmt == 'z'); pszFmt++;
979 switch (pParam->fUse & ( DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64
980 | DISUSE_IMMEDIATE16_SX8 | DISUSE_IMMEDIATE32_SX8 | DISUSE_IMMEDIATE64_SX8))
981 {
982 case DISUSE_IMMEDIATE8:
983 if ( (fFlags & DIS_FMT_FLAGS_STRICT)
984 && ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
985 || (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
986 )
987 PUT_SZ("strict byte ");
988 PUT_NUM_8(pParam->uValue);
989 break;
990
991 case DISUSE_IMMEDIATE16:
992 if ( pDis->uCpuMode != pDis->uOpMode
993 || ( (fFlags & DIS_FMT_FLAGS_STRICT)
994 && ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
995 || (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
996 || (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
997 )
998 )
999 {
1000 if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1001 PUT_SZ_STRICT("strict byte ", "byte ");
1002 else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1003 || OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1004 PUT_SZ_STRICT("strict word ", "word ");
1005 }
1006 PUT_NUM_16(pParam->uValue);
1007 break;
1008
1009 case DISUSE_IMMEDIATE16_SX8:
1010 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1011 || pDis->pCurInstr->uOpcode != OP_PUSH)
1012 PUT_SZ_STRICT("strict byte ", "byte ");
1013 else
1014 PUT_SZ("word ");
1015 PUT_NUM_16(pParam->uValue);
1016 break;
1017
1018 case DISUSE_IMMEDIATE32:
1019 if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1020 || ( (fFlags & DIS_FMT_FLAGS_STRICT)
1021 && ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1022 || (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1023 || (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1024 )
1025 )
1026 {
1027 if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1028 PUT_SZ_STRICT("strict byte ", "byte ");
1029 else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1030 || OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1031 PUT_SZ_STRICT("strict dword ", "dword ");
1032 }
1033 PUT_NUM_32(pParam->uValue);
1034 if (pDis->uCpuMode == DISCPUMODE_32BIT)
1035 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1036 break;
1037
1038 case DISUSE_IMMEDIATE32_SX8:
1039 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1040 || pDis->pCurInstr->uOpcode != OP_PUSH)
1041 PUT_SZ_STRICT("strict byte ", "byte ");
1042 else
1043 PUT_SZ("dword ");
1044 PUT_NUM_32(pParam->uValue);
1045 break;
1046
1047 case DISUSE_IMMEDIATE64_SX8:
1048 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1049 || pDis->pCurInstr->uOpcode != OP_PUSH)
1050 PUT_SZ_STRICT("strict byte ", "byte ");
1051 else
1052 PUT_SZ("qword ");
1053 PUT_NUM_64(pParam->uValue);
1054 break;
1055
1056 case DISUSE_IMMEDIATE64:
1057 PUT_NUM_64(pParam->uValue);
1058 break;
1059
1060 default:
1061 AssertFailed();
1062 break;
1063 }
1064 break;
1065
1066 case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1067 {
1068 int32_t offDisplacement;
1069 Assert(iParam == 1);
1070 bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1071 && pOp->uOpcode != OP_CALL
1072 && pOp->uOpcode != OP_LOOP
1073 && pOp->uOpcode != OP_LOOPE
1074 && pOp->uOpcode != OP_LOOPNE
1075 && pOp->uOpcode != OP_JECXZ;
1076 if (pOp->uOpcode == OP_CALL)
1077 fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1078
1079 if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1080 {
1081 if (fPrefix)
1082 PUT_SZ("short ");
1083 offDisplacement = (int8_t)pParam->uValue;
1084 Assert(*pszFmt == 'b'); pszFmt++;
1085
1086 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1087 PUT_NUM_S8(offDisplacement);
1088 }
1089 else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1090 {
1091 if (fPrefix)
1092 PUT_SZ("near ");
1093 offDisplacement = (int16_t)pParam->uValue;
1094 Assert(*pszFmt == 'v'); pszFmt++;
1095
1096 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1097 PUT_NUM_S16(offDisplacement);
1098 }
1099 else
1100 {
1101 if (fPrefix)
1102 PUT_SZ("near ");
1103 offDisplacement = (int32_t)pParam->uValue;
1104 Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL | DISUSE_IMMEDIATE64_REL));
1105 Assert(*pszFmt == 'v'); pszFmt++;
1106
1107 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1108 PUT_NUM_S32(offDisplacement);
1109 }
1110 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1111 PUT_SZ(" (");
1112
1113 RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1114 if (pDis->uCpuMode == DISCPUMODE_16BIT)
1115 PUT_NUM_16(uTrgAddr);
1116 else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1117 PUT_NUM_32(uTrgAddr);
1118 else
1119 PUT_NUM_64(uTrgAddr);
1120
1121 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1122 {
1123 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1124 PUT_C(')');
1125 }
1126 else
1127 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1128 break;
1129 }
1130
1131 case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1132 {
1133 Assert(*pszFmt == 'p'); pszFmt++;
1134 PUT_FAR();
1135 PUT_SIZE_OVERRIDE();
1136 PUT_SEGMENT_OVERRIDE();
1137 off = 0;
1138 int rc = VERR_SYMBOL_NOT_FOUND;
1139 switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1140 {
1141 case DISUSE_IMMEDIATE_ADDR_16_16:
1142 PUT_NUM_16(pParam->uValue >> 16);
1143 PUT_C(':');
1144 PUT_NUM_16(pParam->uValue);
1145 if (pfnGetSymbol)
1146 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1147 break;
1148 case DISUSE_IMMEDIATE_ADDR_16_32:
1149 PUT_NUM_16(pParam->uValue >> 32);
1150 PUT_C(':');
1151 PUT_NUM_32(pParam->uValue);
1152 if (pfnGetSymbol)
1153 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1154 break;
1155 case DISUSE_DISPLACEMENT16:
1156 PUT_NUM_16(pParam->uValue);
1157 if (pfnGetSymbol)
1158 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1159 break;
1160 case DISUSE_DISPLACEMENT32:
1161 PUT_NUM_32(pParam->uValue);
1162 if (pfnGetSymbol)
1163 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1164 break;
1165 case DISUSE_DISPLACEMENT64:
1166 PUT_NUM_64(pParam->uValue);
1167 if (pfnGetSymbol)
1168 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1169 break;
1170 default:
1171 AssertFailed();
1172 break;
1173 }
1174
1175 PUT_SYMBOL_TWO(rc, " [", ']');
1176 break;
1177 }
1178
1179 case 'O': /* No ModRM byte (ParseImmAddr). */
1180 {
1181 Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
1182 PUT_FAR();
1183 PUT_SIZE_OVERRIDE();
1184 PUT_C('[');
1185 PUT_SEGMENT_OVERRIDE();
1186 off = 0;
1187 int rc = VERR_SYMBOL_NOT_FOUND;
1188 switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1189 {
1190 case DISUSE_IMMEDIATE_ADDR_16_16:
1191 PUT_NUM_16(pParam->uValue >> 16);
1192 PUT_C(':');
1193 PUT_NUM_16(pParam->uValue);
1194 if (pfnGetSymbol)
1195 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1196 break;
1197 case DISUSE_IMMEDIATE_ADDR_16_32:
1198 PUT_NUM_16(pParam->uValue >> 32);
1199 PUT_C(':');
1200 PUT_NUM_32(pParam->uValue);
1201 if (pfnGetSymbol)
1202 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1203 break;
1204 case DISUSE_DISPLACEMENT16:
1205 PUT_NUM_16(pParam->uDisp.i16);
1206 if (pfnGetSymbol)
1207 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1208 break;
1209 case DISUSE_DISPLACEMENT32:
1210 PUT_NUM_32(pParam->uDisp.i32);
1211 if (pfnGetSymbol)
1212 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1213 break;
1214 case DISUSE_DISPLACEMENT64:
1215 PUT_NUM_64(pParam->uDisp.i64);
1216 if (pfnGetSymbol)
1217 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1218 break;
1219 default:
1220 AssertFailed();
1221 break;
1222 }
1223 PUT_C(']');
1224
1225 PUT_SYMBOL_TWO(rc, " (", ')');
1226 break;
1227 }
1228
1229 case 'X': /* DS:SI (ParseXb, ParseXv). */
1230 case 'Y': /* ES:DI (ParseYb, ParseYv). */
1231 {
1232 Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
1233 PUT_FAR();
1234 PUT_SIZE_OVERRIDE();
1235 PUT_C('[');
1236 if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1237 PUT_SZ("ds:");
1238 else
1239 PUT_SZ("es:");
1240
1241 size_t cchReg;
1242 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1243 PUT_STR(pszReg, cchReg);
1244 PUT_C(']');
1245 break;
1246 }
1247
1248 case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1249 {
1250 Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1251 pszFmt += 2;
1252 size_t cchReg;
1253 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1254 PUT_STR(pszReg, cchReg);
1255 break;
1256 }
1257
1258 default:
1259 AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1260 break;
1261 }
1262 AssertMsg(*pszFmt == ',' || *pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1263 }
1264 else
1265 {
1266 PUT_C(ch);
1267 if (ch == ',')
1268 {
1269 Assert(*pszFmt != ' ');
1270 PUT_C(' ');
1271 switch (++iParam)
1272 {
1273 case 2: pParam = &pDis->Param2; break;
1274 case 3: pParam = &pDis->Param3; break;
1275 case 4: pParam = &pDis->Param4; break;
1276 default: pParam = NULL; break;
1277 }
1278 }
1279 }
1280 } /* while more to format */
1281 }
1282
1283 /*
1284 * Any additional output to the right of the instruction?
1285 */
1286 if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
1287 {
1288 /* some up front padding. */
1289 size_t cchPadding = cchOutput - offInstruction;
1290 cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1291 PUT_STR(g_szSpaces, cchPadding);
1292
1293 /* comment? */
1294 if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
1295 PUT_SZ(";");
1296
1297 /*
1298 * The address?
1299 */
1300 if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1301 {
1302 PUT_C(' ');
1303#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1304 if (pDis->uInstrAddr >= _4G)
1305 PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1306#endif
1307 PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1308 }
1309
1310 /*
1311 * Opcode bytes?
1312 */
1313 if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1314 {
1315 PUT_C(' ');
1316 size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1317 cchOutput += cchTmp;
1318 if (cchTmp >= cchDst)
1319 cchTmp = cchDst - (cchDst != 0);
1320 cchDst -= cchTmp;
1321 pszDst += cchTmp;
1322 }
1323 }
1324
1325 /*
1326 * Terminate it - on overflow we'll have reserved one byte for this.
1327 */
1328 if (cchDst > 0)
1329 *pszDst = '\0';
1330 else
1331 Assert(!cchBuf);
1332
1333 /* clean up macros */
1334#undef PUT_PSZ
1335#undef PUT_SZ
1336#undef PUT_STR
1337#undef PUT_C
1338 return cchOutput;
1339}
1340
1341
1342/**
1343 * Formats the current instruction in Yasm (/ Nasm) style.
1344 *
1345 * This is a simplified version of DISFormatYasmEx() provided for your convenience.
1346 *
1347 *
1348 * @returns The number of output characters. If this is >= cchBuf, then the content
1349 * of pszBuf will be truncated.
1350 * @param pDis Pointer to the disassembler state.
1351 * @param pszBuf The output buffer.
1352 * @param cchBuf The size of the output buffer.
1353 */
1354DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1355{
1356 return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags */, NULL /* pfnGetSymbol */, NULL /* pvUser */);
1357}
1358
1359
1360/**
1361 * Checks if the encoding of the given disassembled instruction is something we
1362 * can never get YASM to produce.
1363 *
1364 * @returns true if it's odd, false if it isn't.
1365 * @param pDis The disassembler output. The byte fetcher callback will
1366 * be used if present as we might need to fetch opcode
1367 * bytes.
1368 */
1369DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1370{
1371 /*
1372 * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1373 */
1374 if ( pDis->uAddrMode != DISCPUMODE_16BIT /// @todo correct?
1375 && pDis->ModRM.Bits.Rm == 4
1376 && pDis->ModRM.Bits.Mod != 3)
1377 {
1378 /* No scaled index SIB (index=4), except for ESP. */
1379 if ( pDis->SIB.Bits.Index == 4
1380 && pDis->SIB.Bits.Base != 4)
1381 return true;
1382
1383 /* EBP + displacement */
1384 if ( pDis->ModRM.Bits.Mod != 0
1385 && pDis->SIB.Bits.Base == 5
1386 && pDis->SIB.Bits.Scale == 0)
1387 return true;
1388 }
1389
1390 /*
1391 * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1392 */
1393 if ( pDis->pCurInstr->uOpcode == OP_SHL
1394 && pDis->ModRM.Bits.Reg == 6)
1395 return true;
1396
1397 /*
1398 * Check for multiple prefixes of the same kind.
1399 */
1400 uint8_t off1stSeg = UINT8_MAX;
1401 uint8_t offOpSize = UINT8_MAX;
1402 uint8_t offAddrSize = UINT8_MAX;
1403 uint32_t fPrefixes = 0;
1404 for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1405 {
1406 uint32_t f;
1407 switch (pDis->abInstr[offOpcode])
1408 {
1409 case 0xf0:
1410 f = DISPREFIX_LOCK;
1411 break;
1412
1413 case 0xf2:
1414 case 0xf3:
1415 f = DISPREFIX_REP; /* yes, both */
1416 break;
1417
1418 case 0x2e:
1419 case 0x3e:
1420 case 0x26:
1421 case 0x36:
1422 case 0x64:
1423 case 0x65:
1424 if (off1stSeg == UINT8_MAX)
1425 off1stSeg = offOpcode;
1426 f = DISPREFIX_SEG;
1427 break;
1428
1429 case 0x66:
1430 if (offOpSize == UINT8_MAX)
1431 offOpSize = offOpcode;
1432 f = DISPREFIX_OPSIZE;
1433 break;
1434
1435 case 0x67:
1436 if (offAddrSize == UINT8_MAX)
1437 offAddrSize = offOpcode;
1438 f = DISPREFIX_ADDRSIZE;
1439 break;
1440
1441 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1442 case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1443 f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1444 break;
1445
1446 default:
1447 f = 0;
1448 break;
1449 }
1450 if (!f)
1451 break; /* done */
1452 if (fPrefixes & f)
1453 return true;
1454 fPrefixes |= f;
1455 }
1456
1457 /* segment overrides are fun */
1458 if (fPrefixes & DISPREFIX_SEG)
1459 {
1460 /* no effective address which it may apply to. */
1461 Assert((pDis->fPrefix & DISPREFIX_SEG) || pDis->uCpuMode == DISCPUMODE_64BIT);
1462 if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1463 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1464 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1465 return true;
1466
1467 /* Yasm puts the segment prefixes before the operand prefix with no
1468 way of overriding it. */
1469 if (offOpSize < off1stSeg)
1470 return true;
1471 }
1472
1473 /* fixed register + addr override doesn't go down all that well. */
1474 if (fPrefixes & DISPREFIX_ADDRSIZE)
1475 {
1476 Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1477 if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1478 && pDis->pCurInstr->fParam2 == OP_PARM_NONE
1479 && ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1480 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1481 return true;
1482 }
1483
1484 /* Almost all prefixes are bad for jumps. */
1485 if (fPrefixes)
1486 {
1487 switch (pDis->pCurInstr->uOpcode)
1488 {
1489 /* nop w/ prefix(es). */
1490 case OP_NOP:
1491 return true;
1492
1493 case OP_JMP:
1494 if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1495 && pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1496 break;
1497 /* fall thru */
1498 case OP_JO:
1499 case OP_JNO:
1500 case OP_JC:
1501 case OP_JNC:
1502 case OP_JE:
1503 case OP_JNE:
1504 case OP_JBE:
1505 case OP_JNBE:
1506 case OP_JS:
1507 case OP_JNS:
1508 case OP_JP:
1509 case OP_JNP:
1510 case OP_JL:
1511 case OP_JNL:
1512 case OP_JLE:
1513 case OP_JNLE:
1514 /** @todo branch hinting 0x2e/0x3e... */
1515 return true;
1516 }
1517
1518 }
1519
1520 /* All but the segment prefix is bad news for push/pop. */
1521 if (fPrefixes & ~DISPREFIX_SEG)
1522 {
1523 switch (pDis->pCurInstr->uOpcode)
1524 {
1525 case OP_POP:
1526 case OP_PUSH:
1527 if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1528 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1529 return true;
1530 if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1531 && pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1532 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1533 return true;
1534 break;
1535
1536 case OP_POPA:
1537 case OP_POPF:
1538 case OP_PUSHA:
1539 case OP_PUSHF:
1540 if (fPrefixes & ~DISPREFIX_OPSIZE)
1541 return true;
1542 break;
1543 }
1544 }
1545
1546 /* Implicit 8-bit register instructions doesn't mix with operand size. */
1547 if ( (fPrefixes & DISPREFIX_OPSIZE)
1548 && ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1549 && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1550 || ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1551 && pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1552 )
1553 {
1554 switch (pDis->pCurInstr->uOpcode)
1555 {
1556 case OP_ADD:
1557 case OP_OR:
1558 case OP_ADC:
1559 case OP_SBB:
1560 case OP_AND:
1561 case OP_SUB:
1562 case OP_XOR:
1563 case OP_CMP:
1564 return true;
1565 default:
1566 break;
1567 }
1568 }
1569
1570 /* Instructions taking no address or operand which thus may be annoyingly
1571 difficult to format for yasm. */
1572 if (fPrefixes)
1573 {
1574 switch (pDis->pCurInstr->uOpcode)
1575 {
1576 case OP_STI:
1577 case OP_STC:
1578 case OP_CLI:
1579 case OP_CLD:
1580 case OP_CLC:
1581 case OP_INT:
1582 case OP_INT3:
1583 case OP_INTO:
1584 case OP_HLT:
1585 /** @todo Many more to can be added here. */
1586 return true;
1587 default:
1588 break;
1589 }
1590 }
1591
1592 /* FPU and other instructions that ignores operand size override. */
1593 if (fPrefixes & DISPREFIX_OPSIZE)
1594 {
1595 switch (pDis->pCurInstr->uOpcode)
1596 {
1597 /* FPU: */
1598 case OP_FIADD:
1599 case OP_FIMUL:
1600 case OP_FISUB:
1601 case OP_FISUBR:
1602 case OP_FIDIV:
1603 case OP_FIDIVR:
1604 /** @todo there are many more. */
1605 return true;
1606
1607 case OP_MOV:
1608 /** @todo could be that we're not disassembling these correctly. */
1609 if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1610 return true;
1611 /** @todo what about the other way? */
1612 break;
1613
1614 default:
1615 break;
1616 }
1617 }
1618
1619
1620 /*
1621 * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1622 *
1623 * For example:
1624 * expected: 1aee sbb ch, dh ; SBB r8, r/m8
1625 * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1626 */
1627 if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1628 {
1629 switch (pDis->pCurInstr->uOpcode)
1630 {
1631 case OP_ADD:
1632 case OP_OR:
1633 case OP_ADC:
1634 case OP_SBB:
1635 case OP_AND:
1636 case OP_SUB:
1637 case OP_XOR:
1638 case OP_CMP:
1639 if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1640 && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1641 || ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1642 && pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1643 return true;
1644
1645 /* 82 (see table A-6). */
1646 if (pDis->bOpCode == 0x82)
1647 return true;
1648 break;
1649
1650 /* ff /0, fe /0, ff /1, fe /0 */
1651 case OP_DEC:
1652 case OP_INC:
1653 return true;
1654
1655 case OP_POP:
1656 case OP_PUSH:
1657 Assert(pDis->bOpCode == 0x8f);
1658 return true;
1659
1660 case OP_MOV:
1661 if ( pDis->bOpCode == 0x8a
1662 || pDis->bOpCode == 0x8b)
1663 return true;
1664 break;
1665
1666 default:
1667 break;
1668 }
1669 }
1670
1671 /* shl eax,1 will be assembled to the form without the immediate byte. */
1672 if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1673 && (uint8_t)pDis->Param2.uValue == 1)
1674 {
1675 switch (pDis->pCurInstr->uOpcode)
1676 {
1677 case OP_SHL:
1678 case OP_SHR:
1679 case OP_SAR:
1680 case OP_RCL:
1681 case OP_RCR:
1682 case OP_ROL:
1683 case OP_ROR:
1684 return true;
1685 }
1686 }
1687
1688 /* And some more - see table A-6. */
1689 if (pDis->bOpCode == 0x82)
1690 {
1691 switch (pDis->pCurInstr->uOpcode)
1692 {
1693 case OP_ADD:
1694 case OP_OR:
1695 case OP_ADC:
1696 case OP_SBB:
1697 case OP_AND:
1698 case OP_SUB:
1699 case OP_XOR:
1700 case OP_CMP:
1701 return true;
1702 break;
1703 }
1704 }
1705
1706
1707 /* check for REX.X = 1 without SIB. */
1708
1709 /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1710 says (intel doesn't appear to care). */
1711 switch (pDis->pCurInstr->uOpcode)
1712 {
1713 case OP_SETO:
1714 case OP_SETNO:
1715 case OP_SETC:
1716 case OP_SETNC:
1717 case OP_SETE:
1718 case OP_SETNE:
1719 case OP_SETBE:
1720 case OP_SETNBE:
1721 case OP_SETS:
1722 case OP_SETNS:
1723 case OP_SETP:
1724 case OP_SETNP:
1725 case OP_SETL:
1726 case OP_SETNL:
1727 case OP_SETLE:
1728 case OP_SETNLE:
1729 AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1730 if (pDis->ModRM.Bits.Reg != 2)
1731 return true;
1732 break;
1733 }
1734
1735 /*
1736 * The MOVZX reg32,mem16 instruction without an operand size prefix
1737 * doesn't quite make sense...
1738 */
1739 if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1740 && pDis->bOpCode == 0xB7
1741 && (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1742 return true;
1743
1744 return false;
1745}
1746
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