VirtualBox

source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 63206

Last change on this file since 63206 was 62594, checked in by vboxsync, 8 years ago

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1/* $Id: DisasmFormatYasm.cpp 62594 2016-07-27 14:32:14Z vboxsync $ */
2/** @file
3 * VBox Disassembler - Yasm(/Nasm) Style Formatter.
4 */
5
6/*
7 * Copyright (C) 2008-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#include <VBox/dis.h>
23#include "DisasmInternal.h"
24#include <iprt/string.h>
25#include <iprt/assert.h>
26#include <iprt/ctype.h>
27
28
29/*********************************************************************************************************************************
30* Global Variables *
31*********************************************************************************************************************************/
32static const char g_szSpaces[] =
33" ";
34static const char g_aszYasmRegGen8[20][5] =
35{
36 "al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
37};
38static const char g_aszYasmRegGen16[16][5] =
39{
40 "ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
41};
42static const char g_aszYasmRegGen1616[8][6] =
43{
44 "bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
45};
46static const char g_aszYasmRegGen32[16][5] =
47{
48 "eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
49};
50static const char g_aszYasmRegGen64[16][4] =
51{
52 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
53};
54static const char g_aszYasmRegSeg[6][3] =
55{
56 "es", "cs", "ss", "ds", "fs", "gs"
57};
58static const char g_aszYasmRegFP[8][4] =
59{
60 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
61};
62static const char g_aszYasmRegMMX[8][4] =
63{
64 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
65};
66static const char g_aszYasmRegXMM[16][6] =
67{
68 "xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
69};
70static const char g_aszYasmRegYMM[16][6] =
71{
72 "ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
73};
74static const char g_aszYasmRegCRx[16][5] =
75{
76 "cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
77};
78static const char g_aszYasmRegDRx[16][5] =
79{
80 "dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
81};
82static const char g_aszYasmRegTRx[16][5] =
83{
84 "tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
85};
86
87
88
89/**
90 * Gets the base register name for the given parameter.
91 *
92 * @returns Pointer to the register name.
93 * @param pDis The disassembler state.
94 * @param pParam The parameter.
95 * @param pcchReg Where to store the length of the name.
96 */
97static const char *disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
98{
99 RT_NOREF_PV(pDis);
100
101 switch (pParam->fUse & ( DISUSE_REG_GEN8 | DISUSE_REG_GEN16 | DISUSE_REG_GEN32 | DISUSE_REG_GEN64
102 | DISUSE_REG_FP | DISUSE_REG_MMX | DISUSE_REG_XMM | DISUSE_REG_YMM
103 | DISUSE_REG_CR | DISUSE_REG_DBG | DISUSE_REG_SEG | DISUSE_REG_TEST))
104
105 {
106 case DISUSE_REG_GEN8:
107 {
108 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
109 const char *psz = g_aszYasmRegGen8[pParam->Base.idxGenReg];
110 *pcchReg = 2 + !!psz[2] + !!psz[3];
111 return psz;
112 }
113
114 case DISUSE_REG_GEN16:
115 {
116 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
117 const char *psz = g_aszYasmRegGen16[pParam->Base.idxGenReg];
118 *pcchReg = 2 + !!psz[2] + !!psz[3];
119 return psz;
120 }
121
122 // VSIB
123 case DISUSE_REG_XMM | DISUSE_REG_GEN32:
124 case DISUSE_REG_YMM | DISUSE_REG_GEN32:
125 case DISUSE_REG_GEN32:
126 {
127 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
128 const char *psz = g_aszYasmRegGen32[pParam->Base.idxGenReg];
129 *pcchReg = 2 + !!psz[2] + !!psz[3];
130 return psz;
131 }
132
133 // VSIB
134 case DISUSE_REG_XMM | DISUSE_REG_GEN64:
135 case DISUSE_REG_YMM | DISUSE_REG_GEN64:
136 case DISUSE_REG_GEN64:
137 {
138 Assert(pParam->Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
139 const char *psz = g_aszYasmRegGen64[pParam->Base.idxGenReg];
140 *pcchReg = 2 + !!psz[2] + !!psz[3];
141 return psz;
142 }
143
144 case DISUSE_REG_FP:
145 {
146 Assert(pParam->Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
147 const char *psz = g_aszYasmRegFP[pParam->Base.idxFpuReg];
148 *pcchReg = 3;
149 return psz;
150 }
151
152 case DISUSE_REG_MMX:
153 {
154 Assert(pParam->Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
155 const char *psz = g_aszYasmRegMMX[pParam->Base.idxMmxReg];
156 *pcchReg = 3;
157 return psz;
158 }
159
160 case DISUSE_REG_XMM:
161 {
162 Assert(pParam->Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
163 const char *psz = g_aszYasmRegXMM[pParam->Base.idxXmmReg];
164 *pcchReg = 4 + !!psz[4];
165 return psz;
166 }
167
168 case DISUSE_REG_YMM:
169 {
170 Assert(pParam->Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
171 const char *psz = g_aszYasmRegYMM[pParam->Base.idxYmmReg];
172 *pcchReg = 4 + !!psz[4];
173 return psz;
174 }
175
176 case DISUSE_REG_CR:
177 {
178 Assert(pParam->Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
179 const char *psz = g_aszYasmRegCRx[pParam->Base.idxCtrlReg];
180 *pcchReg = 3;
181 return psz;
182 }
183
184 case DISUSE_REG_DBG:
185 {
186 Assert(pParam->Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
187 const char *psz = g_aszYasmRegDRx[pParam->Base.idxDbgReg];
188 *pcchReg = 3;
189 return psz;
190 }
191
192 case DISUSE_REG_SEG:
193 {
194 Assert(pParam->Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
195 const char *psz = g_aszYasmRegSeg[pParam->Base.idxSegReg];
196 *pcchReg = 2;
197 return psz;
198 }
199
200 case DISUSE_REG_TEST:
201 {
202 Assert(pParam->Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
203 const char *psz = g_aszYasmRegTRx[pParam->Base.idxTestReg];
204 *pcchReg = 3;
205 return psz;
206 }
207
208 default:
209 AssertMsgFailed(("%#x\n", pParam->fUse));
210 *pcchReg = 3;
211 return "r??";
212 }
213}
214
215
216/**
217 * Gets the index register name for the given parameter.
218 *
219 * @returns The index register name.
220 * @param pDis The disassembler state.
221 * @param pParam The parameter.
222 * @param pcchReg Where to store the length of the name.
223 */
224static const char *disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
225{
226 if (pParam->fUse & DISUSE_REG_XMM)
227 {
228 Assert(pParam->Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
229 const char *psz = g_aszYasmRegXMM[pParam->Index.idxXmmReg];
230 *pcchReg = 4 + !!psz[4];
231 return psz;
232 }
233 else if (pParam->fUse & DISUSE_REG_YMM)
234 {
235 Assert(pParam->Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
236 const char *psz = g_aszYasmRegYMM[pParam->Index.idxYmmReg];
237 *pcchReg = 4 + !!psz[4];
238 return psz;
239
240 }
241 else
242 switch (pDis->uAddrMode)
243 {
244 case DISCPUMODE_16BIT:
245 {
246 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
247 const char *psz = g_aszYasmRegGen16[pParam->Index.idxGenReg];
248 *pcchReg = 2 + !!psz[2] + !!psz[3];
249 return psz;
250 }
251
252 case DISCPUMODE_32BIT:
253 {
254 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
255 const char *psz = g_aszYasmRegGen32[pParam->Index.idxGenReg];
256 *pcchReg = 2 + !!psz[2] + !!psz[3];
257 return psz;
258 }
259
260 case DISCPUMODE_64BIT:
261 {
262 Assert(pParam->Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
263 const char *psz = g_aszYasmRegGen64[pParam->Index.idxGenReg];
264 *pcchReg = 2 + !!psz[2] + !!psz[3];
265 return psz;
266 }
267
268 default:
269 AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->uAddrMode));
270 *pcchReg = 3;
271 return "r??";
272 }
273}
274
275
276/**
277 * Formats the current instruction in Yasm (/ Nasm) style.
278 *
279 *
280 * @returns The number of output characters. If this is >= cchBuf, then the content
281 * of pszBuf will be truncated.
282 * @param pDis Pointer to the disassembler state.
283 * @param pszBuf The output buffer.
284 * @param cchBuf The size of the output buffer.
285 * @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
286 * @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
287 * @param pvUser User argument for pfnGetSymbol.
288 */
289DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
290 PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
291{
292/** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
293 /*
294 * Input validation and massaging.
295 */
296 AssertPtr(pDis);
297 AssertPtrNull(pszBuf);
298 Assert(pszBuf || !cchBuf);
299 AssertPtrNull(pfnGetSymbol);
300 AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
301 if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
302 fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) | DIS_FMT_FLAGS_ADDR_RIGHT;
303 if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
304 fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) | DIS_FMT_FLAGS_BYTES_RIGHT;
305
306 PCDISOPCODE const pOp = pDis->pCurInstr;
307
308 /*
309 * Output macros
310 */
311 char *pszDst = pszBuf;
312 size_t cchDst = cchBuf;
313 size_t cchOutput = 0;
314#define PUT_C(ch) \
315 do { \
316 cchOutput++; \
317 if (cchDst > 1) \
318 { \
319 cchDst--; \
320 *pszDst++ = (ch); \
321 } \
322 } while (0)
323#define PUT_STR(pszSrc, cchSrc) \
324 do { \
325 cchOutput += (cchSrc); \
326 if (cchDst > (cchSrc)) \
327 { \
328 memcpy(pszDst, (pszSrc), (cchSrc)); \
329 pszDst += (cchSrc); \
330 cchDst -= (cchSrc); \
331 } \
332 else if (cchDst > 1) \
333 { \
334 memcpy(pszDst, (pszSrc), cchDst - 1); \
335 pszDst += cchDst - 1; \
336 cchDst = 1; \
337 } \
338 } while (0)
339#define PUT_SZ(sz) \
340 PUT_STR((sz), sizeof(sz) - 1)
341#define PUT_SZ_STRICT(szStrict, szRelaxed) \
342 do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
343#define PUT_PSZ(psz) \
344 do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
345#define PUT_NUM(cch, fmt, num) \
346 do { \
347 cchOutput += (cch); \
348 if (cchDst > 1) \
349 { \
350 const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
351 pszDst += cchTmp; \
352 cchDst -= cchTmp; \
353 Assert(cchTmp == (cch) || cchDst == 1); \
354 } \
355 } while (0)
356/** @todo add two flags for choosing between %X / %x and h / 0x. */
357#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
358#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
359#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
360#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
361
362#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
363 do { \
364 if ((stype)(num) >= 0) \
365 { \
366 PUT_C('+'); \
367 PUT_NUM(cch, fmt, (utype)(num)); \
368 } \
369 else \
370 { \
371 PUT_C('-'); \
372 PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
373 } \
374 } while (0)
375#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
376#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
377#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
378#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
379
380#define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
381 do { \
382 if (RT_SUCCESS(a_rcSym)) \
383 { \
384 PUT_SZ(a_szStart); \
385 PUT_PSZ(szSymbol); \
386 if (off != 0) \
387 { \
388 if ((int8_t)off == off) \
389 PUT_NUM_S8(off); \
390 else if ((int16_t)off == off) \
391 PUT_NUM_S16(off); \
392 else if ((int32_t)off == off) \
393 PUT_NUM_S32(off); \
394 else \
395 PUT_NUM_S64(off); \
396 } \
397 PUT_C(a_chEnd); \
398 } \
399 } while (0)
400
401#define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
402 do { \
403 if (pfnGetSymbol) \
404 { \
405 int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
406 PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
407 } \
408 } while (0)
409
410
411 /*
412 * The address?
413 */
414 if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
415 {
416#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
417 if (pDis->uInstrAddr >= _4G)
418 PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
419#endif
420 PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
421 PUT_C(' ');
422 }
423
424 /*
425 * The opcode bytes?
426 */
427 if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
428 {
429 size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
430 cchOutput += cchTmp;
431 if (cchDst > 1)
432 {
433 if (cchTmp <= cchDst)
434 {
435 cchDst -= cchTmp;
436 pszDst += cchTmp;
437 }
438 else
439 {
440 pszDst += cchDst - 1;
441 cchDst = 1;
442 }
443 }
444
445 /* Some padding to align the instruction. */
446 size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
447 + !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
448 + 2;
449 cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
450 PUT_STR(g_szSpaces, cchPadding);
451 }
452
453
454 /*
455 * Filter out invalid opcodes first as they need special
456 * treatment. UD2 is an exception and should be handled normally.
457 */
458 size_t const offInstruction = cchOutput;
459 if ( pOp->uOpcode == OP_INVALID
460 || ( pOp->uOpcode == OP_ILLUD2
461 && (pDis->fPrefix & DISPREFIX_LOCK)))
462 PUT_SZ("Illegal opcode");
463 else
464 {
465 /*
466 * Prefixes
467 */
468 if (pDis->fPrefix & DISPREFIX_LOCK)
469 PUT_SZ("lock ");
470 if (pDis->fPrefix & DISPREFIX_REP)
471 PUT_SZ("rep ");
472 else if(pDis->fPrefix & DISPREFIX_REPNE)
473 PUT_SZ("repne ");
474
475 /*
476 * Adjust the format string to the correct mnemonic
477 * or to avoid things the assembler cannot handle correctly.
478 */
479 char szTmpFmt[48];
480 const char *pszFmt = pOp->pszOpcode;
481 bool fIgnoresOpSize = false;
482 bool fMayNeedAddrSize = false;
483 switch (pOp->uOpcode)
484 {
485 case OP_JECXZ:
486 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
487 break;
488 case OP_PUSHF:
489 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
490 break;
491 case OP_POPF:
492 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
493 break;
494 case OP_PUSHA:
495 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
496 break;
497 case OP_POPA:
498 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
499 break;
500 case OP_INSB:
501 pszFmt = "insb";
502 fIgnoresOpSize = fMayNeedAddrSize = true;
503 break;
504 case OP_INSWD:
505 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
506 fMayNeedAddrSize = true;
507 break;
508 case OP_OUTSB:
509 pszFmt = "outsb";
510 fIgnoresOpSize = fMayNeedAddrSize = true;
511 break;
512 case OP_OUTSWD:
513 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
514 fMayNeedAddrSize = true;
515 break;
516 case OP_MOVSB:
517 pszFmt = "movsb";
518 fIgnoresOpSize = fMayNeedAddrSize = true;
519 break;
520 case OP_MOVSWD:
521 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
522 fMayNeedAddrSize = true;
523 break;
524 case OP_CMPSB:
525 pszFmt = "cmpsb";
526 fIgnoresOpSize = fMayNeedAddrSize = true;
527 break;
528 case OP_CMPWD:
529 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
530 fMayNeedAddrSize = true;
531 break;
532 case OP_SCASB:
533 pszFmt = "scasb";
534 fIgnoresOpSize = fMayNeedAddrSize = true;
535 break;
536 case OP_SCASWD:
537 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
538 fMayNeedAddrSize = true;
539 break;
540 case OP_LODSB:
541 pszFmt = "lodsb";
542 fIgnoresOpSize = fMayNeedAddrSize = true;
543 break;
544 case OP_LODSWD:
545 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
546 fMayNeedAddrSize = true;
547 break;
548 case OP_STOSB:
549 pszFmt = "stosb";
550 fIgnoresOpSize = fMayNeedAddrSize = true;
551 break;
552 case OP_STOSWD:
553 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
554 fMayNeedAddrSize = true;
555 break;
556 case OP_CBW:
557 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
558 break;
559 case OP_CWD:
560 pszFmt = pDis->uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
561 break;
562 case OP_SHL:
563 Assert(pszFmt[3] == '/');
564 pszFmt += 4;
565 break;
566 case OP_XLAT:
567 pszFmt = "xlatb";
568 break;
569 case OP_INT3:
570 pszFmt = "int3";
571 break;
572
573 /*
574 * Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
575 */
576 case OP_NOP:
577 if (pDis->bOpCode == 0x90)
578 /* fine, fine */;
579 else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
580 pszFmt = "prefetch %Eb";
581 else if (pDis->bOpCode == 0x1f)
582 {
583 Assert(pDis->cbInstr >= 3);
584 PUT_SZ("db 00fh, 01fh,");
585 PUT_NUM_8(MAKE_MODRM(pDis->ModRM.Bits.Mod, pDis->ModRM.Bits.Reg, pDis->ModRM.Bits.Rm));
586 for (unsigned i = 3; i < pDis->cbInstr; i++)
587 {
588 PUT_C(',');
589 PUT_NUM_8(0x90); ///@todo fixme.
590 }
591 pszFmt = "";
592 }
593 break;
594
595 default:
596 /* ST(X) -> stX (floating point) */
597 if (*pszFmt == 'f' && strchr(pszFmt, '('))
598 {
599 char *pszFmtDst = szTmpFmt;
600 char ch;
601 do
602 {
603 ch = *pszFmt++;
604 if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
605 {
606 *pszFmtDst++ = 's';
607 *pszFmtDst++ = 't';
608 pszFmt += 2;
609 ch = *pszFmt;
610 Assert(pszFmt[1] == ')');
611 pszFmt += 2;
612 *pszFmtDst++ = ch;
613 }
614 else
615 *pszFmtDst++ = ch;
616 } while (ch != '\0');
617 pszFmt = szTmpFmt;
618 }
619 if (strchr ("#@&", *pszFmt))
620 {
621 const char *pszDelim = strchr(pszFmt, '/');
622 const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
623 if (pszDelim != NULL)
624 {
625 char *pszFmtDst = szTmpFmt;
626 if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
627 if ( (*pszFmt == '#' && pDis->bVexWFlag)
628 || (*pszFmt == '@' && !VEXREG_IS256B(pDis->bVexDestReg))
629 || (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
630 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
631 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
632 || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
633 {
634 strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
635 pszFmtDst += pszDelim - pszFmt - 1;
636 }
637 else
638 {
639 strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
640 pszFmtDst += pszSpace - pszDelim - 1;
641 }
642 strcpy (pszFmtDst, pszSpace);
643 pszFmt = szTmpFmt;
644 }
645 }
646 break;
647
648 /*
649 * Horrible hacks.
650 */
651 case OP_FLD:
652 if (pDis->bOpCode == 0xdb) /* m80fp workaround. */
653 *(int *)&pDis->Param1.fParam &= ~0x1f; /* make it pure OP_PARM_M */
654 break;
655 case OP_LAR: /* hack w -> v, probably not correct. */
656 *(int *)&pDis->Param2.fParam &= ~0x1f;
657 *(int *)&pDis->Param2.fParam |= OP_PARM_v;
658 break;
659 }
660
661 /*
662 * Add operand size and address prefixes for outsb, movsb, etc.
663 */
664 if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
665 {
666 if (fIgnoresOpSize && (pDis->fPrefix & DISPREFIX_OPSIZE) )
667 {
668 if (pDis->uCpuMode == DISCPUMODE_16BIT)
669 PUT_SZ("o32 ");
670 else
671 PUT_SZ("o16 ");
672 }
673 if (fMayNeedAddrSize && (pDis->fPrefix & DISPREFIX_ADDRSIZE) )
674 {
675 if (pDis->uCpuMode == DISCPUMODE_16BIT)
676 PUT_SZ("a32 ");
677 else
678 PUT_SZ("a16 ");
679 }
680 }
681
682 /*
683 * Formatting context and associated macros.
684 */
685 PCDISOPPARAM pParam = &pDis->Param1;
686 int iParam = 1;
687
688#define PUT_FAR() \
689 do { \
690 if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_p \
691 && pOp->uOpcode != OP_LDS /* table bugs? */ \
692 && pOp->uOpcode != OP_LES \
693 && pOp->uOpcode != OP_LFS \
694 && pOp->uOpcode != OP_LGS \
695 && pOp->uOpcode != OP_LSS ) \
696 PUT_SZ("far "); \
697 } while (0)
698 /** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
699 /** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
700#define PUT_SIZE_OVERRIDE() \
701 do { \
702 switch (OP_PARM_VSUBTYPE(pParam->fParam)) \
703 { \
704 case OP_PARM_v: \
705 case OP_PARM_y: \
706 switch (pDis->uOpMode) \
707 { \
708 case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->fParam) != OP_PARM_y) PUT_SZ("word "); break; \
709 case DISCPUMODE_32BIT: \
710 if (pDis->pCurInstr->uOpcode != OP_GATHER || pDis->bVexWFlag) { PUT_SZ("dword "); break; } \
711 case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
712 default: break; \
713 } \
714 break; \
715 case OP_PARM_b: PUT_SZ("byte "); break; \
716 case OP_PARM_w: \
717 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
718 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
719 { \
720 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("dword "); \
721 else PUT_SZ("word "); \
722 } \
723 break; \
724 case OP_PARM_d: \
725 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
726 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
727 { \
728 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("qword "); \
729 else PUT_SZ("dword "); \
730 } \
731 break; \
732 case OP_PARM_q: \
733 if (OP_PARM_VTYPE(pParam->fParam) == OP_PARM_W || \
734 OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M) \
735 { \
736 if (VEXREG_IS256B(pDis->bVexDestReg)) PUT_SZ("oword "); \
737 else PUT_SZ("qword "); \
738 } \
739 break; \
740 case OP_PARM_ps: \
741 case OP_PARM_pd: \
742 case OP_PARM_x: if (VEXREG_IS256B(pDis->bVexDestReg)) { PUT_SZ("yword "); break; } \
743 case OP_PARM_ss: \
744 case OP_PARM_sd: \
745 case OP_PARM_dq: PUT_SZ("oword "); break; \
746 case OP_PARM_qq: PUT_SZ("yword "); break; \
747 case OP_PARM_p: break; /* see PUT_FAR */ \
748 case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
749 case OP_PARM_z: break; \
750 case OP_PARM_NONE: \
751 if ( OP_PARM_VTYPE(pParam->fParam) == OP_PARM_M \
752 && ((pParam->fUse & DISUSE_REG_FP) || pOp->uOpcode == OP_FLD)) \
753 PUT_SZ("tword "); \
754 break; \
755 default: break; /*no pointer type specified/necessary*/ \
756 } \
757 } while (0)
758 static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
759#define PUT_SEGMENT_OVERRIDE() \
760 do { \
761 if (pDis->fPrefix & DISPREFIX_SEG) \
762 PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 3); \
763 } while (0)
764
765
766 /*
767 * Segment prefixing for instructions that doesn't do memory access.
768 */
769 if ( (pDis->fPrefix & DISPREFIX_SEG)
770 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
771 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
772 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
773 {
774 PUT_STR(s_szSegPrefix[pDis->idxSegPrefix], 2);
775 PUT_C(' ');
776 }
777
778
779 /*
780 * The formatting loop.
781 */
782 RTINTPTR off;
783 char szSymbol[128];
784 char ch;
785 while ((ch = *pszFmt++) != '\0')
786 {
787 if (ch == '%')
788 {
789 ch = *pszFmt++;
790 switch (ch)
791 {
792 /*
793 * ModRM - Register only.
794 */
795 case 'C': /* Control register (ParseModRM / UseModRM). */
796 case 'D': /* Debug register (ParseModRM / UseModRM). */
797 case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
798 case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
799 case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
800 case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
801 case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
802 case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
803 case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
804 {
805 pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
806 Assert(!(pParam->fUse & (DISUSE_INDEX | DISUSE_SCALE) /* No SIB here... */));
807 Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)));
808
809 size_t cchReg;
810 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
811 PUT_STR(pszReg, cchReg);
812 break;
813 }
814
815 /*
816 * ModRM - Register or memory.
817 */
818 case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
819 case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
820 case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
821 case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
822 case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
823 {
824 pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
825
826 PUT_FAR();
827 uint32_t const fUse = pParam->fUse;
828 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
829 {
830 /* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
831 while the register variants deals with 16, 32 & 64 in the normal fashion. */
832 if ( pParam->fParam != OP_PARM_Ev
833 || pOp->uOpcode != OP_MOV
834 || ( pOp->fParam1 != OP_PARM_Sw
835 && pOp->fParam2 != OP_PARM_Sw))
836 PUT_SIZE_OVERRIDE();
837 PUT_C('[');
838 }
839 if ( (fFlags & DIS_FMT_FLAGS_STRICT)
840 && (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)))
841 {
842 if ( (fUse & DISUSE_DISPLACEMENT8)
843 && !pParam->uDisp.i8)
844 PUT_SZ("byte ");
845 else if ( (fUse & DISUSE_DISPLACEMENT16)
846 && (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
847 PUT_SZ("word ");
848 else if ( (fUse & DISUSE_DISPLACEMENT32)
849 && (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
850 PUT_SZ("dword ");
851 else if ( (fUse & DISUSE_DISPLACEMENT64)
852 && (pDis->SIB.Bits.Base != 5 || pDis->ModRM.Bits.Mod != 0)
853 && (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
854 PUT_SZ("qword ");
855 }
856 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
857 PUT_SEGMENT_OVERRIDE();
858
859 bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
860 || ( (fUse & ( DISUSE_REG_GEN8
861 | DISUSE_REG_GEN16
862 | DISUSE_REG_GEN32
863 | DISUSE_REG_GEN64
864 | DISUSE_REG_FP
865 | DISUSE_REG_MMX
866 | DISUSE_REG_XMM
867 | DISUSE_REG_YMM
868 | DISUSE_REG_CR
869 | DISUSE_REG_DBG
870 | DISUSE_REG_SEG
871 | DISUSE_REG_TEST ))
872 && !DISUSE_IS_EFFECTIVE_ADDR(fUse));
873 if (fBase)
874 {
875 size_t cchReg;
876 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
877 PUT_STR(pszReg, cchReg);
878 }
879
880 if (fUse & DISUSE_INDEX)
881 {
882 if (fBase)
883 PUT_C('+');
884
885 size_t cchReg;
886 const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
887 PUT_STR(pszReg, cchReg);
888
889 if (fUse & DISUSE_SCALE)
890 {
891 PUT_C('*');
892 PUT_C('0' + pParam->uScale);
893 }
894 }
895 else
896 Assert(!(fUse & DISUSE_SCALE));
897
898 int64_t off2 = 0;
899 if (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))
900 {
901 if (fUse & DISUSE_DISPLACEMENT8)
902 off2 = pParam->uDisp.i8;
903 else if (fUse & DISUSE_DISPLACEMENT16)
904 off2 = pParam->uDisp.i16;
905 else if (fUse & (DISUSE_DISPLACEMENT32 | DISUSE_RIPDISPLACEMENT32))
906 off2 = pParam->uDisp.i32;
907 else if (fUse & DISUSE_DISPLACEMENT64)
908 off2 = pParam->uDisp.i64;
909 else
910 {
911 AssertFailed();
912 off2 = 0;
913 }
914
915 int64_t off3 = off2;
916 if (fBase || (fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)))
917 {
918 PUT_C(off3 >= 0 ? '+' : '-');
919 if (off3 < 0)
920 off3 = -off3;
921 }
922 if (fUse & DISUSE_DISPLACEMENT8)
923 PUT_NUM_8( off3);
924 else if (fUse & DISUSE_DISPLACEMENT16)
925 PUT_NUM_16(off3);
926 else if (fUse & DISUSE_DISPLACEMENT32)
927 PUT_NUM_32(off3);
928 else if (fUse & DISUSE_DISPLACEMENT64)
929 PUT_NUM_64(off3);
930 else
931 {
932 PUT_NUM_32(off3);
933 PUT_SZ(" wrt rip (");
934 off2 += pDis->uInstrAddr + pDis->cbInstr;
935 PUT_NUM_64(off2);
936 if (pfnGetSymbol)
937 PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
938 ? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
939 : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
940 pDis->uAddrMode == DISCPUMODE_64BIT
941 ? (uint64_t)off2
942 : pDis->uAddrMode == DISCPUMODE_32BIT
943 ? (uint32_t)off2
944 : (uint16_t)off2,
945 " = ",
946 ')');
947 else
948 PUT_C(')');
949 }
950 }
951
952 if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
953 {
954 if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
955 PUT_SYMBOL((pDis->fPrefix & DISPREFIX_SEG)
956 ? DIS_FMT_SEL_FROM_REG(pDis->idxSegPrefix)
957 : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
958 pDis->uAddrMode == DISCPUMODE_64BIT
959 ? (uint64_t)off2
960 : pDis->uAddrMode == DISCPUMODE_32BIT
961 ? (uint32_t)off2
962 : (uint16_t)off2,
963 " (=",
964 ')');
965 PUT_C(']');
966 }
967 break;
968 }
969
970 case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
971 AssertFailed();
972 break;
973
974 case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
975 Assert(*pszFmt == 'b' || *pszFmt == 'v' || *pszFmt == 'w' || *pszFmt == 'z'); pszFmt++;
976 switch (pParam->fUse & ( DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64
977 | DISUSE_IMMEDIATE16_SX8 | DISUSE_IMMEDIATE32_SX8 | DISUSE_IMMEDIATE64_SX8))
978 {
979 case DISUSE_IMMEDIATE8:
980 if ( (fFlags & DIS_FMT_FLAGS_STRICT)
981 && ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
982 || (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
983 )
984 PUT_SZ("strict byte ");
985 PUT_NUM_8(pParam->uValue);
986 break;
987
988 case DISUSE_IMMEDIATE16:
989 if ( pDis->uCpuMode != pDis->uOpMode
990 || ( (fFlags & DIS_FMT_FLAGS_STRICT)
991 && ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
992 || (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
993 || (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
994 )
995 )
996 {
997 if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
998 PUT_SZ_STRICT("strict byte ", "byte ");
999 else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1000 || OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1001 PUT_SZ_STRICT("strict word ", "word ");
1002 }
1003 PUT_NUM_16(pParam->uValue);
1004 break;
1005
1006 case DISUSE_IMMEDIATE16_SX8:
1007 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1008 || pDis->pCurInstr->uOpcode != OP_PUSH)
1009 PUT_SZ_STRICT("strict byte ", "byte ");
1010 else
1011 PUT_SZ("word ");
1012 PUT_NUM_16(pParam->uValue);
1013 break;
1014
1015 case DISUSE_IMMEDIATE32:
1016 if ( pDis->uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
1017 || ( (fFlags & DIS_FMT_FLAGS_STRICT)
1018 && ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
1019 || (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
1020 || (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
1021 )
1022 )
1023 {
1024 if (OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_b)
1025 PUT_SZ_STRICT("strict byte ", "byte ");
1026 else if ( OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_v
1027 || OP_PARM_VSUBTYPE(pParam->fParam) == OP_PARM_z)
1028 PUT_SZ_STRICT("strict dword ", "dword ");
1029 }
1030 PUT_NUM_32(pParam->uValue);
1031 if (pDis->uCpuMode == DISCPUMODE_32BIT)
1032 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
1033 break;
1034
1035 case DISUSE_IMMEDIATE32_SX8:
1036 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1037 || pDis->pCurInstr->uOpcode != OP_PUSH)
1038 PUT_SZ_STRICT("strict byte ", "byte ");
1039 else
1040 PUT_SZ("dword ");
1041 PUT_NUM_32(pParam->uValue);
1042 break;
1043
1044 case DISUSE_IMMEDIATE64_SX8:
1045 if ( !(pDis->fPrefix & DISPREFIX_OPSIZE)
1046 || pDis->pCurInstr->uOpcode != OP_PUSH)
1047 PUT_SZ_STRICT("strict byte ", "byte ");
1048 else
1049 PUT_SZ("qword ");
1050 PUT_NUM_64(pParam->uValue);
1051 break;
1052
1053 case DISUSE_IMMEDIATE64:
1054 PUT_NUM_64(pParam->uValue);
1055 break;
1056
1057 default:
1058 AssertFailed();
1059 break;
1060 }
1061 break;
1062
1063 case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
1064 {
1065 int32_t offDisplacement;
1066 Assert(iParam == 1);
1067 bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
1068 && pOp->uOpcode != OP_CALL
1069 && pOp->uOpcode != OP_LOOP
1070 && pOp->uOpcode != OP_LOOPE
1071 && pOp->uOpcode != OP_LOOPNE
1072 && pOp->uOpcode != OP_JECXZ;
1073 if (pOp->uOpcode == OP_CALL)
1074 fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
1075
1076 if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
1077 {
1078 if (fPrefix)
1079 PUT_SZ("short ");
1080 offDisplacement = (int8_t)pParam->uValue;
1081 Assert(*pszFmt == 'b'); pszFmt++;
1082
1083 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1084 PUT_NUM_S8(offDisplacement);
1085 }
1086 else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
1087 {
1088 if (fPrefix)
1089 PUT_SZ("near ");
1090 offDisplacement = (int16_t)pParam->uValue;
1091 Assert(*pszFmt == 'v'); pszFmt++;
1092
1093 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1094 PUT_NUM_S16(offDisplacement);
1095 }
1096 else
1097 {
1098 if (fPrefix)
1099 PUT_SZ("near ");
1100 offDisplacement = (int32_t)pParam->uValue;
1101 Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL | DISUSE_IMMEDIATE64_REL));
1102 Assert(*pszFmt == 'v'); pszFmt++;
1103
1104 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1105 PUT_NUM_S32(offDisplacement);
1106 }
1107 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1108 PUT_SZ(" (");
1109
1110 RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
1111 if (pDis->uCpuMode == DISCPUMODE_16BIT)
1112 PUT_NUM_16(uTrgAddr);
1113 else if (pDis->uCpuMode == DISCPUMODE_32BIT)
1114 PUT_NUM_32(uTrgAddr);
1115 else
1116 PUT_NUM_64(uTrgAddr);
1117
1118 if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
1119 {
1120 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
1121 PUT_C(')');
1122 }
1123 else
1124 PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
1125 break;
1126 }
1127
1128 case 'A': /* Direct (jump/call) address (ParseImmAddr). */
1129 {
1130 Assert(*pszFmt == 'p'); pszFmt++;
1131 PUT_FAR();
1132 PUT_SIZE_OVERRIDE();
1133 PUT_SEGMENT_OVERRIDE();
1134 off = 0;
1135 int rc = VERR_SYMBOL_NOT_FOUND;
1136 switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1137 {
1138 case DISUSE_IMMEDIATE_ADDR_16_16:
1139 PUT_NUM_16(pParam->uValue >> 16);
1140 PUT_C(':');
1141 PUT_NUM_16(pParam->uValue);
1142 if (pfnGetSymbol)
1143 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1144 break;
1145 case DISUSE_IMMEDIATE_ADDR_16_32:
1146 PUT_NUM_16(pParam->uValue >> 32);
1147 PUT_C(':');
1148 PUT_NUM_32(pParam->uValue);
1149 if (pfnGetSymbol)
1150 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1151 break;
1152 case DISUSE_DISPLACEMENT16:
1153 PUT_NUM_16(pParam->uValue);
1154 if (pfnGetSymbol)
1155 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1156 break;
1157 case DISUSE_DISPLACEMENT32:
1158 PUT_NUM_32(pParam->uValue);
1159 if (pfnGetSymbol)
1160 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1161 break;
1162 case DISUSE_DISPLACEMENT64:
1163 PUT_NUM_64(pParam->uValue);
1164 if (pfnGetSymbol)
1165 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1166 break;
1167 default:
1168 AssertFailed();
1169 break;
1170 }
1171
1172 PUT_SYMBOL_TWO(rc, " [", ']');
1173 break;
1174 }
1175
1176 case 'O': /* No ModRM byte (ParseImmAddr). */
1177 {
1178 Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
1179 PUT_FAR();
1180 PUT_SIZE_OVERRIDE();
1181 PUT_C('[');
1182 PUT_SEGMENT_OVERRIDE();
1183 off = 0;
1184 int rc = VERR_SYMBOL_NOT_FOUND;
1185 switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1186 {
1187 case DISUSE_IMMEDIATE_ADDR_16_16:
1188 PUT_NUM_16(pParam->uValue >> 16);
1189 PUT_C(':');
1190 PUT_NUM_16(pParam->uValue);
1191 if (pfnGetSymbol)
1192 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1193 break;
1194 case DISUSE_IMMEDIATE_ADDR_16_32:
1195 PUT_NUM_16(pParam->uValue >> 32);
1196 PUT_C(':');
1197 PUT_NUM_32(pParam->uValue);
1198 if (pfnGetSymbol)
1199 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
1200 break;
1201 case DISUSE_DISPLACEMENT16:
1202 PUT_NUM_16(pParam->uDisp.i16);
1203 if (pfnGetSymbol)
1204 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
1205 break;
1206 case DISUSE_DISPLACEMENT32:
1207 PUT_NUM_32(pParam->uDisp.i32);
1208 if (pfnGetSymbol)
1209 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
1210 break;
1211 case DISUSE_DISPLACEMENT64:
1212 PUT_NUM_64(pParam->uDisp.i64);
1213 if (pfnGetSymbol)
1214 rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
1215 break;
1216 default:
1217 AssertFailed();
1218 break;
1219 }
1220 PUT_C(']');
1221
1222 PUT_SYMBOL_TWO(rc, " (", ')');
1223 break;
1224 }
1225
1226 case 'X': /* DS:SI (ParseXb, ParseXv). */
1227 case 'Y': /* ES:DI (ParseYb, ParseYv). */
1228 {
1229 Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
1230 PUT_FAR();
1231 PUT_SIZE_OVERRIDE();
1232 PUT_C('[');
1233 if (pParam->fUse & DISUSE_POINTER_DS_BASED)
1234 PUT_SZ("ds:");
1235 else
1236 PUT_SZ("es:");
1237
1238 size_t cchReg;
1239 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1240 PUT_STR(pszReg, cchReg);
1241 PUT_C(']');
1242 break;
1243 }
1244
1245 case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
1246 {
1247 Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
1248 pszFmt += 2;
1249 size_t cchReg;
1250 const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
1251 PUT_STR(pszReg, cchReg);
1252 break;
1253 }
1254
1255 default:
1256 AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1257 break;
1258 }
1259 AssertMsg(*pszFmt == ',' || *pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1260 }
1261 else
1262 {
1263 PUT_C(ch);
1264 if (ch == ',')
1265 {
1266 Assert(*pszFmt != ' ');
1267 PUT_C(' ');
1268 switch (++iParam)
1269 {
1270 case 2: pParam = &pDis->Param2; break;
1271 case 3: pParam = &pDis->Param3; break;
1272 case 4: pParam = &pDis->Param4; break;
1273 default: pParam = NULL; break;
1274 }
1275 }
1276 }
1277 } /* while more to format */
1278 }
1279
1280 /*
1281 * Any additional output to the right of the instruction?
1282 */
1283 if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
1284 {
1285 /* some up front padding. */
1286 size_t cchPadding = cchOutput - offInstruction;
1287 cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1288 PUT_STR(g_szSpaces, cchPadding);
1289
1290 /* comment? */
1291 if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
1292 PUT_SZ(";");
1293
1294 /*
1295 * The address?
1296 */
1297 if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1298 {
1299 PUT_C(' ');
1300#if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
1301 if (pDis->uInstrAddr >= _4G)
1302 PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
1303#endif
1304 PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
1305 }
1306
1307 /*
1308 * Opcode bytes?
1309 */
1310 if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1311 {
1312 PUT_C(' ');
1313 size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
1314 cchOutput += cchTmp;
1315 if (cchTmp >= cchDst)
1316 cchTmp = cchDst - (cchDst != 0);
1317 cchDst -= cchTmp;
1318 pszDst += cchTmp;
1319 }
1320 }
1321
1322 /*
1323 * Terminate it - on overflow we'll have reserved one byte for this.
1324 */
1325 if (cchDst > 0)
1326 *pszDst = '\0';
1327 else
1328 Assert(!cchBuf);
1329
1330 /* clean up macros */
1331#undef PUT_PSZ
1332#undef PUT_SZ
1333#undef PUT_STR
1334#undef PUT_C
1335 return cchOutput;
1336}
1337
1338
1339/**
1340 * Formats the current instruction in Yasm (/ Nasm) style.
1341 *
1342 * This is a simplified version of DISFormatYasmEx() provided for your convenience.
1343 *
1344 *
1345 * @returns The number of output characters. If this is >= cchBuf, then the content
1346 * of pszBuf will be truncated.
1347 * @param pDis Pointer to the disassembler state.
1348 * @param pszBuf The output buffer.
1349 * @param cchBuf The size of the output buffer.
1350 */
1351DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
1352{
1353 return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags */, NULL /* pfnGetSymbol */, NULL /* pvUser */);
1354}
1355
1356
1357/**
1358 * Checks if the encoding of the given disassembled instruction is something we
1359 * can never get YASM to produce.
1360 *
1361 * @returns true if it's odd, false if it isn't.
1362 * @param pDis The disassembler output. The byte fetcher callback will
1363 * be used if present as we might need to fetch opcode
1364 * bytes.
1365 */
1366DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
1367{
1368 /*
1369 * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
1370 */
1371 if ( pDis->uAddrMode != DISCPUMODE_16BIT ///@todo correct?
1372 && pDis->ModRM.Bits.Rm == 4
1373 && pDis->ModRM.Bits.Mod != 3)
1374 {
1375 /* No scaled index SIB (index=4), except for ESP. */
1376 if ( pDis->SIB.Bits.Index == 4
1377 && pDis->SIB.Bits.Base != 4)
1378 return true;
1379
1380 /* EBP + displacement */
1381 if ( pDis->ModRM.Bits.Mod != 0
1382 && pDis->SIB.Bits.Base == 5
1383 && pDis->SIB.Bits.Scale == 0)
1384 return true;
1385 }
1386
1387 /*
1388 * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
1389 */
1390 if ( pDis->pCurInstr->uOpcode == OP_SHL
1391 && pDis->ModRM.Bits.Reg == 6)
1392 return true;
1393
1394 /*
1395 * Check for multiple prefixes of the same kind.
1396 */
1397 uint8_t off1stSeg = UINT8_MAX;
1398 uint8_t offOpSize = UINT8_MAX;
1399 uint8_t offAddrSize = UINT8_MAX;
1400 uint32_t fPrefixes = 0;
1401 for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->abInstr); offOpcode++)
1402 {
1403 uint32_t f;
1404 switch (pDis->abInstr[offOpcode])
1405 {
1406 case 0xf0:
1407 f = DISPREFIX_LOCK;
1408 break;
1409
1410 case 0xf2:
1411 case 0xf3:
1412 f = DISPREFIX_REP; /* yes, both */
1413 break;
1414
1415 case 0x2e:
1416 case 0x3e:
1417 case 0x26:
1418 case 0x36:
1419 case 0x64:
1420 case 0x65:
1421 if (off1stSeg == UINT8_MAX)
1422 off1stSeg = offOpcode;
1423 f = DISPREFIX_SEG;
1424 break;
1425
1426 case 0x66:
1427 if (offOpSize == UINT8_MAX)
1428 offOpSize = offOpcode;
1429 f = DISPREFIX_OPSIZE;
1430 break;
1431
1432 case 0x67:
1433 if (offAddrSize == UINT8_MAX)
1434 offAddrSize = offOpcode;
1435 f = DISPREFIX_ADDRSIZE;
1436 break;
1437
1438 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1439 case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1440 f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
1441 break;
1442
1443 default:
1444 f = 0;
1445 break;
1446 }
1447 if (!f)
1448 break; /* done */
1449 if (fPrefixes & f)
1450 return true;
1451 fPrefixes |= f;
1452 }
1453
1454 /* segment overrides are fun */
1455 if (fPrefixes & DISPREFIX_SEG)
1456 {
1457 /* no effective address which it may apply to. */
1458 Assert((pDis->fPrefix & DISPREFIX_SEG) || pDis->uCpuMode == DISCPUMODE_64BIT);
1459 if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
1460 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
1461 && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
1462 return true;
1463
1464 /* Yasm puts the segment prefixes before the operand prefix with no
1465 way of overriding it. */
1466 if (offOpSize < off1stSeg)
1467 return true;
1468 }
1469
1470 /* fixed register + addr override doesn't go down all that well. */
1471 if (fPrefixes & DISPREFIX_ADDRSIZE)
1472 {
1473 Assert(pDis->fPrefix & DISPREFIX_ADDRSIZE);
1474 if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
1475 && pDis->pCurInstr->fParam2 == OP_PARM_NONE
1476 && ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1477 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
1478 return true;
1479 }
1480
1481 /* Almost all prefixes are bad for jumps. */
1482 if (fPrefixes)
1483 {
1484 switch (pDis->pCurInstr->uOpcode)
1485 {
1486 /* nop w/ prefix(es). */
1487 case OP_NOP:
1488 return true;
1489
1490 case OP_JMP:
1491 if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
1492 && pDis->pCurInstr->fParam1 != OP_PARM_Jv)
1493 break;
1494 /* fall thru */
1495 case OP_JO:
1496 case OP_JNO:
1497 case OP_JC:
1498 case OP_JNC:
1499 case OP_JE:
1500 case OP_JNE:
1501 case OP_JBE:
1502 case OP_JNBE:
1503 case OP_JS:
1504 case OP_JNS:
1505 case OP_JP:
1506 case OP_JNP:
1507 case OP_JL:
1508 case OP_JNL:
1509 case OP_JLE:
1510 case OP_JNLE:
1511 /** @todo branch hinting 0x2e/0x3e... */
1512 return true;
1513 }
1514
1515 }
1516
1517 /* All but the segment prefix is bad news for push/pop. */
1518 if (fPrefixes & ~DISPREFIX_SEG)
1519 {
1520 switch (pDis->pCurInstr->uOpcode)
1521 {
1522 case OP_POP:
1523 case OP_PUSH:
1524 if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
1525 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
1526 return true;
1527 if ( (fPrefixes & ~DISPREFIX_OPSIZE)
1528 && pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
1529 && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
1530 return true;
1531 break;
1532
1533 case OP_POPA:
1534 case OP_POPF:
1535 case OP_PUSHA:
1536 case OP_PUSHF:
1537 if (fPrefixes & ~DISPREFIX_OPSIZE)
1538 return true;
1539 break;
1540 }
1541 }
1542
1543 /* Implicit 8-bit register instructions doesn't mix with operand size. */
1544 if ( (fPrefixes & DISPREFIX_OPSIZE)
1545 && ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1546 && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1547 || ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
1548 && pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
1549 )
1550 {
1551 switch (pDis->pCurInstr->uOpcode)
1552 {
1553 case OP_ADD:
1554 case OP_OR:
1555 case OP_ADC:
1556 case OP_SBB:
1557 case OP_AND:
1558 case OP_SUB:
1559 case OP_XOR:
1560 case OP_CMP:
1561 return true;
1562 default:
1563 break;
1564 }
1565 }
1566
1567 /* Instructions taking no address or operand which thus may be annoyingly
1568 difficult to format for yasm. */
1569 if (fPrefixes)
1570 {
1571 switch (pDis->pCurInstr->uOpcode)
1572 {
1573 case OP_STI:
1574 case OP_STC:
1575 case OP_CLI:
1576 case OP_CLD:
1577 case OP_CLC:
1578 case OP_INT:
1579 case OP_INT3:
1580 case OP_INTO:
1581 case OP_HLT:
1582 /** @todo Many more to can be added here. */
1583 return true;
1584 default:
1585 break;
1586 }
1587 }
1588
1589 /* FPU and other instructions that ignores operand size override. */
1590 if (fPrefixes & DISPREFIX_OPSIZE)
1591 {
1592 switch (pDis->pCurInstr->uOpcode)
1593 {
1594 /* FPU: */
1595 case OP_FIADD:
1596 case OP_FIMUL:
1597 case OP_FISUB:
1598 case OP_FISUBR:
1599 case OP_FIDIV:
1600 case OP_FIDIVR:
1601 /** @todo there are many more. */
1602 return true;
1603
1604 case OP_MOV:
1605 /** @todo could be that we're not disassembling these correctly. */
1606 if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
1607 return true;
1608 /** @todo what about the other way? */
1609 break;
1610
1611 default:
1612 break;
1613 }
1614 }
1615
1616
1617 /*
1618 * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
1619 *
1620 * For example:
1621 * expected: 1aee sbb ch, dh ; SBB r8, r/m8
1622 * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
1623 */
1624 if (pDis->ModRM.Bits.Mod == 3 /* reg,reg */)
1625 {
1626 switch (pDis->pCurInstr->uOpcode)
1627 {
1628 case OP_ADD:
1629 case OP_OR:
1630 case OP_ADC:
1631 case OP_SBB:
1632 case OP_AND:
1633 case OP_SUB:
1634 case OP_XOR:
1635 case OP_CMP:
1636 if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
1637 && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
1638 || ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
1639 && pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
1640 return true;
1641
1642 /* 82 (see table A-6). */
1643 if (pDis->bOpCode == 0x82)
1644 return true;
1645 break;
1646
1647 /* ff /0, fe /0, ff /1, fe /0 */
1648 case OP_DEC:
1649 case OP_INC:
1650 return true;
1651
1652 case OP_POP:
1653 case OP_PUSH:
1654 Assert(pDis->bOpCode == 0x8f);
1655 return true;
1656
1657 case OP_MOV:
1658 if ( pDis->bOpCode == 0x8a
1659 || pDis->bOpCode == 0x8b)
1660 return true;
1661 break;
1662
1663 default:
1664 break;
1665 }
1666 }
1667
1668 /* shl eax,1 will be assembled to the form without the immediate byte. */
1669 if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
1670 && (uint8_t)pDis->Param2.uValue == 1)
1671 {
1672 switch (pDis->pCurInstr->uOpcode)
1673 {
1674 case OP_SHL:
1675 case OP_SHR:
1676 case OP_SAR:
1677 case OP_RCL:
1678 case OP_RCR:
1679 case OP_ROL:
1680 case OP_ROR:
1681 return true;
1682 }
1683 }
1684
1685 /* And some more - see table A-6. */
1686 if (pDis->bOpCode == 0x82)
1687 {
1688 switch (pDis->pCurInstr->uOpcode)
1689 {
1690 case OP_ADD:
1691 case OP_OR:
1692 case OP_ADC:
1693 case OP_SBB:
1694 case OP_AND:
1695 case OP_SUB:
1696 case OP_XOR:
1697 case OP_CMP:
1698 return true;
1699 break;
1700 }
1701 }
1702
1703
1704 /* check for REX.X = 1 without SIB. */
1705
1706 /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
1707 says (intel doesn't appear to care). */
1708 switch (pDis->pCurInstr->uOpcode)
1709 {
1710 case OP_SETO:
1711 case OP_SETNO:
1712 case OP_SETC:
1713 case OP_SETNC:
1714 case OP_SETE:
1715 case OP_SETNE:
1716 case OP_SETBE:
1717 case OP_SETNBE:
1718 case OP_SETS:
1719 case OP_SETNS:
1720 case OP_SETP:
1721 case OP_SETNP:
1722 case OP_SETL:
1723 case OP_SETNL:
1724 case OP_SETLE:
1725 case OP_SETNLE:
1726 AssertMsg(pDis->bOpCode >= 0x90 && pDis->bOpCode <= 0x9f, ("%#x\n", pDis->bOpCode));
1727 if (pDis->ModRM.Bits.Reg != 2)
1728 return true;
1729 break;
1730 }
1731
1732 /*
1733 * The MOVZX reg32,mem16 instruction without an operand size prefix
1734 * doesn't quite make sense...
1735 */
1736 if ( pDis->pCurInstr->uOpcode == OP_MOVZX
1737 && pDis->bOpCode == 0xB7
1738 && (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
1739 return true;
1740
1741 return false;
1742}
1743
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