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source: vbox/trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp@ 16560

Last change on this file since 16560 was 11493, checked in by vboxsync, 16 years ago
fixed assertion
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 49.8 KB

Line
1	/* $Id: DisasmFormatYasm.cpp 11493 2008-08-19 15:59:34Z vboxsync $ */
2	/** @file
3	* VBox Disassembler - Yasm(/Nasm) Style Formatter.
4	*/
5
6	/*
7	* Copyright (C) 2008 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#include <VBox/dis.h>
27	#include "DisasmInternal.h"
28	#include <iprt/string.h>
29	#include <iprt/assert.h>
30	#include <iprt/ctype.h>
31
32
33	/*******************************************************************************
34	* Global Variables *
35	*******************************************************************************/
36	static const char g_szSpaces[] =
37	" ";
38	static const char g_aszYasmRegGen8[20][5] =
39	{
40	"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
41	};
42	static const char g_aszYasmRegGen16[16][5] =
43	{
44	"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
45	};
46	static const char g_aszYasmRegGen1616[8][6] =
47	{
48	"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
49	};
50	static const char g_aszYasmRegGen32[16][5] =
51	{
52	"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
53	};
54	static const char g_aszYasmRegGen64[16][4] =
55	{
56	"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
57	};
58	static const char g_aszYasmRegSeg[6][3] =
59	{
60	"es", "cs", "ss", "ds", "fs", "gs"
61	};
62	static const char g_aszYasmRegFP[8][4] =
63	{
64	"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
65	};
66	static const char g_aszYasmRegMMX[8][4] =
67	{
68	"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
69	};
70	static const char g_aszYasmRegXMM[16][6] =
71	{
72	"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
73	};
74	static const char g_aszYasmRegCRx[16][5] =
75	{
76	"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
77	};
78	static const char g_aszYasmRegDRx[16][5] =
79	{
80	"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
81	};
82	static const char g_aszYasmRegTRx[16][5] =
83	{
84	"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
85	};
86
87
88
89	/**
90	* Gets the base register name for the given parameter.
91	*
92	* @returns Pointer to the register name.
93	* @param pCpu The disassembler cpu state.
94	* @param pParam The parameter.
95	* @param pcchReg Where to store the length of the name.
96	*/
97	static const char disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCOP_PARAMETER pParam, size_t pcchReg)
98	{
99	switch (pParam->flags & ( USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32 \| USE_REG_GEN64
100	\| USE_REG_FP \| USE_REG_MMX \| USE_REG_XMM \| USE_REG_CR
101	\| USE_REG_DBG \| USE_REG_SEG \| USE_REG_TEST))
102
103	{
104	case USE_REG_GEN8:
105	{
106	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8));
107	const char *psz = g_aszYasmRegGen8[pParam->base.reg_gen];
108	*pcchReg = 2 + !!psz[2] + !!psz[3];
109	return psz;
110	}
111
112	case USE_REG_GEN16:
113	{
114	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
115	const char *psz = g_aszYasmRegGen16[pParam->base.reg_gen];
116	*pcchReg = 2 + !!psz[2] + !!psz[3];
117	return psz;
118	}
119
120	case USE_REG_GEN32:
121	{
122	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
123	const char *psz = g_aszYasmRegGen32[pParam->base.reg_gen];
124	*pcchReg = 2 + !!psz[2] + !!psz[3];
125	return psz;
126	}
127
128	case USE_REG_GEN64:
129	{
130	Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
131	const char *psz = g_aszYasmRegGen64[pParam->base.reg_gen];
132	*pcchReg = 2 + !!psz[2] + !!psz[3];
133	return psz;
134	}
135
136	case USE_REG_FP:
137	{
138	Assert(pParam->base.reg_fp < RT_ELEMENTS(g_aszYasmRegFP));
139	const char *psz = g_aszYasmRegFP[pParam->base.reg_fp];
140	*pcchReg = 3;
141	return psz;
142	}
143
144	case USE_REG_MMX:
145	{
146	Assert(pParam->base.reg_mmx < RT_ELEMENTS(g_aszYasmRegMMX));
147	const char *psz = g_aszYasmRegMMX[pParam->base.reg_mmx];
148	*pcchReg = 3;
149	return psz;
150	}
151
152	case USE_REG_XMM:
153	{
154	Assert(pParam->base.reg_xmm < RT_ELEMENTS(g_aszYasmRegXMM));
155	const char *psz = g_aszYasmRegXMM[pParam->base.reg_mmx];
156	*pcchReg = 4 + !!psz[4];
157	return psz;
158	}
159
160	case USE_REG_CR:
161	{
162	Assert(pParam->base.reg_ctrl < RT_ELEMENTS(g_aszYasmRegCRx));
163	const char *psz = g_aszYasmRegCRx[pParam->base.reg_ctrl];
164	*pcchReg = 3;
165	return psz;
166	}
167
168	case USE_REG_DBG:
169	{
170	Assert(pParam->base.reg_dbg < RT_ELEMENTS(g_aszYasmRegDRx));
171	const char *psz = g_aszYasmRegDRx[pParam->base.reg_dbg];
172	*pcchReg = 3;
173	return psz;
174	}
175
176	case USE_REG_SEG:
177	{
178	Assert(pParam->base.reg_seg < (DIS_SELREG)RT_ELEMENTS(g_aszYasmRegCRx));
179	const char *psz = g_aszYasmRegSeg[pParam->base.reg_seg];
180	*pcchReg = 2;
181	return psz;
182	}
183
184	case USE_REG_TEST:
185	{
186	Assert(pParam->base.reg_test < RT_ELEMENTS(g_aszYasmRegTRx));
187	const char *psz = g_aszYasmRegTRx[pParam->base.reg_test];
188	*pcchReg = 3;
189	return psz;
190	}
191
192	default:
193	AssertMsgFailed(("%#x\n", pParam->flags));
194	*pcchReg = 3;
195	return "r??";
196	}
197	}
198
199
200	/**
201	* Gets the index register name for the given parameter.
202	*
203	* @returns The index register name.
204	* @param pCpu The disassembler cpu state.
205	* @param pParam The parameter.
206	* @param pcchReg Where to store the length of the name.
207	*/
208	static const char disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCOP_PARAMETER pParam, size_t pcchReg)
209	{
210	switch (pCpu->addrmode)
211	{
212	case CPUMODE_16BIT:
213	{
214	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
215	const char *psz = g_aszYasmRegGen16[pParam->index.reg_gen];
216	*pcchReg = 2 + !!psz[2] + !!psz[3];
217	return psz;
218	}
219
220	case CPUMODE_32BIT:
221	{
222	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
223	const char *psz = g_aszYasmRegGen32[pParam->index.reg_gen];
224	*pcchReg = 2 + !!psz[2] + !!psz[3];
225	return psz;
226	}
227
228	case CPUMODE_64BIT:
229	{
230	Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
231	const char *psz = g_aszYasmRegGen64[pParam->index.reg_gen];
232	*pcchReg = 2 + !!psz[2] + !!psz[3];
233	return psz;
234	}
235
236	default:
237	AssertMsgFailed(("%#x %#x\n", pParam->flags, pCpu->addrmode));
238	*pcchReg = 3;
239	return "r??";
240	}
241	}
242
243
244	/**
245	* Formats the current instruction in Yasm (/ Nasm) style.
246	*
247	*
248	* @returns The number of output characters. If this is >= cchBuf, then the content
249	* of pszBuf will be truncated.
250	* @param pCpu Pointer to the disassembler CPU state.
251	* @param pszBuf The output buffer.
252	* @param cchBuf The size of the output buffer.
253	* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
254	* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
255	* @param pvUser User argument for pfnGetSymbol.
256	*/
257	DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags,
258	PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
259	{
260	/*
261	* Input validation and massaging.
262	*/
263	AssertPtr(pCpu);
264	AssertPtrNull(pszBuf);
265	Assert(pszBuf \|\| !cchBuf);
266	AssertPtrNull(pfnGetSymbol);
267	AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
268	if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
269	fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) \| DIS_FMT_FLAGS_ADDR_RIGHT;
270	if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
271	fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) \| DIS_FMT_FLAGS_BYTES_RIGHT;
272
273	PCOPCODE const pOp = pCpu->pCurInstr;
274
275	/*
276	* Output macros
277	*/
278	char *pszDst = pszBuf;
279	size_t cchDst = cchBuf;
280	size_t cchOutput = 0;
281	#define PUT_C(ch) \
282	do { \
283	cchOutput++; \
284	if (cchDst > 1) \
285	{ \
286	cchDst--; \
287	*pszDst++ = (ch); \
288	} \
289	} while (0)
290	#define PUT_STR(pszSrc, cchSrc) \
291	do { \
292	cchOutput += (cchSrc); \
293	if (cchDst > (cchSrc)) \
294	{ \
295	memcpy(pszDst, (pszSrc), (cchSrc)); \
296	pszDst += (cchSrc); \
297	cchDst -= (cchSrc); \
298	} \
299	else if (cchDst > 1) \
300	{ \
301	memcpy(pszDst, (pszSrc), cchDst - 1); \
302	pszDst += cchDst - 1; \
303	cchDst = 1; \
304	} \
305	} while (0)
306	#define PUT_SZ(sz) \
307	PUT_STR((sz), sizeof(sz) - 1)
308	#define PUT_SZ_STRICT(szStrict, szRelaxed) \
309	do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
310	#define PUT_PSZ(psz) \
311	do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
312	#define PUT_NUM(cch, fmt, num) \
313	do { \
314	cchOutput += (cch); \
315	if (cchDst > 1) \
316	{ \
317	const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
318	pszDst += cchTmp; \
319	cchDst -= cchTmp; \
320	Assert(cchTmp == (cch) \|\| cchDst == 1); \
321	} \
322	} while (0)
323	/** @todo add two flags for choosing between %X / %x and h / 0x. */
324	#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
325	#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
326	#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
327	#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
328
329	#define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
330	do { \
331	if ((stype)(num) >= 0) \
332	{ \
333	PUT_C('+'); \
334	PUT_NUM(cch, fmt, (utype)(num)); \
335	} \
336	else \
337	{ \
338	PUT_C('-'); \
339	PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
340	} \
341	} while (0)
342	#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
343	#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
344	#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
345	#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
346
347
348	/*
349	* The address?
350	*/
351	if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
352	{
353	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
354	if (pCpu->opaddr >= _4G)
355	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->opaddr >> 32));
356	#endif
357	PUT_NUM(8, "%08x", (uint32_t)pCpu->opaddr);
358	PUT_C(' ');
359	}
360
361	/*
362	* The opcode bytes?
363	*/
364	if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
365	{
366	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
367	cchOutput += cchTmp;
368	if (cchDst > 1)
369	{
370	if (cchTmp <= cchDst)
371	{
372	cchDst -= cchTmp;
373	pszDst += cchTmp;
374	}
375	else
376	{
377	pszDst += cchDst - 1;
378	cchDst = 1;
379	}
380	}
381
382	/* Some padding to align the instruction. */
383	size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
384	+ !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
385	+ 2;
386	cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
387	PUT_STR(g_szSpaces, cchPadding);
388	}
389
390
391	/*
392	* Filter out invalid opcodes first as they need special
393	* treatment. UD2 is an exception and should be handled normally.
394	*/
395	size_t const offInstruction = cchOutput;
396	if ( pOp->opcode == OP_INVALID
397	\|\| ( pOp->opcode == OP_ILLUD2
398	&& (pCpu->prefix & PREFIX_LOCK)))
399	{
400
401	}
402	else
403	{
404	/*
405	* Prefixes
406	*/
407	if (pCpu->prefix & PREFIX_LOCK)
408	PUT_SZ("lock ");
409	if(pCpu->prefix & PREFIX_REP)
410	PUT_SZ("rep ");
411	else if(pCpu->prefix & PREFIX_REPNE)
412	PUT_SZ("repne ");
413
414	/*
415	* Adjust the format string to the correct mnemonic
416	* or to avoid things the assembler cannot handle correctly.
417	*/
418	char szTmpFmt[48];
419	const char *pszFmt = pOp->pszOpcode;
420	switch (pOp->opcode)
421	{
422	case OP_JECXZ:
423	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "jcxz %Jb" : pCpu->opmode == CPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
424	break;
425	case OP_PUSHF:
426	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushfw" : pCpu->opmode == CPUMODE_32BIT ? "pushfd" : "pushfq";
427	break;
428	case OP_POPF:
429	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popfw" : pCpu->opmode == CPUMODE_32BIT ? "popfd" : "popfq";
430	break;
431	case OP_PUSHA:
432	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "pushaw" : "pushad";
433	break;
434	case OP_POPA:
435	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "popaw" : "popad";
436	break;
437	case OP_INSB:
438	pszFmt = "insb";
439	break;
440	case OP_INSWD:
441	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "insw" : pCpu->opmode == CPUMODE_32BIT ? "insd" : "insq";
442	break;
443	case OP_OUTSB:
444	pszFmt = "outsb";
445	break;
446	case OP_OUTSWD:
447	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "outsw" : pCpu->opmode == CPUMODE_32BIT ? "outsd" : "outsq";
448	break;
449	case OP_MOVSB:
450	pszFmt = "movsb";
451	break;
452	case OP_MOVSWD:
453	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "movsw" : pCpu->opmode == CPUMODE_32BIT ? "movsd" : "movsq";
454	break;
455	case OP_CMPSB:
456	pszFmt = "cmpsb";
457	break;
458	case OP_CMPWD:
459	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cmpsw" : pCpu->opmode == CPUMODE_32BIT ? "cmpsd" : "cmpsq";
460	break;
461	case OP_SCASB:
462	pszFmt = "scasb";
463	break;
464	case OP_SCASWD:
465	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "scasw" : pCpu->opmode == CPUMODE_32BIT ? "scasd" : "scasq";
466	break;
467	case OP_LODSB:
468	pszFmt = "lodsb";
469	break;
470	case OP_LODSWD:
471	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "lodsw" : pCpu->opmode == CPUMODE_32BIT ? "lodsd" : "lodsq";
472	break;
473	case OP_STOSB:
474	pszFmt = "stosb";
475	break;
476	case OP_STOSWD:
477	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "stosw" : pCpu->opmode == CPUMODE_32BIT ? "stosd" : "stosq";
478	break;
479	case OP_CBW:
480	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cbw" : pCpu->opmode == CPUMODE_32BIT ? "cwde" : "cdqe";
481	break;
482	case OP_CWD:
483	pszFmt = pCpu->opmode == CPUMODE_16BIT ? "cwd" : pCpu->opmode == CPUMODE_32BIT ? "cdq" : "cqo";
484	break;
485	case OP_SHL:
486	Assert(pszFmt[3] == '/');
487	pszFmt += 4;
488	break;
489	case OP_XLAT:
490	pszFmt = "xlatb";
491	break;
492	case OP_INT3:
493	pszFmt = "int3";
494	break;
495
496	/*
497	* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
498	*/
499	case OP_NOP:
500	if (pCpu->opcode == 0x90)
501	/* fine, fine */;
502	else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
503	pszFmt = "prefetch %Eb";
504	else if (pCpu->opcode == 0x1f)
505	{
506	Assert(pCpu->opsize >= 3);
507	PUT_SZ("db 00fh, 01fh,");
508	PUT_NUM_8(pCpu->ModRM.u);
509	for (unsigned i = 3; i < pCpu->opsize; i++)
510	{
511	PUT_C(',');
512	PUT_NUM_8(0x90); ///@todo fixme.
513	}
514	pszFmt = "";
515	}
516	break;
517
518	default:
519	/* ST(X) -> stX (floating point) */
520	if (*pszFmt == 'f' && strchr(pszFmt, '('))
521	{
522	char *pszFmtDst = szTmpFmt;
523	char ch;
524	do
525	{
526	ch = *pszFmt++;
527	if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
528	{
529	*pszFmtDst++ = 's';
530	*pszFmtDst++ = 't';
531	pszFmt += 2;
532	ch = *pszFmt;
533	Assert(pszFmt[1] == ')');
534	pszFmt += 2;
535	*pszFmtDst++ = ch;
536	}
537	else
538	*pszFmtDst++ = ch;
539	} while (ch != '\0');
540	pszFmt = szTmpFmt;
541	}
542	break;
543
544	/*
545	* Horrible hacks.
546	*/
547	case OP_FLD:
548	if (pCpu->opcode == 0xdb) /* m80fp workaround. */
549	(int )&pCpu->param1.param &= ~0x1f; /* make it pure OP_PARM_M */
550	break;
551	case OP_LAR: /* hack w -> v, probably not correct. */
552	(int )&pCpu->param2.param &= ~0x1f;
553	(int )&pCpu->param2.param \|= OP_PARM_v;
554	break;
555	}
556
557	/*
558	* Formatting context and associated macros.
559	*/
560	PCOP_PARAMETER pParam = &pCpu->param1;
561	int iParam = 1;
562
563	#define PUT_FAR() \
564	do { \
565	if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p \
566	&& pOp->opcode != OP_LDS /* table bugs? */ \
567	&& pOp->opcode != OP_LES \
568	&& pOp->opcode != OP_LFS \
569	&& pOp->opcode != OP_LGS \
570	&& pOp->opcode != OP_LSS ) \
571	PUT_SZ("far "); \
572	} while (0)
573	/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
574	/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
575	#define PUT_SIZE_OVERRIDE() \
576	do { \
577	switch (OP_PARM_VSUBTYPE(pParam->param)) \
578	{ \
579	case OP_PARM_v: \
580	switch (pCpu->opmode) \
581	{ \
582	case CPUMODE_16BIT: PUT_SZ("word "); break; \
583	case CPUMODE_32BIT: PUT_SZ("dword "); break; \
584	case CPUMODE_64BIT: PUT_SZ("qword "); break; \
585	default: break; \
586	} \
587	break; \
588	case OP_PARM_b: PUT_SZ("byte "); break; \
589	case OP_PARM_w: PUT_SZ("word "); break; \
590	case OP_PARM_d: PUT_SZ("dword "); break; \
591	case OP_PARM_q: PUT_SZ("qword "); break; \
592	case OP_PARM_dq: \
593	if (OP_PARM_VTYPE(pParam->param) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
594	PUT_SZ("qword "); \
595	break; \
596	case OP_PARM_p: break; /* see PUT_FAR */ \
597	case OP_PARM_s: if (pParam->flags & USE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
598	case OP_PARM_z: break; \
599	case OP_PARM_NONE: \
600	if ( OP_PARM_VTYPE(pParam->param) == OP_PARM_M \
601	&& ((pParam->flags & USE_REG_FP) \|\| pOp->opcode == OP_FLD)) \
602	PUT_SZ("tword "); \
603	break; \
604	default: break; /no pointer type specified/necessary/ \
605	} \
606	} while (0)
607	static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
608	#define PUT_SEGMENT_OVERRIDE() \
609	do { \
610	if (pCpu->prefix & PREFIX_SEG) \
611	PUT_STR(s_szSegPrefix[pCpu->enmPrefixSeg], 3); \
612	} while (0)
613
614
615	/*
616	* Segment prefixing for instructions that doesn't do memory access.
617	*/
618	if ( (pCpu->prefix & PREFIX_SEG)
619	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param1.flags)
620	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param2.flags)
621	&& !DIS_IS_EFFECTIVE_ADDR(pCpu->param3.flags))
622	{
623	PUT_STR(s_szSegPrefix[pCpu->enmPrefixSeg], 2);
624	PUT_C(' ');
625	}
626
627
628	/*
629	* The formatting loop.
630	*/
631	RTINTPTR off;
632	char szSymbol[128];
633	char ch;
634	while ((ch = *pszFmt++) != '\0')
635	{
636	if (ch == '%')
637	{
638	ch = *pszFmt++;
639	switch (ch)
640	{
641	/*
642	* ModRM - Register only.
643	*/
644	case 'C': /* Control register (ParseModRM / UseModRM). */
645	case 'D': /* Debug register (ParseModRM / UseModRM). */
646	case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
647	case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
648	case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
649	case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
650	case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
651	{
652	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
653	Assert(!(pParam->flags & (USE_INDEX \| USE_SCALE) /* No SIB here... */));
654	Assert(!(pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32)));
655
656	size_t cchReg;
657	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
658	PUT_STR(pszReg, cchReg);
659	break;
660	}
661
662	/*
663	* ModRM - Register or memory.
664	*/
665	case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
666	case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
667	case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
668	case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
669	case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
670	{
671	pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
672
673	PUT_FAR();
674	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
675	{
676	/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
677	while the register variants deals with 16, 32 & 64 in the normal fashion. */
678	if ( pParam->param != OP_PARM_Ev
679	\|\| pOp->opcode != OP_MOV
680	\|\| ( pOp->param1 != OP_PARM_Sw
681	&& pOp->param2 != OP_PARM_Sw))
682	PUT_SIZE_OVERRIDE();
683	PUT_C('[');
684	}
685	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
686	&& (pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32)))
687	{
688	if ( (pParam->flags & USE_DISPLACEMENT8)
689	&& !pParam->disp8)
690	PUT_SZ("byte ");
691	else if ( (pParam->flags & USE_DISPLACEMENT16)
692	&& (int8_t)pParam->disp16 == (int16_t)pParam->disp16)
693	PUT_SZ("word ");
694	else if ( (pParam->flags & USE_DISPLACEMENT32)
695	&& (int8_t)pParam->disp32 == (int32_t)pParam->disp32)
696	PUT_SZ("dword ");
697	else if ( (pParam->flags & USE_DISPLACEMENT64)
698	&& (int8_t)pParam->disp64 == (int64_t)pParam->disp32)
699	PUT_SZ("qword ");
700	}
701	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
702	PUT_SEGMENT_OVERRIDE();
703
704	bool fBase = (pParam->flags & USE_BASE) /* When exactly is USE_BASE supposed to be set? disasmModRMReg doesn't set it. */
705	\|\| ( (pParam->flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32 \| USE_REG_GEN64))
706	&& !DIS_IS_EFFECTIVE_ADDR(pParam->flags));
707	if (fBase)
708	{
709	size_t cchReg;
710	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
711	PUT_STR(pszReg, cchReg);
712	}
713
714	if (pParam->flags & USE_INDEX)
715	{
716	if (fBase)
717	PUT_C('+');
718
719	size_t cchReg;
720	const char *pszReg = disasmFormatYasmIndexReg(pCpu, pParam, &cchReg);
721	PUT_STR(pszReg, cchReg);
722
723	if (pParam->flags & USE_SCALE)
724	{
725	PUT_C('*');
726	PUT_C('0' + pParam->scale);
727	}
728	}
729	else
730	Assert(!(pParam->flags & USE_SCALE));
731
732	if (pParam->flags & (USE_DISPLACEMENT8 \| USE_DISPLACEMENT16 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT64 \| USE_RIPDISPLACEMENT32))
733	{
734	int64_t off;
735	if (pParam->flags & USE_DISPLACEMENT8)
736	off = pParam->disp8;
737	else if (pParam->flags & USE_DISPLACEMENT16)
738	off = pParam->disp16;
739	else if (pParam->flags & (USE_DISPLACEMENT32 \| USE_RIPDISPLACEMENT32))
740	off = pParam->disp32;
741	else if (pParam->flags & USE_DISPLACEMENT64)
742	off = pParam->disp64;
743	else
744	{
745	AssertFailed();
746	off = 0;
747	}
748
749	if (fBase \|\| (pParam->flags & USE_INDEX))
750	{
751	PUT_C(off >= 0 ? '+' : '-');
752	if (off < 0)
753	off = -off;
754	}
755	if (pParam->flags & USE_DISPLACEMENT8)
756	PUT_NUM_8( off);
757	else if (pParam->flags & USE_DISPLACEMENT16)
758	PUT_NUM_16(off);
759	else if (pParam->flags & USE_DISPLACEMENT32)
760	PUT_NUM_32(off);
761	else if (pParam->flags & USE_DISPLACEMENT64)
762	PUT_NUM_64(off);
763	else
764	{
765	PUT_NUM_32(off);
766	PUT_SZ(" wrt rip"); //??
767	}
768	}
769
770	if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
771	PUT_C(']');
772	break;
773	}
774
775	case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
776	AssertFailed();
777	break;
778
779	case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
780	Assert(pszFmt == 'b' \|\| pszFmt == 'v' \|\| pszFmt == 'w' \|\| pszFmt == 'z'); pszFmt++;
781	switch (pParam->flags & ( USE_IMMEDIATE8 \| USE_IMMEDIATE16 \| USE_IMMEDIATE32 \| USE_IMMEDIATE64
782	\| USE_IMMEDIATE16_SX8 \| USE_IMMEDIATE32_SX8 \| USE_IMMEDIATE64_SX8))
783	{
784	case USE_IMMEDIATE8:
785	if ( (fFlags & DIS_FMT_FLAGS_STRICT)
786	&& ( (pOp->param1 >= OP_PARM_REG_GEN8_START && pOp->param1 <= OP_PARM_REG_GEN8_END)
787	\|\| (pOp->param2 >= OP_PARM_REG_GEN8_START && pOp->param2 <= OP_PARM_REG_GEN8_END))
788	)
789	PUT_SZ("strict byte ");
790	PUT_NUM_8(pParam->parval);
791	break;
792
793	case USE_IMMEDIATE16:
794	if ( pCpu->mode != pCpu->opmode
795	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
796	&& ( (int8_t)pParam->parval == (int16_t)pParam->parval
797	\|\| (pOp->param1 >= OP_PARM_REG_GEN16_START && pOp->param1 <= OP_PARM_REG_GEN16_END)
798	\|\| (pOp->param2 >= OP_PARM_REG_GEN16_START && pOp->param2 <= OP_PARM_REG_GEN16_END))
799	)
800	)
801	{
802	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
803	PUT_SZ_STRICT("strict byte ", "byte ");
804	else if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v)
805	PUT_SZ_STRICT("strict word ", "word ");
806	}
807	PUT_NUM_16(pParam->parval);
808	break;
809
810	case USE_IMMEDIATE16_SX8:
811	PUT_SZ_STRICT("strict byte ", "byte ");
812	PUT_NUM_16(pParam->parval);
813	break;
814
815	case USE_IMMEDIATE32:
816	if ( pCpu->opmode != (pCpu->mode == CPUMODE_16BIT ? CPUMODE_16BIT : CPUMODE_32BIT) /* not perfect */
817	\|\| ( (fFlags & DIS_FMT_FLAGS_STRICT)
818	&& ( (int8_t)pParam->parval == (int32_t)pParam->parval
819	\|\| (pOp->param1 >= OP_PARM_REG_GEN32_START && pOp->param1 <= OP_PARM_REG_GEN32_END)
820	\|\| (pOp->param2 >= OP_PARM_REG_GEN32_START && pOp->param2 <= OP_PARM_REG_GEN32_END))
821	)
822	)
823	{
824	if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_b)
825	PUT_SZ_STRICT("strict byte ", "byte ");
826	else if (OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v)
827	PUT_SZ_STRICT("strict dword ", "dword ");
828	}
829	PUT_NUM_32(pParam->parval);
830	break;
831
832	case USE_IMMEDIATE32_SX8:
833	PUT_SZ_STRICT("strict byte ", "byte ");
834	PUT_NUM_32(pParam->parval);
835	break;
836
837	case USE_IMMEDIATE64_SX8:
838	PUT_SZ_STRICT("strict byte ", "byte ");
839	PUT_NUM_64(pParam->parval);
840	break;
841
842	case USE_IMMEDIATE64:
843	PUT_NUM_64(pParam->parval);
844	break;
845
846	default:
847	AssertFailed();
848	break;
849	}
850	break;
851
852	case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
853	{
854	int32_t offDisplacement;
855	Assert(iParam == 1);
856	bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
857	&& pOp->opcode != OP_CALL
858	&& pOp->opcode != OP_LOOP
859	&& pOp->opcode != OP_LOOPE
860	&& pOp->opcode != OP_LOOPNE
861	&& pOp->opcode != OP_JECXZ;
862	if (pOp->opcode == OP_CALL)
863	fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
864
865	if (pParam->flags & USE_IMMEDIATE8_REL)
866	{
867	if (fPrefix)
868	PUT_SZ("short ");
869	offDisplacement = (int8_t)pParam->parval;
870	Assert(*pszFmt == 'b'); pszFmt++;
871
872	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
873	PUT_NUM_S8(offDisplacement);
874	}
875	else if (pParam->flags & USE_IMMEDIATE16_REL)
876	{
877	if (fPrefix)
878	PUT_SZ("near ");
879	offDisplacement = (int16_t)pParam->parval;
880	Assert(*pszFmt == 'v'); pszFmt++;
881
882	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
883	PUT_NUM_S16(offDisplacement);
884	}
885	else
886	{
887	if (fPrefix)
888	PUT_SZ("near ");
889	offDisplacement = (int32_t)pParam->parval;
890	Assert(pParam->flags & (USE_IMMEDIATE32_REL\|USE_IMMEDIATE64_REL));
891	Assert(*pszFmt == 'v'); pszFmt++;
892
893	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
894	PUT_NUM_S32(offDisplacement);
895	}
896	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
897	PUT_SZ(" (");
898
899	RTUINTPTR uTrgAddr = pCpu->opaddr + pCpu->opsize + offDisplacement;
900	if (pCpu->mode == CPUMODE_16BIT)
901	PUT_NUM_16(uTrgAddr);
902	else if (pCpu->mode == CPUMODE_32BIT)
903	PUT_NUM_32(uTrgAddr);
904	else
905	PUT_NUM_64(uTrgAddr);
906
907	if (pfnGetSymbol)
908	{
909	int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
910	if (RT_SUCCESS(rc))
911	{
912	PUT_SZ(" [");
913	PUT_PSZ(szSymbol);
914	if (off != 0)
915	{
916	if ((int8_t)off == off)
917	PUT_NUM_S8(off);
918	else if ((int16_t)off == off)
919	PUT_NUM_S16(off);
920	else if ((int32_t)off == off)
921	PUT_NUM_S32(off);
922	else
923	PUT_NUM_S64(off);
924	}
925	PUT_C(']');
926	}
927	}
928
929	if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
930	PUT_C(')');
931	break;
932	}
933
934	case 'A': /* Direct (jump/call) address (ParseImmAddr). */
935	{
936	Assert(*pszFmt == 'p'); pszFmt++;
937	PUT_FAR();
938	PUT_SIZE_OVERRIDE();
939	PUT_SEGMENT_OVERRIDE();
940	int rc = VERR_SYMBOL_NOT_FOUND;
941	switch (pParam->flags & (USE_IMMEDIATE_ADDR_16_16 \| USE_IMMEDIATE_ADDR_16_32 \| USE_DISPLACEMENT64 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT16))
942	{
943	case USE_IMMEDIATE_ADDR_16_16:
944	PUT_NUM_16(pParam->parval >> 16);
945	PUT_C(':');
946	PUT_NUM_16(pParam->parval);
947	if (pfnGetSymbol)
948	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
949	break;
950	case USE_IMMEDIATE_ADDR_16_32:
951	PUT_NUM_16(pParam->parval >> 32);
952	PUT_C(':');
953	PUT_NUM_32(pParam->parval);
954	if (pfnGetSymbol)
955	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
956	break;
957	case USE_DISPLACEMENT16:
958	PUT_NUM_16(pParam->parval);
959	if (pfnGetSymbol)
960	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
961	break;
962	case USE_DISPLACEMENT32:
963	PUT_NUM_32(pParam->parval);
964	if (pfnGetSymbol)
965	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
966	break;
967	case USE_DISPLACEMENT64:
968	PUT_NUM_64(pParam->parval);
969	if (pfnGetSymbol)
970	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
971	break;
972	default:
973	AssertFailed();
974	break;
975	}
976
977	if (RT_SUCCESS(rc))
978	{
979	PUT_SZ(" [");
980	PUT_PSZ(szSymbol);
981	if (off != 0)
982	{
983	if ((int8_t)off == off)
984	PUT_NUM_S8(off);
985	else if ((int16_t)off == off)
986	PUT_NUM_S16(off);
987	else if ((int32_t)off == off)
988	PUT_NUM_S32(off);
989	else
990	PUT_NUM_S64(off);
991	}
992	PUT_C(']');
993	}
994	break;
995	}
996
997	case 'O': /* No ModRM byte (ParseImmAddr). */
998	{
999	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1000	PUT_FAR();
1001	PUT_SIZE_OVERRIDE();
1002	PUT_C('[');
1003	PUT_SEGMENT_OVERRIDE();
1004	int rc = VERR_SYMBOL_NOT_FOUND;
1005	switch (pParam->flags & (USE_IMMEDIATE_ADDR_16_16 \| USE_IMMEDIATE_ADDR_16_32 \| USE_DISPLACEMENT64 \| USE_DISPLACEMENT32 \| USE_DISPLACEMENT16))
1006	{
1007	case USE_IMMEDIATE_ADDR_16_16:
1008	PUT_NUM_16(pParam->parval >> 16);
1009	PUT_C(':');
1010	PUT_NUM_16(pParam->parval);
1011	if (pfnGetSymbol)
1012	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1013	break;
1014	case USE_IMMEDIATE_ADDR_16_32:
1015	PUT_NUM_16(pParam->parval >> 32);
1016	PUT_C(':');
1017	PUT_NUM_32(pParam->parval);
1018	if (pfnGetSymbol)
1019	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1020	break;
1021	case USE_DISPLACEMENT16:
1022	PUT_NUM_16(pParam->disp16);
1023	if (pfnGetSymbol)
1024	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint16_t)pParam->disp16, szSymbol, sizeof(szSymbol), &off, pvUser);
1025	break;
1026	case USE_DISPLACEMENT32:
1027	PUT_NUM_32(pParam->disp32);
1028	if (pfnGetSymbol)
1029	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint32_t)pParam->disp32, szSymbol, sizeof(szSymbol), &off, pvUser);
1030	break;
1031	case USE_DISPLACEMENT64:
1032	PUT_NUM_64(pParam->disp64);
1033	if (pfnGetSymbol)
1034	rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint64_t)pParam->disp64, szSymbol, sizeof(szSymbol), &off, pvUser);
1035	break;
1036	default:
1037	AssertFailed();
1038	break;
1039	}
1040	PUT_C(']');
1041
1042	if (RT_SUCCESS(rc))
1043	{
1044	PUT_SZ(" (");
1045	PUT_PSZ(szSymbol);
1046	if (off != 0)
1047	{
1048	if ((int8_t)off == off)
1049	PUT_NUM_S8(off);
1050	else if ((int16_t)off == off)
1051	PUT_NUM_S16(off);
1052	else if ((int32_t)off == off)
1053	PUT_NUM_S32(off);
1054	else
1055	PUT_NUM_S64(off);
1056	}
1057	PUT_C(')');
1058	}
1059	break;
1060	}
1061
1062	case 'X': /* DS:SI (ParseXb, ParseXv). */
1063	case 'Y': /* ES:DI (ParseYb, ParseYv). */
1064	{
1065	Assert(pszFmt == 'b' \|\| pszFmt == 'v'); pszFmt++;
1066	PUT_FAR();
1067	PUT_SIZE_OVERRIDE();
1068	PUT_C('[');
1069	if (pParam->flags & USE_POINTER_DS_BASED)
1070	PUT_SZ("ds:");
1071	else
1072	PUT_SZ("es:");
1073
1074	size_t cchReg;
1075	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1076	PUT_STR(pszReg, cchReg);
1077	PUT_C(']');
1078	break;
1079	}
1080
1081	case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
1082	{
1083	Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
1084	size_t cchReg;
1085	const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
1086	PUT_STR(pszReg, cchReg);
1087	break;
1088	}
1089
1090	default:
1091	AssertMsgFailed(("%c%s!\n", ch, pszFmt));
1092	break;
1093	}
1094	AssertMsg(pszFmt == ',' \|\| pszFmt == '\0', ("%c%s\n", ch, pszFmt));
1095	}
1096	else
1097	{
1098	PUT_C(ch);
1099	if (ch == ',')
1100	{
1101	Assert(*pszFmt != ' ');
1102	PUT_C(' ');
1103	switch (++iParam)
1104	{
1105	case 2: pParam = &pCpu->param2; break;
1106	case 3: pParam = &pCpu->param3; break;
1107	default: pParam = NULL; break;
1108	}
1109	}
1110	}
1111	} /* while more to format */
1112	}
1113
1114	/*
1115	* Any additional output to the right of the instruction?
1116	*/
1117	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1118	{
1119	/* some up front padding. */
1120	size_t cchPadding = cchOutput - offInstruction;
1121	cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
1122	PUT_STR(g_szSpaces, cchPadding);
1123
1124	/* comment? */
1125	if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_ADDR_RIGHT))
1126	PUT_SZ(";");
1127
1128	/*
1129	* The address?
1130	*/
1131	if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
1132	{
1133	PUT_C(' ');
1134	#if HC_ARCH_BITS == 64 \|\| GC_ARCH_BITS == 64
1135	if (pCpu->opaddr >= _4G)
1136	PUT_NUM(9, "%08x`", (uint32_t)(pCpu->opaddr >> 32));
1137	#endif
1138	PUT_NUM(8, "%08x", (uint32_t)pCpu->opaddr);
1139	}
1140
1141	/*
1142	* Opcode bytes?
1143	*/
1144	if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
1145	{
1146	PUT_C(' ');
1147	size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
1148	cchOutput += cchTmp;
1149	if (cchTmp >= cchDst)
1150	cchTmp = cchDst - (cchDst != 0);
1151	cchDst -= cchTmp;
1152	pszDst += cchTmp;
1153	}
1154	}
1155
1156	/*
1157	* Terminate it - on overflow we'll have reserved one byte for this.
1158	*/
1159	if (cchDst > 0)
1160	*pszDst = '\0';
1161	else
1162	Assert(!cchBuf);
1163
1164	/* clean up macros */
1165	#undef PUT_PSZ
1166	#undef PUT_SZ
1167	#undef PUT_STR
1168	#undef PUT_C
1169	return cchOutput;
1170	}
1171
1172
1173	/**
1174	* Formats the current instruction in Yasm (/ Nasm) style.
1175	*
1176	* This is a simplified version of DISFormatYasmEx() provided for your convenience.
1177	*
1178	*
1179	* @returns The number of output characters. If this is >= cchBuf, then the content
1180	* of pszBuf will be truncated.
1181	* @param pCpu Pointer to the disassembler CPU state.
1182	* @param pszBuf The output buffer.
1183	* @param cchBuf The size of the output buffer.
1184	*/
1185	DISDECL(size_t) DISFormatYasm(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf)
1186	{
1187	return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags /, NULL / pfnGetSymbol /, NULL / pvUser */);
1188	}
1189

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