1 | /* $Id: DisasmFormatYasm.cpp 103511 2024-02-22 01:16:10Z vboxsync $ */
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2 | /** @file
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3 | * VBox Disassembler - Yasm(/Nasm) Style Formatter.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2008-2023 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * SPDX-License-Identifier: GPL-3.0-only
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #include <VBox/dis.h>
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33 | #include "DisasmInternal.h"
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34 | #include <iprt/assert.h>
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35 | #include <iprt/ctype.h>
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36 | #include <iprt/err.h>
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37 | #include <iprt/string.h>
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38 |
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39 |
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40 | /*********************************************************************************************************************************
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41 | * Global Variables *
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42 | *********************************************************************************************************************************/
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43 | static const char g_szSpaces[] =
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44 | " ";
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45 | static const char g_aszYasmRegGen8[20][5] =
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46 | {
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47 | "al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
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48 | };
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49 | static const char g_aszYasmRegGen16[16][5] =
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50 | {
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51 | "ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
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52 | };
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53 | #if 0 /* unused */
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54 | static const char g_aszYasmRegGen1616[8][6] =
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55 | {
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56 | "bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
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57 | };
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58 | #endif
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59 | static const char g_aszYasmRegGen32[16][5] =
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60 | {
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61 | "eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
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62 | };
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63 | static const char g_aszYasmRegGen64[16][4] =
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64 | {
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65 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
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66 | };
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67 | static const char g_aszYasmRegSeg[6][3] =
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68 | {
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69 | "es", "cs", "ss", "ds", "fs", "gs"
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70 | };
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71 | static const char g_aszYasmRegFP[8][4] =
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72 | {
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73 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
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74 | };
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75 | static const char g_aszYasmRegMMX[8][4] =
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76 | {
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77 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
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78 | };
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79 | static const char g_aszYasmRegXMM[16][6] =
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80 | {
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81 | "xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
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82 | };
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83 | static const char g_aszYasmRegYMM[16][6] =
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84 | {
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85 | "ymm0\0", "ymm1\0", "ymm2\0", "ymm3\0", "ymm4\0", "ymm5\0", "ymm6\0", "ymm7\0", "ymm8\0", "ymm9\0", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15"
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86 | };
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87 | static const char g_aszYasmRegCRx[16][5] =
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88 | {
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89 | "cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
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90 | };
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91 | static const char g_aszYasmRegDRx[16][5] =
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92 | {
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93 | "dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
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94 | };
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95 | static const char g_aszYasmRegTRx[16][5] =
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96 | {
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97 | "tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
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98 | };
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99 |
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100 |
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101 |
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102 | /**
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103 | * Gets the base register name for the given parameter.
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104 | *
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105 | * @returns Pointer to the register name.
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106 | * @param pDis The disassembler state.
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107 | * @param pParam The parameter.
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108 | * @param pcchReg Where to store the length of the name.
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109 | */
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110 | static const char *disasmFormatYasmBaseReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
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111 | {
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112 | RT_NOREF_PV(pDis);
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113 |
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114 | switch (pParam->fUse & ( DISUSE_REG_GEN8 | DISUSE_REG_GEN16 | DISUSE_REG_GEN32 | DISUSE_REG_GEN64
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115 | | DISUSE_REG_FP | DISUSE_REG_MMX | DISUSE_REG_XMM | DISUSE_REG_YMM
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116 | | DISUSE_REG_CR | DISUSE_REG_DBG | DISUSE_REG_SEG | DISUSE_REG_TEST))
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117 |
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118 | {
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119 | case DISUSE_REG_GEN8:
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120 | {
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121 | Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen8));
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122 | const char *psz = g_aszYasmRegGen8[pParam->x86.Base.idxGenReg];
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123 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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124 | return psz;
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125 | }
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126 |
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127 | case DISUSE_REG_GEN16:
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128 | {
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129 | Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
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130 | const char *psz = g_aszYasmRegGen16[pParam->x86.Base.idxGenReg];
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131 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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132 | return psz;
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133 | }
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134 |
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135 | // VSIB
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136 | case DISUSE_REG_XMM | DISUSE_REG_GEN32:
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137 | case DISUSE_REG_YMM | DISUSE_REG_GEN32:
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138 | case DISUSE_REG_GEN32:
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139 | {
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140 | Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
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141 | const char *psz = g_aszYasmRegGen32[pParam->x86.Base.idxGenReg];
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142 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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143 | return psz;
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144 | }
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145 |
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146 | // VSIB
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147 | case DISUSE_REG_XMM | DISUSE_REG_GEN64:
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148 | case DISUSE_REG_YMM | DISUSE_REG_GEN64:
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149 | case DISUSE_REG_GEN64:
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150 | {
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151 | Assert(pParam->x86.Base.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
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152 | const char *psz = g_aszYasmRegGen64[pParam->x86.Base.idxGenReg];
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153 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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154 | return psz;
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155 | }
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156 |
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157 | case DISUSE_REG_FP:
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158 | {
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159 | Assert(pParam->x86.Base.idxFpuReg < RT_ELEMENTS(g_aszYasmRegFP));
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160 | const char *psz = g_aszYasmRegFP[pParam->x86.Base.idxFpuReg];
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161 | *pcchReg = 3;
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162 | return psz;
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163 | }
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164 |
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165 | case DISUSE_REG_MMX:
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166 | {
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167 | Assert(pParam->x86.Base.idxMmxReg < RT_ELEMENTS(g_aszYasmRegMMX));
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168 | const char *psz = g_aszYasmRegMMX[pParam->x86.Base.idxMmxReg];
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169 | *pcchReg = 3;
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170 | return psz;
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171 | }
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172 |
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173 | case DISUSE_REG_XMM:
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174 | {
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175 | Assert(pParam->x86.Base.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
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176 | const char *psz = g_aszYasmRegXMM[pParam->x86.Base.idxXmmReg];
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177 | *pcchReg = 4 + !!psz[4];
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178 | return psz;
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179 | }
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180 |
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181 | case DISUSE_REG_YMM:
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182 | {
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183 | Assert(pParam->x86.Base.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
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184 | const char *psz = g_aszYasmRegYMM[pParam->x86.Base.idxYmmReg];
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185 | *pcchReg = 4 + !!psz[4];
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186 | return psz;
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187 | }
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188 |
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189 | case DISUSE_REG_CR:
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190 | {
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191 | Assert(pParam->x86.Base.idxCtrlReg < RT_ELEMENTS(g_aszYasmRegCRx));
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192 | const char *psz = g_aszYasmRegCRx[pParam->x86.Base.idxCtrlReg];
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193 | *pcchReg = 3;
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194 | return psz;
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195 | }
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196 |
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197 | case DISUSE_REG_DBG:
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198 | {
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199 | Assert(pParam->x86.Base.idxDbgReg < RT_ELEMENTS(g_aszYasmRegDRx));
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200 | const char *psz = g_aszYasmRegDRx[pParam->x86.Base.idxDbgReg];
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201 | *pcchReg = 3;
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202 | return psz;
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203 | }
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204 |
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205 | case DISUSE_REG_SEG:
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206 | {
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207 | Assert(pParam->x86.Base.idxSegReg < RT_ELEMENTS(g_aszYasmRegCRx));
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208 | const char *psz = g_aszYasmRegSeg[pParam->x86.Base.idxSegReg];
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209 | *pcchReg = 2;
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210 | return psz;
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211 | }
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212 |
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213 | case DISUSE_REG_TEST:
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214 | {
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215 | Assert(pParam->x86.Base.idxTestReg < RT_ELEMENTS(g_aszYasmRegTRx));
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216 | const char *psz = g_aszYasmRegTRx[pParam->x86.Base.idxTestReg];
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217 | *pcchReg = 3;
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218 | return psz;
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219 | }
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220 |
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221 | default:
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222 | AssertMsgFailed(("%#x\n", pParam->fUse));
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223 | *pcchReg = 3;
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224 | return "r??";
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225 | }
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226 | }
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227 |
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228 |
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229 | /**
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230 | * Gets the index register name for the given parameter.
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231 | *
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232 | * @returns The index register name.
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233 | * @param pDis The disassembler state.
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234 | * @param pParam The parameter.
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235 | * @param pcchReg Where to store the length of the name.
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236 | */
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237 | static const char *disasmFormatYasmIndexReg(PCDISSTATE pDis, PCDISOPPARAM pParam, size_t *pcchReg)
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238 | {
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239 | if (pParam->fUse & DISUSE_REG_XMM)
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240 | {
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241 | Assert(pParam->x86.Index.idxXmmReg < RT_ELEMENTS(g_aszYasmRegXMM));
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242 | const char *psz = g_aszYasmRegXMM[pParam->x86.Index.idxXmmReg];
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243 | *pcchReg = 4 + !!psz[4];
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244 | return psz;
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245 | }
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246 | else if (pParam->fUse & DISUSE_REG_YMM)
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247 | {
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248 | Assert(pParam->x86.Index.idxYmmReg < RT_ELEMENTS(g_aszYasmRegYMM));
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249 | const char *psz = g_aszYasmRegYMM[pParam->x86.Index.idxYmmReg];
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250 | *pcchReg = 4 + !!psz[4];
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251 | return psz;
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252 |
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253 | }
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254 | else
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255 | switch (pDis->x86.uAddrMode)
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256 | {
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257 | case DISCPUMODE_16BIT:
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258 | {
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259 | Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen16));
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260 | const char *psz = g_aszYasmRegGen16[pParam->x86.Index.idxGenReg];
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261 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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262 | return psz;
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263 | }
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264 |
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265 | case DISCPUMODE_32BIT:
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266 | {
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267 | Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen32));
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268 | const char *psz = g_aszYasmRegGen32[pParam->x86.Index.idxGenReg];
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269 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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270 | return psz;
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271 | }
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272 |
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273 | case DISCPUMODE_64BIT:
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274 | {
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275 | Assert(pParam->x86.Index.idxGenReg < RT_ELEMENTS(g_aszYasmRegGen64));
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276 | const char *psz = g_aszYasmRegGen64[pParam->x86.Index.idxGenReg];
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277 | *pcchReg = 2 + !!psz[2] + !!psz[3];
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278 | return psz;
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279 | }
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280 |
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281 | default:
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282 | AssertMsgFailed(("%#x %#x\n", pParam->fUse, pDis->x86.uAddrMode));
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283 | *pcchReg = 3;
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284 | return "r??";
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285 | }
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286 | }
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287 |
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288 |
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289 | /**
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290 | * Formats the current instruction in Yasm (/ Nasm) style.
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291 | *
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292 | *
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293 | * @returns The number of output characters. If this is >= cchBuf, then the content
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294 | * of pszBuf will be truncated.
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295 | * @param pDis Pointer to the disassembler state.
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296 | * @param pszBuf The output buffer.
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297 | * @param cchBuf The size of the output buffer.
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298 | * @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
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299 | * @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
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300 | * @param pvUser User argument for pfnGetSymbol.
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301 | */
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302 | DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags,
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303 | PFNDISGETSYMBOL pfnGetSymbol, void *pvUser)
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304 | {
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305 | /** @todo monitor and mwait aren't formatted correctly in 64-bit mode. */
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306 | /*
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307 | * Input validation and massaging.
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308 | */
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309 | AssertPtr(pDis);
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310 | AssertPtrNull(pszBuf);
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311 | Assert(pszBuf || !cchBuf);
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312 | AssertPtrNull(pfnGetSymbol);
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313 | AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
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314 | if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
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315 | fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) | DIS_FMT_FLAGS_ADDR_RIGHT;
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316 | if (fFlags & DIS_FMT_FLAGS_BYTES_COMMENT)
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317 | fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) | DIS_FMT_FLAGS_BYTES_RIGHT;
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318 |
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319 | PCDISOPCODE const pOp = pDis->pCurInstr;
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320 |
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321 | /*
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322 | * Output macros
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323 | */
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324 | char *pszDst = pszBuf;
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325 | size_t cchDst = cchBuf;
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326 | size_t cchOutput = 0;
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327 | #define PUT_C(ch) \
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328 | do { \
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329 | cchOutput++; \
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330 | if (cchDst > 1) \
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331 | { \
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332 | cchDst--; \
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333 | *pszDst++ = (ch); \
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334 | } \
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335 | } while (0)
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336 | #define PUT_STR(pszSrc, cchSrc) \
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337 | do { \
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338 | cchOutput += (cchSrc); \
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339 | if (cchDst > (cchSrc)) \
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340 | { \
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341 | memcpy(pszDst, (pszSrc), (cchSrc)); \
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342 | pszDst += (cchSrc); \
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343 | cchDst -= (cchSrc); \
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344 | } \
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345 | else if (cchDst > 1) \
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346 | { \
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347 | memcpy(pszDst, (pszSrc), cchDst - 1); \
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348 | pszDst += cchDst - 1; \
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349 | cchDst = 1; \
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350 | } \
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351 | } while (0)
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352 | #define PUT_SZ(sz) \
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353 | PUT_STR((sz), sizeof(sz) - 1)
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354 | #define PUT_SZ_STRICT(szStrict, szRelaxed) \
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355 | do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
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356 | #define PUT_PSZ(psz) \
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357 | do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
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358 | #define PUT_NUM(cch, fmt, num) \
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359 | do { \
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360 | cchOutput += (cch); \
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361 | if (cchDst > 1) \
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362 | { \
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363 | const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
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364 | pszDst += cchTmp; \
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365 | cchDst -= cchTmp; \
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366 | Assert(cchTmp == (cch) || cchDst == 1); \
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367 | } \
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368 | } while (0)
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369 | #define PUT_NUM_8(num) PUT_NUM(4, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%02xh" : "%#04x", (uint8_t)(num))
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370 | #define PUT_NUM_16(num) PUT_NUM(6, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%04xh" : "%#06x", (uint16_t)(num))
|
---|
371 | #define PUT_NUM_32(num) PUT_NUM(10, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%08xh" : "%#010x", (uint32_t)(num))
|
---|
372 | #define PUT_NUM_64(num) PUT_NUM(18, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%016RX64h" : "%#018RX64", (uint64_t)(num))
|
---|
373 |
|
---|
374 | #define PUT_NUM_SIGN(cch, fmt, num, stype, utype) \
|
---|
375 | do { \
|
---|
376 | if ((stype)(num) >= 0) \
|
---|
377 | { \
|
---|
378 | PUT_C('+'); \
|
---|
379 | PUT_NUM(cch, fmt, (utype)(num)); \
|
---|
380 | } \
|
---|
381 | else \
|
---|
382 | { \
|
---|
383 | PUT_C('-'); \
|
---|
384 | PUT_NUM(cch, fmt, (utype)-(stype)(num)); \
|
---|
385 | } \
|
---|
386 | } while (0)
|
---|
387 | #define PUT_NUM_S8(num) PUT_NUM_SIGN(4, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%02xh" : "%#04x", num, int8_t, uint8_t)
|
---|
388 | #define PUT_NUM_S16(num) PUT_NUM_SIGN(6, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%04xh" : "%#06x", num, int16_t, uint16_t)
|
---|
389 | #define PUT_NUM_S32(num) PUT_NUM_SIGN(10, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%08xh" : "%#010x", num, int32_t, uint32_t)
|
---|
390 | #define PUT_NUM_S64(num) PUT_NUM_SIGN(18, !(fFlags & DIS_FMT_FLAGS_C_HEX) ? "0%016RX64h" : "%#018RX64", num, int64_t, uint64_t)
|
---|
391 |
|
---|
392 | #define PUT_SYMBOL_TWO(a_rcSym, a_szStart, a_chEnd) \
|
---|
393 | do { \
|
---|
394 | if (RT_SUCCESS(a_rcSym)) \
|
---|
395 | { \
|
---|
396 | PUT_SZ(a_szStart); \
|
---|
397 | PUT_PSZ(szSymbol); \
|
---|
398 | if (off != 0) \
|
---|
399 | { \
|
---|
400 | if ((int8_t)off == off) \
|
---|
401 | PUT_NUM_S8(off); \
|
---|
402 | else if ((int16_t)off == off) \
|
---|
403 | PUT_NUM_S16(off); \
|
---|
404 | else if ((int32_t)off == off) \
|
---|
405 | PUT_NUM_S32(off); \
|
---|
406 | else \
|
---|
407 | PUT_NUM_S64(off); \
|
---|
408 | } \
|
---|
409 | PUT_C(a_chEnd); \
|
---|
410 | } \
|
---|
411 | } while (0)
|
---|
412 |
|
---|
413 | #define PUT_SYMBOL(a_uSeg, a_uAddr, a_szStart, a_chEnd) \
|
---|
414 | do { \
|
---|
415 | if (pfnGetSymbol) \
|
---|
416 | { \
|
---|
417 | int rcSym = pfnGetSymbol(pDis, a_uSeg, a_uAddr, szSymbol, sizeof(szSymbol), &off, pvUser); \
|
---|
418 | PUT_SYMBOL_TWO(rcSym, a_szStart, a_chEnd); \
|
---|
419 | } \
|
---|
420 | } while (0)
|
---|
421 |
|
---|
422 |
|
---|
423 | /*
|
---|
424 | * The address?
|
---|
425 | */
|
---|
426 | if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
|
---|
427 | {
|
---|
428 | #if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
|
---|
429 | if (pDis->uInstrAddr >= _4G)
|
---|
430 | PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
|
---|
431 | #endif
|
---|
432 | PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
|
---|
433 | PUT_C(' ');
|
---|
434 | }
|
---|
435 |
|
---|
436 | /*
|
---|
437 | * The opcode bytes?
|
---|
438 | */
|
---|
439 | if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
|
---|
440 | {
|
---|
441 | size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
|
---|
442 | cchOutput += cchTmp;
|
---|
443 | if (cchDst > 1)
|
---|
444 | {
|
---|
445 | if (cchTmp <= cchDst)
|
---|
446 | {
|
---|
447 | cchDst -= cchTmp;
|
---|
448 | pszDst += cchTmp;
|
---|
449 | }
|
---|
450 | else
|
---|
451 | {
|
---|
452 | pszDst += cchDst - 1;
|
---|
453 | cchDst = 1;
|
---|
454 | }
|
---|
455 | }
|
---|
456 |
|
---|
457 | /* Some padding to align the instruction. */
|
---|
458 | uint32_t cbWidth = (fFlags & DIS_FMT_FLAGS_BYTES_WIDTH_MASK) >> DIS_FMT_FLAGS_BYTES_WIDTH_SHIFT;
|
---|
459 | if (!cbWidth)
|
---|
460 | cbWidth = 7;
|
---|
461 | size_t cchPadding = (cbWidth * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
|
---|
462 | + !!(fFlags & DIS_FMT_FLAGS_BYTES_BRACKETS) * 2
|
---|
463 | + 2;
|
---|
464 | cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
|
---|
465 | PUT_STR(g_szSpaces, cchPadding);
|
---|
466 | }
|
---|
467 |
|
---|
468 |
|
---|
469 | /*
|
---|
470 | * Filter out invalid opcodes first as they need special
|
---|
471 | * treatment. UD2 is an exception and should be handled normally.
|
---|
472 | */
|
---|
473 | size_t const offInstruction = cchOutput;
|
---|
474 | if ( pOp->uOpcode == OP_INVALID
|
---|
475 | || ( pOp->uOpcode == OP_ILLUD2
|
---|
476 | && (pDis->x86.fPrefix & DISPREFIX_LOCK)))
|
---|
477 | PUT_SZ("Illegal opcode");
|
---|
478 | else
|
---|
479 | {
|
---|
480 | /*
|
---|
481 | * Prefixes
|
---|
482 | */
|
---|
483 | if (pDis->x86.fPrefix & DISPREFIX_LOCK)
|
---|
484 | PUT_SZ("lock ");
|
---|
485 | if (pDis->x86.fPrefix & DISPREFIX_REP)
|
---|
486 | PUT_SZ("rep ");
|
---|
487 | else if(pDis->x86.fPrefix & DISPREFIX_REPNE)
|
---|
488 | PUT_SZ("repne ");
|
---|
489 |
|
---|
490 | /*
|
---|
491 | * Adjust the format string to the correct mnemonic
|
---|
492 | * or to avoid things the assembler cannot handle correctly.
|
---|
493 | */
|
---|
494 | char szTmpFmt[48];
|
---|
495 | const char *pszFmt = pOp->pszOpcode;
|
---|
496 | bool fIgnoresOpSize = false;
|
---|
497 | bool fMayNeedAddrSize = false;
|
---|
498 | switch (pOp->uOpcode)
|
---|
499 | {
|
---|
500 | case OP_JECXZ:
|
---|
501 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
|
---|
502 | break;
|
---|
503 | case OP_PUSHF:
|
---|
504 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "pushfw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
|
---|
505 | break;
|
---|
506 | case OP_POPF:
|
---|
507 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "popfw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
|
---|
508 | break;
|
---|
509 | case OP_PUSHA:
|
---|
510 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
|
---|
511 | break;
|
---|
512 | case OP_POPA:
|
---|
513 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "popaw" : "popad";
|
---|
514 | break;
|
---|
515 | case OP_INSB:
|
---|
516 | pszFmt = "insb";
|
---|
517 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
518 | break;
|
---|
519 | case OP_INSWD:
|
---|
520 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "insw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
|
---|
521 | fMayNeedAddrSize = true;
|
---|
522 | break;
|
---|
523 | case OP_OUTSB:
|
---|
524 | pszFmt = "outsb";
|
---|
525 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
526 | break;
|
---|
527 | case OP_OUTSWD:
|
---|
528 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "outsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
|
---|
529 | fMayNeedAddrSize = true;
|
---|
530 | break;
|
---|
531 | case OP_MOVSB:
|
---|
532 | pszFmt = "movsb";
|
---|
533 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
534 | break;
|
---|
535 | case OP_MOVSWD:
|
---|
536 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "movsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
|
---|
537 | fMayNeedAddrSize = true;
|
---|
538 | break;
|
---|
539 | case OP_CMPSB:
|
---|
540 | pszFmt = "cmpsb";
|
---|
541 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
542 | break;
|
---|
543 | case OP_CMPWD:
|
---|
544 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
|
---|
545 | fMayNeedAddrSize = true;
|
---|
546 | break;
|
---|
547 | case OP_SCASB:
|
---|
548 | pszFmt = "scasb";
|
---|
549 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
550 | break;
|
---|
551 | case OP_SCASWD:
|
---|
552 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "scasw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
|
---|
553 | fMayNeedAddrSize = true;
|
---|
554 | break;
|
---|
555 | case OP_LODSB:
|
---|
556 | pszFmt = "lodsb";
|
---|
557 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
558 | break;
|
---|
559 | case OP_LODSWD:
|
---|
560 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "lodsw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
|
---|
561 | fMayNeedAddrSize = true;
|
---|
562 | break;
|
---|
563 | case OP_STOSB:
|
---|
564 | pszFmt = "stosb";
|
---|
565 | fIgnoresOpSize = fMayNeedAddrSize = true;
|
---|
566 | break;
|
---|
567 | case OP_STOSWD:
|
---|
568 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "stosw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
|
---|
569 | fMayNeedAddrSize = true;
|
---|
570 | break;
|
---|
571 | case OP_CBW:
|
---|
572 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cbw" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
|
---|
573 | break;
|
---|
574 | case OP_CWD:
|
---|
575 | pszFmt = pDis->x86.uOpMode == DISCPUMODE_16BIT ? "cwd" : pDis->x86.uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
|
---|
576 | break;
|
---|
577 | case OP_SHL:
|
---|
578 | Assert(pszFmt[3] == '/');
|
---|
579 | pszFmt += 4;
|
---|
580 | break;
|
---|
581 | case OP_XLAT:
|
---|
582 | pszFmt = "xlatb";
|
---|
583 | break;
|
---|
584 | case OP_INT3:
|
---|
585 | pszFmt = "int3";
|
---|
586 | break;
|
---|
587 |
|
---|
588 | /*
|
---|
589 | * Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
|
---|
590 | */
|
---|
591 | case OP_NOP:
|
---|
592 | if (pDis->x86.bOpCode == 0x90)
|
---|
593 | /* fine, fine */;
|
---|
594 | else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
|
---|
595 | pszFmt = "prefetch %Eb";
|
---|
596 | else if (pDis->x86.bOpCode == 0x1f)
|
---|
597 | {
|
---|
598 | Assert(pDis->cbInstr >= 3);
|
---|
599 | PUT_SZ("db 00fh, 01fh");
|
---|
600 | for (unsigned off = 2; off < pDis->cbInstr; off++)
|
---|
601 | {
|
---|
602 | PUT_C(',');
|
---|
603 | PUT_C(' ');
|
---|
604 | PUT_NUM_8(pDis->Instr.ab[off]);
|
---|
605 | }
|
---|
606 | pszFmt = "";
|
---|
607 | }
|
---|
608 | break;
|
---|
609 |
|
---|
610 | default:
|
---|
611 | /* ST(X) -> stX (floating point) */
|
---|
612 | if (*pszFmt == 'f' && strchr(pszFmt, '('))
|
---|
613 | {
|
---|
614 | char *pszFmtDst = szTmpFmt;
|
---|
615 | char ch;
|
---|
616 | do
|
---|
617 | {
|
---|
618 | ch = *pszFmt++;
|
---|
619 | if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
|
---|
620 | {
|
---|
621 | *pszFmtDst++ = 's';
|
---|
622 | *pszFmtDst++ = 't';
|
---|
623 | pszFmt += 2;
|
---|
624 | ch = *pszFmt;
|
---|
625 | Assert(pszFmt[1] == ')');
|
---|
626 | pszFmt += 2;
|
---|
627 | *pszFmtDst++ = ch;
|
---|
628 | }
|
---|
629 | else
|
---|
630 | *pszFmtDst++ = ch;
|
---|
631 | } while (ch != '\0');
|
---|
632 | pszFmt = szTmpFmt;
|
---|
633 | }
|
---|
634 | if (strchr("#@&", *pszFmt))
|
---|
635 | {
|
---|
636 | const char *pszDelim = strchr(pszFmt, '/');
|
---|
637 | const char *pszSpace = (pszDelim ? strchr(pszDelim, ' ') : NULL);
|
---|
638 | if (pszDelim != NULL)
|
---|
639 | {
|
---|
640 | char *pszFmtDst = szTmpFmt;
|
---|
641 | if (pszSpace == NULL) pszSpace = strchr(pszDelim, 0);
|
---|
642 | if ( (*pszFmt == '#' && !(pDis->x86.bVexByte2 & DISPREFIX_VEX_F_W)) /** @todo check this*/
|
---|
643 | || (*pszFmt == '@' && !VEXREG_IS256B(pDis->x86.bVexDestReg))
|
---|
644 | || (*pszFmt == '&' && ( DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
|
---|
645 | || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
|
---|
646 | || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse)
|
---|
647 | || DISUSE_IS_EFFECTIVE_ADDR(pDis->Param4.fUse))))
|
---|
648 | {
|
---|
649 | strncpy(pszFmtDst, pszFmt + 1, pszDelim - pszFmt - 1);
|
---|
650 | pszFmtDst += pszDelim - pszFmt - 1;
|
---|
651 | }
|
---|
652 | else
|
---|
653 | {
|
---|
654 | strncpy(pszFmtDst, pszDelim + 1, pszSpace - pszDelim - 1);
|
---|
655 | pszFmtDst += pszSpace - pszDelim - 1;
|
---|
656 | }
|
---|
657 | strcpy (pszFmtDst, pszSpace);
|
---|
658 | pszFmt = szTmpFmt;
|
---|
659 | }
|
---|
660 | }
|
---|
661 | break;
|
---|
662 |
|
---|
663 | /*
|
---|
664 | * Horrible hacks.
|
---|
665 | */
|
---|
666 | case OP_FLD:
|
---|
667 | if (pDis->x86.bOpCode == 0xdb) /* m80fp workaround. */
|
---|
668 | *(int *)&pDis->Param1.x86.fParam &= ~0x1f; /* make it pure OP_PARM_M */
|
---|
669 | break;
|
---|
670 | case OP_LAR: /* hack w -> v, probably not correct. */
|
---|
671 | *(int *)&pDis->Param2.x86.fParam &= ~0x1f;
|
---|
672 | *(int *)&pDis->Param2.x86.fParam |= OP_PARM_v;
|
---|
673 | break;
|
---|
674 | }
|
---|
675 |
|
---|
676 | /*
|
---|
677 | * Add operand size and address prefixes for outsb, movsb, etc.
|
---|
678 | */
|
---|
679 | if (pDis->x86.fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
|
---|
680 | {
|
---|
681 | if (fIgnoresOpSize && (pDis->x86.fPrefix & DISPREFIX_OPSIZE) )
|
---|
682 | {
|
---|
683 | if (pDis->uCpuMode == DISCPUMODE_16BIT)
|
---|
684 | PUT_SZ("o32 ");
|
---|
685 | else
|
---|
686 | PUT_SZ("o16 ");
|
---|
687 | }
|
---|
688 | if (fMayNeedAddrSize && (pDis->x86.fPrefix & DISPREFIX_ADDRSIZE) )
|
---|
689 | {
|
---|
690 | if (pDis->uCpuMode == DISCPUMODE_16BIT)
|
---|
691 | PUT_SZ("a32 ");
|
---|
692 | else
|
---|
693 | PUT_SZ("a16 ");
|
---|
694 | }
|
---|
695 | }
|
---|
696 |
|
---|
697 | /*
|
---|
698 | * Formatting context and associated macros.
|
---|
699 | */
|
---|
700 | PCDISOPPARAM pParam = &pDis->Param1;
|
---|
701 | int iParam = 1;
|
---|
702 |
|
---|
703 | #define PUT_FAR() \
|
---|
704 | do { \
|
---|
705 | if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_p \
|
---|
706 | && pOp->uOpcode != OP_LDS /* table bugs? */ \
|
---|
707 | && pOp->uOpcode != OP_LES \
|
---|
708 | && pOp->uOpcode != OP_LFS \
|
---|
709 | && pOp->uOpcode != OP_LGS \
|
---|
710 | && pOp->uOpcode != OP_LSS ) \
|
---|
711 | PUT_SZ("far "); \
|
---|
712 | } while (0)
|
---|
713 | /** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
|
---|
714 | /** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
|
---|
715 | #define PUT_SIZE_OVERRIDE() \
|
---|
716 | do { \
|
---|
717 | switch (OP_PARM_VSUBTYPE(pParam->x86.fParam)) \
|
---|
718 | { \
|
---|
719 | case OP_PARM_v: \
|
---|
720 | case OP_PARM_y: \
|
---|
721 | switch (pDis->x86.uOpMode) \
|
---|
722 | { \
|
---|
723 | case DISCPUMODE_16BIT: if (OP_PARM_VSUBTYPE(pParam->x86.fParam) != OP_PARM_y) PUT_SZ("word "); break; \
|
---|
724 | case DISCPUMODE_32BIT: \
|
---|
725 | if (pDis->pCurInstr->uOpcode != OP_GATHER || (pDis->x86.bVexByte2 & DISPREFIX_VEX_F_W)) \
|
---|
726 | { PUT_SZ("dword "); break; } \
|
---|
727 | RT_FALL_THRU(); \
|
---|
728 | case DISCPUMODE_64BIT: PUT_SZ("qword "); break; \
|
---|
729 | default: break; \
|
---|
730 | } \
|
---|
731 | break; \
|
---|
732 | case OP_PARM_b: PUT_SZ("byte "); break; \
|
---|
733 | case OP_PARM_w: \
|
---|
734 | if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
|
---|
735 | || OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
|
---|
736 | { \
|
---|
737 | if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("dword "); \
|
---|
738 | else PUT_SZ("word "); \
|
---|
739 | } \
|
---|
740 | break; \
|
---|
741 | case OP_PARM_d: \
|
---|
742 | if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
|
---|
743 | || OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
|
---|
744 | { \
|
---|
745 | if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("qword "); \
|
---|
746 | else PUT_SZ("dword "); \
|
---|
747 | } \
|
---|
748 | break; \
|
---|
749 | case OP_PARM_q: \
|
---|
750 | if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_W \
|
---|
751 | || OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M) \
|
---|
752 | { \
|
---|
753 | if (VEXREG_IS256B(pDis->x86.bVexDestReg)) PUT_SZ("oword "); \
|
---|
754 | else PUT_SZ("qword "); \
|
---|
755 | } \
|
---|
756 | break; \
|
---|
757 | case OP_PARM_ps: \
|
---|
758 | case OP_PARM_pd: \
|
---|
759 | case OP_PARM_x: if (VEXREG_IS256B(pDis->x86.bVexDestReg)) { PUT_SZ("yword "); break; } RT_FALL_THRU(); \
|
---|
760 | case OP_PARM_ss: \
|
---|
761 | case OP_PARM_sd: \
|
---|
762 | case OP_PARM_dq: PUT_SZ("oword "); break; \
|
---|
763 | case OP_PARM_qq: PUT_SZ("yword "); break; \
|
---|
764 | case OP_PARM_p: break; /* see PUT_FAR */ \
|
---|
765 | case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
|
---|
766 | case OP_PARM_z: break; \
|
---|
767 | case OP_PARM_NONE: \
|
---|
768 | if ( OP_PARM_VTYPE(pParam->x86.fParam) == OP_PARM_M \
|
---|
769 | && ((pParam->fUse & DISUSE_REG_FP) || pOp->uOpcode == OP_FLD)) \
|
---|
770 | PUT_SZ("tword "); \
|
---|
771 | break; \
|
---|
772 | default: break; /*no pointer type specified/necessary*/ \
|
---|
773 | } \
|
---|
774 | } while (0)
|
---|
775 | static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
|
---|
776 | #define PUT_SEGMENT_OVERRIDE() \
|
---|
777 | do { \
|
---|
778 | if (pDis->x86.fPrefix & DISPREFIX_SEG) \
|
---|
779 | PUT_STR(s_szSegPrefix[pDis->x86.idxSegPrefix], 3); \
|
---|
780 | } while (0)
|
---|
781 |
|
---|
782 |
|
---|
783 | /*
|
---|
784 | * Segment prefixing for instructions that doesn't do memory access.
|
---|
785 | */
|
---|
786 | if ( (pDis->x86.fPrefix & DISPREFIX_SEG)
|
---|
787 | && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
|
---|
788 | && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
|
---|
789 | && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
|
---|
790 | {
|
---|
791 | PUT_STR(s_szSegPrefix[pDis->x86.idxSegPrefix], 2);
|
---|
792 | PUT_C(' ');
|
---|
793 | }
|
---|
794 |
|
---|
795 |
|
---|
796 | /*
|
---|
797 | * The formatting loop.
|
---|
798 | */
|
---|
799 | RTINTPTR off;
|
---|
800 | char szSymbol[128];
|
---|
801 | char ch;
|
---|
802 | while ((ch = *pszFmt++) != '\0')
|
---|
803 | {
|
---|
804 | if (ch == '%')
|
---|
805 | {
|
---|
806 | ch = *pszFmt++;
|
---|
807 | switch (ch)
|
---|
808 | {
|
---|
809 | /*
|
---|
810 | * ModRM - Register only / VEX.vvvv.
|
---|
811 | */
|
---|
812 | case 'C': /* Control register (ParseModRM / UseModRM). */
|
---|
813 | case 'D': /* Debug register (ParseModRM / UseModRM). */
|
---|
814 | case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
|
---|
815 | case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
|
---|
816 | case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
|
---|
817 | case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
|
---|
818 | case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
|
---|
819 | case 'H': /* The VEX.vvvv field of the VEX prefix selects a XMM/YMM register. */
|
---|
820 | case 'B': /* The VEX.vvvv field of the VEX prefix selects a general register (ParseVexDest). */
|
---|
821 | case 'L': /* The upper 4 bits of the 8-bit immediate selects a XMM/YMM register. */
|
---|
822 | {
|
---|
823 | pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
|
---|
824 | Assert(!(pParam->fUse & (DISUSE_INDEX | DISUSE_SCALE) /* No SIB here... */));
|
---|
825 | Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)));
|
---|
826 |
|
---|
827 | size_t cchReg;
|
---|
828 | const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
|
---|
829 | PUT_STR(pszReg, cchReg);
|
---|
830 | break;
|
---|
831 | }
|
---|
832 |
|
---|
833 | /*
|
---|
834 | * ModRM - Register or memory.
|
---|
835 | */
|
---|
836 | case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
|
---|
837 | case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
|
---|
838 | case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
|
---|
839 | case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
|
---|
840 | case 'U': /* ModRM byte may only refer to a XMM/SSE register (ParseModRM / UseModRM). */
|
---|
841 | case 'M': /* ModRM byte may only refer to memory (ParseModRM / UseModRM). */
|
---|
842 | {
|
---|
843 | pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
|
---|
844 |
|
---|
845 | PUT_FAR();
|
---|
846 | uint32_t const fUse = pParam->fUse;
|
---|
847 | if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
|
---|
848 | {
|
---|
849 | /* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
|
---|
850 | while the register variants deals with 16, 32 & 64 in the normal fashion. */
|
---|
851 | if ( pParam->x86.fParam != OP_PARM_Ev
|
---|
852 | || pOp->uOpcode != OP_MOV
|
---|
853 | || ( pOp->fParam1 != OP_PARM_Sw
|
---|
854 | && pOp->fParam2 != OP_PARM_Sw))
|
---|
855 | PUT_SIZE_OVERRIDE();
|
---|
856 | PUT_C('[');
|
---|
857 | }
|
---|
858 | if ( (fFlags & DIS_FMT_FLAGS_STRICT)
|
---|
859 | && (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)))
|
---|
860 | {
|
---|
861 | if ( (fUse & DISUSE_DISPLACEMENT8)
|
---|
862 | && !pParam->x86.uDisp.i8)
|
---|
863 | PUT_SZ("byte ");
|
---|
864 | else if ( (fUse & DISUSE_DISPLACEMENT16)
|
---|
865 | && (int8_t)pParam->x86.uDisp.i16 == (int16_t)pParam->x86.uDisp.i16)
|
---|
866 | PUT_SZ("word ");
|
---|
867 | else if ( (fUse & DISUSE_DISPLACEMENT32)
|
---|
868 | && (int16_t)pParam->x86.uDisp.i32 == (int32_t)pParam->x86.uDisp.i32) //??
|
---|
869 | PUT_SZ("dword ");
|
---|
870 | else if ( (fUse & DISUSE_DISPLACEMENT64)
|
---|
871 | && (pDis->x86.SIB.Bits.Base != 5 || pDis->x86.ModRM.Bits.Mod != 0)
|
---|
872 | && (int32_t)pParam->x86.uDisp.i64 == (int64_t)pParam->x86.uDisp.i64) //??
|
---|
873 | PUT_SZ("qword ");
|
---|
874 | }
|
---|
875 | if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
|
---|
876 | PUT_SEGMENT_OVERRIDE();
|
---|
877 |
|
---|
878 | bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
|
---|
879 | || ( (fUse & ( DISUSE_REG_GEN8
|
---|
880 | | DISUSE_REG_GEN16
|
---|
881 | | DISUSE_REG_GEN32
|
---|
882 | | DISUSE_REG_GEN64
|
---|
883 | | DISUSE_REG_FP
|
---|
884 | | DISUSE_REG_MMX
|
---|
885 | | DISUSE_REG_XMM
|
---|
886 | | DISUSE_REG_YMM
|
---|
887 | | DISUSE_REG_CR
|
---|
888 | | DISUSE_REG_DBG
|
---|
889 | | DISUSE_REG_SEG
|
---|
890 | | DISUSE_REG_TEST ))
|
---|
891 | && !DISUSE_IS_EFFECTIVE_ADDR(fUse));
|
---|
892 | if (fBase)
|
---|
893 | {
|
---|
894 | size_t cchReg;
|
---|
895 | const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
|
---|
896 | PUT_STR(pszReg, cchReg);
|
---|
897 | }
|
---|
898 |
|
---|
899 | if (fUse & DISUSE_INDEX)
|
---|
900 | {
|
---|
901 | if (fBase)
|
---|
902 | PUT_C('+');
|
---|
903 |
|
---|
904 | size_t cchReg;
|
---|
905 | const char *pszReg = disasmFormatYasmIndexReg(pDis, pParam, &cchReg);
|
---|
906 | PUT_STR(pszReg, cchReg);
|
---|
907 |
|
---|
908 | if (fUse & DISUSE_SCALE)
|
---|
909 | {
|
---|
910 | PUT_C('*');
|
---|
911 | PUT_C('0' + pParam->x86.uScale);
|
---|
912 | }
|
---|
913 | }
|
---|
914 | else
|
---|
915 | Assert(!(fUse & DISUSE_SCALE));
|
---|
916 |
|
---|
917 | int64_t off2 = 0;
|
---|
918 | if (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))
|
---|
919 | {
|
---|
920 | if (fUse & DISUSE_DISPLACEMENT8)
|
---|
921 | off2 = pParam->x86.uDisp.i8;
|
---|
922 | else if (fUse & DISUSE_DISPLACEMENT16)
|
---|
923 | off2 = pParam->x86.uDisp.i16;
|
---|
924 | else if (fUse & (DISUSE_DISPLACEMENT32 | DISUSE_RIPDISPLACEMENT32))
|
---|
925 | off2 = pParam->x86.uDisp.i32;
|
---|
926 | else if (fUse & DISUSE_DISPLACEMENT64)
|
---|
927 | off2 = pParam->x86.uDisp.i64;
|
---|
928 | else
|
---|
929 | {
|
---|
930 | AssertFailed();
|
---|
931 | off2 = 0;
|
---|
932 | }
|
---|
933 |
|
---|
934 | int64_t off3 = off2;
|
---|
935 | if (fBase || (fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)))
|
---|
936 | {
|
---|
937 | PUT_C(off3 >= 0 ? '+' : '-');
|
---|
938 | if (off3 < 0)
|
---|
939 | off3 = -off3;
|
---|
940 | }
|
---|
941 | if (fUse & DISUSE_DISPLACEMENT8)
|
---|
942 | PUT_NUM_8( off3);
|
---|
943 | else if (fUse & DISUSE_DISPLACEMENT16)
|
---|
944 | PUT_NUM_16(off3);
|
---|
945 | else if (fUse & DISUSE_DISPLACEMENT32)
|
---|
946 | PUT_NUM_32(off3);
|
---|
947 | else if (fUse & DISUSE_DISPLACEMENT64)
|
---|
948 | PUT_NUM_64(off3);
|
---|
949 | else
|
---|
950 | {
|
---|
951 | PUT_NUM_32(off3);
|
---|
952 | PUT_SZ(" wrt rip (");
|
---|
953 | off2 += pDis->uInstrAddr + pDis->cbInstr;
|
---|
954 | PUT_NUM_64(off2);
|
---|
955 | if (pfnGetSymbol)
|
---|
956 | PUT_SYMBOL((pDis->x86.fPrefix & DISPREFIX_SEG)
|
---|
957 | ? DIS_FMT_SEL_FROM_REG(pDis->x86.idxSegPrefix)
|
---|
958 | : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
|
---|
959 | pDis->x86.uAddrMode == DISCPUMODE_64BIT
|
---|
960 | ? (uint64_t)off2
|
---|
961 | : pDis->x86.uAddrMode == DISCPUMODE_32BIT
|
---|
962 | ? (uint32_t)off2
|
---|
963 | : (uint16_t)off2,
|
---|
964 | " = ",
|
---|
965 | ')');
|
---|
966 | else
|
---|
967 | PUT_C(')');
|
---|
968 | }
|
---|
969 | }
|
---|
970 |
|
---|
971 | if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
|
---|
972 | {
|
---|
973 | if (pfnGetSymbol && !fBase && !(fUse & (DISUSE_INDEX | DISUSE_RIPDISPLACEMENT32)) && off2 != 0)
|
---|
974 | PUT_SYMBOL((pDis->x86.fPrefix & DISPREFIX_SEG)
|
---|
975 | ? DIS_FMT_SEL_FROM_REG(pDis->x86.idxSegPrefix)
|
---|
976 | : DIS_FMT_SEL_FROM_REG(DISSELREG_DS),
|
---|
977 | pDis->x86.uAddrMode == DISCPUMODE_64BIT
|
---|
978 | ? (uint64_t)off2
|
---|
979 | : pDis->x86.uAddrMode == DISCPUMODE_32BIT
|
---|
980 | ? (uint32_t)off2
|
---|
981 | : (uint16_t)off2,
|
---|
982 | " (=",
|
---|
983 | ')');
|
---|
984 | PUT_C(']');
|
---|
985 | }
|
---|
986 | break;
|
---|
987 | }
|
---|
988 |
|
---|
989 | case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
|
---|
990 | AssertFailed();
|
---|
991 | break;
|
---|
992 |
|
---|
993 | case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
|
---|
994 | Assert(*pszFmt == 'b' || *pszFmt == 'v' || *pszFmt == 'w' || *pszFmt == 'z'); pszFmt++;
|
---|
995 | switch (pParam->fUse & ( DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64
|
---|
996 | | DISUSE_IMMEDIATE16_SX8 | DISUSE_IMMEDIATE32_SX8 | DISUSE_IMMEDIATE64_SX8))
|
---|
997 | {
|
---|
998 | case DISUSE_IMMEDIATE8:
|
---|
999 | if ( (fFlags & DIS_FMT_FLAGS_STRICT)
|
---|
1000 | && ( (pOp->fParam1 >= OP_PARM_REG_GEN8_START && pOp->fParam1 <= OP_PARM_REG_GEN8_END)
|
---|
1001 | || (pOp->fParam2 >= OP_PARM_REG_GEN8_START && pOp->fParam2 <= OP_PARM_REG_GEN8_END))
|
---|
1002 | )
|
---|
1003 | PUT_SZ("strict byte ");
|
---|
1004 | PUT_NUM_8(pParam->uValue);
|
---|
1005 | break;
|
---|
1006 |
|
---|
1007 | case DISUSE_IMMEDIATE16:
|
---|
1008 | if ( pDis->uCpuMode != pDis->x86.uOpMode
|
---|
1009 | || ( (fFlags & DIS_FMT_FLAGS_STRICT)
|
---|
1010 | && ( (int8_t)pParam->uValue == (int16_t)pParam->uValue
|
---|
1011 | || (pOp->fParam1 >= OP_PARM_REG_GEN16_START && pOp->fParam1 <= OP_PARM_REG_GEN16_END)
|
---|
1012 | || (pOp->fParam2 >= OP_PARM_REG_GEN16_START && pOp->fParam2 <= OP_PARM_REG_GEN16_END))
|
---|
1013 | )
|
---|
1014 | )
|
---|
1015 | {
|
---|
1016 | if (OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_b)
|
---|
1017 | PUT_SZ_STRICT("strict byte ", "byte ");
|
---|
1018 | else if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_v
|
---|
1019 | || OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_z)
|
---|
1020 | PUT_SZ_STRICT("strict word ", "word ");
|
---|
1021 | }
|
---|
1022 | PUT_NUM_16(pParam->uValue);
|
---|
1023 | break;
|
---|
1024 |
|
---|
1025 | case DISUSE_IMMEDIATE16_SX8:
|
---|
1026 | if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
|
---|
1027 | || pDis->pCurInstr->uOpcode != OP_PUSH)
|
---|
1028 | PUT_SZ_STRICT("strict byte ", "byte ");
|
---|
1029 | else
|
---|
1030 | PUT_SZ("word ");
|
---|
1031 | PUT_NUM_16(pParam->uValue);
|
---|
1032 | break;
|
---|
1033 |
|
---|
1034 | case DISUSE_IMMEDIATE32:
|
---|
1035 | if ( pDis->x86.uOpMode != (pDis->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
|
---|
1036 | || ( (fFlags & DIS_FMT_FLAGS_STRICT)
|
---|
1037 | && ( (int8_t)pParam->uValue == (int32_t)pParam->uValue
|
---|
1038 | || (pOp->fParam1 >= OP_PARM_REG_GEN32_START && pOp->fParam1 <= OP_PARM_REG_GEN32_END)
|
---|
1039 | || (pOp->fParam2 >= OP_PARM_REG_GEN32_START && pOp->fParam2 <= OP_PARM_REG_GEN32_END))
|
---|
1040 | )
|
---|
1041 | )
|
---|
1042 | {
|
---|
1043 | if (OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_b)
|
---|
1044 | PUT_SZ_STRICT("strict byte ", "byte ");
|
---|
1045 | else if ( OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_v
|
---|
1046 | || OP_PARM_VSUBTYPE(pParam->x86.fParam) == OP_PARM_z)
|
---|
1047 | PUT_SZ_STRICT("strict dword ", "dword ");
|
---|
1048 | }
|
---|
1049 | PUT_NUM_32(pParam->uValue);
|
---|
1050 | if (pDis->uCpuMode == DISCPUMODE_32BIT)
|
---|
1051 | PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uValue, " (=", ')');
|
---|
1052 | break;
|
---|
1053 |
|
---|
1054 | case DISUSE_IMMEDIATE32_SX8:
|
---|
1055 | if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
|
---|
1056 | || pDis->pCurInstr->uOpcode != OP_PUSH)
|
---|
1057 | PUT_SZ_STRICT("strict byte ", "byte ");
|
---|
1058 | else
|
---|
1059 | PUT_SZ("dword ");
|
---|
1060 | PUT_NUM_32(pParam->uValue);
|
---|
1061 | break;
|
---|
1062 |
|
---|
1063 | case DISUSE_IMMEDIATE64_SX8:
|
---|
1064 | if ( !(pDis->x86.fPrefix & DISPREFIX_OPSIZE)
|
---|
1065 | || pDis->pCurInstr->uOpcode != OP_PUSH)
|
---|
1066 | PUT_SZ_STRICT("strict byte ", "byte ");
|
---|
1067 | else
|
---|
1068 | PUT_SZ("qword ");
|
---|
1069 | PUT_NUM_64(pParam->uValue);
|
---|
1070 | break;
|
---|
1071 |
|
---|
1072 | case DISUSE_IMMEDIATE64:
|
---|
1073 | PUT_NUM_64(pParam->uValue);
|
---|
1074 | break;
|
---|
1075 |
|
---|
1076 | default:
|
---|
1077 | AssertFailed();
|
---|
1078 | break;
|
---|
1079 | }
|
---|
1080 | break;
|
---|
1081 |
|
---|
1082 | case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
|
---|
1083 | {
|
---|
1084 | int32_t offDisplacement;
|
---|
1085 | Assert(iParam == 1);
|
---|
1086 | bool fPrefix = (fFlags & DIS_FMT_FLAGS_STRICT)
|
---|
1087 | && pOp->uOpcode != OP_CALL
|
---|
1088 | && pOp->uOpcode != OP_LOOP
|
---|
1089 | && pOp->uOpcode != OP_LOOPE
|
---|
1090 | && pOp->uOpcode != OP_LOOPNE
|
---|
1091 | && pOp->uOpcode != OP_JECXZ;
|
---|
1092 | if (pOp->uOpcode == OP_CALL)
|
---|
1093 | fFlags &= ~DIS_FMT_FLAGS_RELATIVE_BRANCH;
|
---|
1094 |
|
---|
1095 | if (pParam->fUse & DISUSE_IMMEDIATE8_REL)
|
---|
1096 | {
|
---|
1097 | if (fPrefix)
|
---|
1098 | PUT_SZ("short ");
|
---|
1099 | offDisplacement = (int8_t)pParam->uValue;
|
---|
1100 | Assert(*pszFmt == 'b'); pszFmt++;
|
---|
1101 |
|
---|
1102 | if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
|
---|
1103 | PUT_NUM_S8(offDisplacement);
|
---|
1104 | }
|
---|
1105 | else if (pParam->fUse & DISUSE_IMMEDIATE16_REL)
|
---|
1106 | {
|
---|
1107 | if (fPrefix)
|
---|
1108 | PUT_SZ("near ");
|
---|
1109 | offDisplacement = (int16_t)pParam->uValue;
|
---|
1110 | Assert(*pszFmt == 'v'); pszFmt++;
|
---|
1111 |
|
---|
1112 | if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
|
---|
1113 | PUT_NUM_S16(offDisplacement);
|
---|
1114 | }
|
---|
1115 | else
|
---|
1116 | {
|
---|
1117 | if (fPrefix)
|
---|
1118 | PUT_SZ("near ");
|
---|
1119 | offDisplacement = (int32_t)pParam->uValue;
|
---|
1120 | Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL | DISUSE_IMMEDIATE64_REL));
|
---|
1121 | Assert(*pszFmt == 'v'); pszFmt++;
|
---|
1122 |
|
---|
1123 | if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
|
---|
1124 | PUT_NUM_S32(offDisplacement);
|
---|
1125 | }
|
---|
1126 | if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
|
---|
1127 | PUT_SZ(" (");
|
---|
1128 |
|
---|
1129 | RTUINTPTR uTrgAddr = pDis->uInstrAddr + pDis->cbInstr + offDisplacement;
|
---|
1130 | if (pDis->uCpuMode == DISCPUMODE_16BIT)
|
---|
1131 | PUT_NUM_16(uTrgAddr);
|
---|
1132 | else if (pDis->uCpuMode == DISCPUMODE_32BIT)
|
---|
1133 | PUT_NUM_32(uTrgAddr);
|
---|
1134 | else
|
---|
1135 | PUT_NUM_64(uTrgAddr);
|
---|
1136 |
|
---|
1137 | if (fFlags & DIS_FMT_FLAGS_RELATIVE_BRANCH)
|
---|
1138 | {
|
---|
1139 | PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " = ", ' ');
|
---|
1140 | PUT_C(')');
|
---|
1141 | }
|
---|
1142 | else
|
---|
1143 | PUT_SYMBOL(DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, " (", ')');
|
---|
1144 | break;
|
---|
1145 | }
|
---|
1146 |
|
---|
1147 | case 'A': /* Direct (jump/call) address (ParseImmAddr). */
|
---|
1148 | {
|
---|
1149 | Assert(*pszFmt == 'p'); pszFmt++;
|
---|
1150 | PUT_FAR();
|
---|
1151 | PUT_SIZE_OVERRIDE();
|
---|
1152 | PUT_SEGMENT_OVERRIDE();
|
---|
1153 | off = 0;
|
---|
1154 | int rc = VERR_SYMBOL_NOT_FOUND;
|
---|
1155 | switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
|
---|
1156 | {
|
---|
1157 | case DISUSE_IMMEDIATE_ADDR_16_16:
|
---|
1158 | PUT_NUM_16(pParam->uValue >> 16);
|
---|
1159 | PUT_C(':');
|
---|
1160 | PUT_NUM_16(pParam->uValue);
|
---|
1161 | if (pfnGetSymbol)
|
---|
1162 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1163 | break;
|
---|
1164 | case DISUSE_IMMEDIATE_ADDR_16_32:
|
---|
1165 | PUT_NUM_16(pParam->uValue >> 32);
|
---|
1166 | PUT_C(':');
|
---|
1167 | PUT_NUM_32(pParam->uValue);
|
---|
1168 | if (pfnGetSymbol)
|
---|
1169 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1170 | break;
|
---|
1171 | case DISUSE_DISPLACEMENT16:
|
---|
1172 | PUT_NUM_16(pParam->uValue);
|
---|
1173 | if (pfnGetSymbol)
|
---|
1174 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1175 | break;
|
---|
1176 | case DISUSE_DISPLACEMENT32:
|
---|
1177 | PUT_NUM_32(pParam->uValue);
|
---|
1178 | if (pfnGetSymbol)
|
---|
1179 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1180 | break;
|
---|
1181 | case DISUSE_DISPLACEMENT64:
|
---|
1182 | PUT_NUM_64(pParam->uValue);
|
---|
1183 | if (pfnGetSymbol)
|
---|
1184 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1185 | break;
|
---|
1186 | default:
|
---|
1187 | AssertFailed();
|
---|
1188 | break;
|
---|
1189 | }
|
---|
1190 |
|
---|
1191 | PUT_SYMBOL_TWO(rc, " [", ']');
|
---|
1192 | break;
|
---|
1193 | }
|
---|
1194 |
|
---|
1195 | case 'O': /* No ModRM byte (ParseImmAddr). */
|
---|
1196 | {
|
---|
1197 | Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
|
---|
1198 | PUT_FAR();
|
---|
1199 | PUT_SIZE_OVERRIDE();
|
---|
1200 | PUT_C('[');
|
---|
1201 | PUT_SEGMENT_OVERRIDE();
|
---|
1202 | off = 0;
|
---|
1203 | int rc = VERR_SYMBOL_NOT_FOUND;
|
---|
1204 | switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
|
---|
1205 | {
|
---|
1206 | case DISUSE_IMMEDIATE_ADDR_16_16:
|
---|
1207 | PUT_NUM_16(pParam->uValue >> 16);
|
---|
1208 | PUT_C(':');
|
---|
1209 | PUT_NUM_16(pParam->uValue);
|
---|
1210 | if (pfnGetSymbol)
|
---|
1211 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint16_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1212 | break;
|
---|
1213 | case DISUSE_IMMEDIATE_ADDR_16_32:
|
---|
1214 | PUT_NUM_16(pParam->uValue >> 32);
|
---|
1215 | PUT_C(':');
|
---|
1216 | PUT_NUM_32(pParam->uValue);
|
---|
1217 | if (pfnGetSymbol)
|
---|
1218 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_VALUE(pParam->uValue >> 16), (uint32_t)pParam->uValue, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1219 | break;
|
---|
1220 | case DISUSE_DISPLACEMENT16:
|
---|
1221 | PUT_NUM_16(pParam->x86.uDisp.i16);
|
---|
1222 | if (pfnGetSymbol)
|
---|
1223 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1224 | break;
|
---|
1225 | case DISUSE_DISPLACEMENT32:
|
---|
1226 | PUT_NUM_32(pParam->x86.uDisp.i32);
|
---|
1227 | if (pfnGetSymbol)
|
---|
1228 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1229 | break;
|
---|
1230 | case DISUSE_DISPLACEMENT64:
|
---|
1231 | PUT_NUM_64(pParam->x86.uDisp.i64);
|
---|
1232 | if (pfnGetSymbol)
|
---|
1233 | rc = pfnGetSymbol(pDis, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->x86.uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
|
---|
1234 | break;
|
---|
1235 | default:
|
---|
1236 | AssertFailed();
|
---|
1237 | break;
|
---|
1238 | }
|
---|
1239 | PUT_C(']');
|
---|
1240 |
|
---|
1241 | PUT_SYMBOL_TWO(rc, " (", ')');
|
---|
1242 | break;
|
---|
1243 | }
|
---|
1244 |
|
---|
1245 | case 'X': /* DS:SI (ParseXb, ParseXv). */
|
---|
1246 | case 'Y': /* ES:DI (ParseYb, ParseYv). */
|
---|
1247 | {
|
---|
1248 | Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
|
---|
1249 | PUT_FAR();
|
---|
1250 | PUT_SIZE_OVERRIDE();
|
---|
1251 | PUT_C('[');
|
---|
1252 | if (pParam->fUse & DISUSE_POINTER_DS_BASED)
|
---|
1253 | PUT_SZ("ds:");
|
---|
1254 | else
|
---|
1255 | PUT_SZ("es:");
|
---|
1256 |
|
---|
1257 | size_t cchReg;
|
---|
1258 | const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
|
---|
1259 | PUT_STR(pszReg, cchReg);
|
---|
1260 | PUT_C(']');
|
---|
1261 | break;
|
---|
1262 | }
|
---|
1263 |
|
---|
1264 | case 'e': /* Register based on operand size (e.g. %eAX, %eAH) (ParseFixedReg). */
|
---|
1265 | {
|
---|
1266 | Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2]));
|
---|
1267 | pszFmt += 2;
|
---|
1268 | size_t cchReg;
|
---|
1269 | const char *pszReg = disasmFormatYasmBaseReg(pDis, pParam, &cchReg);
|
---|
1270 | PUT_STR(pszReg, cchReg);
|
---|
1271 | break;
|
---|
1272 | }
|
---|
1273 |
|
---|
1274 | default:
|
---|
1275 | AssertMsgFailed(("%c%s!\n", ch, pszFmt));
|
---|
1276 | break;
|
---|
1277 | }
|
---|
1278 | AssertMsg(*pszFmt == ',' || *pszFmt == '\0', ("%c%s\n", ch, pszFmt));
|
---|
1279 | }
|
---|
1280 | else
|
---|
1281 | {
|
---|
1282 | PUT_C(ch);
|
---|
1283 | if (ch == ',')
|
---|
1284 | {
|
---|
1285 | Assert(*pszFmt != ' ');
|
---|
1286 | PUT_C(' ');
|
---|
1287 | switch (++iParam)
|
---|
1288 | {
|
---|
1289 | case 2: pParam = &pDis->Param2; break;
|
---|
1290 | case 3: pParam = &pDis->Param3; break;
|
---|
1291 | case 4: pParam = &pDis->Param4; break;
|
---|
1292 | default: pParam = NULL; break;
|
---|
1293 | }
|
---|
1294 | }
|
---|
1295 | }
|
---|
1296 | } /* while more to format */
|
---|
1297 | }
|
---|
1298 |
|
---|
1299 | /*
|
---|
1300 | * Any additional output to the right of the instruction?
|
---|
1301 | */
|
---|
1302 | if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
|
---|
1303 | {
|
---|
1304 | /* some up front padding. */
|
---|
1305 | size_t cchPadding = cchOutput - offInstruction;
|
---|
1306 | cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
|
---|
1307 | PUT_STR(g_szSpaces, cchPadding);
|
---|
1308 |
|
---|
1309 | /* comment? */
|
---|
1310 | if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
|
---|
1311 | PUT_SZ(";");
|
---|
1312 |
|
---|
1313 | /*
|
---|
1314 | * The address?
|
---|
1315 | */
|
---|
1316 | if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
|
---|
1317 | {
|
---|
1318 | PUT_C(' ');
|
---|
1319 | #if HC_ARCH_BITS == 64 || GC_ARCH_BITS == 64
|
---|
1320 | if (pDis->uInstrAddr >= _4G)
|
---|
1321 | PUT_NUM(9, "%08x`", (uint32_t)(pDis->uInstrAddr >> 32));
|
---|
1322 | #endif
|
---|
1323 | PUT_NUM(8, "%08x", (uint32_t)pDis->uInstrAddr);
|
---|
1324 | }
|
---|
1325 |
|
---|
1326 | /*
|
---|
1327 | * Opcode bytes?
|
---|
1328 | */
|
---|
1329 | if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
|
---|
1330 | {
|
---|
1331 | PUT_C(' ');
|
---|
1332 | size_t cchTmp = disFormatBytes(pDis, pszDst, cchDst, fFlags);
|
---|
1333 | cchOutput += cchTmp;
|
---|
1334 | if (cchTmp >= cchDst)
|
---|
1335 | cchTmp = cchDst - (cchDst != 0);
|
---|
1336 | cchDst -= cchTmp;
|
---|
1337 | pszDst += cchTmp;
|
---|
1338 | }
|
---|
1339 | }
|
---|
1340 |
|
---|
1341 | /*
|
---|
1342 | * Terminate it - on overflow we'll have reserved one byte for this.
|
---|
1343 | */
|
---|
1344 | if (cchDst > 0)
|
---|
1345 | *pszDst = '\0';
|
---|
1346 | else
|
---|
1347 | Assert(!cchBuf);
|
---|
1348 |
|
---|
1349 | /* clean up macros */
|
---|
1350 | #undef PUT_PSZ
|
---|
1351 | #undef PUT_SZ
|
---|
1352 | #undef PUT_STR
|
---|
1353 | #undef PUT_C
|
---|
1354 | return cchOutput;
|
---|
1355 | }
|
---|
1356 |
|
---|
1357 |
|
---|
1358 | /**
|
---|
1359 | * Formats the current instruction in Yasm (/ Nasm) style.
|
---|
1360 | *
|
---|
1361 | * This is a simplified version of DISFormatYasmEx() provided for your convenience.
|
---|
1362 | *
|
---|
1363 | *
|
---|
1364 | * @returns The number of output characters. If this is >= cchBuf, then the content
|
---|
1365 | * of pszBuf will be truncated.
|
---|
1366 | * @param pDis Pointer to the disassembler state.
|
---|
1367 | * @param pszBuf The output buffer.
|
---|
1368 | * @param cchBuf The size of the output buffer.
|
---|
1369 | */
|
---|
1370 | DISDECL(size_t) DISFormatYasm(PCDISSTATE pDis, char *pszBuf, size_t cchBuf)
|
---|
1371 | {
|
---|
1372 | return DISFormatYasmEx(pDis, pszBuf, cchBuf, 0 /* fFlags */, NULL /* pfnGetSymbol */, NULL /* pvUser */);
|
---|
1373 | }
|
---|
1374 |
|
---|
1375 |
|
---|
1376 | /**
|
---|
1377 | * Checks if the encoding of the given disassembled instruction is something we
|
---|
1378 | * can never get YASM to produce.
|
---|
1379 | *
|
---|
1380 | * @returns true if it's odd, false if it isn't.
|
---|
1381 | * @param pDis The disassembler output. The byte fetcher callback will
|
---|
1382 | * be used if present as we might need to fetch opcode
|
---|
1383 | * bytes.
|
---|
1384 | */
|
---|
1385 | DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis)
|
---|
1386 | {
|
---|
1387 | /*
|
---|
1388 | * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
|
---|
1389 | */
|
---|
1390 | if ( pDis->x86.uAddrMode != DISCPUMODE_16BIT /// @todo correct?
|
---|
1391 | && pDis->x86.ModRM.Bits.Rm == 4
|
---|
1392 | && pDis->x86.ModRM.Bits.Mod != 3)
|
---|
1393 | {
|
---|
1394 | /* No scaled index SIB (index=4), except for ESP. */
|
---|
1395 | if ( pDis->x86.SIB.Bits.Index == 4
|
---|
1396 | && pDis->x86.SIB.Bits.Base != 4)
|
---|
1397 | return true;
|
---|
1398 |
|
---|
1399 | /* EBP + displacement */
|
---|
1400 | if ( pDis->x86.ModRM.Bits.Mod != 0
|
---|
1401 | && pDis->x86.SIB.Bits.Base == 5
|
---|
1402 | && pDis->x86.SIB.Bits.Scale == 0)
|
---|
1403 | return true;
|
---|
1404 | }
|
---|
1405 |
|
---|
1406 | /*
|
---|
1407 | * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
|
---|
1408 | */
|
---|
1409 | if ( pDis->pCurInstr->uOpcode == OP_SHL
|
---|
1410 | && pDis->x86.ModRM.Bits.Reg == 6)
|
---|
1411 | return true;
|
---|
1412 |
|
---|
1413 | /*
|
---|
1414 | * Check for multiple prefixes of the same kind.
|
---|
1415 | */
|
---|
1416 | uint8_t off1stSeg = UINT8_MAX;
|
---|
1417 | uint8_t offOpSize = UINT8_MAX;
|
---|
1418 | uint8_t offAddrSize = UINT8_MAX;
|
---|
1419 | uint32_t fPrefixes = 0;
|
---|
1420 | for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pDis->Instr.ab); offOpcode++)
|
---|
1421 | {
|
---|
1422 | uint32_t f;
|
---|
1423 | switch (pDis->Instr.ab[offOpcode])
|
---|
1424 | {
|
---|
1425 | case 0xf0:
|
---|
1426 | f = DISPREFIX_LOCK;
|
---|
1427 | break;
|
---|
1428 |
|
---|
1429 | case 0xf2:
|
---|
1430 | case 0xf3:
|
---|
1431 | f = DISPREFIX_REP; /* yes, both */
|
---|
1432 | break;
|
---|
1433 |
|
---|
1434 | case 0x2e:
|
---|
1435 | case 0x3e:
|
---|
1436 | case 0x26:
|
---|
1437 | case 0x36:
|
---|
1438 | case 0x64:
|
---|
1439 | case 0x65:
|
---|
1440 | if (off1stSeg == UINT8_MAX)
|
---|
1441 | off1stSeg = offOpcode;
|
---|
1442 | f = DISPREFIX_SEG;
|
---|
1443 | break;
|
---|
1444 |
|
---|
1445 | case 0x66:
|
---|
1446 | if (offOpSize == UINT8_MAX)
|
---|
1447 | offOpSize = offOpcode;
|
---|
1448 | f = DISPREFIX_OPSIZE;
|
---|
1449 | break;
|
---|
1450 |
|
---|
1451 | case 0x67:
|
---|
1452 | if (offAddrSize == UINT8_MAX)
|
---|
1453 | offAddrSize = offOpcode;
|
---|
1454 | f = DISPREFIX_ADDRSIZE;
|
---|
1455 | break;
|
---|
1456 |
|
---|
1457 | case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
|
---|
1458 | case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
|
---|
1459 | f = pDis->uCpuMode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
|
---|
1460 | break;
|
---|
1461 |
|
---|
1462 | default:
|
---|
1463 | f = 0;
|
---|
1464 | break;
|
---|
1465 | }
|
---|
1466 | if (!f)
|
---|
1467 | break; /* done */
|
---|
1468 | if (fPrefixes & f)
|
---|
1469 | return true;
|
---|
1470 | fPrefixes |= f;
|
---|
1471 | }
|
---|
1472 |
|
---|
1473 | /* segment overrides are fun */
|
---|
1474 | if (fPrefixes & DISPREFIX_SEG)
|
---|
1475 | {
|
---|
1476 | /* no effective address which it may apply to. */
|
---|
1477 | Assert((pDis->x86.fPrefix & DISPREFIX_SEG) || pDis->uCpuMode == DISCPUMODE_64BIT);
|
---|
1478 | if ( !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param1.fUse)
|
---|
1479 | && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param2.fUse)
|
---|
1480 | && !DISUSE_IS_EFFECTIVE_ADDR(pDis->Param3.fUse))
|
---|
1481 | return true;
|
---|
1482 |
|
---|
1483 | /* Yasm puts the segment prefixes before the operand prefix with no
|
---|
1484 | way of overriding it. */
|
---|
1485 | if (offOpSize < off1stSeg)
|
---|
1486 | return true;
|
---|
1487 | }
|
---|
1488 |
|
---|
1489 | /* fixed register + addr override doesn't go down all that well. */
|
---|
1490 | if (fPrefixes & DISPREFIX_ADDRSIZE)
|
---|
1491 | {
|
---|
1492 | Assert(pDis->x86.fPrefix & DISPREFIX_ADDRSIZE);
|
---|
1493 | if ( pDis->pCurInstr->fParam3 == OP_PARM_NONE
|
---|
1494 | && pDis->pCurInstr->fParam2 == OP_PARM_NONE
|
---|
1495 | && ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
|
---|
1496 | && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END))
|
---|
1497 | return true;
|
---|
1498 | }
|
---|
1499 |
|
---|
1500 | /* Almost all prefixes are bad for jumps. */
|
---|
1501 | if (fPrefixes)
|
---|
1502 | {
|
---|
1503 | switch (pDis->pCurInstr->uOpcode)
|
---|
1504 | {
|
---|
1505 | /* nop w/ prefix(es). */
|
---|
1506 | case OP_NOP:
|
---|
1507 | return true;
|
---|
1508 |
|
---|
1509 | case OP_JMP:
|
---|
1510 | if ( pDis->pCurInstr->fParam1 != OP_PARM_Jb
|
---|
1511 | && pDis->pCurInstr->fParam1 != OP_PARM_Jv)
|
---|
1512 | break;
|
---|
1513 | RT_FALL_THRU();
|
---|
1514 | case OP_JO:
|
---|
1515 | case OP_JNO:
|
---|
1516 | case OP_JC:
|
---|
1517 | case OP_JNC:
|
---|
1518 | case OP_JE:
|
---|
1519 | case OP_JNE:
|
---|
1520 | case OP_JBE:
|
---|
1521 | case OP_JNBE:
|
---|
1522 | case OP_JS:
|
---|
1523 | case OP_JNS:
|
---|
1524 | case OP_JP:
|
---|
1525 | case OP_JNP:
|
---|
1526 | case OP_JL:
|
---|
1527 | case OP_JNL:
|
---|
1528 | case OP_JLE:
|
---|
1529 | case OP_JNLE:
|
---|
1530 | /** @todo branch hinting 0x2e/0x3e... */
|
---|
1531 | return true;
|
---|
1532 | }
|
---|
1533 |
|
---|
1534 | }
|
---|
1535 |
|
---|
1536 | /* All but the segment prefix is bad news for push/pop. */
|
---|
1537 | if (fPrefixes & ~DISPREFIX_SEG)
|
---|
1538 | {
|
---|
1539 | switch (pDis->pCurInstr->uOpcode)
|
---|
1540 | {
|
---|
1541 | case OP_POP:
|
---|
1542 | case OP_PUSH:
|
---|
1543 | if ( pDis->pCurInstr->fParam1 >= OP_PARM_REG_SEG_START
|
---|
1544 | && pDis->pCurInstr->fParam1 <= OP_PARM_REG_SEG_END)
|
---|
1545 | return true;
|
---|
1546 | if ( (fPrefixes & ~DISPREFIX_OPSIZE)
|
---|
1547 | && pDis->pCurInstr->fParam1 >= OP_PARM_REG_GEN32_START
|
---|
1548 | && pDis->pCurInstr->fParam1 <= OP_PARM_REG_GEN32_END)
|
---|
1549 | return true;
|
---|
1550 | break;
|
---|
1551 |
|
---|
1552 | case OP_POPA:
|
---|
1553 | case OP_POPF:
|
---|
1554 | case OP_PUSHA:
|
---|
1555 | case OP_PUSHF:
|
---|
1556 | if (fPrefixes & ~DISPREFIX_OPSIZE)
|
---|
1557 | return true;
|
---|
1558 | break;
|
---|
1559 | }
|
---|
1560 | }
|
---|
1561 |
|
---|
1562 | /* Implicit 8-bit register instructions doesn't mix with operand size. */
|
---|
1563 | if ( (fPrefixes & DISPREFIX_OPSIZE)
|
---|
1564 | && ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
|
---|
1565 | && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
|
---|
1566 | || ( pDis->pCurInstr->fParam2 == OP_PARM_Gb /* r8 */
|
---|
1567 | && pDis->pCurInstr->fParam1 == OP_PARM_Eb /* r8/mem8 */))
|
---|
1568 | )
|
---|
1569 | {
|
---|
1570 | switch (pDis->pCurInstr->uOpcode)
|
---|
1571 | {
|
---|
1572 | case OP_ADD:
|
---|
1573 | case OP_OR:
|
---|
1574 | case OP_ADC:
|
---|
1575 | case OP_SBB:
|
---|
1576 | case OP_AND:
|
---|
1577 | case OP_SUB:
|
---|
1578 | case OP_XOR:
|
---|
1579 | case OP_CMP:
|
---|
1580 | return true;
|
---|
1581 | default:
|
---|
1582 | break;
|
---|
1583 | }
|
---|
1584 | }
|
---|
1585 |
|
---|
1586 | /* Instructions taking no address or operand which thus may be annoyingly
|
---|
1587 | difficult to format for yasm. */
|
---|
1588 | if (fPrefixes)
|
---|
1589 | {
|
---|
1590 | switch (pDis->pCurInstr->uOpcode)
|
---|
1591 | {
|
---|
1592 | case OP_STI:
|
---|
1593 | case OP_STC:
|
---|
1594 | case OP_CLI:
|
---|
1595 | case OP_CLD:
|
---|
1596 | case OP_CLC:
|
---|
1597 | case OP_INT:
|
---|
1598 | case OP_INT3:
|
---|
1599 | case OP_INTO:
|
---|
1600 | case OP_HLT:
|
---|
1601 | /** @todo Many more to can be added here. */
|
---|
1602 | return true;
|
---|
1603 | default:
|
---|
1604 | break;
|
---|
1605 | }
|
---|
1606 | }
|
---|
1607 |
|
---|
1608 | /* FPU and other instructions that ignores operand size override. */
|
---|
1609 | if (fPrefixes & DISPREFIX_OPSIZE)
|
---|
1610 | {
|
---|
1611 | switch (pDis->pCurInstr->uOpcode)
|
---|
1612 | {
|
---|
1613 | /* FPU: */
|
---|
1614 | case OP_FIADD:
|
---|
1615 | case OP_FIMUL:
|
---|
1616 | case OP_FISUB:
|
---|
1617 | case OP_FISUBR:
|
---|
1618 | case OP_FIDIV:
|
---|
1619 | case OP_FIDIVR:
|
---|
1620 | /** @todo there are many more. */
|
---|
1621 | return true;
|
---|
1622 |
|
---|
1623 | case OP_MOV:
|
---|
1624 | /** @todo could be that we're not disassembling these correctly. */
|
---|
1625 | if (pDis->pCurInstr->fParam1 == OP_PARM_Sw)
|
---|
1626 | return true;
|
---|
1627 | /** @todo what about the other way? */
|
---|
1628 | break;
|
---|
1629 |
|
---|
1630 | default:
|
---|
1631 | break;
|
---|
1632 | }
|
---|
1633 | }
|
---|
1634 |
|
---|
1635 |
|
---|
1636 | /*
|
---|
1637 | * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
|
---|
1638 | *
|
---|
1639 | * For example:
|
---|
1640 | * expected: 1aee sbb ch, dh ; SBB r8, r/m8
|
---|
1641 | * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
|
---|
1642 | */
|
---|
1643 | if (pDis->x86.ModRM.Bits.Mod == 3 /* reg,reg */)
|
---|
1644 | {
|
---|
1645 | switch (pDis->pCurInstr->uOpcode)
|
---|
1646 | {
|
---|
1647 | case OP_ADD:
|
---|
1648 | case OP_OR:
|
---|
1649 | case OP_ADC:
|
---|
1650 | case OP_SBB:
|
---|
1651 | case OP_AND:
|
---|
1652 | case OP_SUB:
|
---|
1653 | case OP_XOR:
|
---|
1654 | case OP_CMP:
|
---|
1655 | if ( ( pDis->pCurInstr->fParam1 == OP_PARM_Gb /* r8 */
|
---|
1656 | && pDis->pCurInstr->fParam2 == OP_PARM_Eb /* r8/mem8 */)
|
---|
1657 | || ( pDis->pCurInstr->fParam1 == OP_PARM_Gv /* rX */
|
---|
1658 | && pDis->pCurInstr->fParam2 == OP_PARM_Ev /* rX/memX */))
|
---|
1659 | return true;
|
---|
1660 |
|
---|
1661 | /* 82 (see table A-6). */
|
---|
1662 | if (pDis->x86.bOpCode == 0x82)
|
---|
1663 | return true;
|
---|
1664 | break;
|
---|
1665 |
|
---|
1666 | /* ff /0, fe /0, ff /1, fe /0 */
|
---|
1667 | case OP_DEC:
|
---|
1668 | case OP_INC:
|
---|
1669 | return true;
|
---|
1670 |
|
---|
1671 | case OP_POP:
|
---|
1672 | case OP_PUSH:
|
---|
1673 | Assert(pDis->x86.bOpCode == 0x8f);
|
---|
1674 | return true;
|
---|
1675 |
|
---|
1676 | case OP_MOV:
|
---|
1677 | if ( pDis->x86.bOpCode == 0x8a
|
---|
1678 | || pDis->x86.bOpCode == 0x8b)
|
---|
1679 | return true;
|
---|
1680 | break;
|
---|
1681 |
|
---|
1682 | default:
|
---|
1683 | break;
|
---|
1684 | }
|
---|
1685 | }
|
---|
1686 |
|
---|
1687 | /* shl eax,1 will be assembled to the form without the immediate byte. */
|
---|
1688 | if ( pDis->pCurInstr->fParam2 == OP_PARM_Ib
|
---|
1689 | && (uint8_t)pDis->Param2.uValue == 1)
|
---|
1690 | {
|
---|
1691 | switch (pDis->pCurInstr->uOpcode)
|
---|
1692 | {
|
---|
1693 | case OP_SHL:
|
---|
1694 | case OP_SHR:
|
---|
1695 | case OP_SAR:
|
---|
1696 | case OP_RCL:
|
---|
1697 | case OP_RCR:
|
---|
1698 | case OP_ROL:
|
---|
1699 | case OP_ROR:
|
---|
1700 | return true;
|
---|
1701 | }
|
---|
1702 | }
|
---|
1703 |
|
---|
1704 | /* And some more - see table A-6. */
|
---|
1705 | if (pDis->x86.bOpCode == 0x82)
|
---|
1706 | {
|
---|
1707 | switch (pDis->pCurInstr->uOpcode)
|
---|
1708 | {
|
---|
1709 | case OP_ADD:
|
---|
1710 | case OP_OR:
|
---|
1711 | case OP_ADC:
|
---|
1712 | case OP_SBB:
|
---|
1713 | case OP_AND:
|
---|
1714 | case OP_SUB:
|
---|
1715 | case OP_XOR:
|
---|
1716 | case OP_CMP:
|
---|
1717 | return true;
|
---|
1718 | break;
|
---|
1719 | }
|
---|
1720 | }
|
---|
1721 |
|
---|
1722 |
|
---|
1723 | /* check for REX.X = 1 without SIB. */
|
---|
1724 |
|
---|
1725 | /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
|
---|
1726 | says (intel doesn't appear to care). */
|
---|
1727 | switch (pDis->pCurInstr->uOpcode)
|
---|
1728 | {
|
---|
1729 | case OP_SETO:
|
---|
1730 | case OP_SETNO:
|
---|
1731 | case OP_SETC:
|
---|
1732 | case OP_SETNC:
|
---|
1733 | case OP_SETE:
|
---|
1734 | case OP_SETNE:
|
---|
1735 | case OP_SETBE:
|
---|
1736 | case OP_SETNBE:
|
---|
1737 | case OP_SETS:
|
---|
1738 | case OP_SETNS:
|
---|
1739 | case OP_SETP:
|
---|
1740 | case OP_SETNP:
|
---|
1741 | case OP_SETL:
|
---|
1742 | case OP_SETNL:
|
---|
1743 | case OP_SETLE:
|
---|
1744 | case OP_SETNLE:
|
---|
1745 | AssertMsg(pDis->x86.bOpCode >= 0x90 && pDis->x86.bOpCode <= 0x9f, ("%#x\n", pDis->x86.bOpCode));
|
---|
1746 | if (pDis->x86.ModRM.Bits.Reg != 2)
|
---|
1747 | return true;
|
---|
1748 | break;
|
---|
1749 | }
|
---|
1750 |
|
---|
1751 | /*
|
---|
1752 | * The MOVZX reg32,mem16 instruction without an operand size prefix
|
---|
1753 | * doesn't quite make sense...
|
---|
1754 | */
|
---|
1755 | if ( pDis->pCurInstr->uOpcode == OP_MOVZX
|
---|
1756 | && pDis->x86.bOpCode == 0xB7
|
---|
1757 | && (pDis->uCpuMode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
|
---|
1758 | return true;
|
---|
1759 |
|
---|
1760 | /*
|
---|
1761 | * YASM doesn't do ICEBP/INT1/INT01, unlike NASM.
|
---|
1762 | */
|
---|
1763 | if (pDis->x86.bOpCode == 0xF1)
|
---|
1764 | return true;
|
---|
1765 |
|
---|
1766 | return false;
|
---|
1767 | }
|
---|
1768 |
|
---|