DevLsiLogicSCSI.h@ 81744

Last change on this file since 81744 was 81744, checked in by vboxsync, 6 years ago
DevLsiLogicSCSI.h: Kicked out a lot of unnecessary #pragma pack(1). The ones around MptConfigurationPagesSas being very much out of place. bugref:9218
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1	/* $Id: DevLsiLogicSCSI.h 81744 2019-11-07 19:14:18Z vboxsync $ */
2	/** @file
3	* VBox storage devices: LsiLogic LSI53c1030 SCSI controller - Defines and structures.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Storage_DevLsiLogicSCSI_h
19	#define VBOX_INCLUDED_SRC_Storage_DevLsiLogicSCSI_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/stdint.h>
25
26	/*
27	* Custom fixed I/O ports for BIOS controller access. Note that these should
28	* not be in the ISA range (below 400h) to avoid conflicts with ISA device
29	* probing. Addresses in the 300h-340h range should be especially avoided.
30	*/
31	#define LSILOGIC_BIOS_IO_PORT 0x434
32	#define LSILOGIC_SAS_BIOS_IO_PORT 0x438
33
34	#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT 256
35	#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT 256
36
37	#define LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH 3
38
39	#define LSILOGIC_NR_OF_ALLOWED_BIGGER_LISTS 100
40
41	/** Equal for all devices */
42	#define LSILOGICSCSI_PCI_VENDOR_ID (0x1000)
43
44	/** SPI SCSI controller (LSI53C1030) */
45	#define LSILOGICSCSI_PCI_SPI_CTRLNAME "LSI53C1030"
46	#define LSILOGICSCSI_PCI_SPI_DEVICE_ID (0x0030)
47	#define LSILOGICSCSI_PCI_SPI_REVISION_ID (0x00)
48	#define LSILOGICSCSI_PCI_SPI_CLASS_CODE (0x01)
49	#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID (0x1000)
50	#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID (0x8000)
51	#define LSILOGICSCSI_PCI_SPI_PORTS_MAX 1
52	#define LSILOGICSCSI_PCI_SPI_BUSES_MAX 1
53	#define LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX 16
54	#define LSILOGICSCSI_PCI_SPI_DEVICES_MAX (LSILOGICSCSI_PCI_SPI_BUSES_MAX*LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX)
55
56	/** SAS SCSI controller (SAS1068 PCI-X Fusion-MPT SAS) */
57	#define LSILOGICSCSI_PCI_SAS_CTRLNAME "SAS1068"
58	#define LSILOGICSCSI_PCI_SAS_DEVICE_ID (0x0054)
59	#define LSILOGICSCSI_PCI_SAS_REVISION_ID (0x00)
60	#define LSILOGICSCSI_PCI_SAS_CLASS_CODE (0x00)
61	#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID (0x1000)
62	#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID (0x8000)
63	#define LSILOGICSCSI_PCI_SAS_PORTS_MAX 256
64	#define LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT 8
65	#define LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX 1
66	#define LSILOGICSCSI_PCI_SAS_DEVICES_MAX (LSILOGICSCSI_PCI_SAS_PORTS_MAX * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX)
67
68	/**
69	* A SAS address.
70	*/
71	typedef union SASADDRESS
72	{
73	/** 64bit view. */
74	uint64_t u64Address;
75	/** 32bit view. */
76	uint32_t u32Address[2];
77	/** 16bit view. */
78	uint16_t u16Address[4];
79	/** Byte view. */
80	uint8_t u8Address[8];
81	} SASADDRESS, *PSASADDRESS;
82	AssertCompileSize(SASADDRESS, 8);
83
84	/**
85	* Possible device types we support.
86	*/
87	typedef enum LSILOGICCTRLTYPE
88	{
89	/** SPI SCSI controller (PCI dev id 0x0030) */
90	LSILOGICCTRLTYPE_SCSI_SPI = 0,
91	/** SAS SCSI controller (PCI dev id 0x0054) */
92	LSILOGICCTRLTYPE_SCSI_SAS = 1,
93	/** 32bit hack */
94	LSILOGICCTRLTYPE_32BIT_HACK = 0x7fffffff
95	} LSILOGICCTRLTYPE, *PLSILOGICCTRLTYPE;
96
97	/**
98	* A simple SG element for a 64bit address.
99	*/
100	typedef struct MptSGEntrySimple64
101	{
102	/** Length of the buffer this entry describes. */
103	unsigned u24Length: 24;
104	/** Flag whether this element is the end of the list. */
105	unsigned fEndOfList: 1;
106	/** Flag whether the address is 32bit or 64bits wide. */
107	unsigned f64BitAddress: 1;
108	/** Flag whether this buffer contains data to be transferred or is the destination. */
109	unsigned fBufferContainsData: 1;
110	/** Flag whether this is a local address or a system address. */
111	unsigned fLocalAddress: 1;
112	/** Element type. */
113	unsigned u2ElementType: 2;
114	/** Flag whether this is the last element of the buffer. */
115	unsigned fEndOfBuffer: 1;
116	/** Flag whether this is the last element of the current segment. */
117	unsigned fLastElement: 1;
118	/** Lower 32bits of the address of the data buffer. */
119	unsigned u32DataBufferAddressLow: 32;
120	/** Upper 32bits of the address of the data buffer. */
121	unsigned u32DataBufferAddressHigh: 32;
122	} MptSGEntrySimple64, *PMptSGEntrySimple64;
123	AssertCompileSize(MptSGEntrySimple64, 12);
124
125	/**
126	* A simple SG element for a 32bit address.
127	*/
128	typedef struct MptSGEntrySimple32
129	{
130	/** Length of the buffer this entry describes. */
131	unsigned u24Length: 24;
132	/** Flag whether this element is the end of the list. */
133	unsigned fEndOfList: 1;
134	/** Flag whether the address is 32bit or 64bits wide. */
135	unsigned f64BitAddress: 1;
136	/** Flag whether this buffer contains data to be transferred or is the destination. */
137	unsigned fBufferContainsData: 1;
138	/** Flag whether this is a local address or a system address. */
139	unsigned fLocalAddress: 1;
140	/** Element type. */
141	unsigned u2ElementType: 2;
142	/** Flag whether this is the last element of the buffer. */
143	unsigned fEndOfBuffer: 1;
144	/** Flag whether this is the last element of the current segment. */
145	unsigned fLastElement: 1;
146	/** Lower 32bits of the address of the data buffer. */
147	unsigned u32DataBufferAddressLow: 32;
148	} MptSGEntrySimple32, *PMptSGEntrySimple32;
149	AssertCompileSize(MptSGEntrySimple32, 8);
150
151	/**
152	* A chain SG element.
153	*/
154	typedef struct MptSGEntryChain
155	{
156	/** Size of the segment. */
157	unsigned u16Length: 16;
158	/** Offset in 32bit words of the next chain element in the segment
159	* identified by this element. */
160	unsigned u8NextChainOffset: 8;
161	/** Reserved. */
162	unsigned fReserved0: 1;
163	/** Flag whether the address is 32bit or 64bits wide. */
164	unsigned f64BitAddress: 1;
165	/** Reserved. */
166	unsigned fReserved1: 1;
167	/** Flag whether this is a local address or a system address. */
168	unsigned fLocalAddress: 1;
169	/** Element type. */
170	unsigned u2ElementType: 2;
171	/** Flag whether this is the last element of the buffer. */
172	unsigned u2Reserved2: 2;
173	/** Lower 32bits of the address of the data buffer. */
174	unsigned u32SegmentAddressLow: 32;
175	/** Upper 32bits of the address of the data buffer. */
176	unsigned u32SegmentAddressHigh: 32;
177	} MptSGEntryChain, *PMptSGEntryChain;
178	AssertCompileSize(MptSGEntryChain, 12);
179
180	typedef union MptSGEntryUnion
181	{
182	MptSGEntrySimple64 Simple64;
183	MptSGEntrySimple32 Simple32;
184	MptSGEntryChain Chain;
185	} MptSGEntryUnion, *PMptSGEntryUnion;
186
187	/**
188	* MPT Fusion message header - Common for all message frames.
189	* This is filled in by the guest.
190	*/
191	typedef struct MptMessageHdr
192	{
193	/** Function dependent data. */
194	uint16_t u16FunctionDependent;
195	/** Chain offset. */
196	uint8_t u8ChainOffset;
197	/** The function code. */
198	uint8_t u8Function;
199	/** Function dependent data. */
200	uint8_t au8FunctionDependent[3];
201	/** Message flags. */
202	uint8_t u8MessageFlags;
203	/** Message context - Unique ID from the guest unmodified by the device. */
204	uint32_t u32MessageContext;
205	} MptMessageHdr, *PMptMessageHdr;
206	AssertCompileSize(MptMessageHdr, 12);
207
208	/** Defined function codes found in the message header. */
209	#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST (0x00)
210	#define MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT (0x01)
211	#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT (0x02)
212	#define MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS (0x03)
213	#define MPT_MESSAGE_HDR_FUNCTION_CONFIG (0x04)
214	#define MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS (0x05)
215	#define MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE (0x06)
216	#define MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION (0x07)
217	#define MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK (0x08)
218	#define MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD (0x09)
219	#define MPT_MESSAGE_HDR_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A)
220	#define MPT_MESSAGE_HDR_FUNCTION_TARGET_ASSIST (0x0B)
221	#define MPT_MESSAGE_HDR_FUNCTION_TARGET_STATUS_SEND (0x0C)
222	#define MPT_MESSAGE_HDR_FUNCTION_TARGET_MODE_ABORT (0x0D)
223	#define MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD (0x12)
224
225	#ifdef DEBUG
226	/**
227	* Function names
228	*/
229	static const char * const g_apszMPTFunctionNames[] =
230	{
231	"SCSI I/O Request",
232	"SCSI Task Management",
233	"IOC Init",
234	"IOC Facts",
235	"Config",
236	"Port Facts",
237	"Port Enable",
238	"Event Notification",
239	"Event Ack",
240	"Firmware Download"
241	};
242	#endif
243
244	/**
245	* Default reply message.
246	* Send from the device to the guest upon completion of a request.
247	*/
248	typedef struct MptDefaultReplyMessage
249	{
250	/** Function dependent data. */
251	uint16_t u16FunctionDependent;
252	/** Length of the message in 32bit DWords. */
253	uint8_t u8MessageLength;
254	/** Function which completed. */
255	uint8_t u8Function;
256	/** Function dependent. */
257	uint8_t au8FunctionDependent[3];
258	/** Message flags. */
259	uint8_t u8MessageFlags;
260	/** Message context given in the request. */
261	uint32_t u32MessageContext;
262	/** Function dependent status code. */
263	uint16_t u16FunctionDependentStatus;
264	/** Status of the IOC. */
265	uint16_t u16IOCStatus;
266	/** Additional log info. */
267	uint32_t u32IOCLogInfo;
268	} MptDefaultReplyMessage, *PMptDefaultReplyMessage;
269	AssertCompileSize(MptDefaultReplyMessage, 20);
270
271	/**
272	* IO controller init request.
273	*/
274	typedef struct MptIOCInitRequest
275	{
276	/** Which system send this init request. */
277	uint8_t u8WhoInit;
278	/** Reserved */
279	uint8_t u8Reserved;
280	/** Chain offset in the SG list. */
281	uint8_t u8ChainOffset;
282	/** Function to execute. */
283	uint8_t u8Function;
284	/** Flags */
285	uint8_t u8Flags;
286	/** Maximum number of devices the driver can handle. */
287	uint8_t u8MaxDevices;
288	/** Maximum number of buses the driver can handle. */
289	uint8_t u8MaxBuses;
290	/** Message flags. */
291	uint8_t u8MessageFlags;
292	/** Message context ID. */
293	uint32_t u32MessageContext;
294	/** Reply frame size. */
295	uint16_t u16ReplyFrameSize;
296	/** Reserved */
297	uint16_t u16Reserved;
298	/** Upper 32bit part of the 64bit address the message frames are in.
299	* That means all frames must be in the same 4GB segment. */
300	uint32_t u32HostMfaHighAddr;
301	/** Upper 32bit of the sense buffer. */
302	uint32_t u32SenseBufferHighAddr;
303	} MptIOCInitRequest, *PMptIOCInitRequest;
304	AssertCompileSize(MptIOCInitRequest, 24);
305
306	/**
307	* IO controller init reply.
308	*/
309	typedef struct MptIOCInitReply
310	{
311	/** Which subsystem send this init request. */
312	uint8_t u8WhoInit;
313	/** Reserved */
314	uint8_t u8Reserved;
315	/** Message length */
316	uint8_t u8MessageLength;
317	/** Function. */
318	uint8_t u8Function;
319	/** Flags */
320	uint8_t u8Flags;
321	/** Maximum number of devices the driver can handle. */
322	uint8_t u8MaxDevices;
323	/** Maximum number of busses the driver can handle. */
324	uint8_t u8MaxBuses;
325	/** Message flags. */
326	uint8_t u8MessageFlags;
327	/** Message context ID */
328	uint32_t u32MessageContext;
329	/** Reserved */
330	uint16_t u16Reserved;
331	/** IO controller status. */
332	uint16_t u16IOCStatus;
333	/** IO controller log information. */
334	uint32_t u32IOCLogInfo;
335	} MptIOCInitReply, *PMptIOCInitReply;
336	AssertCompileSize(MptIOCInitReply, 20);
337
338	/**
339	* IO controller facts request.
340	*/
341	typedef struct MptIOCFactsRequest
342	{
343	/** Reserved. */
344	uint16_t u16Reserved;
345	/** Chain offset in SG list. */
346	uint8_t u8ChainOffset;
347	/** Function number. */
348	uint8_t u8Function;
349	/** Reserved */
350	uint8_t u8Reserved[3];
351	/** Message flags. */
352	uint8_t u8MessageFlags;
353	/** Message context ID. */
354	uint32_t u32MessageContext;
355	} MptIOCFactsRequest, *PMptIOCFactsRequest;
356	AssertCompileSize(MptIOCFactsRequest, 12);
357
358	/**
359	* IO controller facts reply.
360	*/
361	typedef struct MptIOCFactsReply
362	{
363	/** Message version. */
364	uint16_t u16MessageVersion;
365	/** Message length. */
366	uint8_t u8MessageLength;
367	/** Function number. */
368	uint8_t u8Function;
369	/** Reserved */
370	uint16_t u16Reserved1;
371	/** IO controller number */
372	uint8_t u8IOCNumber;
373	/** Message flags. */
374	uint8_t u8MessageFlags;
375	/** Message context ID. */
376	uint32_t u32MessageContext;
377	/** IO controller exceptions */
378	uint16_t u16IOCExceptions;
379	/** IO controller status. */
380	uint16_t u16IOCStatus;
381	/** IO controller log information. */
382	uint32_t u32IOCLogInfo;
383	/** Maximum chain depth. */
384	uint8_t u8MaxChainDepth;
385	/** The current value of the WhoInit field. */
386	uint8_t u8WhoInit;
387	/** Block size. */
388	uint8_t u8BlockSize;
389	/** Flags. */
390	uint8_t u8Flags;
391	/** Depth of the reply queue. */
392	uint16_t u16ReplyQueueDepth;
393	/** Size of a request frame. */
394	uint16_t u16RequestFrameSize;
395	/** Reserved */
396	uint16_t u16Reserved2;
397	/** Product ID. */
398	uint16_t u16ProductID;
399	/** Current value of the high 32bit MFA address. */
400	uint32_t u32CurrentHostMFAHighAddr;
401	/** Global credits - Number of entries allocated to queues */
402	uint16_t u16GlobalCredits;
403	/** Number of ports on the IO controller */
404	uint8_t u8NumberOfPorts;
405	/** Event state. */
406	uint8_t u8EventState;
407	/** Current value of the high 32bit sense buffer address. */
408	uint32_t u32CurrentSenseBufferHighAddr;
409	/** Current reply frame size. */
410	uint16_t u16CurReplyFrameSize;
411	/** Maximum number of devices. */
412	uint8_t u8MaxDevices;
413	/** Maximum number of buses. */
414	uint8_t u8MaxBuses;
415	/** Size of the firmware image. */
416	uint32_t u32FwImageSize;
417	/** Reserved. */
418	uint32_t u32Reserved;
419	/** Firmware version */
420	uint32_t u32FWVersion;
421	} MptIOCFactsReply, *PMptIOCFactsReply;
422	AssertCompileSize(MptIOCFactsReply, 60);
423
424	/**
425	* Port facts request
426	*/
427	typedef struct MptPortFactsRequest
428	{
429	/** Reserved */
430	uint16_t u16Reserved1;
431	/** Message length. */
432	uint8_t u8MessageLength;
433	/** Function number. */
434	uint8_t u8Function;
435	/** Reserved */
436	uint16_t u16Reserved2;
437	/** Port number to get facts for. */
438	uint8_t u8PortNumber;
439	/** Message flags. */
440	uint8_t u8MessageFlags;
441	/** Message context ID. */
442	uint32_t u32MessageContext;
443	} MptPortFactsRequest, *PMptPortFactsRequest;
444	AssertCompileSize(MptPortFactsRequest, 12);
445
446	/**
447	* Port facts reply.
448	*/
449	typedef struct MptPortFactsReply
450	{
451	/** Reserved. */
452	uint16_t u16Reserved1;
453	/** Message length. */
454	uint8_t u8MessageLength;
455	/** Function number. */
456	uint8_t u8Function;
457	/** Reserved */
458	uint16_t u16Reserved2;
459	/** Port number the facts are for. */
460	uint8_t u8PortNumber;
461	/** Message flags. */
462	uint8_t u8MessageFlags;
463	/** Message context ID. */
464	uint32_t u32MessageContext;
465	/** Reserved. */
466	uint16_t u16Reserved3;
467	/** IO controller status. */
468	uint16_t u16IOCStatus;
469	/** IO controller log information. */
470	uint32_t u32IOCLogInfo;
471	/** Reserved */
472	uint8_t u8Reserved;
473	/** Port type */
474	uint8_t u8PortType;
475	/** Maximum number of devices on this port. */
476	uint16_t u16MaxDevices;
477	/** SCSI ID of this port on the attached bus. */
478	uint16_t u16PortSCSIID;
479	/** Protocol flags. */
480	uint16_t u16ProtocolFlags;
481	/** Maximum number of target command buffers which can be posted to this port at a time. */
482	uint16_t u16MaxPostedCmdBuffers;
483	/** Maximum number of target IDs that remain persistent between power/reset cycles. */
484	uint16_t u16MaxPersistentIDs;
485	/** Maximum number of LAN buckets. */
486	uint16_t u16MaxLANBuckets;
487	/** Reserved. */
488	uint16_t u16Reserved4;
489	/** Reserved. */
490	uint32_t u32Reserved;
491	} MptPortFactsReply, *PMptPortFactsReply;
492	AssertCompileSize(MptPortFactsReply, 40);
493
494	/**
495	* Port Enable request.
496	*/
497	typedef struct MptPortEnableRequest
498	{
499	/** Reserved. */
500	uint16_t u16Reserved1;
501	/** Message length. */
502	uint8_t u8MessageLength;
503	/** Function number. */
504	uint8_t u8Function;
505	/** Reserved. */
506	uint16_t u16Reserved2;
507	/** Port number to enable. */
508	uint8_t u8PortNumber;
509	/** Message flags. */
510	uint8_t u8MessageFlags;
511	/** Message context ID. */
512	uint32_t u32MessageContext;
513	} MptPortEnableRequest, *PMptPortEnableRequest;
514	AssertCompileSize(MptPortEnableRequest, 12);
515
516	/**
517	* Port enable reply.
518	*/
519	typedef struct MptPortEnableReply
520	{
521	/** Reserved. */
522	uint16_t u16Reserved1;
523	/** Message length. */
524	uint8_t u8MessageLength;
525	/** Function number. */
526	uint8_t u8Function;
527	/** Reserved */
528	uint16_t u16Reserved2;
529	/** Port number which was enabled. */
530	uint8_t u8PortNumber;
531	/** Message flags. */
532	uint8_t u8MessageFlags;
533	/** Message context ID. */
534	uint32_t u32MessageContext;
535	/** Reserved. */
536	uint16_t u16Reserved3;
537	/** IO controller status */
538	uint16_t u16IOCStatus;
539	/** IO controller log information. */
540	uint32_t u32IOCLogInfo;
541	} MptPortEnableReply, *PMptPortEnableReply;
542	AssertCompileSize(MptPortEnableReply, 20);
543
544	/**
545	* Event notification request.
546	*/
547	typedef struct MptEventNotificationRequest
548	{
549	/** Switch - Turns event notification on and off. */
550	uint8_t u8Switch;
551	/** Reserved. */
552	uint8_t u8Reserved1;
553	/** Chain offset. */
554	uint8_t u8ChainOffset;
555	/** Function number. */
556	uint8_t u8Function;
557	/** Reserved. */
558	uint8_t u8reserved2[3];
559	/** Message flags. */
560	uint8_t u8MessageFlags;
561	/** Message context ID. */
562	uint32_t u32MessageContext;
563	} MptEventNotificationRequest, *PMptEventNotificationRequest;
564	AssertCompileSize(MptEventNotificationRequest, 12);
565
566	/**
567	* Event notification reply.
568	*/
569	typedef struct MptEventNotificationReply
570	{
571	/** Event data length. */
572	uint16_t u16EventDataLength;
573	/** Message length. */
574	uint8_t u8MessageLength;
575	/** Function number. */
576	uint8_t u8Function;
577	/** Reserved. */
578	uint16_t u16Reserved1;
579	/** Ack required. */
580	uint8_t u8AckRequired;
581	/** Message flags. */
582	uint8_t u8MessageFlags;
583	/** Message context ID. */
584	uint32_t u32MessageContext;
585	/** Reserved. */
586	uint16_t u16Reserved2;
587	/** IO controller status. */
588	uint16_t u16IOCStatus;
589	/** IO controller log information. */
590	uint32_t u32IOCLogInfo;
591	/** Notification event. */
592	uint32_t u32Event;
593	/** Event context. */
594	uint32_t u32EventContext;
595	/** Event data. */
596	uint32_t u32EventData;
597	} MptEventNotificationReply, *PMptEventNotificationReply;
598	AssertCompileSize(MptEventNotificationReply, 32);
599
600	#define MPT_EVENT_EVENT_CHANGE (0x0000000a)
601
602	/**
603	* FW download request.
604	*/
605	typedef struct MptFWDownloadRequest
606	{
607	/** Switch - Turns event notification on and off. */
608	uint8_t u8ImageType;
609	/** Reserved. */
610	uint8_t u8Reserved1;
611	/** Chain offset. */
612	uint8_t u8ChainOffset;
613	/** Function number. */
614	uint8_t u8Function;
615	/** Reserved. */
616	uint8_t u8Reserved2[3];
617	/** Message flags. */
618	uint8_t u8MessageFlags;
619	/** Message context ID. */
620	uint32_t u32MessageContext;
621	} MptFWDownloadRequest, *PMptFWDownloadRequest;
622	AssertCompileSize(MptFWDownloadRequest, 12);
623
624	#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_RESERVED 0
625	#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_FIRMWARE 1
626	#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_MPI_BIOS 2
627	#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_NVDATA 3
628
629	/**
630	* FW download reply.
631	*/
632	typedef struct MptFWDownloadReply
633	{
634	/** Reserved. */
635	uint16_t u16Reserved1;
636	/** Message length. */
637	uint8_t u8MessageLength;
638	/** Function number. */
639	uint8_t u8Function;
640	/** Reserved. */
641	uint8_t u8Reserved2[3];
642	/** Message flags. */
643	uint8_t u8MessageFlags;
644	/** Message context ID. */
645	uint32_t u32MessageContext;
646	/** Reserved. */
647	uint16_t u16Reserved2;
648	/** IO controller status. */
649	uint16_t u16IOCStatus;
650	/** IO controller log information. */
651	uint32_t u32IOCLogInfo;
652	} MptFWDownloadReply, *PMptFWDownloadReply;
653	AssertCompileSize(MptFWDownloadReply, 20);
654
655	/**
656	* FW upload request.
657	*/
658	typedef struct MptFWUploadRequest
659	{
660	/** Requested image type. */
661	uint8_t u8ImageType;
662	/** Reserved. */
663	uint8_t u8Reserved1;
664	/** Chain offset. */
665	uint8_t u8ChainOffset;
666	/** Function number. */
667	uint8_t u8Function;
668	/** Reserved. */
669	uint8_t u8Reserved2[3];
670	/** Message flags. */
671	uint8_t u8MessageFlags;
672	/** Message context ID. */
673	uint32_t u32MessageContext;
674	} MptFWUploadRequest, *PMptFWUploadRequest;
675	AssertCompileSize(MptFWUploadRequest, 12);
676
677	/**
678	* FW upload reply.
679	*/
680	typedef struct MptFWUploadReply
681	{
682	/** Image type. */
683	uint8_t u8ImageType;
684	/** Reserved. */
685	uint8_t u8Reserved1;
686	/** Message length. */
687	uint8_t u8MessageLength;
688	/** Function number. */
689	uint8_t u8Function;
690	/** Reserved. */
691	uint8_t u8Reserved2[3];
692	/** Message flags. */
693	uint8_t u8MessageFlags;
694	/** Message context ID. */
695	uint32_t u32MessageContext;
696	/** Reserved. */
697	uint16_t u16Reserved2;
698	/** IO controller status. */
699	uint16_t u16IOCStatus;
700	/** IO controller log information. */
701	uint32_t u32IOCLogInfo;
702	/** Uploaded image size. */
703	uint32_t u32ActualImageSize;
704	} MptFWUploadReply, *PMptFWUploadReply;
705	AssertCompileSize(MptFWUploadReply, 24);
706
707	/**
708	* SCSI IO Request
709	*/
710	typedef struct MptSCSIIORequest
711	{
712	/** Target ID */
713	uint8_t u8TargetID;
714	/** Bus number */
715	uint8_t u8Bus;
716	/** Chain offset */
717	uint8_t u8ChainOffset;
718	/** Function number. */
719	uint8_t u8Function;
720	/** CDB length. */
721	uint8_t u8CDBLength;
722	/** Sense buffer length. */
723	uint8_t u8SenseBufferLength;
724	/** Reserved */
725	uint8_t u8Reserved;
726	/** Message flags. */
727	uint8_t u8MessageFlags;
728	/** Message context ID. */
729	uint32_t u32MessageContext;
730	/** LUN */
731	uint8_t au8LUN[8];
732	/** Control values. */
733	uint32_t u32Control;
734	/** The CDB. */
735	uint8_t au8CDB[16];
736	/** Data length. */
737	uint32_t u32DataLength;
738	/** Sense buffer low 32bit address. */
739	uint32_t u32SenseBufferLowAddress;
740	} MptSCSIIORequest, *PMptSCSIIORequest;
741	AssertCompileSize(MptSCSIIORequest, 48);
742
743	#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(x) (((x) & 0x3000000) >> 24)
744	#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE (0x0)
745	#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE (0x1)
746	#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ (0x2)
747
748	/**
749	* SCSI IO error reply.
750	*/
751	typedef struct MptSCSIIOErrorReply
752	{
753	/** Target ID */
754	uint8_t u8TargetID;
755	/** Bus number */
756	uint8_t u8Bus;
757	/** Message length. */
758	uint8_t u8MessageLength;
759	/** Function number. */
760	uint8_t u8Function;
761	/** CDB length */
762	uint8_t u8CDBLength;
763	/** Sense buffer length */
764	uint8_t u8SenseBufferLength;
765	/** Reserved */
766	uint8_t u8Reserved;
767	/** Message flags */
768	uint8_t u8MessageFlags;
769	/** Message context ID */
770	uint32_t u32MessageContext;
771	/** SCSI status. */
772	uint8_t u8SCSIStatus;
773	/** SCSI state */
774	uint8_t u8SCSIState;
775	/** IO controller status */
776	uint16_t u16IOCStatus;
777	/** IO controller log information */
778	uint32_t u32IOCLogInfo;
779	/** Transfer count */
780	uint32_t u32TransferCount;
781	/** Sense count */
782	uint32_t u32SenseCount;
783	/** Response information */
784	uint32_t u32ResponseInfo;
785	} MptSCSIIOErrorReply, *PMptSCSIIOErrorReply;
786	AssertCompileSize(MptSCSIIOErrorReply, 32);
787
788	#define MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID (0x01)
789	#define MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED (0x08)
790
791	/**
792	* IOC status codes specific to the SCSI I/O error reply.
793	*/
794	#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS (0x0041)
795	#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID (0x0042)
796	#define MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE (0x0043)
797
798	/**
799	* SCSI task management request.
800	*/
801	typedef struct MptSCSITaskManagementRequest
802	{
803	/** Target ID */
804	uint8_t u8TargetID;
805	/** Bus number */
806	uint8_t u8Bus;
807	/** Chain offset */
808	uint8_t u8ChainOffset;
809	/** Function number */
810	uint8_t u8Function;
811	/** Reserved */
812	uint8_t u8Reserved1;
813	/** Task type */
814	uint8_t u8TaskType;
815	/** Reserved */
816	uint8_t u8Reserved2;
817	/** Message flags */
818	uint8_t u8MessageFlags;
819	/** Message context ID */
820	uint32_t u32MessageContext;
821	/** LUN */
822	uint8_t au8LUN[8];
823	/** Reserved */
824	uint8_t auReserved[28];
825	/** Task message context ID. */
826	uint32_t u32TaskMessageContext;
827	} MptSCSITaskManagementRequest, *PMptSCSITaskManagementRequest;
828	AssertCompileSize(MptSCSITaskManagementRequest, 52);
829
830	/**
831	* SCSI task management reply.
832	*/
833	typedef struct MptSCSITaskManagementReply
834	{
835	/** Target ID */
836	uint8_t u8TargetID;
837	/** Bus number */
838	uint8_t u8Bus;
839	/** Message length */
840	uint8_t u8MessageLength;
841	/** Function number */
842	uint8_t u8Function;
843	/** Reserved */
844	uint8_t u8Reserved1;
845	/** Task type */
846	uint8_t u8TaskType;
847	/** Reserved */
848	uint8_t u8Reserved2;
849	/** Message flags */
850	uint8_t u8MessageFlags;
851	/** Message context ID */
852	uint32_t u32MessageContext;
853	/** Reserved */
854	uint16_t u16Reserved;
855	/** IO controller status */
856	uint16_t u16IOCStatus;
857	/** IO controller log information */
858	uint32_t u32IOCLogInfo;
859	/** Termination count */
860	uint32_t u32TerminationCount;
861	} MptSCSITaskManagementReply, *PMptSCSITaskManagementReply;
862	AssertCompileSize(MptSCSITaskManagementReply, 24);
863
864	/**
865	* Page address for SAS expander page types.
866	*/
867	typedef union MptConfigurationPageAddressSASExpander
868	{
869	struct
870	{
871	uint16_t u16Handle;
872	uint16_t u16Reserved;
873	} Form0And2;
874	struct
875	{
876	uint16_t u16Handle;
877	uint8_t u8PhyNum;
878	uint8_t u8Reserved;
879	} Form1;
880	} MptConfigurationPageAddressSASExpander, *PMptConfigurationPageAddressSASExpander;
881	AssertCompileSize(MptConfigurationPageAddressSASExpander, 4);
882
883	/**
884	* Page address for SAS device page types.
885	*/
886	typedef union MptConfigurationPageAddressSASDevice
887	{
888	struct
889	{
890	uint16_t u16Handle;
891	uint16_t u16Reserved;
892	} Form0And2;
893	struct
894	{
895	uint8_t u8TargetID;
896	uint8_t u8Bus;
897	uint8_t u8Reserved;
898	} Form1; /*< r=bird: only three bytes? /
899	} MptConfigurationPageAddressSASDevice, *PMptConfigurationPageAddressSASDevice;
900	AssertCompileSize(MptConfigurationPageAddressSASDevice, 4);
901
902	/**
903	* Page address for SAS PHY page types.
904	*/
905	typedef union MptConfigurationPageAddressSASPHY
906	{
907	struct
908	{
909	uint8_t u8PhyNumber;
910	uint8_t u8Reserved[3];
911	} Form0;
912	struct
913	{
914	uint16_t u16Index;
915	uint16_t u16Reserved;
916	} Form1;
917	} MptConfigurationPageAddressSASPHY, *PMptConfigurationPageAddressSASPHY;
918	AssertCompileSize(MptConfigurationPageAddressSASPHY, 4);
919
920	/**
921	* Page address for SAS Enclosure page types.
922	*/
923	typedef struct MptConfigurationPageAddressSASEnclosure
924	{
925	uint16_t u16Handle;
926	uint16_t u16Reserved;
927	} MptConfigurationPageAddressSASEnclosure, *PMptConfigurationPageAddressSASEnclosure;
928	AssertCompileSize(MptConfigurationPageAddressSASEnclosure, 4);
929
930	/**
931	* Union of all possible address types.
932	*/
933	typedef union MptConfigurationPageAddress
934	{
935	/** 32bit view. */
936	uint32_t u32PageAddress;
937	struct
938	{
939	/** Port number to get the configuration page for. */
940	uint8_t u8PortNumber;
941	/** Reserved. */
942	uint8_t u8Reserved[3];
943	} MPIPortNumber;
944	struct
945	{
946	/** Target ID to get the configuration page for. */
947	uint8_t u8TargetID;
948	/** Bus number to get the configuration page for. */
949	uint8_t u8Bus;
950	/** Reserved. */
951	uint8_t u8Reserved[2];
952	} BusAndTargetId;
953	MptConfigurationPageAddressSASExpander SASExpander;
954	MptConfigurationPageAddressSASDevice SASDevice;
955	MptConfigurationPageAddressSASPHY SASPHY;
956	MptConfigurationPageAddressSASEnclosure SASEnclosure;
957	} MptConfigurationPageAddress, *PMptConfigurationPageAddress;
958	AssertCompileSize(MptConfigurationPageAddress, 4);
959
960	#define MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(x) (((x).u32PageAddress >> 28) & 0x0f)
961
962	/**
963	* Configuration request
964	*/
965	typedef struct MptConfigurationRequest
966	{
967	/** Action code. */
968	uint8_t u8Action;
969	/** Reserved. */
970	uint8_t u8Reserved1;
971	/** Chain offset. */
972	uint8_t u8ChainOffset;
973	/** Function number. */
974	uint8_t u8Function;
975	/** Extended page length. */
976	uint16_t u16ExtPageLength;
977	/** Extended page type */
978	uint8_t u8ExtPageType;
979	/** Message flags. */
980	uint8_t u8MessageFlags;
981	/** Message context ID. */
982	uint32_t u32MessageContext;
983	/** Reserved. */
984	uint8_t u8Reserved2[8];
985	/** Version number of the page. */
986	uint8_t u8PageVersion;
987	/** Length of the page in 32bit Dwords. */
988	uint8_t u8PageLength;
989	/** Page number to access. */
990	uint8_t u8PageNumber;
991	/** Type of the page being accessed. */
992	uint8_t u8PageType;
993	/** Page type dependent address. */
994	MptConfigurationPageAddress PageAddress;
995	/** Simple SG element describing the buffer. */
996	MptSGEntrySimple64 SimpleSGElement;
997	} MptConfigurationRequest, *PMptConfigurationRequest;
998	AssertCompileSize(MptConfigurationRequest, 40);
999
1000	/** Possible action codes. */
1001	#define MPT_CONFIGURATION_REQUEST_ACTION_HEADER (0x00)
1002	#define MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT (0x01)
1003	#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT (0x02)
1004	#define MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT (0x03)
1005	#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM (0x04)
1006	#define MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT (0x05)
1007	#define MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM (0x06)
1008
1009	/** Page type codes. */
1010	#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IO_UNIT (0x00)
1011	#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IOC (0x01)
1012	#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_BIOS (0x02)
1013	#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_SCSI_PORT (0x03)
1014	#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_EXTENDED (0x0F)
1015
1016	/**
1017	* Configuration reply.
1018	*/
1019	typedef struct MptConfigurationReply
1020	{
1021	/** Action code. */
1022	uint8_t u8Action;
1023	/** Reserved. */
1024	uint8_t u8Reserved;
1025	/** Message length. */
1026	uint8_t u8MessageLength;
1027	/** Function number. */
1028	uint8_t u8Function;
1029	/** Extended page length. */
1030	uint16_t u16ExtPageLength;
1031	/** Extended page type */
1032	uint8_t u8ExtPageType;
1033	/** Message flags. */
1034	uint8_t u8MessageFlags;
1035	/** Message context ID. */
1036	uint32_t u32MessageContext;
1037	/** Reserved. */
1038	uint16_t u16Reserved;
1039	/** I/O controller status. */
1040	uint16_t u16IOCStatus;
1041	/** I/O controller log information. */
1042	uint32_t u32IOCLogInfo;
1043	/** Version number of the page. */
1044	uint8_t u8PageVersion;
1045	/** Length of the page in 32bit Dwords. */
1046	uint8_t u8PageLength;
1047	/** Page number to access. */
1048	uint8_t u8PageNumber;
1049	/** Type of the page being accessed. */
1050	uint8_t u8PageType;
1051	} MptConfigurationReply, *PMptConfigurationReply;
1052	AssertCompileSize(MptConfigurationReply, 24);
1053
1054	/** Additional I/O controller status codes for the configuration reply. */
1055	#define MPT_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
1056	#define MPT_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
1057	#define MPT_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
1058	#define MPT_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
1059	#define MPT_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
1060	#define MPT_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
1061
1062	/**
1063	* Union of all possible request messages.
1064	*/
1065	typedef union MptRequestUnion
1066	{
1067	MptMessageHdr Header;
1068	MptIOCInitRequest IOCInit;
1069	MptIOCFactsRequest IOCFacts;
1070	MptPortFactsRequest PortFacts;
1071	MptPortEnableRequest PortEnable;
1072	MptEventNotificationRequest EventNotification;
1073	MptSCSIIORequest SCSIIO;
1074	MptSCSITaskManagementRequest SCSITaskManagement;
1075	MptConfigurationRequest Configuration;
1076	MptFWDownloadRequest FWDownload;
1077	MptFWUploadRequest FWUpload;
1078	} MptRequestUnion, *PMptRequestUnion;
1079
1080	/**
1081	* Union of all possible reply messages.
1082	*/
1083	typedef union MptReplyUnion
1084	{
1085	/** 16bit view. */
1086	uint16_t au16Reply[30];
1087	MptDefaultReplyMessage Header;
1088	MptIOCInitReply IOCInit;
1089	MptIOCFactsReply IOCFacts;
1090	MptPortFactsReply PortFacts;
1091	MptPortEnableReply PortEnable;
1092	MptEventNotificationReply EventNotification;
1093	MptSCSIIOErrorReply SCSIIOError;
1094	MptSCSITaskManagementReply SCSITaskManagement;
1095	MptConfigurationReply Configuration;
1096	MptFWDownloadReply FWDownload;
1097	MptFWUploadReply FWUpload;
1098	} MptReplyUnion, *PMptReplyUnion;
1099	AssertCompileSize(MptReplyUnion, 60);
1100
1101	/**
1102	* Firmware image header.
1103	*/
1104	typedef struct FwImageHdr
1105	{
1106	/** ARM branch instruction. */
1107	uint32_t u32ArmBrInsn;
1108	/** Signature part 1. */
1109	uint32_t u32Signature1;
1110	/** Signature part 2. */
1111	uint32_t u32Signature2;
1112	/** Signature part 3. */
1113	uint32_t u32Signature3;
1114	/** Another ARM branch instruction. */
1115	uint32_t u32ArmBrInsn2;
1116	/** Yet another ARM branch instruction. */
1117	uint32_t u32ArmBrInsn3;
1118	/** Reserved. */
1119	uint32_t u32Reserved;
1120	/** Checksum of the image. */
1121	uint32_t u32Checksum;
1122	/** Vendor ID. */
1123	uint16_t u16VendorId;
1124	/** Product ID. */
1125	uint16_t u16ProductId;
1126	/** Firmware version. */
1127	uint32_t u32FwVersion;
1128	/** Firmware sequencer Code version. */
1129	uint32_t u32SeqCodeVersion;
1130	/** Image size in bytes including the header. */
1131	uint32_t u32ImageSize;
1132	/** Offset of the first extended image header. */
1133	uint32_t u32NextImageHeaderOffset;
1134	/** Start address of the image in IOC memory. */
1135	uint32_t u32LoadStartAddress;
1136	/** Absolute start address of the Iop ARM. */
1137	uint32_t u32IopResetVectorValue;
1138	/** Address of the IopResetVector register. */
1139	uint32_t u32IopResetVectorRegAddr;
1140	/** Marker value for what utility. */
1141	uint32_t u32VersionNameWhat;
1142	/** ASCII string of version. */
1143	uint8_t aszVersionName[256];
1144	/** Marker value for what utility. */
1145	uint32_t u32VendorNameWhat;
1146	/** ASCII string of vendor name. */
1147	uint8_t aszVendorName[256];
1148	} FwImageHdr, *PFwImageHdr;
1149	AssertCompileSize(FwImageHdr, 584);
1150
1151	/** First part of the signature. */
1152	#define LSILOGIC_FWIMGHDR_SIGNATURE1 UINT32_C(0x5aeaa55a)
1153	/** Second part of the signature. */
1154	#define LSILOGIC_FWIMGHDR_SIGNATURE2 UINT32_C(0xa55aeaa5)
1155	/** Third part of the signature. */
1156	#define LSILOGIC_FWIMGHDR_SIGNATURE3 UINT32_C(0x5aa55aea)
1157	/** Load address of the firmware image to watch for,
1158	* seen used by Solaris 9. When this value is written to the
1159	* diagnostic address register we know a firmware image is downloaded.
1160	*/
1161	#define LSILOGIC_FWIMGHDR_LOAD_ADDRESS UINT32_C(0x21ff5e00)
1162
1163	/**
1164	* Configuration Page attributes.
1165	*/
1166	#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY (0x00)
1167	#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE (0x10)
1168	#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT (0x20)
1169	#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY (0x30)
1170
1171	#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(u8PageType) ((u8PageType) & 0xf0)
1172
1173	/**
1174	* Configuration Page types.
1175	*/
1176	#define MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT (0x00)
1177	#define MPT_CONFIGURATION_PAGE_TYPE_IOC (0x01)
1178	#define MPT_CONFIGURATION_PAGE_TYPE_BIOS (0x02)
1179	#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT (0x03)
1180	#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE (0x04)
1181	#define MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING (0x09)
1182	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED (0x0F)
1183
1184	#define MPT_CONFIGURATION_PAGE_TYPE_GET(u8PageType) ((u8PageType) & 0x0f)
1185
1186	/**
1187	* Extented page types.
1188	*/
1189	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT (0x10)
1190	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER (0x11)
1191	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE (0x12)
1192	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS (0x13)
1193	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_LOG (0x14)
1194	#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE (0x15)
1195
1196	/**
1197	* Configuration Page header - Common to all pages.
1198	*/
1199	typedef struct MptConfigurationPageHeader
1200	{
1201	/** Version of the page. */
1202	uint8_t u8PageVersion;
1203	/** The length of the page in 32bit D-Words. */
1204	uint8_t u8PageLength;
1205	/** Number of the page. */
1206	uint8_t u8PageNumber;
1207	/** Type of the page. */
1208	uint8_t u8PageType;
1209	} MptConfigurationPageHeader, *PMptConfigurationPageHeader;
1210	AssertCompileSize(MptConfigurationPageHeader, 4);
1211
1212	/**
1213	* Extended configuration page header - Common to all extended pages.
1214	*/
1215	typedef struct MptExtendedConfigurationPageHeader
1216	{
1217	/** Version of the page. */
1218	uint8_t u8PageVersion;
1219	/** Reserved. */
1220	uint8_t u8Reserved1;
1221	/** Number of the page. */
1222	uint8_t u8PageNumber;
1223	/** Type of the page. */
1224	uint8_t u8PageType;
1225	/** Extended page length. */
1226	uint16_t u16ExtPageLength;
1227	/** Extended page type. */
1228	uint8_t u8ExtPageType;
1229	/** Reserved */
1230	uint8_t u8Reserved2;
1231	} MptExtendedConfigurationPageHeader, *PMptExtendedConfigurationPageHeader;
1232	AssertCompileSize(MptExtendedConfigurationPageHeader, 8);
1233
1234	/**
1235	* Manufacturing page 0. - Readonly.
1236	*/
1237	typedef struct MptConfigurationPageManufacturing0 /*< @todo r=bird: This and a series of other structs could save a lot of 'u.' typing by promoting the inner 'u' union... /
1238	{
1239	/** Union. */
1240	union
1241	{
1242	/** Byte view. */
1243	uint8_t abPageData[76];
1244	/** Field view. */
1245	struct
1246	{
1247	/** The omnipresent header. */
1248	MptConfigurationPageHeader Header;
1249	/** Name of the chip. */
1250	uint8_t abChipName[16];
1251	/** Chip revision. */
1252	uint8_t abChipRevision[8];
1253	/** Board name. */
1254	uint8_t abBoardName[16];
1255	/** Board assembly. */
1256	uint8_t abBoardAssembly[16];
1257	/** Board tracer number. */
1258	uint8_t abBoardTracerNumber[16];
1259	} fields;
1260	} u;
1261	} MptConfigurationPageManufacturing0, *PMptConfigurationPageManufacturing0;
1262	AssertCompileSize(MptConfigurationPageManufacturing0, 76);
1263
1264	/**
1265	* Manufacturing page 1. - Readonly Persistent.
1266	*/
1267	typedef struct MptConfigurationPageManufacturing1
1268	{
1269	/** Union */
1270	union
1271	{
1272	/** Byte view */
1273	uint8_t abPageData[260];
1274	/** Field view */
1275	struct
1276	{
1277	/** The omnipresent header. */
1278	MptConfigurationPageHeader Header;
1279	/** VPD info - don't know what belongs here so all zero. */
1280	uint8_t abVPDInfo[256];
1281	} fields;
1282	} u;
1283	} MptConfigurationPageManufacturing1, *PMptConfigurationPageManufacturing1;
1284	AssertCompileSize(MptConfigurationPageManufacturing1, 260);
1285
1286	/**
1287	* Manufacturing page 2. - Readonly.
1288	*/
1289	typedef struct MptConfigurationPageManufacturing2
1290	{
1291	/** Union. */
1292	union
1293	{
1294	/** Byte view. */
1295	uint8_t abPageData[8];
1296	/** Field view. */
1297	struct
1298	{
1299	/** The omnipresent header. */
1300	MptConfigurationPageHeader Header;
1301	/** PCI Device ID. */
1302	uint16_t u16PCIDeviceID;
1303	/** PCI Revision ID. */
1304	uint8_t u8PCIRevisionID;
1305	/** Reserved. */
1306	uint8_t u8Reserved;
1307	/** Hardware specific settings... */
1308	} fields;
1309	} u;
1310	} MptConfigurationPageManufacturing2, *PMptConfigurationPageManufacturing2;
1311	AssertCompileSize(MptConfigurationPageManufacturing2, 8);
1312
1313	/**
1314	* Manufacturing page 3. - Readonly.
1315	*/
1316	typedef struct MptConfigurationPageManufacturing3
1317	{
1318	/** Union. */
1319	union
1320	{
1321	/** Byte view. */
1322	uint8_t abPageData[8];
1323	/** Field view. */
1324	struct
1325	{
1326	/** The omnipresent header. */
1327	MptConfigurationPageHeader Header;
1328	/** PCI Device ID. */
1329	uint16_t u16PCIDeviceID;
1330	/** PCI Revision ID. */
1331	uint8_t u8PCIRevisionID;
1332	/** Reserved. */
1333	uint8_t u8Reserved;
1334	/** Chip specific settings... */
1335	} fields;
1336	} u;
1337	} MptConfigurationPageManufacturing3, *PMptConfigurationPageManufacturing3;
1338	AssertCompileSize(MptConfigurationPageManufacturing3, 8);
1339
1340	/**
1341	* Manufacturing page 4. - Readonly.
1342	*/
1343	typedef struct MptConfigurationPageManufacturing4
1344	{
1345	/** Union. */
1346	union
1347	{
1348	/** Byte view. */
1349	uint8_t abPageData[84];
1350	/** Field view. */
1351	struct
1352	{
1353	/** The omnipresent header. */
1354	MptConfigurationPageHeader Header;
1355	/** Reserved. */
1356	uint32_t u32Reserved;
1357	/** InfoOffset0. */
1358	uint8_t u8InfoOffset0;
1359	/** Info size. */
1360	uint8_t u8InfoSize0;
1361	/** InfoOffset1. */
1362	uint8_t u8InfoOffset1;
1363	/** Info size. */
1364	uint8_t u8InfoSize1;
1365	/** Size of the inquiry data. */
1366	uint8_t u8InquirySize;
1367	/** Reserved. */
1368	uint8_t abReserved[3];
1369	/** Inquiry data. */
1370	uint8_t abInquiryData[56];
1371	/** IS volume settings. */
1372	uint32_t u32ISVolumeSettings;
1373	/** IME volume settings. */
1374	uint32_t u32IMEVolumeSettings;
1375	/** IM volume settings. */
1376	uint32_t u32IMVolumeSettings;
1377	} fields;
1378	} u;
1379	} MptConfigurationPageManufacturing4, *PMptConfigurationPageManufacturing4;
1380	AssertCompileSize(MptConfigurationPageManufacturing4, 84);
1381
1382	/**
1383	* Manufacturing page 5 - Readonly.
1384	*/
1385	#pragma pack(1) /* u64BaseWWID is at offset 4, which isn't natural for uint64_t. */
1386	typedef struct MptConfigurationPageManufacturing5
1387	{
1388	/** Union. */
1389	union
1390	{
1391	/** Byte view. */
1392	uint8_t abPageData[88];
1393	/** Field view. */
1394	struct
1395	{
1396	/** The omnipresent header. */
1397	MptConfigurationPageHeader Header;
1398	/** Base WWID.
1399	* @note Not aligned on 8-byte boundrary */
1400	uint64_t u64BaseWWID;
1401	/** Flags */
1402	uint8_t u8Flags;
1403	/** Number of ForceWWID fields in this page. */
1404	uint8_t u8NumForceWWID;
1405	/** Reserved */
1406	uint16_t u16Reserved;
1407	/** Reserved */
1408	uint32_t au32Reserved[2];
1409	/** ForceWWID entries Maximum of 8 because the SAS controller doesn't has more */
1410	uint64_t au64ForceWWID[8];
1411	} fields;
1412	} u;
1413	} MptConfigurationPageManufacturing5, *PMptConfigurationPageManufacturing5;
1414	#pragma pack()
1415	AssertCompileSize(MptConfigurationPageManufacturing5, 24+64);
1416
1417	/**
1418	* Manufacturing page 6 - Readonly.
1419	*/
1420	typedef struct MptConfigurationPageManufacturing6
1421	{
1422	/** Union. */
1423	union
1424	{
1425	/** Byte view. */
1426	uint8_t abPageData[4];
1427	/** Field view. */
1428	struct
1429	{
1430	/** The omnipresent header. */
1431	MptConfigurationPageHeader Header;
1432	/** Product specific data - 0 for now */
1433	} fields;
1434	} u;
1435	} MptConfigurationPageManufacturing6, *PMptConfigurationPageManufacturing6;
1436	AssertCompileSize(MptConfigurationPageManufacturing6, 4);
1437
1438	/**
1439	* Manufacutring page 7 - PHY element.
1440	*/
1441	typedef struct MptConfigurationPageManufacturing7PHY
1442	{
1443	/** Pinout */
1444	uint32_t u32Pinout;
1445	/** Connector name */
1446	uint8_t szConnector[16];
1447	/** Location */
1448	uint8_t u8Location;
1449	/** reserved */
1450	uint8_t u8Reserved;
1451	/** Slot */
1452	uint16_t u16Slot;
1453	} MptConfigurationPageManufacturing7PHY, *PMptConfigurationPageManufacturing7PHY;
1454	AssertCompileSize(MptConfigurationPageManufacturing7PHY, 24);
1455
1456	/**
1457	* Manufacturing page 7 - Readonly.
1458	*/
1459	typedef struct MptConfigurationPageManufacturing7
1460	{
1461	/** Union. */
1462	union
1463	{
1464	/** Byte view. */
1465	uint8_t abPageData[1];
1466	/** Field view. */
1467	struct
1468	{
1469	/** The omnipresent header. */
1470	MptConfigurationPageHeader Header;
1471	/** Reserved */
1472	uint32_t au32Reserved[2];
1473	/** Flags */
1474	uint32_t u32Flags;
1475	/** Enclosure name */
1476	uint8_t szEnclosureName[16];
1477	/** Number of PHYs */
1478	uint8_t u8NumPhys;
1479	/** Reserved */
1480	uint8_t au8Reserved[3];
1481	/** PHY list for the SAS controller - variable depending on the number of ports */
1482	MptConfigurationPageManufacturing7PHY aPHY[1];
1483	} fields;
1484	} u;
1485	} MptConfigurationPageManufacturing7, *PMptConfigurationPageManufacturing7;
1486	AssertCompileSize(MptConfigurationPageManufacturing7, 36+sizeof(MptConfigurationPageManufacturing7PHY));
1487
1488	#define LSILOGICSCSI_MANUFACTURING7_GET_SIZE(ports) (sizeof(MptConfigurationPageManufacturing7) + ((ports) - 1) * sizeof(MptConfigurationPageManufacturing7PHY))
1489
1490	/** Flags for the flags field */
1491	#define LSILOGICSCSI_MANUFACTURING7_FLAGS_USE_PROVIDED_INFORMATION RT_BIT(0)
1492
1493	/** Flags for the pinout field */
1494	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_UNKNOWN RT_BIT(0)
1495	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8482 RT_BIT(1)
1496	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE1 RT_BIT(8)
1497	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE2 RT_BIT(9)
1498	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE3 RT_BIT(10)
1499	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE4 RT_BIT(11)
1500	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE1 RT_BIT(16)
1501	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE2 RT_BIT(17)
1502	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE3 RT_BIT(18)
1503	#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE4 RT_BIT(19)
1504
1505	/** Flags for the location field */
1506	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_UNKNOWN 0x01
1507	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_INTERNAL 0x02
1508	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_EXTERNAL 0x04
1509	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_SWITCHABLE 0x08
1510	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO 0x10
1511	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_PRESENT 0x20
1512	#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_CONNECTED 0x80
1513
1514	/**
1515	* Manufacturing page 8 - Readonly.
1516	*/
1517	typedef struct MptConfigurationPageManufacturing8
1518	{
1519	/** Union. */
1520	union
1521	{
1522	/** Byte view. */
1523	uint8_t abPageData[4];
1524	/** Field view. */
1525	struct
1526	{
1527	/** The omnipresent header. */
1528	MptConfigurationPageHeader Header;
1529	/** Product specific information */
1530	} fields;
1531	} u;
1532	} MptConfigurationPageManufacturing8, *PMptConfigurationPageManufacturing8;
1533	AssertCompileSize(MptConfigurationPageManufacturing8, 4);
1534
1535	/**
1536	* Manufacturing page 9 - Readonly.
1537	*/
1538	typedef struct MptConfigurationPageManufacturing9
1539	{
1540	/** Union. */
1541	union
1542	{
1543	/** Byte view. */
1544	uint8_t abPageData[4];
1545	/** Field view. */
1546	struct
1547	{
1548	/** The omnipresent header. */
1549	MptConfigurationPageHeader Header;
1550	/** Product specific information */
1551	} fields;
1552	} u;
1553	} MptConfigurationPageManufacturing9, *PMptConfigurationPageManufacturing9;
1554	AssertCompileSize(MptConfigurationPageManufacturing9, 4);
1555
1556	/**
1557	* Manufacturing page 10 - Readonly.
1558	*/
1559	typedef struct MptConfigurationPageManufacturing10
1560	{
1561	/** Union. */
1562	union
1563	{
1564	/** Byte view. */
1565	uint8_t abPageData[4];
1566	/** Field view. */
1567	struct
1568	{
1569	/** The omnipresent header. */
1570	MptConfigurationPageHeader Header;
1571	/** Product specific information */
1572	} fields;
1573	} u;
1574	} MptConfigurationPageManufacturing10, *PMptConfigurationPageManufacturing10;
1575	AssertCompileSize(MptConfigurationPageManufacturing10, 4);
1576
1577	/**
1578	* IO Unit page 0. - Readonly.
1579	*/
1580	#pragma pack(1) /* u64UniqueIdentifier is at offset 4, which isn't natural for uint64_t. */
1581	typedef struct MptConfigurationPageIOUnit0
1582	{
1583	/** Union. */
1584	union
1585	{
1586	/** Byte view. */
1587	uint8_t abPageData[12];
1588	/** Field view. */
1589	struct
1590	{
1591	/** The omnipresent header. */
1592	MptConfigurationPageHeader Header;
1593	/** A unique identifier. */
1594	uint64_t u64UniqueIdentifier;
1595	} fields;
1596	} u;
1597	} MptConfigurationPageIOUnit0, *PMptConfigurationPageIOUnit0;
1598	#pragma pack()
1599	AssertCompileSize(MptConfigurationPageIOUnit0, 12);
1600
1601	/**
1602	* IO Unit page 1. - Read/Write.
1603	*/
1604	typedef struct MptConfigurationPageIOUnit1
1605	{
1606	/** Union. */
1607	union
1608	{
1609	/** Byte view. */
1610	uint8_t abPageData[8];
1611	/** Field view. */
1612	struct
1613	{
1614	/** The omnipresent header. */
1615	MptConfigurationPageHeader Header;
1616	/** Flag whether this is a single function PCI device. */
1617	unsigned fSingleFunction: 1;
1618	/** Flag whether all possible paths to a device are mapped. */
1619	unsigned fAllPathsMapped: 1;
1620	/** Reserved. */
1621	unsigned u4Reserved: 4;
1622	/** Flag whether all RAID functionality is disabled. */
1623	unsigned fIntegratedRAIDDisabled: 1;
1624	/** Flag whether 32bit PCI accesses are forced. */
1625	unsigned f32BitAccessForced: 1;
1626	/** Reserved. */
1627	unsigned abReserved: 24;
1628	} fields;
1629	} u;
1630	} MptConfigurationPageIOUnit1, *PMptConfigurationPageIOUnit1;
1631	AssertCompileSize(MptConfigurationPageIOUnit1, 8);
1632
1633	/**
1634	* Adapter Ordering.
1635	*/
1636	typedef struct MptConfigurationPageIOUnit2AdapterOrdering
1637	{
1638	/** PCI bus number. */
1639	unsigned u8PCIBusNumber: 8;
1640	/** PCI device and function number. */
1641	unsigned u8PCIDevFn: 8;
1642	/** Flag whether the adapter is embedded. */
1643	unsigned fAdapterEmbedded: 1;
1644	/** Flag whether the adapter is enabled. */
1645	unsigned fAdapterEnabled: 1;
1646	/** Reserved. */
1647	unsigned u6Reserved: 6;
1648	/** Reserved. */
1649	unsigned u8Reserved: 8;
1650	} MptConfigurationPageIOUnit2AdapterOrdering, *PMptConfigurationPageIOUnit2AdapterOrdering;
1651	AssertCompileSize(MptConfigurationPageIOUnit2AdapterOrdering, 4);
1652
1653	/**
1654	* IO Unit page 2. - Read/Write.
1655	*/
1656	typedef struct MptConfigurationPageIOUnit2
1657	{
1658	/** Union. */
1659	union
1660	{
1661	/** Byte view. */
1662	uint8_t abPageData[28];
1663	/** Field view. */
1664	struct
1665	{
1666	/** The omnipresent header. */
1667	MptConfigurationPageHeader Header;
1668	/** Reserved. */
1669	unsigned fReserved: 1;
1670	/** Flag whether Pause on error is enabled. */
1671	unsigned fPauseOnError: 1;
1672	/** Flag whether verbose mode is enabled. */
1673	unsigned fVerboseModeEnabled: 1;
1674	/** Set to disable color video. */
1675	unsigned fDisableColorVideo: 1;
1676	/** Flag whether int 40h is hooked. */
1677	unsigned fNotHookInt40h: 1;
1678	/** Reserved. */
1679	unsigned u3Reserved: 3;
1680	/** Reserved. */
1681	unsigned abReserved: 24;
1682	/** BIOS version. */
1683	uint32_t u32BIOSVersion;
1684	/** Adapter ordering. */
1685	MptConfigurationPageIOUnit2AdapterOrdering aAdapterOrder[4];
1686	} fields;
1687	} u;
1688	} MptConfigurationPageIOUnit2, *PMptConfigurationPageIOUnit2;
1689	AssertCompileSize(MptConfigurationPageIOUnit2, 28);
1690
1691	/*
1692	* IO Unit page 3. - Read/Write.
1693	*/
1694	typedef struct MptConfigurationPageIOUnit3
1695	{
1696	/** Union. */
1697	union
1698	{
1699	/** Byte view. */
1700	uint8_t abPageData[8];
1701	/** Field view. */
1702	struct
1703	{
1704	/** The omnipresent header. */
1705	MptConfigurationPageHeader Header;
1706	/** Number of GPIO values. */
1707	uint8_t u8GPIOCount;
1708	/** Reserved. */
1709	uint8_t abReserved[3];
1710	} fields;
1711	} u;
1712	} MptConfigurationPageIOUnit3, *PMptConfigurationPageIOUnit3;
1713	AssertCompileSize(MptConfigurationPageIOUnit3, 8);
1714
1715	/*
1716	* IO Unit page 4. - Readonly for everyone except the BIOS.
1717	*/
1718	typedef struct MptConfigurationPageIOUnit4
1719	{
1720	/** Union. */
1721	union
1722	{
1723	/** Byte view. */
1724	uint8_t abPageData[20];
1725	/** Field view. */
1726	struct
1727	{
1728	/** The omnipresent header. */
1729	MptConfigurationPageHeader Header;
1730	/** Reserved */
1731	uint32_t u32Reserved;
1732	/** SG entry describing the Firmware location. */
1733	MptSGEntrySimple64 FWImageSGE;
1734	} fields;
1735	} u;
1736	} MptConfigurationPageIOUnit4, *PMptConfigurationPageIOUnit4;
1737	AssertCompileSize(MptConfigurationPageIOUnit4, 20);
1738
1739	/**
1740	* IOC page 0. - Readonly
1741	*/
1742	typedef struct MptConfigurationPageIOC0
1743	{
1744	/** Union. */
1745	union
1746	{
1747	/** Byte view. */
1748	uint8_t abPageData[28];
1749	/** Field view. */
1750	struct
1751	{
1752	/** The omnipresent header. */
1753	MptConfigurationPageHeader Header;
1754	/** Total amount of NV memory in bytes. */
1755	uint32_t u32TotalNVStore;
1756	/** Number of free bytes in the NV store. */
1757	uint32_t u32FreeNVStore;
1758	/** PCI vendor ID. */
1759	uint16_t u16VendorId;
1760	/** PCI device ID. */
1761	uint16_t u16DeviceId;
1762	/** PCI revision ID. */
1763	uint8_t u8RevisionId;
1764	/** Reserved. */
1765	uint8_t abReserved[3];
1766	/** PCI class code. */
1767	uint32_t u32ClassCode;
1768	/** Subsystem vendor Id. */
1769	uint16_t u16SubsystemVendorId;
1770	/** Subsystem Id. */
1771	uint16_t u16SubsystemId;
1772	} fields;
1773	} u;
1774	} MptConfigurationPageIOC0, *PMptConfigurationPageIOC0;
1775	AssertCompileSize(MptConfigurationPageIOC0, 28);
1776
1777	/**
1778	* IOC page 1. - Read/Write
1779	*/
1780	typedef struct MptConfigurationPageIOC1
1781	{
1782	/** Union. */
1783	union
1784	{
1785	/** Byte view. */
1786	uint8_t abPageData[16];
1787	/** Field view. */
1788	struct
1789	{
1790	/** The omnipresent header. */
1791	MptConfigurationPageHeader Header;
1792	/** Flag whether reply coalescing is enabled. */
1793	unsigned fReplyCoalescingEnabled: 1;
1794	/** Reserved. */
1795	unsigned u31Reserved: 31;
1796	/** Coalescing Timeout in microseconds. */
1797	unsigned u32CoalescingTimeout: 32;
1798	/** Coalescing depth. */
1799	unsigned u8CoalescingDepth: 8;
1800	/** Reserved. */
1801	unsigned u8Reserved0: 8;
1802	unsigned u8Reserved1: 8;
1803	unsigned u8Reserved2: 8;
1804	} fields;
1805	} u;
1806	} MptConfigurationPageIOC1, *PMptConfigurationPageIOC1;
1807	AssertCompileSize(MptConfigurationPageIOC1, 16);
1808
1809	/**
1810	* IOC page 2. - Readonly
1811	*/
1812	typedef struct MptConfigurationPageIOC2
1813	{
1814	/** Union. */
1815	union
1816	{
1817	/** Byte view. */
1818	uint8_t abPageData[12];
1819	/** Field view. */
1820	struct
1821	{
1822	/** The omnipresent header. */
1823	MptConfigurationPageHeader Header;
1824	/** Flag whether striping is supported. */
1825	unsigned fStripingSupported: 1;
1826	/** Flag whether enhanced mirroring is supported. */
1827	unsigned fEnhancedMirroringSupported: 1;
1828	/** Flag whether mirroring is supported. */
1829	unsigned fMirroringSupported: 1;
1830	/** Reserved. */
1831	unsigned u26Reserved: 26;
1832	/** Flag whether SES is supported. */
1833	unsigned fSESSupported: 1;
1834	/** Flag whether SAF-TE is supported. */
1835	unsigned fSAFTESupported: 1;
1836	/** Flag whether cross channel volumes are supported. */
1837	unsigned fCrossChannelVolumesSupported: 1;
1838	/** Number of active integrated RAID volumes. */
1839	unsigned u8NumActiveVolumes: 8;
1840	/** Maximum number of integrated RAID volumes supported. */
1841	unsigned u8MaxVolumes: 8;
1842	/** Number of active integrated RAID physical disks. */
1843	unsigned u8NumActivePhysDisks: 8;
1844	/** Maximum number of integrated RAID physical disks supported. */
1845	unsigned u8MaxPhysDisks: 8;
1846	/** RAID volumes... - not supported. */
1847	} fields;
1848	} u;
1849	} MptConfigurationPageIOC2, *PMptConfigurationPageIOC2;
1850	AssertCompileSize(MptConfigurationPageIOC2, 12);
1851
1852	/**
1853	* IOC page 3. - Readonly
1854	*/
1855	typedef struct MptConfigurationPageIOC3
1856	{
1857	/** Union. */
1858	union
1859	{
1860	/** Byte view. */
1861	uint8_t abPageData[8];
1862	/** Field view. */
1863	struct
1864	{
1865	/** The omnipresent header. */
1866	MptConfigurationPageHeader Header;
1867	/** Number of active integrated RAID physical disks. */
1868	uint8_t u8NumPhysDisks;
1869	/** Reserved. */
1870	uint8_t abReserved[3];
1871	} fields;
1872	} u;
1873	} MptConfigurationPageIOC3, *PMptConfigurationPageIOC3;
1874	AssertCompileSize(MptConfigurationPageIOC3, 8);
1875
1876	/**
1877	* IOC page 4. - Read/Write
1878	*/
1879	typedef struct MptConfigurationPageIOC4
1880	{
1881	/** Union. */
1882	union
1883	{
1884	/** Byte view. */
1885	uint8_t abPageData[8];
1886	/** Field view. */
1887	struct
1888	{
1889	/** The omnipresent header. */
1890	MptConfigurationPageHeader Header;
1891	/** Number of SEP entries in this page. */
1892	uint8_t u8ActiveSEP;
1893	/** Maximum number of SEp entries supported. */
1894	uint8_t u8MaxSEP;
1895	/** Reserved. */
1896	uint16_t u16Reserved;
1897	/** SEP entries... - not supported. */
1898	} fields;
1899	} u;
1900	} MptConfigurationPageIOC4, *PMptConfigurationPageIOC4;
1901	AssertCompileSize(MptConfigurationPageIOC4, 8);
1902
1903	/**
1904	* IOC page 6. - Read/Write
1905	*/
1906	typedef struct MptConfigurationPageIOC6
1907	{
1908	/** Union. */
1909	union
1910	{
1911	/** Byte view. */
1912	uint8_t abPageData[60];
1913	/** Field view. */
1914	struct
1915	{
1916	/** The omnipresent header. */
1917	MptConfigurationPageHeader Header;
1918	uint32_t u32CapabilitiesFlags;
1919	uint8_t u8MaxDrivesIS;
1920	uint8_t u8MaxDrivesIM;
1921	uint8_t u8MaxDrivesIME;
1922	uint8_t u8Reserved1;
1923	uint8_t u8MinDrivesIS;
1924	uint8_t u8MinDrivesIM;
1925	uint8_t u8MinDrivesIME;
1926	uint8_t u8Reserved2;
1927	uint8_t u8MaxGlobalHotSpares;
1928	uint8_t u8Reserved3;
1929	uint16_t u16Reserved4;
1930	uint32_t u32Reserved5;
1931	uint32_t u32SupportedStripeSizeMapIS;
1932	uint32_t u32SupportedStripeSizeMapIME;
1933	uint32_t u32Reserved6;
1934	uint8_t u8MetadataSize;
1935	uint8_t u8Reserved7;
1936	uint16_t u16Reserved8;
1937	uint16_t u16MaxBadBlockTableEntries;
1938	uint16_t u16Reserved9;
1939	uint16_t u16IRNvsramUsage;
1940	uint16_t u16Reserved10;
1941	uint32_t u32IRNvsramVersion;
1942	uint32_t u32Reserved11;
1943	} fields;
1944	} u;
1945	} MptConfigurationPageIOC6, *PMptConfigurationPageIOC6;
1946	AssertCompileSize(MptConfigurationPageIOC6, 60);
1947
1948	/**
1949	* BIOS page 1 - Read/write.
1950	*/
1951	typedef struct MptConfigurationPageBIOS1
1952	{
1953	/** Union. */
1954	union
1955	{
1956	/** Byte view. */
1957	uint8_t abPageData[48];
1958	/** Field view. */
1959	struct
1960	{
1961	/** The omnipresent header. */
1962	MptConfigurationPageHeader Header;
1963	/** BIOS options */
1964	uint32_t u32BiosOptions;
1965	/** IOC settings */
1966	uint32_t u32IOCSettings;
1967	/** Reserved */
1968	uint32_t u32Reserved;
1969	/** Device settings */
1970	uint32_t u32DeviceSettings;
1971	/** Number of devices */
1972	uint16_t u16NumberOfDevices;
1973	/** Expander spinup */
1974	uint8_t u8ExpanderSpinup;
1975	/** Reserved */
1976	uint8_t u8Reserved;
1977	/** I/O timeout of block devices without removable media */
1978	uint16_t u16IOTimeoutBlockDevicesNonRM;
1979	/** I/O timeout sequential */
1980	uint16_t u16IOTimeoutSequential;
1981	/** I/O timeout other */
1982	uint16_t u16IOTimeoutOther;
1983	/** I/O timeout of block devices with removable media */
1984	uint16_t u16IOTimeoutBlockDevicesRM;
1985	} fields;
1986	} u;
1987	} MptConfigurationPageBIOS1, *PMptConfigurationPageBIOS1;
1988	AssertCompileSize(MptConfigurationPageBIOS1, 48);
1989
1990	#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_DISABLE RT_BIT(0)
1991	#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_SCAN_FROM_HIGH_TO_LOW RT_BIT(1)
1992	#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SAS_SUPPORT RT_BIT(8)
1993	#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_FC_SUPPORT RT_BIT(9)
1994	#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SPI_SUPPORT RT_BIT(10)
1995
1996	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ALTERNATE_CHS RT_BIT(3)
1997
1998	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_SET(x) ((x) << 4)
1999	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_DISABLED 0x00
2000	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BIOS_ONLY 0x01
2001	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_OS_ONLY 0x02
2002	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BOT 0x03
2003
2004	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_SET(x) ((x) << 6)
2005	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_NO_INT13H 0x00
2006	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_BOOT_MEDIA_INT13H 0x01
2007	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_INT13H 0x02
2008
2009	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_SET(x) ((x & 0xF) << 8)
2010	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_GET(x) ((x >> 8) & 0x0F)
2011	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_SET(x) ((x & 0xF) << 12)
2012	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_GET(x) ((x >> 12) & 0x0F)
2013
2014	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SET(x) (((x) & 0x3) << 16)
2015	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_ENCLOSURE 0x0
2016	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SAS_ADDRESS 0x1
2017
2018	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_DIRECT_ATTACH_SPINUP_MODE_ALL RT_BIT(18)
2019	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_AUTO_PORT_ENABLE RT_BIT(19)
2020
2021	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_SET(x) (((x) & 0xF) << 20)
2022	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_GET(x) ((x >> 20) & 0x0F)
2023
2024	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_SET(x) (((x) & 0xF) << 24)
2025	#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_GET(x) ((x >> 24) & 0x0F)
2026
2027	#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS RT_BIT(0)
2028	#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_NON_REMOVABLE_DEVICES RT_BIT(1)
2029	#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_REMOVABLE_DEVICES RT_BIT(2)
2030	#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS2 RT_BIT(3)
2031	#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_SMART_POLLING RT_BIT(4)
2032
2033	#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_SET(x) ((x) & 0x0F)
2034	#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_GET(x) ((x) & 0x0F)
2035	#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_SET(x) (((x) & 0x0F) << 4)
2036	#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_GET(x) ((x >> 4) & 0x0F)
2037
2038	/**
2039	* BIOS page 2 - Read/write.
2040	*/
2041	typedef struct MptConfigurationPageBIOS2
2042	{
2043	/** Union. */
2044	union
2045	{
2046	/** Byte view. */
2047	uint8_t abPageData[384];
2048	/** Field view. */
2049	struct
2050	{
2051	/** The omnipresent header. */
2052	MptConfigurationPageHeader Header;
2053	/** Reserved */
2054	uint32_t au32Reserved[6];
2055	/** Format of the boot device field. */
2056	uint8_t u8BootDeviceForm;
2057	/** Previous format of the boot device field. */
2058	uint8_t u8PrevBootDeviceForm;
2059	/** Reserved */
2060	uint16_t u16Reserved;
2061	/** Boot device fields - dependent on the format */
2062	union
2063	{
2064	/** Device for AdapterNumber:Bus:Target:LUN */
2065	struct
2066	{
2067	/** Target ID */
2068	uint8_t u8TargetID;
2069	/** Bus */
2070	uint8_t u8Bus;
2071	/** Adapter Number */
2072	uint8_t u8AdapterNumber;
2073	/** Reserved */
2074	uint8_t u8Reserved;
2075	/** Reserved */
2076	uint32_t au32Reserved[3];
2077	/** LUN */
2078	uint32_t aLUN[5];
2079	/** Reserved */
2080	uint32_t au32Reserved2[56];
2081	} AdapterNumberBusTargetLUN;
2082	/** Device for PCIAddress:Bus:Target:LUN */
2083	struct
2084	{
2085	/** Target ID */
2086	uint8_t u8TargetID;
2087	/** Bus */
2088	uint8_t u8Bus;
2089	/** Adapter Number */
2090	uint16_t u16PCIAddress;
2091	/** Reserved */
2092	uint32_t au32Reserved[3];
2093	/** LUN */
2094	uint32_t aLUN[5];
2095	/** Reserved */
2096	uint32_t au32Reserved2[56];
2097	} PCIAddressBusTargetLUN;
2098	#if 0 /** @todo r=bird: The u16PCISlotNo member looks like it has the wrong type, but I cannot immediately locate specs and check. */
2099	/** Device for PCISlotNo:Bus:Target:LUN */
2100	struct
2101	{
2102	/** Target ID */
2103	uint8_t u8TargetID;
2104	/** Bus */
2105	uint8_t u8Bus;
2106	/** PCI Slot Number */
2107	uint8_t u16PCISlotNo;
2108	/** Reserved */
2109	uint32_t au32Reserved[3];
2110	/** LUN */
2111	uint32_t aLUN[5];
2112	/** Reserved */
2113	uint32_t au32Reserved2[56];
2114	} PCIAddressBusSlotLUN;
2115	#endif
2116	/** Device for FC channel world wide name */
2117	struct
2118	{
2119	/** World wide port name low */
2120	uint32_t u32WorldWidePortNameLow;
2121	/** World wide port name high */
2122	uint32_t u32WorldWidePortNameHigh;
2123	/** Reserved */
2124	uint32_t au32Reserved[3];
2125	/** LUN */
2126	uint32_t aLUN[5];
2127	/** Reserved */
2128	uint32_t au32Reserved2[56];
2129	} FCWorldWideName;
2130	/** Device for FC channel world wide name */
2131	struct
2132	{
2133	/** SAS address */
2134	SASADDRESS SASAddress;
2135	/** Reserved */
2136	uint32_t au32Reserved[3];
2137	/** LUN */
2138	uint32_t aLUN[5];
2139	/** Reserved */
2140	uint32_t au32Reserved2[56];
2141	} SASWorldWideName;
2142	/** Device for Enclosure/Slot */
2143	struct
2144	{
2145	/** Enclosure logical ID */
2146	uint64_t u64EnclosureLogicalID;
2147	/** Reserved */
2148	uint32_t au32Reserved[3];
2149	/** LUN */
2150	uint32_t aLUN[5];
2151	/** Reserved */
2152	uint32_t au32Reserved2[56];
2153	} EnclosureSlot;
2154	} BootDevice;
2155	} fields;
2156	} u;
2157	} MptConfigurationPageBIOS2, *PMptConfigurationPageBIOS2;
2158	AssertCompileMemberAlignment(MptConfigurationPageBIOS2, u.fields, 8);
2159	AssertCompileSize(MptConfigurationPageBIOS2, 384);
2160
2161	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SET(x) ((x) & 0x0F)
2162	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FIRST 0x0
2163	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ADAPTER_BUS_TARGET_LUN 0x1
2164	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCIADDR_BUS_TARGET_LUN 0x2
2165	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCISLOT_BUS_TARGET_LUN 0x3
2166	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FC_WWN 0x4
2167	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SAS_WWN 0x5
2168	#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ENCLOSURE_SLOT 0x6
2169
2170	/**
2171	* BIOS page 4 - Read/Write (Where is 3? - not defined in the spec)
2172	*/
2173	#pragma pack(1) /* u64ReassignmentBaseWWID starts at offset 4, which isn't normally natural for uint64_t. */
2174	typedef struct MptConfigurationPageBIOS4
2175	{
2176	/** Union. */
2177	union
2178	{
2179	/** Byte view. */
2180	uint8_t abPageData[12];
2181	/** Field view. */
2182	struct
2183	{
2184	/** The omnipresent header. */
2185	MptConfigurationPageHeader Header;
2186	/** Reassignment Base WWID */
2187	uint64_t u64ReassignmentBaseWWID;
2188	} fields;
2189	} u;
2190	} MptConfigurationPageBIOS4, *PMptConfigurationPageBIOS4;
2191	#pragma pack()
2192	AssertCompileSize(MptConfigurationPageBIOS4, 12);
2193
2194	/**
2195	* SCSI-SPI port page 0. - Readonly
2196	*/
2197	typedef struct MptConfigurationPageSCSISPIPort0
2198	{
2199	/** Union. */
2200	union
2201	{
2202	/** Byte view. */
2203	uint8_t abPageData[12];
2204	/** Field view. */
2205	struct
2206	{
2207	/** The omnipresent header. */
2208	MptConfigurationPageHeader Header;
2209	/** Flag whether this port is information unit transfers capable. */
2210	unsigned fInformationUnitTransfersCapable: 1;
2211	/** Flag whether the port is DT (Dual Transfer) capable. */
2212	unsigned fDTCapable: 1;
2213	/** Flag whether the port is QAS (Quick Arbitrate and Select) capable. */
2214	unsigned fQASCapable: 1;
2215	/** Reserved. */
2216	unsigned u5Reserved1: 5;
2217	/** Minimum Synchronous transfer period. */
2218	unsigned u8MinimumSynchronousTransferPeriod: 8;
2219	/** Maximum synchronous offset. */
2220	unsigned u8MaximumSynchronousOffset: 8;
2221	/** Reserved. */
2222	unsigned u5Reserved2: 5;
2223	/** Flag whether indicating the width of the bus - 0 narrow and 1 for wide. */
2224	unsigned fWide: 1;
2225	/** Reserved */
2226	unsigned fReserved: 1;
2227	/** Flag whether the port is AIP (Asynchronous Information Protection) capable. */
2228	unsigned fAIPCapable: 1;
2229	/** Signaling Type. */
2230	unsigned u2SignalingType: 2;
2231	/** Reserved. */
2232	unsigned u30Reserved: 30;
2233	} fields;
2234	} u;
2235	} MptConfigurationPageSCSISPIPort0, *PMptConfigurationPageSCSISPIPort0;
2236	AssertCompileSize(MptConfigurationPageSCSISPIPort0, 12);
2237
2238	/**
2239	* SCSI-SPI port page 1. - Read/Write
2240	*/
2241	typedef struct MptConfigurationPageSCSISPIPort1
2242	{
2243	/** Union. */
2244	union
2245	{
2246	/** Byte view. */
2247	uint8_t abPageData[12];
2248	/** Field view. */
2249	struct
2250	{
2251	/** The omnipresent header. */
2252	MptConfigurationPageHeader Header;
2253	/** The SCSI ID of the port. */
2254	uint8_t u8SCSIID;
2255	/** Reserved. */
2256	uint8_t u8Reserved;
2257	/** Port response IDs Bit mask field. */
2258	uint16_t u16PortResponseIDsBitmask;
2259	/** Value for the on BUS timer. */
2260	uint32_t u32OnBusTimerValue;
2261	} fields;
2262	} u;
2263	} MptConfigurationPageSCSISPIPort1, *PMptConfigurationPageSCSISPIPort1;
2264	AssertCompileSize(MptConfigurationPageSCSISPIPort1, 12);
2265
2266	/**
2267	* Device settings for one device.
2268	*/
2269	typedef struct MptDeviceSettings
2270	{
2271	/** Timeout for I/O in seconds. */
2272	unsigned u8Timeout: 8;
2273	/** Minimum synchronous factor. */
2274	unsigned u8SyncFactor: 8;
2275	/** Flag whether disconnect is enabled. */
2276	unsigned fDisconnectEnable: 1;
2277	/** Flag whether Scan ID is enabled. */
2278	unsigned fScanIDEnable: 1;
2279	/** Flag whether Scan LUNs is enabled. */
2280	unsigned fScanLUNEnable: 1;
2281	/** Flag whether tagged queuing is enabled. */
2282	unsigned fTaggedQueuingEnabled: 1;
2283	/** Flag whether wide is enabled. */
2284	unsigned fWideDisable: 1;
2285	/** Flag whether this device is bootable. */
2286	unsigned fBootChoice: 1;
2287	/** Reserved. */
2288	unsigned u10Reserved: 10;
2289	} MptDeviceSettings, *PMptDeviceSettings;
2290	AssertCompileSize(MptDeviceSettings, 4);
2291
2292	/**
2293	* SCSI-SPI port page 2. - Read/Write for the BIOS
2294	*/
2295	typedef struct MptConfigurationPageSCSISPIPort2
2296	{
2297	/** Union. */
2298	union
2299	{
2300	/** Byte view. */
2301	uint8_t abPageData[76];
2302	/** Field view. */
2303	struct
2304	{
2305	/** The omnipresent header. */
2306	MptConfigurationPageHeader Header;
2307	/** Flag indicating the bus scan order. */
2308	unsigned fBusScanOrderHighToLow: 1;
2309	/** Reserved. */
2310	unsigned fReserved: 1;
2311	/** Flag whether SCSI Bus resets are avoided. */
2312	unsigned fAvoidSCSIBusResets: 1;
2313	/** Flag whether alternate CHS is used. */
2314	unsigned fAlternateCHS: 1;
2315	/** Flag whether termination is disabled. */
2316	unsigned fTerminationDisabled: 1;
2317	/** Reserved. */
2318	unsigned u27Reserved: 27;
2319	/** Host SCSI ID. */
2320	unsigned u4HostSCSIID: 4;
2321	/** Initialize HBA. */
2322	unsigned u2InitializeHBA: 2;
2323	/** Removeable media setting. */
2324	unsigned u2RemovableMediaSetting: 2;
2325	/** Spinup delay. */
2326	unsigned u4SpinupDelay: 4;
2327	/** Negotiating settings. */
2328	unsigned u2NegotitatingSettings: 2;
2329	/** Reserved. */
2330	unsigned u18Reserved: 18;
2331	/** Device Settings. */
2332	MptDeviceSettings aDeviceSettings[16];
2333	} fields;
2334	} u;
2335	} MptConfigurationPageSCSISPIPort2, *PMptConfigurationPageSCSISPIPort2;
2336	AssertCompileSize(MptConfigurationPageSCSISPIPort2, 76);
2337
2338	/**
2339	* SCSI-SPI device page 0. - Readonly
2340	*/
2341	typedef struct MptConfigurationPageSCSISPIDevice0
2342	{
2343	/** Union. */
2344	union
2345	{
2346	/** Byte view. */
2347	uint8_t abPageData[12];
2348	/** Field view. */
2349	struct
2350	{
2351	/** The omnipresent header. */
2352	MptConfigurationPageHeader Header;
2353	/** Negotiated Parameters. */
2354	/** Information Units enabled. */
2355	unsigned fInformationUnitsEnabled: 1;
2356	/** Dual Transfers Enabled. */
2357	unsigned fDTEnabled: 1;
2358	/** QAS enabled. */
2359	unsigned fQASEnabled: 1;
2360	/** Reserved. */
2361	unsigned u5Reserved1: 5;
2362	/** Synchronous Transfer period. */
2363	unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2364	/** Synchronous offset. */
2365	unsigned u8NegotiatedSynchronousOffset: 8;
2366	/** Reserved. */
2367	unsigned u5Reserved2: 5;
2368	/** Width - 0 for narrow and 1 for wide. */
2369	unsigned fWide: 1;
2370	/** Reserved. */
2371	unsigned fReserved: 1;
2372	/** AIP enabled. */
2373	unsigned fAIPEnabled: 1;
2374	/** Flag whether negotiation occurred. */
2375	unsigned fNegotationOccured: 1;
2376	/** Flag whether a SDTR message was rejected. */
2377	unsigned fSDTRRejected: 1;
2378	/** Flag whether a WDTR message was rejected. */
2379	unsigned fWDTRRejected: 1;
2380	/** Flag whether a PPR message was rejected. */
2381	unsigned fPPRRejected: 1;
2382	/** Reserved. */
2383	unsigned u28Reserved: 28;
2384	} fields;
2385	} u;
2386	} MptConfigurationPageSCSISPIDevice0, *PMptConfigurationPageSCSISPIDevice0;
2387	AssertCompileSize(MptConfigurationPageSCSISPIDevice0, 12);
2388
2389	/**
2390	* SCSI-SPI device page 1. - Read/Write
2391	*/
2392	typedef struct MptConfigurationPageSCSISPIDevice1
2393	{
2394	/** Union. */
2395	union
2396	{
2397	/** Byte view. */
2398	uint8_t abPageData[16];
2399	/** Field view. */
2400	struct
2401	{
2402	/** The omnipresent header. */
2403	MptConfigurationPageHeader Header;
2404	/** Requested Parameters. */
2405	/** Information Units enable. */
2406	unsigned fInformationUnitsEnable: 1;
2407	/** Dual Transfers Enable. */
2408	unsigned fDTEnable: 1;
2409	/** QAS enable. */
2410	unsigned fQASEnable: 1;
2411	/** Reserved. */
2412	unsigned u5Reserved1: 5;
2413	/** Synchronous Transfer period. */
2414	unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2415	/** Synchronous offset. */
2416	unsigned u8NegotiatedSynchronousOffset: 8;
2417	/** Reserved. */
2418	unsigned u5Reserved2: 5;
2419	/** Width - 0 for narrow and 1 for wide. */
2420	unsigned fWide: 1;
2421	/** Reserved. */
2422	unsigned fReserved1: 1;
2423	/** AIP enable. */
2424	unsigned fAIPEnable: 1;
2425	/** Reserved. */
2426	unsigned fReserved2: 1;
2427	/** WDTR disallowed. */
2428	unsigned fWDTRDisallowed: 1;
2429	/** SDTR disallowed. */
2430	unsigned fSDTRDisallowed: 1;
2431	/** Reserved. */
2432	unsigned u29Reserved: 29;
2433	} fields;
2434	} u;
2435	} MptConfigurationPageSCSISPIDevice1, *PMptConfigurationPageSCSISPIDevice1;
2436	AssertCompileSize(MptConfigurationPageSCSISPIDevice1, 16);
2437
2438	/**
2439	* SCSI-SPI device page 2. - Read/Write
2440	*/
2441	typedef struct MptConfigurationPageSCSISPIDevice2
2442	{
2443	/** Union. */
2444	union
2445	{
2446	/** Byte view. */
2447	uint8_t abPageData[16];
2448	/** Field view. */
2449	struct
2450	{
2451	/** The omnipresent header. */
2452	MptConfigurationPageHeader Header;
2453	/** Reserved. */
2454	unsigned u4Reserved: 4;
2455	/** ISI enable. */
2456	unsigned fISIEnable: 1;
2457	/** Secondary driver enable. */
2458	unsigned fSecondaryDriverEnable: 1;
2459	/** Reserved. */
2460	unsigned fReserved: 1;
2461	/** Slew create controller. */
2462	unsigned u3SlewRateControler: 3;
2463	/** Primary drive strength controller. */
2464	unsigned u3PrimaryDriveStrengthControl: 3;
2465	/** Secondary drive strength controller. */
2466	unsigned u3SecondaryDriveStrengthControl: 3;
2467	/** Reserved. */
2468	unsigned u12Reserved: 12;
2469	/** XCLKH_ST. */
2470	unsigned fXCLKH_ST: 1;
2471	/** XCLKS_ST. */
2472	unsigned fXCLKS_ST: 1;
2473	/** XCLKH_DT. */
2474	unsigned fXCLKH_DT: 1;
2475	/** XCLKS_DT. */
2476	unsigned fXCLKS_DT: 1;
2477	/** Parity pipe select. */
2478	unsigned u2ParityPipeSelect: 2;
2479	/** Reserved. */
2480	unsigned u30Reserved: 30;
2481	/** Data bit pipeline select. */
2482	unsigned u32DataPipelineSelect: 32;
2483	} fields;
2484	} u;
2485	} MptConfigurationPageSCSISPIDevice2, *PMptConfigurationPageSCSISPIDevice2;
2486	AssertCompileSize(MptConfigurationPageSCSISPIDevice2, 16);
2487
2488	/**
2489	* SCSI-SPI device page 3 (Revision G). - Readonly
2490	*/
2491	typedef struct MptConfigurationPageSCSISPIDevice3
2492	{
2493	/** Union. */
2494	union
2495	{
2496	/** Byte view. */
2497	uint8_t abPageData[1];
2498	/** Field view. */
2499	struct
2500	{
2501	/** The omnipresent header. */
2502	MptConfigurationPageHeader Header;
2503	/** Number of times the IOC rejected a message because it doesn't support the operation. */
2504	uint16_t u16MsgRejectCount;
2505	/** Number of times the SCSI bus entered an invalid operation state. */
2506	uint16_t u16PhaseErrorCount;
2507	/** Number of parity errors. */
2508	uint16_t u16ParityCount;
2509	/** Reserved. */
2510	uint16_t u16Reserved;
2511	} fields;
2512	} u;
2513	} MptConfigurationPageSCSISPIDevice3, *PMptConfigurationPageSCSISPIDevice3;
2514	AssertCompileSize(MptConfigurationPageSCSISPIDevice3, 12);
2515
2516	/**
2517	* PHY entry for the SAS I/O unit page 0
2518	*/
2519	typedef struct MptConfigurationPageSASIOUnit0PHY
2520	{
2521	/** Port number */
2522	uint8_t u8Port;
2523	/** Port flags */
2524	uint8_t u8PortFlags;
2525	/** Phy flags */
2526	uint8_t u8PhyFlags;
2527	/** negotiated link rate */
2528	uint8_t u8NegotiatedLinkRate;
2529	/** Controller phy device info */
2530	uint32_t u32ControllerPhyDeviceInfo;
2531	/** Attached device handle */
2532	uint16_t u16AttachedDevHandle;
2533	/** Controller device handle */
2534	uint16_t u16ControllerDevHandle;
2535	/** Discovery status */
2536	uint32_t u32DiscoveryStatus;
2537	} MptConfigurationPageSASIOUnit0PHY, *PMptConfigurationPageSASIOUnit0PHY;
2538	AssertCompileSize(MptConfigurationPageSASIOUnit0PHY, 16);
2539
2540	/**
2541	* SAS I/O Unit page 0 - Readonly
2542	*/
2543	typedef struct MptConfigurationPageSASIOUnit0
2544	{
2545	/** Union. */
2546	union
2547	{
2548	/** Byte view - variable. */
2549	uint8_t abPageData[1];
2550	/** Field view. */
2551	struct
2552	{
2553	/** The omnipresent header. */
2554	MptExtendedConfigurationPageHeader ExtHeader;
2555	/** Nvdata version default */
2556	uint16_t u16NvdataVersionDefault;
2557	/** Nvdata version persistent */
2558	uint16_t u16NvdataVersionPersistent;
2559	/** Number of physical ports */
2560	uint8_t u8NumPhys;
2561	/** Reserved */
2562	uint8_t au8Reserved[3];
2563	/** Content for each physical port - variable depending on the amount of ports. */
2564	MptConfigurationPageSASIOUnit0PHY aPHY[1];
2565	} fields;
2566	} u;
2567	} MptConfigurationPageSASIOUnit0, *PMptConfigurationPageSASIOUnit0;
2568	AssertCompileSize(MptConfigurationPageSASIOUnit0, 8+2+2+1+3+sizeof(MptConfigurationPageSASIOUnit0PHY));
2569
2570	#define LSILOGICSCSI_SASIOUNIT0_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit0) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit0PHY))
2571
2572	#define LSILOGICSCSI_SASIOUNIT0_PORT_CONFIGURATION_AUTO RT_BIT(0)
2573	#define LSILOGICSCSI_SASIOUNIT0_PORT_TARGET_IOC RT_BIT(2)
2574	#define LSILOGICSCSI_SASIOUNIT0_PORT_DISCOVERY_IN_STATUS RT_BIT(3)
2575
2576	#define LSILOGICSCSI_SASIOUNIT0_PHY_RX_INVERTED RT_BIT(0)
2577	#define LSILOGICSCSI_SASIOUNIT0_PHY_TX_INVERTED RT_BIT(1)
2578	#define LSILOGICSCSI_SASIOUNIT0_PHY_DISABLED RT_BIT(2)
2579
2580	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(x) ((x) & 0x0F)
2581	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_GET(x) ((x) & 0x0F)
2582	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_UNKNOWN 0x00
2583	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_DISABLED 0x01
2584	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED 0x02
2585	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SATA_OOB 0x03
2586	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_15GB 0x08
2587	#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB 0x09
2588
2589	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(x) ((x) & 0x3)
2590	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO 0x0
2591	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END 0x1
2592	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_EDGE_EXPANDER 0x2
2593	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2594
2595	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA_HOST RT_BIT(3)
2596	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_INITIATOR RT_BIT(4)
2597	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_INITIATOR RT_BIT(5)
2598	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_INITIATOR RT_BIT(6)
2599	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA RT_BIT(7)
2600	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_TARGET RT_BIT(8)
2601	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_TARGET RT_BIT(9)
2602	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET RT_BIT(10)
2603	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2604	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_LSI RT_BIT(12)
2605	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_ATAPI_DEVICE RT_BIT(13)
2606	#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SEP_DEVICE RT_BIT(14)
2607
2608	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_LOOP RT_BIT(0)
2609	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNADDRESSABLE RT_BIT(1)
2610	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SAME_SAS_ADDR RT_BIT(2)
2611	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXPANDER_ERROR RT_BIT(3)
2612	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_TIMEOUT RT_BIT(4)
2613	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_OOE RT_BIT(5)
2614	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_IDX RT_BIT(6)
2615	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_FUNC_FAILED RT_BIT(7)
2616	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_CRC_ERROR RT_BIT(8)
2617	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SUBTRSCTIVE_LNK RT_BIT(9)
2618	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_TBL_LNK RT_BIT(10)
2619	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNSUPPORTED_DEV RT_BIT(11)
2620	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MAX_SATA_TGTS RT_BIT(12)
2621	#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MULT_CTRLS RT_BIT(13)
2622
2623	/**
2624	* PHY entry for the SAS I/O unit page 1
2625	*/
2626	typedef struct MptConfigurationPageSASIOUnit1PHY
2627	{
2628	/** Port number */
2629	uint8_t u8Port;
2630	/** Port flags */
2631	uint8_t u8PortFlags;
2632	/** Phy flags */
2633	uint8_t u8PhyFlags;
2634	/** Max link rate */
2635	uint8_t u8MaxMinLinkRate;
2636	/** Controller phy device info */
2637	uint32_t u32ControllerPhyDeviceInfo;
2638	/** Maximum target port connect time */
2639	uint16_t u16MaxTargetPortConnectTime;
2640	/** Reserved */
2641	uint16_t u16Reserved;
2642	} MptConfigurationPageSASIOUnit1PHY, *PMptConfigurationPageSASIOUnit1PHY;
2643	AssertCompileSize(MptConfigurationPageSASIOUnit1PHY, 12);
2644
2645	/**
2646	* SAS I/O Unit page 1 - Read/Write
2647	*/
2648	typedef struct MptConfigurationPageSASIOUnit1
2649	{
2650	/** Union. */
2651	union
2652	{
2653	/** Byte view - variable. */
2654	uint8_t abPageData[1];
2655	/** Field view. */
2656	struct
2657	{
2658	/** The omnipresent header. */
2659	MptExtendedConfigurationPageHeader ExtHeader;
2660	/** Control flags */
2661	uint16_t u16ControlFlags;
2662	/** maximum number of SATA targets */
2663	uint16_t u16MaxNumSATATargets;
2664	/** additional control flags */
2665	uint16_t u16AdditionalControlFlags;
2666	/** Reserved */
2667	uint16_t u16Reserved;
2668	/** Number of PHYs */
2669	uint8_t u8NumPhys;
2670	/** maximum SATA queue depth */
2671	uint8_t u8SATAMaxQDepth;
2672	/** Delay for reporting missing devices. */
2673	uint8_t u8ReportDeviceMissingDelay;
2674	/** I/O device missing delay */
2675	uint8_t u8IODeviceMissingDelay;
2676	/** Content for each physical port - variable depending on the number of ports */
2677	MptConfigurationPageSASIOUnit1PHY aPHY[1];
2678	} fields;
2679	} u;
2680	} MptConfigurationPageSASIOUnit1, *PMptConfigurationPageSASIOUnit1;
2681	AssertCompileSize(MptConfigurationPageSASIOUnit1, 8+12+sizeof(MptConfigurationPageSASIOUnit1PHY));
2682
2683	#define LSILOGICSCSI_SASIOUNIT1_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit1) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit1PHY))
2684
2685	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_CLEAR_SATA_AFFILIATION RT_BIT(0)
2686	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_FIRST_LEVEL_DISCOVERY_ONLY RT_BIT(1)
2687	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SUBTRACTIVE_LNK_ILLEGAL RT_BIT(2)
2688	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_IOC_ENABLE_HIGH_PHY RT_BIT(3)
2689	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED RT_BIT(4)
2690	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED RT_BIT(5)
2691	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED RT_BIT(6)
2692	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LBA48_REQUIRED RT_BIT(7)
2693	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_INIT_POSTPONED RT_BIT(8)
2694
2695	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SET(x) (((x) & 0x3) << 9)
2696	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_GET(x) (((x) >> 9) & 0x3)
2697	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS_AND_SATA 0x00
2698	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS 0x01
2699	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SATA 0x02
2700
2701	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_EXP_ADDR RT_BIT(11)
2702	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SETTINGS_PRESERV_REQUIRED RT_BIT(12)
2703	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_15GB RT_BIT(13)
2704	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_30GB RT_BIT(14)
2705	#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SAS_SELF_TEST_ENABLED RT_BIT(15)
2706
2707	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_TBL_LNKS_ALLOW RT_BIT(0)
2708	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_NO_AFFIL RT_BIT(1)
2709	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_SELF_AFFIL RT_BIT(2)
2710	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_OTHER_AFFIL RT_BIT(3)
2711	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_PORT_EN_ONLY RT_BIT(4)
2712	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_HIDE_NON_ZERO_PHYS RT_BIT(5)
2713	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_ASYNC_NOTIF RT_BIT(6)
2714	#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_MULT_PORTS_ILL_SAME_DOMAIN RT_BIT(7)
2715
2716	#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_UNITS_16_SEC RT_BIT(7)
2717	#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_SET(x) ((x) & 0x7F)
2718	#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_GET(x) ((x) & 0x7F)
2719
2720	#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_AUTO RT_BIT(0)
2721	#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_IOC1 RT_BIT(2)
2722
2723	#define LSILOGICSCSI_SASIOUNIT1_PHY_RX_INVERT RT_BIT(0)
2724	#define LSILOGICSCSI_SASIOUNIT1_PHY_TX_INVERT RT_BIT(1)
2725	#define LSILOGICSCSI_SASIOUNIT1_PHY_DISABLE RT_BIT(2)
2726
2727	#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(x) ((x) & 0x0F)
2728	#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_GET(x) ((x) & 0x0F)
2729	#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(x) (((x) & 0x0F) << 4)
2730	#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_GET(x) ((x >> 4) & 0x0F)
2731	#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB 0x8
2732	#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB 0x9
2733
2734	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_SET(x) ((x) & 0x3)
2735	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_GET(x) ((x) & 0x3)
2736	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_NO 0x0
2737	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_END 0x1
2738	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_EDGE_EXPANDER 0x2
2739	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2740	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_INITIATOR RT_BIT(4)
2741	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_INITIATOR RT_BIT(5)
2742	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_INITIATOR RT_BIT(6)
2743	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_TARGET RT_BIT(8)
2744	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_TARGET RT_BIT(9)
2745	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_TARGET RT_BIT(10)
2746	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2747	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_LSI RT_BIT(12)
2748	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_ATAPI RT_BIT(13)
2749	#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SEP RT_BIT(14)
2750
2751	/**
2752	* SAS I/O unit page 2 - Read/Write
2753	*/
2754	typedef struct MptConfigurationPageSASIOUnit2
2755	{
2756	/** Union. */
2757	union
2758	{
2759	/** Byte view - variable. */
2760	uint8_t abPageData[1];
2761	/** Field view. */
2762	struct
2763	{
2764	/** The omnipresent header. */
2765	MptExtendedConfigurationPageHeader ExtHeader;
2766	/** Device numbers per enclosure */
2767	uint8_t u8NumDevsPerEnclosure;
2768	/** Boot device wait time */
2769	uint8_t u8BootDeviceWaitTime;
2770	/** Reserved */
2771	uint16_t u16Reserved;
2772	/** Maximum number of persistent Bus and target ID mappings */
2773	uint16_t u16MaxPersistentIDs;
2774	/** Number of persistent IDs used */
2775	uint16_t u16NumPersistentIDsUsed;
2776	/** Status */
2777	uint8_t u8Status;
2778	/** Flags */
2779	uint8_t u8Flags;
2780	/** Maximum number of physical mapped IDs */
2781	uint16_t u16MaxNumPhysicalMappedIDs;
2782	} fields;
2783	} u;
2784	} MptConfigurationPageSASIOUnit2, *PMptConfigurationPageSASIOUnit2;
2785	AssertCompileSize(MptConfigurationPageSASIOUnit2, 20);
2786
2787	#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_TBL_FULL RT_BIT(0)
2788	#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_DISABLED RT_BIT(1)
2789	#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_ENC_DEV_UNMAPPED RT_BIT(2)
2790	#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_DEV_LIMIT_EXCEEDED RT_BIT(3)
2791
2792	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_MAP_DISABLE RT_BIT(0)
2793	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_SET(x) ((x & 0x7) << 1)
2794	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_GET(x) ((x >> 1) & 0x7)
2795	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_NO 0x0
2796	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_DIRECT_ATTACHED 0x1
2797	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_ENC 0x2
2798	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_HOST 0x7
2799	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_RESERVE_TARGET_ID_ZERO RT_BIT(4)
2800	#define LSILOGICSCSI_SASIOUNIT2_FLAGS_START_SLOT_NUMBER_ONE RT_BIT(5)
2801
2802	/**
2803	* SAS I/O unit page 3 - Read/Write
2804	*/
2805	typedef struct MptConfigurationPageSASIOUnit3
2806	{
2807	/** Union. */
2808	union
2809	{
2810	/** Byte view - variable. */
2811	uint8_t abPageData[1];
2812	/** Field view. */
2813	struct
2814	{
2815	/** The omnipresent header. */
2816	MptExtendedConfigurationPageHeader ExtHeader;
2817	/** Reserved */
2818	uint32_t u32Reserved;
2819	uint32_t u32MaxInvalidDwordCount;
2820	uint32_t u32InvalidDwordCountTime;
2821	uint32_t u32MaxRunningDisparityErrorCount;
2822	uint32_t u32RunningDisparityErrorTime;
2823	uint32_t u32MaxLossDwordSynchCount;
2824	uint32_t u32LossDwordSynchCountTime;
2825	uint32_t u32MaxPhysResetProblemCount;
2826	uint32_t u32PhyResetProblemTime;
2827	} fields;
2828	} u;
2829	} MptConfigurationPageSASIOUnit3, *PMptConfigurationPageSASIOUnit3;
2830	AssertCompileSize(MptConfigurationPageSASIOUnit3, 44);
2831
2832	/**
2833	* SAS PHY page 0 - Readonly
2834	*/
2835	#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
2836	typedef struct MptConfigurationPageSASPHY0
2837	{
2838	/** Union. */
2839	union
2840	{
2841	/** Byte view - variable. */
2842	uint8_t abPageData[1];
2843	/** Field view. */
2844	struct
2845	{
2846	/** The omnipresent header. */
2847	MptExtendedConfigurationPageHeader ExtHeader;
2848	/** Owner dev handle. */
2849	uint16_t u16OwnerDevHandle;
2850	/** Reserved */
2851	uint16_t u16Reserved0;
2852	/** SAS address */
2853	SASADDRESS SASAddress;
2854	/** Attached device handle */
2855	uint16_t u16AttachedDevHandle;
2856	/** Attached phy identifier */
2857	uint8_t u8AttachedPhyIdentifier;
2858	/** Reserved */
2859	uint8_t u8Reserved1;
2860	/** Attached device information */
2861	uint32_t u32AttachedDeviceInfo;
2862	/** Programmed link rate */
2863	uint8_t u8ProgrammedLinkRate;
2864	/** Hardware link rate */
2865	uint8_t u8HwLinkRate;
2866	/** Change count */
2867	uint8_t u8ChangeCount;
2868	/** Flags */
2869	uint8_t u8Flags;
2870	/** Phy information */
2871	uint32_t u32PhyInfo;
2872	} fields;
2873	} u;
2874	} MptConfigurationPageSASPHY0, *PMptConfigurationPageSASPHY0;
2875	#pragma pack()
2876	AssertCompileSize(MptConfigurationPageSASPHY0, 36);
2877
2878	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2879	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2880	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO 0x0
2881	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END 0x1
2882	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2883	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2884	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2885	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2886	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2887	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2888	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2889	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2890	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2891	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2892	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2893	#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2894
2895	/**
2896	* SAS PHY page 1 - Readonly
2897	*/
2898	typedef struct MptConfigurationPageSASPHY1
2899	{
2900	/** Union. */
2901	union
2902	{
2903	/** Byte view - variable. */
2904	uint8_t abPageData[1];
2905	/** Field view. */
2906	struct
2907	{
2908	/** The omnipresent header. */
2909	MptExtendedConfigurationPageHeader ExtHeader;
2910	/** Reserved */
2911	uint32_t u32Reserved0;
2912	uint32_t u32InvalidDwordCound;
2913	uint32_t u32RunningDisparityErrorCount;
2914	uint32_t u32LossDwordSynchCount;
2915	uint32_t u32PhyResetProblemCount;
2916	} fields;
2917	} u;
2918	} MptConfigurationPageSASPHY1, *PMptConfigurationPageSASPHY1;
2919	AssertCompileSize(MptConfigurationPageSASPHY1, 28);
2920
2921	/**
2922	* SAS Device page 0 - Readonly
2923	*/
2924	#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
2925	typedef struct MptConfigurationPageSASDevice0
2926	{
2927	/** Union. */
2928	union
2929	{
2930	/** Byte view - variable. */
2931	uint8_t abPageData[1];
2932	/** Field view. */
2933	struct
2934	{
2935	/** The omnipresent header. */
2936	MptExtendedConfigurationPageHeader ExtHeader;
2937	/** Slot number */
2938	uint16_t u16Slot;
2939	/** Enclosure handle. */
2940	uint16_t u16EnclosureHandle;
2941	/** SAS address */
2942	SASADDRESS SASAddress;
2943	/** Parent device handle */
2944	uint16_t u16ParentDevHandle;
2945	/** Phy number */
2946	uint8_t u8PhyNum;
2947	/** Access status */
2948	uint8_t u8AccessStatus;
2949	/** Device handle */
2950	uint16_t u16DevHandle;
2951	/** Target ID */
2952	uint8_t u8TargetID;
2953	/** Bus */
2954	uint8_t u8Bus;
2955	/** Device info */
2956	uint32_t u32DeviceInfo;
2957	/** Flags */
2958	uint16_t u16Flags;
2959	/** Physical port */
2960	uint8_t u8PhysicalPort;
2961	/** Reserved */
2962	uint8_t u8Reserved0;
2963	} fields;
2964	} u;
2965	} MptConfigurationPageSASDevice0, *PMptConfigurationPageSASDevice0;
2966	#pragma pack()
2967	AssertCompileSize(MptConfigurationPageSASDevice0, 36);
2968
2969	#define LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS (0x00)
2970
2971	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2972	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2973	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_NO 0x0
2974	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_END 0x1
2975	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2976	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2977	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2978	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2979	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2980	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2981	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2982	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2983	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2984	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2985	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2986	#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2987
2988	#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT (RT_BIT(0))
2989	#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID (RT_BIT(1))
2990	#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT (RT_BIT(2))
2991
2992	/**
2993	* SAS Device page 1 - Readonly
2994	*/
2995	#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
2996	typedef struct MptConfigurationPageSASDevice1
2997	{
2998	/** Union. */
2999	union
3000	{
3001	/** Byte view - variable. */
3002	uint8_t abPageData[1];
3003	/** Field view. */
3004	struct
3005	{
3006	/** The omnipresent header. */
3007	MptExtendedConfigurationPageHeader ExtHeader;
3008	/** Reserved */
3009	uint32_t u32Reserved0;
3010	/** SAS address */
3011	SASADDRESS SASAddress;
3012	/** Reserved */
3013	uint32_t u32Reserved;
3014	/** Device handle */
3015	uint16_t u16DevHandle;
3016	/** Target ID */
3017	uint8_t u8TargetID;
3018	/** Bus */
3019	uint8_t u8Bus;
3020	/** Initial REgister device FIS */
3021	uint32_t au32InitialRegDeviceFIS[5];
3022	} fields;
3023	} u;
3024	} MptConfigurationPageSASDevice1, *PMptConfigurationPageSASDevice1;
3025	#pragma pack()
3026	AssertCompileSize(MptConfigurationPageSASDevice1, 48);
3027
3028	/**
3029	* SAS Device page 2 - Read/Write persistent
3030	*/
3031	#pragma pack(1) /* Because of a uint64_t inside SASAddress, the struct size would be 24 without packing. */
3032	typedef struct MptConfigurationPageSASDevice2
3033	{
3034	/** Union. */
3035	union
3036	{
3037	/** Byte view - variable. */
3038	uint8_t abPageData[1];
3039	/** Field view. */
3040	struct
3041	{
3042	/** The omnipresent header. */
3043	MptExtendedConfigurationPageHeader ExtHeader;
3044	/** Physical identifier */
3045	SASADDRESS SASAddress;
3046	/** Enclosure mapping */
3047	uint32_t u32EnclosureMapping;
3048	} fields;
3049	} u;
3050	} MptConfigurationPageSASDevice2, *PMptConfigurationPageSASDevice2;
3051	#pragma pack()
3052	AssertCompileSize(MptConfigurationPageSASDevice2, 20);
3053
3054	/**
3055	* A device entitiy containing all pages.
3056	*/
3057	typedef struct MptSASDevice
3058	{
3059	/** Pointer to the next device if any. */
3060	struct MptSASDevice *pNext;
3061	/** Pointer to the previous device if any. */
3062	struct MptSASDevice *pPrev;
3063
3064	MptConfigurationPageSASDevice0 SASDevicePage0;
3065	MptConfigurationPageSASDevice1 SASDevicePage1;
3066	MptConfigurationPageSASDevice2 SASDevicePage2;
3067	} MptSASDevice, *PMptSASDevice;
3068
3069	/**
3070	* SAS Expander page 0 - Readonly
3071	*/
3072	#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
3073	typedef struct MptConfigurationPageSASExpander0
3074	{
3075	/** Union. */
3076	union
3077	{
3078	/** Byte view - variable. */
3079	uint8_t abPageData[1];
3080	/** Field view. */
3081	struct
3082	{
3083	/** The omnipresent header. */
3084	MptExtendedConfigurationPageHeader ExtHeader;
3085	/** Physical port */
3086	uint8_t u8PhysicalPort;
3087	/** Reserved */
3088	uint8_t u8Reserved0;
3089	/** Enclosure handle */
3090	uint16_t u16EnclosureHandle;
3091	/** SAS address */
3092	SASADDRESS SASAddress;
3093	/** Discovery status */
3094	uint32_t u32DiscoveryStatus;
3095	/** Device handle. */
3096	uint16_t u16DevHandle;
3097	/** Parent device handle */
3098	uint16_t u16ParentDevHandle;
3099	/** Expander change count */
3100	uint16_t u16ExpanderChangeCount;
3101	/** Expander route indexes */
3102	uint16_t u16ExpanderRouteIndexes;
3103	/** Number of PHys in this expander */
3104	uint8_t u8NumPhys;
3105	/** SAS level */
3106	uint8_t u8SASLevel;
3107	/** Flags */
3108	uint8_t u8Flags;
3109	/** Reserved */
3110	uint8_t u8Reserved1;
3111	} fields;
3112	} u;
3113	} MptConfigurationPageSASExpander0, *PMptConfigurationPageSASExpander0;
3114	#pragma pack()
3115	AssertCompileSize(MptConfigurationPageSASExpander0, 36);
3116
3117	/**
3118	* SAS Expander page 1 - Readonly
3119	*/
3120	typedef struct MptConfigurationPageSASExpander1
3121	{
3122	/** Union. */
3123	union
3124	{
3125	/** Byte view - variable. */
3126	uint8_t abPageData[1];
3127	/** Field view. */
3128	struct
3129	{
3130	/** The omnipresent header. */
3131	MptExtendedConfigurationPageHeader ExtHeader;
3132	/** Physical port */
3133	uint8_t u8PhysicalPort;
3134	/** Reserved */
3135	uint8_t u8Reserved0[3];
3136	/** Number of PHYs */
3137	uint8_t u8NumPhys;
3138	/** Number of the Phy the information in this page is for. */
3139	uint8_t u8Phy;
3140	/** Number of routing table entries */
3141	uint16_t u16NumTableEntriesProgrammed;
3142	/** Programmed link rate */
3143	uint8_t u8ProgrammedLinkRate;
3144	/** Hardware link rate */
3145	uint8_t u8HwLinkRate;
3146	/** Attached device handle */
3147	uint16_t u16AttachedDevHandle;
3148	/** Phy information */
3149	uint32_t u32PhyInfo;
3150	/** Attached device information */
3151	uint32_t u32AttachedDeviceInfo;
3152	/** Owner device handle. */
3153	uint16_t u16OwnerDevHandle;
3154	/** Change count */
3155	uint8_t u8ChangeCount;
3156	/** Negotiated link rate */
3157	uint8_t u8NegotiatedLinkRate;
3158	/** Phy identifier */
3159	uint8_t u8PhyIdentifier;
3160	/** Attached phy identifier */
3161	uint8_t u8AttachedPhyIdentifier;
3162	/** Reserved */
3163	uint8_t u8Reserved1;
3164	/** Discovery information */
3165	uint8_t u8DiscoveryInfo;
3166	/** Reserved */
3167	uint32_t u32Reserved;
3168	} fields;
3169	} u;
3170	} MptConfigurationPageSASExpander1, *PMptConfigurationPageSASExpander1;
3171	AssertCompileSize(MptConfigurationPageSASExpander1, 40);
3172
3173	/**
3174	* Structure of all supported pages for the SCSI SPI controller.
3175	* Used to load the device state from older versions.
3176	*/
3177	typedef struct MptConfigurationPagesSupported_SSM_V2
3178	{
3179	MptConfigurationPageManufacturing0 ManufacturingPage0;
3180	MptConfigurationPageManufacturing1 ManufacturingPage1;
3181	MptConfigurationPageManufacturing2 ManufacturingPage2;
3182	MptConfigurationPageManufacturing3 ManufacturingPage3;
3183	MptConfigurationPageManufacturing4 ManufacturingPage4;
3184	MptConfigurationPageIOUnit0 IOUnitPage0;
3185	MptConfigurationPageIOUnit1 IOUnitPage1;
3186	MptConfigurationPageIOUnit2 IOUnitPage2;
3187	MptConfigurationPageIOUnit3 IOUnitPage3;
3188	MptConfigurationPageIOC0 IOCPage0;
3189	MptConfigurationPageIOC1 IOCPage1;
3190	MptConfigurationPageIOC2 IOCPage2;
3191	MptConfigurationPageIOC3 IOCPage3;
3192	MptConfigurationPageIOC4 IOCPage4;
3193	MptConfigurationPageIOC6 IOCPage6;
3194	struct
3195	{
3196	MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3197	MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3198	MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3199	} aPortPages[1]; /* Currently only one port supported. */
3200	struct
3201	{
3202	struct
3203	{
3204	MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3205	MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3206	MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3207	MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3208	} aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3209	} aBuses[1]; /* Only one bus at the moment. */
3210	} MptConfigurationPagesSupported_SSM_V2, *PMptConfigurationPagesSupported_SSM_V2;
3211
3212	typedef struct MptConfigurationPagesSpi
3213	{
3214	struct
3215	{
3216	MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3217	MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3218	MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3219	} aPortPages[1]; /* Currently only one port supported. */
3220	struct
3221	{
3222	struct
3223	{
3224	MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3225	MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3226	MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3227	MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3228	} aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3229	} aBuses[1]; /* Only one bus at the moment. */
3230	} MptConfigurationPagesSpi, *PMptConfigurationPagesSpi;
3231
3232	typedef struct MptPHY
3233	{
3234	MptConfigurationPageSASPHY0 SASPHYPage0;
3235	MptConfigurationPageSASPHY1 SASPHYPage1;
3236	} MptPHY, *PMptPHY;
3237
3238	typedef struct MptConfigurationPagesSas
3239	{
3240	/** Pointer to the manufacturing page 7 */
3241	PMptConfigurationPageManufacturing7 pManufacturingPage7;
3242	/** Size of the manufacturing page 7 */
3243	uint32_t cbManufacturingPage7;
3244	/** Size of the I/O unit page 0 */
3245	uint32_t cbSASIOUnitPage0;
3246	/** Pointer to the I/O unit page 0 */
3247	PMptConfigurationPageSASIOUnit0 pSASIOUnitPage0;
3248	/** Pointer to the I/O unit page 1 */
3249	PMptConfigurationPageSASIOUnit1 pSASIOUnitPage1;
3250	/** Size of the I/O unit page 1 */
3251	uint32_t cbSASIOUnitPage1;
3252	/** I/O unit page 2 */
3253	MptConfigurationPageSASIOUnit2 SASIOUnitPage2;
3254	/** I/O unit page 3 */
3255	MptConfigurationPageSASIOUnit3 SASIOUnitPage3;
3256
3257	/** Number of PHYs in the array. */
3258	uint32_t cPHYs;
3259	/** Pointer to an array of per PHYS pages. */
3260	R3PTRTYPE(PMptPHY) paPHYs;
3261
3262	/** Number of devices detected. */
3263	uint32_t cDevices;
3264	uint32_t u32Padding;
3265	/** Pointer to the first SAS device. */
3266	R3PTRTYPE(PMptSASDevice) pSASDeviceHead;
3267	/** Pointer to the last SAS device. */
3268	R3PTRTYPE(PMptSASDevice) pSASDeviceTail;
3269	} MptConfigurationPagesSas, *PMptConfigurationPagesSas;
3270	AssertCompile(RTASSERT_OFFSET_OF(MptConfigurationPagesSas,cbSASIOUnitPage0) + 4 == RTASSERT_OFFSET_OF(MptConfigurationPagesSas, pSASIOUnitPage0));
3271	AssertCompile(RTASSERT_OFFSET_OF(MptConfigurationPagesSas,cPHYs) + 4 == RTASSERT_OFFSET_OF(MptConfigurationPagesSas, paPHYs));
3272	AssertCompile(RTASSERT_OFFSET_OF(MptConfigurationPagesSas,cDevices) + 8 == RTASSERT_OFFSET_OF(MptConfigurationPagesSas, pSASDeviceHead));
3273
3274
3275	/**
3276	* Structure of all supported pages for both controllers.
3277	*/
3278	typedef struct MptConfigurationPagesSupported
3279	{
3280	MptConfigurationPageManufacturing0 ManufacturingPage0;
3281	MptConfigurationPageManufacturing1 ManufacturingPage1;
3282	MptConfigurationPageManufacturing2 ManufacturingPage2;
3283	MptConfigurationPageManufacturing3 ManufacturingPage3;
3284	MptConfigurationPageManufacturing4 ManufacturingPage4;
3285	MptConfigurationPageManufacturing5 ManufacturingPage5;
3286	MptConfigurationPageManufacturing6 ManufacturingPage6;
3287	MptConfigurationPageManufacturing8 ManufacturingPage8;
3288	MptConfigurationPageManufacturing9 ManufacturingPage9;
3289	MptConfigurationPageManufacturing10 ManufacturingPage10;
3290	MptConfigurationPageIOUnit0 IOUnitPage0;
3291	MptConfigurationPageIOUnit1 IOUnitPage1;
3292	MptConfigurationPageIOUnit2 IOUnitPage2;
3293	MptConfigurationPageIOUnit3 IOUnitPage3;
3294	MptConfigurationPageIOUnit4 IOUnitPage4;
3295	MptConfigurationPageIOC0 IOCPage0;
3296	MptConfigurationPageIOC1 IOCPage1;
3297	MptConfigurationPageIOC2 IOCPage2;
3298	MptConfigurationPageIOC3 IOCPage3;
3299	MptConfigurationPageIOC4 IOCPage4;
3300	MptConfigurationPageIOC6 IOCPage6;
3301	/* BIOS page 0 is not described */
3302	MptConfigurationPageBIOS1 BIOSPage1;
3303	MptConfigurationPageBIOS2 BIOSPage2;
3304	/* BIOS page 3 is not described */
3305	MptConfigurationPageBIOS4 BIOSPage4;
3306
3307	/** Controller dependent data. */
3308	union
3309	{
3310	MptConfigurationPagesSpi SpiPages;
3311	MptConfigurationPagesSas SasPages;
3312	} u;
3313	} MptConfigurationPagesSupported, *PMptConfigurationPagesSupported;
3314
3315	/**
3316	* Initializes a page header.
3317	*/
3318	#define MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags) \
3319	(pg)->u.fields.Header.u8PageType = (flags); \
3320	(pg)->u.fields.Header.u8PageNumber = (nr); \
3321	(pg)->u.fields.Header.u8PageLength = sizeof(type) / 4
3322
3323	#define MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pg, type, nr, flags) \
3324	MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags \| MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING)
3325
3326	#define MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(pg, type, nr, flags) \
3327	MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags \| MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT)
3328
3329	#define MPT_CONFIG_PAGE_HEADER_INIT_IOC(pg, type, nr, flags) \
3330	MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags \| MPT_CONFIGURATION_PAGE_TYPE_IOC)
3331
3332	#define MPT_CONFIG_PAGE_HEADER_INIT_BIOS(pg, type, nr, flags) \
3333	MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags \| MPT_CONFIGURATION_PAGE_TYPE_BIOS)
3334
3335	/**
3336	* Initializes a extended page header.
3337	*/
3338	#define MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pg, cb, nr, flags, exttype) \
3339	(pg)->u.fields.ExtHeader.u8PageType = (flags) \| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED; \
3340	(pg)->u.fields.ExtHeader.u8PageNumber = (nr); \
3341	(pg)->u.fields.ExtHeader.u8ExtPageType = (exttype); \
3342	(pg)->u.fields.ExtHeader.u16ExtPageLength = (cb) / 4
3343
3344	/**
3345	* Possible SG element types.
3346	*/
3347	enum MPTSGENTRYTYPE
3348	{
3349	MPTSGENTRYTYPE_TRANSACTION_CONTEXT = 0x00,
3350	MPTSGENTRYTYPE_SIMPLE = 0x01,
3351	MPTSGENTRYTYPE_CHAIN = 0x03
3352	};
3353
3354	/**
3355	* Register interface.
3356	*/
3357
3358	/**
3359	* Defined states that the SCSI controller can have.
3360	*/
3361	typedef enum LSILOGICSTATE
3362	{
3363	/** Reset state. */
3364	LSILOGICSTATE_RESET = 0x00,
3365	/** Ready state. */
3366	LSILOGICSTATE_READY = 0x01,
3367	/** Operational state. */
3368	LSILOGICSTATE_OPERATIONAL = 0x02,
3369	/** Fault state. */
3370	LSILOGICSTATE_FAULT = 0x04,
3371	/** 32bit size hack */
3372	LSILOGICSTATE_32BIT_HACK = 0x7fffffff
3373	} LSILOGICSTATE;
3374
3375	/**
3376	* Which entity needs to initialize the controller
3377	* to get into the operational state.
3378	*/
3379	typedef enum LSILOGICWHOINIT
3380	{
3381	/** Not initialized. */
3382	LSILOGICWHOINIT_NOT_INITIALIZED = 0x00,
3383	/** System BIOS. */
3384	LSILOGICWHOINIT_SYSTEM_BIOS = 0x01,
3385	/** ROM Bios. */
3386	LSILOGICWHOINIT_ROM_BIOS = 0x02,
3387	/** PCI Peer. */
3388	LSILOGICWHOINIT_PCI_PEER = 0x03,
3389	/** Host driver. */
3390	LSILOGICWHOINIT_HOST_DRIVER = 0x04,
3391	/** Manufacturing. */
3392	LSILOGICWHOINIT_MANUFACTURING = 0x05,
3393	/** 32bit size hack. */
3394	LSILOGICWHOINIT_32BIT_HACK = 0x7fffffff
3395	} LSILOGICWHOINIT;
3396
3397
3398	/**
3399	* Doorbell state.
3400	*/
3401	typedef enum LSILOGICDOORBELLSTATE
3402	{
3403	/** Invalid value. */
3404	LSILOGICDOORBELLSTATE_INVALID = 0,
3405	/** Doorbell not in use. */
3406	LSILOGICDOORBELLSTATE_NOT_IN_USE,
3407	/** Reply frame removal, transfer number of entries, low 16bits. */
3408	LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW,
3409	/** Reply frame removal, transfer number of entries, high 16bits. */
3410	LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH,
3411	/** Reply frame removal, remove next free frame, low part. */
3412	LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW,
3413	/** Reply frame removal, remove next free frame, high part. */
3414	LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH,
3415	/** Function handshake. */
3416	LSILOGICDOORBELLSTATE_FN_HANDSHAKE,
3417	/** 32bit hack. */
3418	LSILOGICDOORBELLSTATE_32BIT_HACK = 0x7fffffff
3419	} LSILOGICDOORBELLSTATE;
3420	/** Pointer to a doorbell state. */
3421	typedef LSILOGICDOORBELLSTATE *PLSILOGICDOORBELLSTATE;
3422
3423
3424	/**
3425	* IOC status codes.
3426	*/
3427	#define LSILOGIC_IOCSTATUS_SUCCESS 0x0000
3428	#define LSILOGIC_IOCSTATUS_INVALID_FUNCTION 0x0001
3429	#define LSILOGIC_IOCSTATUS_BUSY 0x0002
3430	#define LSILOGIC_IOCSTATUS_INVALID_SGL 0x0003
3431	#define LSILOGIC_IOCSTATUS_INTERNAL_ERROR 0x0004
3432	#define LSILOGIC_IOCSTATUS_RESERVED 0x0005
3433	#define LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES 0x0006
3434	#define LSILOGIC_IOCSTATUS_INVALID_FIELD 0x0007
3435	#define LSILOGIC_IOCSTATUS_INVALID_STATE 0x0008
3436	#define LSILOGIC_IOCSTATUS_OP_STATE_NOT_SUPPOTED 0x0009
3437
3438	/**
3439	* Size of the I/O and MMIO space.
3440	*/
3441	#define LSILOGIC_PCI_SPACE_IO_SIZE 256
3442	#define LSILOGIC_PCI_SPACE_MEM_SIZE 128 * _1K
3443
3444	/**
3445	* Doorbell register - Used to get the status of the controller and
3446	* initialise it.
3447	*/
3448	#define LSILOGIC_REG_DOORBELL 0x00
3449	# define LSILOGIC_REG_DOORBELL_SET_STATE(enmState) (((enmState) & 0x0f) << 28)
3450	# define LSILOGIC_REG_DOORBELL_SET_USED(enmDoorbell) (((enmDoorbell != LSILOGICDOORBELLSTATE_NOT_IN_USE) ? 1 : 0) << 27)
3451	# define LSILOGIC_REG_DOORBELL_SET_WHOINIT(enmWhoInit) (((enmWhoInit) & 0x07) << 24)
3452	# define LSILOGIC_REG_DOORBELL_SET_FAULT_CODE(u16Code) (u16Code)
3453	# define LSILOGIC_REG_DOORBELL_GET_FUNCTION(x) (((x) & 0xff000000) >> 24)
3454	# define LSILOGIC_REG_DOORBELL_GET_SIZE(x) (((x) & 0x00ff0000) >> 16)
3455
3456	/**
3457	* Functions which can be passed through the system doorbell.
3458	*/
3459	#define LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET 0x40
3460	#define LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET 0x41
3461	#define LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE 0x42
3462	#define LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL 0x43
3463
3464	/**
3465	* Write sequence register for the diagnostic register.
3466	*/
3467	#define LSILOGIC_REG_WRITE_SEQUENCE 0x04
3468
3469	/**
3470	* Diagnostic register - used to reset the controller.
3471	*/
3472	#define LSILOGIC_REG_HOST_DIAGNOSTIC 0x08
3473	# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_MEM_ENABLE (RT_BIT(0))
3474	# define LSILOGIC_REG_HOST_DIAGNOSTIC_DISABLE_ARM (RT_BIT(1))
3475	# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER (RT_BIT(2))
3476	# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE (RT_BIT(4))
3477	# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_HISTORY (RT_BIT(5))
3478	# define LSILOGIC_REG_HOST_DIAGNOSTIC_FLASH_BAD_SIG (RT_BIT(6))
3479	# define LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE (RT_BIT(7))
3480	# define LSILOGIC_REG_HOST_DIAGNOSTIC_PREVENT_IOC_BOOT (RT_BIT(9))
3481	# define LSILOGIC_REG_HOST_DIAGNOSTIC_CLEAR_FLASH_BAD_SIG (RT_BIT(10))
3482
3483	#define LSILOGIC_REG_TEST_BASE_ADDRESS 0x0c
3484	#define LSILOGIC_REG_DIAG_RW_DATA 0x10
3485	#define LSILOGIC_REG_DIAG_RW_ADDRESS 0x14
3486
3487	/**
3488	* Interrupt status register.
3489	*/
3490	#define LSILOGIC_REG_HOST_INTR_STATUS 0x30
3491	# define LSILOGIC_REG_HOST_INTR_STATUS_W_MASK (RT_BIT(3))
3492	# define LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS (RT_BIT(31))
3493	# define LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR (RT_BIT(3))
3494	# define LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL (RT_BIT(0))
3495
3496	/**
3497	* Interrupt mask register.
3498	*/
3499	#define LSILOGIC_REG_HOST_INTR_MASK 0x34
3500	# define LSILOGIC_REG_HOST_INTR_MASK_W_MASK (RT_BIT(0) \| RT_BIT(3) \| RT_BIT(8) \| RT_BIT(9))
3501	# define LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING (RT_BIT(8) \| RT_BIT(9))
3502	# define LSILOGIC_REG_HOST_INTR_MASK_DOORBELL RT_BIT(0)
3503	# define LSILOGIC_REG_HOST_INTR_MASK_REPLY RT_BIT(3)
3504
3505	/**
3506	* Queue registers.
3507	*/
3508	#define LSILOGIC_REG_REQUEST_QUEUE 0x40
3509	#define LSILOGIC_REG_REPLY_QUEUE 0x44
3510
3511	#endif /* !VBOX_INCLUDED_SRC_Storage_DevLsiLogicSCSI_h */

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source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.h@ 81744

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