VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.h

Last change on this file was 98103, checked in by vboxsync, 16 months ago

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1/* $Id: DevLsiLogicSCSI.h 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * VBox storage devices: LsiLogic LSI53c1030 SCSI controller - Defines and structures.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VBOX_INCLUDED_SRC_Storage_DevLsiLogicSCSI_h
29#define VBOX_INCLUDED_SRC_Storage_DevLsiLogicSCSI_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <iprt/stdint.h>
35
36/*
37 * Custom fixed I/O ports for BIOS controller access. Note that these should
38 * not be in the ISA range (below 400h) to avoid conflicts with ISA device
39 * probing. Addresses in the 300h-340h range should be especially avoided.
40 */
41#define LSILOGIC_BIOS_IO_PORT 0x434
42#define LSILOGIC_SAS_BIOS_IO_PORT 0x438
43
44#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MIN 8 /**< (bird just picked this out thin air) */
45#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_MAX 1024 /**< (bird just picked this out thin air) */
46#define LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT 256
47
48#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_MIN 8 /**< (bird just picked this out thin air) */
49#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_MAX 1024 /**< (bird just picked this out thin air) */
50#define LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT 256
51
52#define LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH 3
53
54#define LSILOGIC_NR_OF_ALLOWED_BIGGER_LISTS 100
55
56/** Equal for all devices */
57#define LSILOGICSCSI_PCI_VENDOR_ID (0x1000)
58
59/** SPI SCSI controller (LSI53C1030) */
60#define LSILOGICSCSI_PCI_SPI_CTRLNAME "LSI53C1030"
61#define LSILOGICSCSI_PCI_SPI_DEVICE_ID (0x0030)
62#define LSILOGICSCSI_PCI_SPI_REVISION_ID (0x00)
63#define LSILOGICSCSI_PCI_SPI_CLASS_CODE (0x01)
64#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID (0x1000)
65#define LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID (0x8000)
66#define LSILOGICSCSI_PCI_SPI_PORTS_MAX 1
67#define LSILOGICSCSI_PCI_SPI_BUSES_MAX 1
68#define LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX 16
69#define LSILOGICSCSI_PCI_SPI_DEVICES_MAX (LSILOGICSCSI_PCI_SPI_BUSES_MAX*LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX)
70
71/** SAS SCSI controller (SAS1068 PCI-X Fusion-MPT SAS) */
72#define LSILOGICSCSI_PCI_SAS_CTRLNAME "SAS1068"
73#define LSILOGICSCSI_PCI_SAS_DEVICE_ID (0x0054)
74#define LSILOGICSCSI_PCI_SAS_REVISION_ID (0x00)
75#define LSILOGICSCSI_PCI_SAS_CLASS_CODE (0x00)
76#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID (0x1000)
77#define LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID (0x8000)
78#define LSILOGICSCSI_PCI_SAS_PORTS_MAX 256
79#define LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT 8
80#define LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX 1
81#define LSILOGICSCSI_PCI_SAS_DEVICES_MAX (LSILOGICSCSI_PCI_SAS_PORTS_MAX * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX)
82
83/**
84 * A SAS address.
85 */
86typedef union SASADDRESS
87{
88 /** 64bit view. */
89 uint64_t u64Address;
90 /** 32bit view. */
91 uint32_t u32Address[2];
92 /** 16bit view. */
93 uint16_t u16Address[4];
94 /** Byte view. */
95 uint8_t u8Address[8];
96} SASADDRESS, *PSASADDRESS;
97AssertCompileSize(SASADDRESS, 8);
98
99/**
100 * Possible device types we support.
101 */
102typedef enum LSILOGICCTRLTYPE
103{
104 /** SPI SCSI controller (PCI dev id 0x0030) */
105 LSILOGICCTRLTYPE_SCSI_SPI = 0,
106 /** SAS SCSI controller (PCI dev id 0x0054) */
107 LSILOGICCTRLTYPE_SCSI_SAS = 1,
108 /** 32bit hack */
109 LSILOGICCTRLTYPE_32BIT_HACK = 0x7fffffff
110} LSILOGICCTRLTYPE, *PLSILOGICCTRLTYPE;
111
112/**
113 * A simple SG element for a 64bit address.
114 */
115typedef struct MptSGEntrySimple64
116{
117 /** Length of the buffer this entry describes. */
118 unsigned u24Length: 24;
119 /** Flag whether this element is the end of the list. */
120 unsigned fEndOfList: 1;
121 /** Flag whether the address is 32bit or 64bits wide. */
122 unsigned f64BitAddress: 1;
123 /** Flag whether this buffer contains data to be transferred or is the destination. */
124 unsigned fBufferContainsData: 1;
125 /** Flag whether this is a local address or a system address. */
126 unsigned fLocalAddress: 1;
127 /** Element type. */
128 unsigned u2ElementType: 2;
129 /** Flag whether this is the last element of the buffer. */
130 unsigned fEndOfBuffer: 1;
131 /** Flag whether this is the last element of the current segment. */
132 unsigned fLastElement: 1;
133 /** Lower 32bits of the address of the data buffer. */
134 unsigned u32DataBufferAddressLow: 32;
135 /** Upper 32bits of the address of the data buffer. */
136 unsigned u32DataBufferAddressHigh: 32;
137} MptSGEntrySimple64, *PMptSGEntrySimple64;
138AssertCompileSize(MptSGEntrySimple64, 12);
139
140/**
141 * A simple SG element for a 32bit address.
142 */
143typedef struct MptSGEntrySimple32
144{
145 /** Length of the buffer this entry describes. */
146 unsigned u24Length: 24;
147 /** Flag whether this element is the end of the list. */
148 unsigned fEndOfList: 1;
149 /** Flag whether the address is 32bit or 64bits wide. */
150 unsigned f64BitAddress: 1;
151 /** Flag whether this buffer contains data to be transferred or is the destination. */
152 unsigned fBufferContainsData: 1;
153 /** Flag whether this is a local address or a system address. */
154 unsigned fLocalAddress: 1;
155 /** Element type. */
156 unsigned u2ElementType: 2;
157 /** Flag whether this is the last element of the buffer. */
158 unsigned fEndOfBuffer: 1;
159 /** Flag whether this is the last element of the current segment. */
160 unsigned fLastElement: 1;
161 /** Lower 32bits of the address of the data buffer. */
162 unsigned u32DataBufferAddressLow: 32;
163} MptSGEntrySimple32, *PMptSGEntrySimple32;
164AssertCompileSize(MptSGEntrySimple32, 8);
165
166/**
167 * A chain SG element.
168 */
169typedef struct MptSGEntryChain
170{
171 /** Size of the segment. */
172 unsigned u16Length: 16;
173 /** Offset in 32bit words of the next chain element in the segment
174 * identified by this element. */
175 unsigned u8NextChainOffset: 8;
176 /** Reserved. */
177 unsigned fReserved0: 1;
178 /** Flag whether the address is 32bit or 64bits wide. */
179 unsigned f64BitAddress: 1;
180 /** Reserved. */
181 unsigned fReserved1: 1;
182 /** Flag whether this is a local address or a system address. */
183 unsigned fLocalAddress: 1;
184 /** Element type. */
185 unsigned u2ElementType: 2;
186 /** Flag whether this is the last element of the buffer. */
187 unsigned u2Reserved2: 2;
188 /** Lower 32bits of the address of the data buffer. */
189 unsigned u32SegmentAddressLow: 32;
190 /** Upper 32bits of the address of the data buffer. */
191 unsigned u32SegmentAddressHigh: 32;
192} MptSGEntryChain, *PMptSGEntryChain;
193AssertCompileSize(MptSGEntryChain, 12);
194
195typedef union MptSGEntryUnion
196{
197 MptSGEntrySimple64 Simple64;
198 MptSGEntrySimple32 Simple32;
199 MptSGEntryChain Chain;
200} MptSGEntryUnion, *PMptSGEntryUnion;
201
202/**
203 * MPT Fusion message header - Common for all message frames.
204 * This is filled in by the guest.
205 */
206typedef struct MptMessageHdr
207{
208 /** Function dependent data. */
209 uint16_t u16FunctionDependent;
210 /** Chain offset. */
211 uint8_t u8ChainOffset;
212 /** The function code. */
213 uint8_t u8Function;
214 /** Function dependent data. */
215 uint8_t au8FunctionDependent[3];
216 /** Message flags. */
217 uint8_t u8MessageFlags;
218 /** Message context - Unique ID from the guest unmodified by the device. */
219 uint32_t u32MessageContext;
220} MptMessageHdr, *PMptMessageHdr;
221AssertCompileSize(MptMessageHdr, 12);
222
223/** Defined function codes found in the message header. */
224#define MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST (0x00)
225#define MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT (0x01)
226#define MPT_MESSAGE_HDR_FUNCTION_IOC_INIT (0x02)
227#define MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS (0x03)
228#define MPT_MESSAGE_HDR_FUNCTION_CONFIG (0x04)
229#define MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS (0x05)
230#define MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE (0x06)
231#define MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION (0x07)
232#define MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK (0x08)
233#define MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD (0x09)
234#define MPT_MESSAGE_HDR_FUNCTION_TARGET_CMD_BUFFER_POST (0x0A)
235#define MPT_MESSAGE_HDR_FUNCTION_TARGET_ASSIST (0x0B)
236#define MPT_MESSAGE_HDR_FUNCTION_TARGET_STATUS_SEND (0x0C)
237#define MPT_MESSAGE_HDR_FUNCTION_TARGET_MODE_ABORT (0x0D)
238#define MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD (0x12)
239
240#ifdef DEBUG
241/**
242 * Function names
243 */
244static const char * const g_apszMPTFunctionNames[] =
245{
246 "SCSI I/O Request",
247 "SCSI Task Management",
248 "IOC Init",
249 "IOC Facts",
250 "Config",
251 "Port Facts",
252 "Port Enable",
253 "Event Notification",
254 "Event Ack",
255 "Firmware Download"
256};
257#endif
258
259/**
260 * Default reply message.
261 * Send from the device to the guest upon completion of a request.
262 */
263typedef struct MptDefaultReplyMessage
264{
265 /** Function dependent data. */
266 uint16_t u16FunctionDependent;
267 /** Length of the message in 32bit DWords. */
268 uint8_t u8MessageLength;
269 /** Function which completed. */
270 uint8_t u8Function;
271 /** Function dependent. */
272 uint8_t au8FunctionDependent[3];
273 /** Message flags. */
274 uint8_t u8MessageFlags;
275 /** Message context given in the request. */
276 uint32_t u32MessageContext;
277 /** Function dependent status code. */
278 uint16_t u16FunctionDependentStatus;
279 /** Status of the IOC. */
280 uint16_t u16IOCStatus;
281 /** Additional log info. */
282 uint32_t u32IOCLogInfo;
283} MptDefaultReplyMessage, *PMptDefaultReplyMessage;
284AssertCompileSize(MptDefaultReplyMessage, 20);
285
286/**
287 * IO controller init request.
288 */
289typedef struct MptIOCInitRequest
290{
291 /** Which system send this init request. */
292 uint8_t u8WhoInit;
293 /** Reserved */
294 uint8_t u8Reserved;
295 /** Chain offset in the SG list. */
296 uint8_t u8ChainOffset;
297 /** Function to execute. */
298 uint8_t u8Function;
299 /** Flags */
300 uint8_t u8Flags;
301 /** Maximum number of devices the driver can handle. */
302 uint8_t u8MaxDevices;
303 /** Maximum number of buses the driver can handle. */
304 uint8_t u8MaxBuses;
305 /** Message flags. */
306 uint8_t u8MessageFlags;
307 /** Message context ID. */
308 uint32_t u32MessageContext;
309 /** Reply frame size. */
310 uint16_t u16ReplyFrameSize;
311 /** Reserved */
312 uint16_t u16Reserved;
313 /** Upper 32bit part of the 64bit address the message frames are in.
314 * That means all frames must be in the same 4GB segment. */
315 uint32_t u32HostMfaHighAddr;
316 /** Upper 32bit of the sense buffer. */
317 uint32_t u32SenseBufferHighAddr;
318} MptIOCInitRequest, *PMptIOCInitRequest;
319AssertCompileSize(MptIOCInitRequest, 24);
320
321/**
322 * IO controller init reply.
323 */
324typedef struct MptIOCInitReply
325{
326 /** Which subsystem send this init request. */
327 uint8_t u8WhoInit;
328 /** Reserved */
329 uint8_t u8Reserved;
330 /** Message length */
331 uint8_t u8MessageLength;
332 /** Function. */
333 uint8_t u8Function;
334 /** Flags */
335 uint8_t u8Flags;
336 /** Maximum number of devices the driver can handle. */
337 uint8_t u8MaxDevices;
338 /** Maximum number of busses the driver can handle. */
339 uint8_t u8MaxBuses;
340 /** Message flags. */
341 uint8_t u8MessageFlags;
342 /** Message context ID */
343 uint32_t u32MessageContext;
344 /** Reserved */
345 uint16_t u16Reserved;
346 /** IO controller status. */
347 uint16_t u16IOCStatus;
348 /** IO controller log information. */
349 uint32_t u32IOCLogInfo;
350} MptIOCInitReply, *PMptIOCInitReply;
351AssertCompileSize(MptIOCInitReply, 20);
352
353/**
354 * IO controller facts request.
355 */
356typedef struct MptIOCFactsRequest
357{
358 /** Reserved. */
359 uint16_t u16Reserved;
360 /** Chain offset in SG list. */
361 uint8_t u8ChainOffset;
362 /** Function number. */
363 uint8_t u8Function;
364 /** Reserved */
365 uint8_t u8Reserved[3];
366 /** Message flags. */
367 uint8_t u8MessageFlags;
368 /** Message context ID. */
369 uint32_t u32MessageContext;
370} MptIOCFactsRequest, *PMptIOCFactsRequest;
371AssertCompileSize(MptIOCFactsRequest, 12);
372
373/**
374 * IO controller facts reply.
375 */
376typedef struct MptIOCFactsReply
377{
378 /** Message version. */
379 uint16_t u16MessageVersion;
380 /** Message length. */
381 uint8_t u8MessageLength;
382 /** Function number. */
383 uint8_t u8Function;
384 /** Reserved */
385 uint16_t u16Reserved1;
386 /** IO controller number */
387 uint8_t u8IOCNumber;
388 /** Message flags. */
389 uint8_t u8MessageFlags;
390 /** Message context ID. */
391 uint32_t u32MessageContext;
392 /** IO controller exceptions */
393 uint16_t u16IOCExceptions;
394 /** IO controller status. */
395 uint16_t u16IOCStatus;
396 /** IO controller log information. */
397 uint32_t u32IOCLogInfo;
398 /** Maximum chain depth. */
399 uint8_t u8MaxChainDepth;
400 /** The current value of the WhoInit field. */
401 uint8_t u8WhoInit;
402 /** Block size. */
403 uint8_t u8BlockSize;
404 /** Flags. */
405 uint8_t u8Flags;
406 /** Depth of the reply queue. */
407 uint16_t u16ReplyQueueDepth;
408 /** Size of a request frame. */
409 uint16_t u16RequestFrameSize;
410 /** Reserved */
411 uint16_t u16Reserved2;
412 /** Product ID. */
413 uint16_t u16ProductID;
414 /** Current value of the high 32bit MFA address. */
415 uint32_t u32CurrentHostMFAHighAddr;
416 /** Global credits - Number of entries allocated to queues */
417 uint16_t u16GlobalCredits;
418 /** Number of ports on the IO controller */
419 uint8_t u8NumberOfPorts;
420 /** Event state. */
421 uint8_t u8EventState;
422 /** Current value of the high 32bit sense buffer address. */
423 uint32_t u32CurrentSenseBufferHighAddr;
424 /** Current reply frame size. */
425 uint16_t u16CurReplyFrameSize;
426 /** Maximum number of devices. */
427 uint8_t u8MaxDevices;
428 /** Maximum number of buses. */
429 uint8_t u8MaxBuses;
430 /** Size of the firmware image. */
431 uint32_t u32FwImageSize;
432 /** Reserved. */
433 uint32_t u32Reserved;
434 /** Firmware version */
435 uint32_t u32FWVersion;
436} MptIOCFactsReply, *PMptIOCFactsReply;
437AssertCompileSize(MptIOCFactsReply, 60);
438
439/**
440 * Port facts request
441 */
442typedef struct MptPortFactsRequest
443{
444 /** Reserved */
445 uint16_t u16Reserved1;
446 /** Message length. */
447 uint8_t u8MessageLength;
448 /** Function number. */
449 uint8_t u8Function;
450 /** Reserved */
451 uint16_t u16Reserved2;
452 /** Port number to get facts for. */
453 uint8_t u8PortNumber;
454 /** Message flags. */
455 uint8_t u8MessageFlags;
456 /** Message context ID. */
457 uint32_t u32MessageContext;
458} MptPortFactsRequest, *PMptPortFactsRequest;
459AssertCompileSize(MptPortFactsRequest, 12);
460
461/**
462 * Port facts reply.
463 */
464typedef struct MptPortFactsReply
465{
466 /** Reserved. */
467 uint16_t u16Reserved1;
468 /** Message length. */
469 uint8_t u8MessageLength;
470 /** Function number. */
471 uint8_t u8Function;
472 /** Reserved */
473 uint16_t u16Reserved2;
474 /** Port number the facts are for. */
475 uint8_t u8PortNumber;
476 /** Message flags. */
477 uint8_t u8MessageFlags;
478 /** Message context ID. */
479 uint32_t u32MessageContext;
480 /** Reserved. */
481 uint16_t u16Reserved3;
482 /** IO controller status. */
483 uint16_t u16IOCStatus;
484 /** IO controller log information. */
485 uint32_t u32IOCLogInfo;
486 /** Reserved */
487 uint8_t u8Reserved;
488 /** Port type */
489 uint8_t u8PortType;
490 /** Maximum number of devices on this port. */
491 uint16_t u16MaxDevices;
492 /** SCSI ID of this port on the attached bus. */
493 uint16_t u16PortSCSIID;
494 /** Protocol flags. */
495 uint16_t u16ProtocolFlags;
496 /** Maximum number of target command buffers which can be posted to this port at a time. */
497 uint16_t u16MaxPostedCmdBuffers;
498 /** Maximum number of target IDs that remain persistent between power/reset cycles. */
499 uint16_t u16MaxPersistentIDs;
500 /** Maximum number of LAN buckets. */
501 uint16_t u16MaxLANBuckets;
502 /** Reserved. */
503 uint16_t u16Reserved4;
504 /** Reserved. */
505 uint32_t u32Reserved;
506} MptPortFactsReply, *PMptPortFactsReply;
507AssertCompileSize(MptPortFactsReply, 40);
508
509/**
510 * Port Enable request.
511 */
512typedef struct MptPortEnableRequest
513{
514 /** Reserved. */
515 uint16_t u16Reserved1;
516 /** Message length. */
517 uint8_t u8MessageLength;
518 /** Function number. */
519 uint8_t u8Function;
520 /** Reserved. */
521 uint16_t u16Reserved2;
522 /** Port number to enable. */
523 uint8_t u8PortNumber;
524 /** Message flags. */
525 uint8_t u8MessageFlags;
526 /** Message context ID. */
527 uint32_t u32MessageContext;
528} MptPortEnableRequest, *PMptPortEnableRequest;
529AssertCompileSize(MptPortEnableRequest, 12);
530
531/**
532 * Port enable reply.
533 */
534typedef struct MptPortEnableReply
535{
536 /** Reserved. */
537 uint16_t u16Reserved1;
538 /** Message length. */
539 uint8_t u8MessageLength;
540 /** Function number. */
541 uint8_t u8Function;
542 /** Reserved */
543 uint16_t u16Reserved2;
544 /** Port number which was enabled. */
545 uint8_t u8PortNumber;
546 /** Message flags. */
547 uint8_t u8MessageFlags;
548 /** Message context ID. */
549 uint32_t u32MessageContext;
550 /** Reserved. */
551 uint16_t u16Reserved3;
552 /** IO controller status */
553 uint16_t u16IOCStatus;
554 /** IO controller log information. */
555 uint32_t u32IOCLogInfo;
556} MptPortEnableReply, *PMptPortEnableReply;
557AssertCompileSize(MptPortEnableReply, 20);
558
559/**
560 * Event notification request.
561 */
562typedef struct MptEventNotificationRequest
563{
564 /** Switch - Turns event notification on and off. */
565 uint8_t u8Switch;
566 /** Reserved. */
567 uint8_t u8Reserved1;
568 /** Chain offset. */
569 uint8_t u8ChainOffset;
570 /** Function number. */
571 uint8_t u8Function;
572 /** Reserved. */
573 uint8_t u8reserved2[3];
574 /** Message flags. */
575 uint8_t u8MessageFlags;
576 /** Message context ID. */
577 uint32_t u32MessageContext;
578} MptEventNotificationRequest, *PMptEventNotificationRequest;
579AssertCompileSize(MptEventNotificationRequest, 12);
580
581/**
582 * Event notification reply.
583 */
584typedef struct MptEventNotificationReply
585{
586 /** Event data length. */
587 uint16_t u16EventDataLength;
588 /** Message length. */
589 uint8_t u8MessageLength;
590 /** Function number. */
591 uint8_t u8Function;
592 /** Reserved. */
593 uint16_t u16Reserved1;
594 /** Ack required. */
595 uint8_t u8AckRequired;
596 /** Message flags. */
597 uint8_t u8MessageFlags;
598 /** Message context ID. */
599 uint32_t u32MessageContext;
600 /** Reserved. */
601 uint16_t u16Reserved2;
602 /** IO controller status. */
603 uint16_t u16IOCStatus;
604 /** IO controller log information. */
605 uint32_t u32IOCLogInfo;
606 /** Notification event. */
607 uint32_t u32Event;
608 /** Event context. */
609 uint32_t u32EventContext;
610 /** Event data. */
611 uint32_t u32EventData;
612} MptEventNotificationReply, *PMptEventNotificationReply;
613AssertCompileSize(MptEventNotificationReply, 32);
614
615#define MPT_EVENT_EVENT_CHANGE (0x0000000a)
616
617/**
618 * FW download request.
619 */
620typedef struct MptFWDownloadRequest
621{
622 /** Switch - Turns event notification on and off. */
623 uint8_t u8ImageType;
624 /** Reserved. */
625 uint8_t u8Reserved1;
626 /** Chain offset. */
627 uint8_t u8ChainOffset;
628 /** Function number. */
629 uint8_t u8Function;
630 /** Reserved. */
631 uint8_t u8Reserved2[3];
632 /** Message flags. */
633 uint8_t u8MessageFlags;
634 /** Message context ID. */
635 uint32_t u32MessageContext;
636} MptFWDownloadRequest, *PMptFWDownloadRequest;
637AssertCompileSize(MptFWDownloadRequest, 12);
638
639#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_RESERVED 0
640#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_FIRMWARE 1
641#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_MPI_BIOS 2
642#define MPT_FW_DOWNLOAD_REQUEST_IMAGE_TYPE_NVDATA 3
643
644/**
645 * FW download reply.
646 */
647typedef struct MptFWDownloadReply
648{
649 /** Reserved. */
650 uint16_t u16Reserved1;
651 /** Message length. */
652 uint8_t u8MessageLength;
653 /** Function number. */
654 uint8_t u8Function;
655 /** Reserved. */
656 uint8_t u8Reserved2[3];
657 /** Message flags. */
658 uint8_t u8MessageFlags;
659 /** Message context ID. */
660 uint32_t u32MessageContext;
661 /** Reserved. */
662 uint16_t u16Reserved2;
663 /** IO controller status. */
664 uint16_t u16IOCStatus;
665 /** IO controller log information. */
666 uint32_t u32IOCLogInfo;
667} MptFWDownloadReply, *PMptFWDownloadReply;
668AssertCompileSize(MptFWDownloadReply, 20);
669
670/**
671 * FW upload request.
672 */
673typedef struct MptFWUploadRequest
674{
675 /** Requested image type. */
676 uint8_t u8ImageType;
677 /** Reserved. */
678 uint8_t u8Reserved1;
679 /** Chain offset. */
680 uint8_t u8ChainOffset;
681 /** Function number. */
682 uint8_t u8Function;
683 /** Reserved. */
684 uint8_t u8Reserved2[3];
685 /** Message flags. */
686 uint8_t u8MessageFlags;
687 /** Message context ID. */
688 uint32_t u32MessageContext;
689} MptFWUploadRequest, *PMptFWUploadRequest;
690AssertCompileSize(MptFWUploadRequest, 12);
691
692/**
693 * FW upload reply.
694 */
695typedef struct MptFWUploadReply
696{
697 /** Image type. */
698 uint8_t u8ImageType;
699 /** Reserved. */
700 uint8_t u8Reserved1;
701 /** Message length. */
702 uint8_t u8MessageLength;
703 /** Function number. */
704 uint8_t u8Function;
705 /** Reserved. */
706 uint8_t u8Reserved2[3];
707 /** Message flags. */
708 uint8_t u8MessageFlags;
709 /** Message context ID. */
710 uint32_t u32MessageContext;
711 /** Reserved. */
712 uint16_t u16Reserved2;
713 /** IO controller status. */
714 uint16_t u16IOCStatus;
715 /** IO controller log information. */
716 uint32_t u32IOCLogInfo;
717 /** Uploaded image size. */
718 uint32_t u32ActualImageSize;
719} MptFWUploadReply, *PMptFWUploadReply;
720AssertCompileSize(MptFWUploadReply, 24);
721
722/**
723 * SCSI IO Request
724 */
725typedef struct MptSCSIIORequest
726{
727 /** Target ID */
728 uint8_t u8TargetID;
729 /** Bus number */
730 uint8_t u8Bus;
731 /** Chain offset */
732 uint8_t u8ChainOffset;
733 /** Function number. */
734 uint8_t u8Function;
735 /** CDB length. */
736 uint8_t u8CDBLength;
737 /** Sense buffer length. */
738 uint8_t u8SenseBufferLength;
739 /** Reserved */
740 uint8_t u8Reserved;
741 /** Message flags. */
742 uint8_t u8MessageFlags;
743 /** Message context ID. */
744 uint32_t u32MessageContext;
745 /** LUN */
746 uint8_t au8LUN[8];
747 /** Control values. */
748 uint32_t u32Control;
749 /** The CDB. */
750 uint8_t au8CDB[16];
751 /** Data length. */
752 uint32_t u32DataLength;
753 /** Sense buffer low 32bit address. */
754 uint32_t u32SenseBufferLowAddress;
755} MptSCSIIORequest, *PMptSCSIIORequest;
756AssertCompileSize(MptSCSIIORequest, 48);
757
758#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(x) (((x) & 0x3000000) >> 24)
759#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE (0x0)
760#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE (0x1)
761#define MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ (0x2)
762
763/**
764 * SCSI IO error reply.
765 */
766typedef struct MptSCSIIOErrorReply
767{
768 /** Target ID */
769 uint8_t u8TargetID;
770 /** Bus number */
771 uint8_t u8Bus;
772 /** Message length. */
773 uint8_t u8MessageLength;
774 /** Function number. */
775 uint8_t u8Function;
776 /** CDB length */
777 uint8_t u8CDBLength;
778 /** Sense buffer length */
779 uint8_t u8SenseBufferLength;
780 /** Reserved */
781 uint8_t u8Reserved;
782 /** Message flags */
783 uint8_t u8MessageFlags;
784 /** Message context ID */
785 uint32_t u32MessageContext;
786 /** SCSI status. */
787 uint8_t u8SCSIStatus;
788 /** SCSI state */
789 uint8_t u8SCSIState;
790 /** IO controller status */
791 uint16_t u16IOCStatus;
792 /** IO controller log information */
793 uint32_t u32IOCLogInfo;
794 /** Transfer count */
795 uint32_t u32TransferCount;
796 /** Sense count */
797 uint32_t u32SenseCount;
798 /** Response information */
799 uint32_t u32ResponseInfo;
800} MptSCSIIOErrorReply, *PMptSCSIIOErrorReply;
801AssertCompileSize(MptSCSIIOErrorReply, 32);
802
803#define MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID (0x01)
804#define MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED (0x08)
805
806/**
807 * IOC status codes specific to the SCSI I/O error reply.
808 */
809#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS (0x0041)
810#define MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID (0x0042)
811#define MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE (0x0043)
812
813/**
814 * SCSI task management request.
815 */
816typedef struct MptSCSITaskManagementRequest
817{
818 /** Target ID */
819 uint8_t u8TargetID;
820 /** Bus number */
821 uint8_t u8Bus;
822 /** Chain offset */
823 uint8_t u8ChainOffset;
824 /** Function number */
825 uint8_t u8Function;
826 /** Reserved */
827 uint8_t u8Reserved1;
828 /** Task type */
829 uint8_t u8TaskType;
830 /** Reserved */
831 uint8_t u8Reserved2;
832 /** Message flags */
833 uint8_t u8MessageFlags;
834 /** Message context ID */
835 uint32_t u32MessageContext;
836 /** LUN */
837 uint8_t au8LUN[8];
838 /** Reserved */
839 uint8_t auReserved[28];
840 /** Task message context ID. */
841 uint32_t u32TaskMessageContext;
842} MptSCSITaskManagementRequest, *PMptSCSITaskManagementRequest;
843AssertCompileSize(MptSCSITaskManagementRequest, 52);
844
845/**
846 * SCSI task management reply.
847 */
848typedef struct MptSCSITaskManagementReply
849{
850 /** Target ID */
851 uint8_t u8TargetID;
852 /** Bus number */
853 uint8_t u8Bus;
854 /** Message length */
855 uint8_t u8MessageLength;
856 /** Function number */
857 uint8_t u8Function;
858 /** Reserved */
859 uint8_t u8Reserved1;
860 /** Task type */
861 uint8_t u8TaskType;
862 /** Reserved */
863 uint8_t u8Reserved2;
864 /** Message flags */
865 uint8_t u8MessageFlags;
866 /** Message context ID */
867 uint32_t u32MessageContext;
868 /** Reserved */
869 uint16_t u16Reserved;
870 /** IO controller status */
871 uint16_t u16IOCStatus;
872 /** IO controller log information */
873 uint32_t u32IOCLogInfo;
874 /** Termination count */
875 uint32_t u32TerminationCount;
876} MptSCSITaskManagementReply, *PMptSCSITaskManagementReply;
877AssertCompileSize(MptSCSITaskManagementReply, 24);
878
879/**
880 * Page address for SAS expander page types.
881 */
882typedef union MptConfigurationPageAddressSASExpander
883{
884 struct
885 {
886 uint16_t u16Handle;
887 uint16_t u16Reserved;
888 } Form0And2;
889 struct
890 {
891 uint16_t u16Handle;
892 uint8_t u8PhyNum;
893 uint8_t u8Reserved;
894 } Form1;
895} MptConfigurationPageAddressSASExpander, *PMptConfigurationPageAddressSASExpander;
896AssertCompileSize(MptConfigurationPageAddressSASExpander, 4);
897
898/**
899 * Page address for SAS device page types.
900 */
901typedef union MptConfigurationPageAddressSASDevice
902{
903 struct
904 {
905 uint16_t u16Handle;
906 uint16_t u16Reserved;
907 } Form0And2;
908 struct
909 {
910 uint8_t u8TargetID;
911 uint8_t u8Bus;
912 uint8_t u8Reserved;
913 } Form1; /**< r=bird: only three bytes? */
914} MptConfigurationPageAddressSASDevice, *PMptConfigurationPageAddressSASDevice;
915AssertCompileSize(MptConfigurationPageAddressSASDevice, 4);
916
917/**
918 * Page address for SAS PHY page types.
919 */
920typedef union MptConfigurationPageAddressSASPHY
921{
922 struct
923 {
924 uint8_t u8PhyNumber;
925 uint8_t u8Reserved[3];
926 } Form0;
927 struct
928 {
929 uint16_t u16Index;
930 uint16_t u16Reserved;
931 } Form1;
932} MptConfigurationPageAddressSASPHY, *PMptConfigurationPageAddressSASPHY;
933AssertCompileSize(MptConfigurationPageAddressSASPHY, 4);
934
935/**
936 * Page address for SAS Enclosure page types.
937 */
938typedef struct MptConfigurationPageAddressSASEnclosure
939{
940 uint16_t u16Handle;
941 uint16_t u16Reserved;
942} MptConfigurationPageAddressSASEnclosure, *PMptConfigurationPageAddressSASEnclosure;
943AssertCompileSize(MptConfigurationPageAddressSASEnclosure, 4);
944
945/**
946 * Union of all possible address types.
947 */
948typedef union MptConfigurationPageAddress
949{
950 /** 32bit view. */
951 uint32_t u32PageAddress;
952 struct
953 {
954 /** Port number to get the configuration page for. */
955 uint8_t u8PortNumber;
956 /** Reserved. */
957 uint8_t u8Reserved[3];
958 } MPIPortNumber;
959 struct
960 {
961 /** Target ID to get the configuration page for. */
962 uint8_t u8TargetID;
963 /** Bus number to get the configuration page for. */
964 uint8_t u8Bus;
965 /** Reserved. */
966 uint8_t u8Reserved[2];
967 } BusAndTargetId;
968 MptConfigurationPageAddressSASExpander SASExpander;
969 MptConfigurationPageAddressSASDevice SASDevice;
970 MptConfigurationPageAddressSASPHY SASPHY;
971 MptConfigurationPageAddressSASEnclosure SASEnclosure;
972} MptConfigurationPageAddress, *PMptConfigurationPageAddress;
973AssertCompileSize(MptConfigurationPageAddress, 4);
974
975#define MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(x) (((x).u32PageAddress >> 28) & 0x0f)
976
977/**
978 * Configuration request
979 */
980typedef struct MptConfigurationRequest
981{
982 /** Action code. */
983 uint8_t u8Action;
984 /** Reserved. */
985 uint8_t u8Reserved1;
986 /** Chain offset. */
987 uint8_t u8ChainOffset;
988 /** Function number. */
989 uint8_t u8Function;
990 /** Extended page length. */
991 uint16_t u16ExtPageLength;
992 /** Extended page type */
993 uint8_t u8ExtPageType;
994 /** Message flags. */
995 uint8_t u8MessageFlags;
996 /** Message context ID. */
997 uint32_t u32MessageContext;
998 /** Reserved. */
999 uint8_t u8Reserved2[8];
1000 /** Version number of the page. */
1001 uint8_t u8PageVersion;
1002 /** Length of the page in 32bit Dwords. */
1003 uint8_t u8PageLength;
1004 /** Page number to access. */
1005 uint8_t u8PageNumber;
1006 /** Type of the page being accessed. */
1007 uint8_t u8PageType;
1008 /** Page type dependent address. */
1009 MptConfigurationPageAddress PageAddress;
1010 /** Simple SG element describing the buffer. */
1011 MptSGEntrySimple64 SimpleSGElement;
1012} MptConfigurationRequest, *PMptConfigurationRequest;
1013AssertCompileSize(MptConfigurationRequest, 40);
1014
1015/** Possible action codes. */
1016#define MPT_CONFIGURATION_REQUEST_ACTION_HEADER (0x00)
1017#define MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT (0x01)
1018#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT (0x02)
1019#define MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT (0x03)
1020#define MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM (0x04)
1021#define MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT (0x05)
1022#define MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM (0x06)
1023
1024/** Page type codes. */
1025#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IO_UNIT (0x00)
1026#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_IOC (0x01)
1027#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_BIOS (0x02)
1028#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_SCSI_PORT (0x03)
1029#define MPT_CONFIGURATION_REQUEST_PAGE_TYPE_EXTENDED (0x0F)
1030
1031/**
1032 * Configuration reply.
1033 */
1034typedef struct MptConfigurationReply
1035{
1036 /** Action code. */
1037 uint8_t u8Action;
1038 /** Reserved. */
1039 uint8_t u8Reserved;
1040 /** Message length. */
1041 uint8_t u8MessageLength;
1042 /** Function number. */
1043 uint8_t u8Function;
1044 /** Extended page length. */
1045 uint16_t u16ExtPageLength;
1046 /** Extended page type */
1047 uint8_t u8ExtPageType;
1048 /** Message flags. */
1049 uint8_t u8MessageFlags;
1050 /** Message context ID. */
1051 uint32_t u32MessageContext;
1052 /** Reserved. */
1053 uint16_t u16Reserved;
1054 /** I/O controller status. */
1055 uint16_t u16IOCStatus;
1056 /** I/O controller log information. */
1057 uint32_t u32IOCLogInfo;
1058 /** Version number of the page. */
1059 uint8_t u8PageVersion;
1060 /** Length of the page in 32bit Dwords. */
1061 uint8_t u8PageLength;
1062 /** Page number to access. */
1063 uint8_t u8PageNumber;
1064 /** Type of the page being accessed. */
1065 uint8_t u8PageType;
1066} MptConfigurationReply, *PMptConfigurationReply;
1067AssertCompileSize(MptConfigurationReply, 24);
1068
1069/** Additional I/O controller status codes for the configuration reply. */
1070#define MPT_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
1071#define MPT_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
1072#define MPT_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
1073#define MPT_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
1074#define MPT_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
1075#define MPT_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
1076
1077/**
1078 * Union of all possible request messages.
1079 */
1080typedef union MptRequestUnion
1081{
1082 MptMessageHdr Header;
1083 MptIOCInitRequest IOCInit;
1084 MptIOCFactsRequest IOCFacts;
1085 MptPortFactsRequest PortFacts;
1086 MptPortEnableRequest PortEnable;
1087 MptEventNotificationRequest EventNotification;
1088 MptSCSIIORequest SCSIIO;
1089 MptSCSITaskManagementRequest SCSITaskManagement;
1090 MptConfigurationRequest Configuration;
1091 MptFWDownloadRequest FWDownload;
1092 MptFWUploadRequest FWUpload;
1093} MptRequestUnion, *PMptRequestUnion;
1094
1095/**
1096 * Union of all possible reply messages.
1097 */
1098typedef union MptReplyUnion
1099{
1100 /** 16bit view. */
1101 uint16_t au16Reply[30];
1102 MptDefaultReplyMessage Header;
1103 MptIOCInitReply IOCInit;
1104 MptIOCFactsReply IOCFacts;
1105 MptPortFactsReply PortFacts;
1106 MptPortEnableReply PortEnable;
1107 MptEventNotificationReply EventNotification;
1108 MptSCSIIOErrorReply SCSIIOError;
1109 MptSCSITaskManagementReply SCSITaskManagement;
1110 MptConfigurationReply Configuration;
1111 MptFWDownloadReply FWDownload;
1112 MptFWUploadReply FWUpload;
1113} MptReplyUnion, *PMptReplyUnion;
1114AssertCompileSize(MptReplyUnion, 60);
1115
1116/**
1117 * Firmware image header.
1118 */
1119typedef struct FwImageHdr
1120{
1121 /** ARM branch instruction. */
1122 uint32_t u32ArmBrInsn;
1123 /** Signature part 1. */
1124 uint32_t u32Signature1;
1125 /** Signature part 2. */
1126 uint32_t u32Signature2;
1127 /** Signature part 3. */
1128 uint32_t u32Signature3;
1129 /** Another ARM branch instruction. */
1130 uint32_t u32ArmBrInsn2;
1131 /** Yet another ARM branch instruction. */
1132 uint32_t u32ArmBrInsn3;
1133 /** Reserved. */
1134 uint32_t u32Reserved;
1135 /** Checksum of the image. */
1136 uint32_t u32Checksum;
1137 /** Vendor ID. */
1138 uint16_t u16VendorId;
1139 /** Product ID. */
1140 uint16_t u16ProductId;
1141 /** Firmware version. */
1142 uint32_t u32FwVersion;
1143 /** Firmware sequencer Code version. */
1144 uint32_t u32SeqCodeVersion;
1145 /** Image size in bytes including the header. */
1146 uint32_t u32ImageSize;
1147 /** Offset of the first extended image header. */
1148 uint32_t u32NextImageHeaderOffset;
1149 /** Start address of the image in IOC memory. */
1150 uint32_t u32LoadStartAddress;
1151 /** Absolute start address of the Iop ARM. */
1152 uint32_t u32IopResetVectorValue;
1153 /** Address of the IopResetVector register. */
1154 uint32_t u32IopResetVectorRegAddr;
1155 /** Marker value for what utility. */
1156 uint32_t u32VersionNameWhat;
1157 /** ASCII string of version. */
1158 uint8_t aszVersionName[256];
1159 /** Marker value for what utility. */
1160 uint32_t u32VendorNameWhat;
1161 /** ASCII string of vendor name. */
1162 uint8_t aszVendorName[256];
1163} FwImageHdr, *PFwImageHdr;
1164AssertCompileSize(FwImageHdr, 584);
1165
1166/** First part of the signature. */
1167#define LSILOGIC_FWIMGHDR_SIGNATURE1 UINT32_C(0x5aeaa55a)
1168/** Second part of the signature. */
1169#define LSILOGIC_FWIMGHDR_SIGNATURE2 UINT32_C(0xa55aeaa5)
1170/** Third part of the signature. */
1171#define LSILOGIC_FWIMGHDR_SIGNATURE3 UINT32_C(0x5aa55aea)
1172/** Load address of the firmware image to watch for,
1173 * seen used by Solaris 9. When this value is written to the
1174 * diagnostic address register we know a firmware image is downloaded.
1175 */
1176#define LSILOGIC_FWIMGHDR_LOAD_ADDRESS UINT32_C(0x21ff5e00)
1177
1178/**
1179 * Configuration Page attributes.
1180 */
1181#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY (0x00)
1182#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE (0x10)
1183#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT (0x20)
1184#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY (0x30)
1185
1186#define MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(u8PageType) ((u8PageType) & 0xf0)
1187
1188/**
1189 * Configuration Page types.
1190 */
1191#define MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT (0x00)
1192#define MPT_CONFIGURATION_PAGE_TYPE_IOC (0x01)
1193#define MPT_CONFIGURATION_PAGE_TYPE_BIOS (0x02)
1194#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT (0x03)
1195#define MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE (0x04)
1196#define MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING (0x09)
1197#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED (0x0F)
1198
1199#define MPT_CONFIGURATION_PAGE_TYPE_GET(u8PageType) ((u8PageType) & 0x0f)
1200
1201/**
1202 * Extented page types.
1203 */
1204#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT (0x10)
1205#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER (0x11)
1206#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE (0x12)
1207#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS (0x13)
1208#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_LOG (0x14)
1209#define MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE (0x15)
1210
1211/**
1212 * Configuration Page header - Common to all pages.
1213 */
1214typedef struct MptConfigurationPageHeader
1215{
1216 /** Version of the page. */
1217 uint8_t u8PageVersion;
1218 /** The length of the page in 32bit D-Words. */
1219 uint8_t u8PageLength;
1220 /** Number of the page. */
1221 uint8_t u8PageNumber;
1222 /** Type of the page. */
1223 uint8_t u8PageType;
1224} MptConfigurationPageHeader, *PMptConfigurationPageHeader;
1225AssertCompileSize(MptConfigurationPageHeader, 4);
1226
1227/**
1228 * Extended configuration page header - Common to all extended pages.
1229 */
1230typedef struct MptExtendedConfigurationPageHeader
1231{
1232 /** Version of the page. */
1233 uint8_t u8PageVersion;
1234 /** Reserved. */
1235 uint8_t u8Reserved1;
1236 /** Number of the page. */
1237 uint8_t u8PageNumber;
1238 /** Type of the page. */
1239 uint8_t u8PageType;
1240 /** Extended page length. */
1241 uint16_t u16ExtPageLength;
1242 /** Extended page type. */
1243 uint8_t u8ExtPageType;
1244 /** Reserved */
1245 uint8_t u8Reserved2;
1246} MptExtendedConfigurationPageHeader, *PMptExtendedConfigurationPageHeader;
1247AssertCompileSize(MptExtendedConfigurationPageHeader, 8);
1248
1249/**
1250 * Manufacturing page 0. - Readonly.
1251 */
1252typedef struct MptConfigurationPageManufacturing0 /**< @todo r=bird: This and a series of other structs could save a lot of 'u.' typing by promoting the inner 'u' union... */
1253{
1254 /** Union. */
1255 union
1256 {
1257 /** Byte view. */
1258 uint8_t abPageData[76];
1259 /** Field view. */
1260 struct
1261 {
1262 /** The omnipresent header. */
1263 MptConfigurationPageHeader Header;
1264 /** Name of the chip. */
1265 uint8_t abChipName[16];
1266 /** Chip revision. */
1267 uint8_t abChipRevision[8];
1268 /** Board name. */
1269 uint8_t abBoardName[16];
1270 /** Board assembly. */
1271 uint8_t abBoardAssembly[16];
1272 /** Board tracer number. */
1273 uint8_t abBoardTracerNumber[16];
1274 } fields;
1275 } u;
1276} MptConfigurationPageManufacturing0, *PMptConfigurationPageManufacturing0;
1277AssertCompileSize(MptConfigurationPageManufacturing0, 76);
1278
1279/**
1280 * Manufacturing page 1. - Readonly Persistent.
1281 */
1282typedef struct MptConfigurationPageManufacturing1
1283{
1284 /** Union */
1285 union
1286 {
1287 /** Byte view */
1288 uint8_t abPageData[260];
1289 /** Field view */
1290 struct
1291 {
1292 /** The omnipresent header. */
1293 MptConfigurationPageHeader Header;
1294 /** VPD info - don't know what belongs here so all zero. */
1295 uint8_t abVPDInfo[256];
1296 } fields;
1297 } u;
1298} MptConfigurationPageManufacturing1, *PMptConfigurationPageManufacturing1;
1299AssertCompileSize(MptConfigurationPageManufacturing1, 260);
1300
1301/**
1302 * Manufacturing page 2. - Readonly.
1303 */
1304typedef struct MptConfigurationPageManufacturing2
1305{
1306 /** Union. */
1307 union
1308 {
1309 /** Byte view. */
1310 uint8_t abPageData[8];
1311 /** Field view. */
1312 struct
1313 {
1314 /** The omnipresent header. */
1315 MptConfigurationPageHeader Header;
1316 /** PCI Device ID. */
1317 uint16_t u16PCIDeviceID;
1318 /** PCI Revision ID. */
1319 uint8_t u8PCIRevisionID;
1320 /** Reserved. */
1321 uint8_t u8Reserved;
1322 /** Hardware specific settings... */
1323 } fields;
1324 } u;
1325} MptConfigurationPageManufacturing2, *PMptConfigurationPageManufacturing2;
1326AssertCompileSize(MptConfigurationPageManufacturing2, 8);
1327
1328/**
1329 * Manufacturing page 3. - Readonly.
1330 */
1331typedef struct MptConfigurationPageManufacturing3
1332{
1333 /** Union. */
1334 union
1335 {
1336 /** Byte view. */
1337 uint8_t abPageData[8];
1338 /** Field view. */
1339 struct
1340 {
1341 /** The omnipresent header. */
1342 MptConfigurationPageHeader Header;
1343 /** PCI Device ID. */
1344 uint16_t u16PCIDeviceID;
1345 /** PCI Revision ID. */
1346 uint8_t u8PCIRevisionID;
1347 /** Reserved. */
1348 uint8_t u8Reserved;
1349 /** Chip specific settings... */
1350 } fields;
1351 } u;
1352} MptConfigurationPageManufacturing3, *PMptConfigurationPageManufacturing3;
1353AssertCompileSize(MptConfigurationPageManufacturing3, 8);
1354
1355/**
1356 * Manufacturing page 4. - Readonly.
1357 */
1358typedef struct MptConfigurationPageManufacturing4
1359{
1360 /** Union. */
1361 union
1362 {
1363 /** Byte view. */
1364 uint8_t abPageData[84];
1365 /** Field view. */
1366 struct
1367 {
1368 /** The omnipresent header. */
1369 MptConfigurationPageHeader Header;
1370 /** Reserved. */
1371 uint32_t u32Reserved;
1372 /** InfoOffset0. */
1373 uint8_t u8InfoOffset0;
1374 /** Info size. */
1375 uint8_t u8InfoSize0;
1376 /** InfoOffset1. */
1377 uint8_t u8InfoOffset1;
1378 /** Info size. */
1379 uint8_t u8InfoSize1;
1380 /** Size of the inquiry data. */
1381 uint8_t u8InquirySize;
1382 /** Reserved. */
1383 uint8_t abReserved[3];
1384 /** Inquiry data. */
1385 uint8_t abInquiryData[56];
1386 /** IS volume settings. */
1387 uint32_t u32ISVolumeSettings;
1388 /** IME volume settings. */
1389 uint32_t u32IMEVolumeSettings;
1390 /** IM volume settings. */
1391 uint32_t u32IMVolumeSettings;
1392 } fields;
1393 } u;
1394} MptConfigurationPageManufacturing4, *PMptConfigurationPageManufacturing4;
1395AssertCompileSize(MptConfigurationPageManufacturing4, 84);
1396
1397/**
1398 * Manufacturing page 5 - Readonly.
1399 */
1400#pragma pack(1) /* u64BaseWWID is at offset 4, which isn't natural for uint64_t. */
1401typedef struct MptConfigurationPageManufacturing5
1402{
1403 /** Union. */
1404 union
1405 {
1406 /** Byte view. */
1407 uint8_t abPageData[88];
1408 /** Field view. */
1409 struct
1410 {
1411 /** The omnipresent header. */
1412 MptConfigurationPageHeader Header;
1413 /** Base WWID.
1414 * @note Not aligned on 8-byte boundrary */
1415 uint64_t u64BaseWWID;
1416 /** Flags */
1417 uint8_t u8Flags;
1418 /** Number of ForceWWID fields in this page. */
1419 uint8_t u8NumForceWWID;
1420 /** Reserved */
1421 uint16_t u16Reserved;
1422 /** Reserved */
1423 uint32_t au32Reserved[2];
1424 /** ForceWWID entries Maximum of 8 because the SAS controller doesn't has more */
1425 uint64_t au64ForceWWID[8];
1426 } fields;
1427 } u;
1428} MptConfigurationPageManufacturing5, *PMptConfigurationPageManufacturing5;
1429#pragma pack()
1430AssertCompileSize(MptConfigurationPageManufacturing5, 24+64);
1431
1432/**
1433 * Manufacturing page 6 - Readonly.
1434 */
1435typedef struct MptConfigurationPageManufacturing6
1436{
1437 /** Union. */
1438 union
1439 {
1440 /** Byte view. */
1441 uint8_t abPageData[4];
1442 /** Field view. */
1443 struct
1444 {
1445 /** The omnipresent header. */
1446 MptConfigurationPageHeader Header;
1447 /** Product specific data - 0 for now */
1448 } fields;
1449 } u;
1450} MptConfigurationPageManufacturing6, *PMptConfigurationPageManufacturing6;
1451AssertCompileSize(MptConfigurationPageManufacturing6, 4);
1452
1453/**
1454 * Manufacutring page 7 - PHY element.
1455 */
1456typedef struct MptConfigurationPageManufacturing7PHY
1457{
1458 /** Pinout */
1459 uint32_t u32Pinout;
1460 /** Connector name */
1461 uint8_t szConnector[16];
1462 /** Location */
1463 uint8_t u8Location;
1464 /** reserved */
1465 uint8_t u8Reserved;
1466 /** Slot */
1467 uint16_t u16Slot;
1468} MptConfigurationPageManufacturing7PHY, *PMptConfigurationPageManufacturing7PHY;
1469AssertCompileSize(MptConfigurationPageManufacturing7PHY, 24);
1470
1471/**
1472 * Manufacturing page 7 - Readonly.
1473 */
1474typedef struct MptConfigurationPageManufacturing7
1475{
1476 /** Union. */
1477 union
1478 {
1479 /** Byte view. */
1480 uint8_t abPageData[1];
1481 /** Field view. */
1482 struct
1483 {
1484 /** The omnipresent header. */
1485 MptConfigurationPageHeader Header;
1486 /** Reserved */
1487 uint32_t au32Reserved[2];
1488 /** Flags */
1489 uint32_t u32Flags;
1490 /** Enclosure name */
1491 uint8_t szEnclosureName[16];
1492 /** Number of PHYs */
1493 uint8_t u8NumPhys;
1494 /** Reserved */
1495 uint8_t au8Reserved[3];
1496 /** PHY list for the SAS controller - variable depending on the number of ports */
1497 MptConfigurationPageManufacturing7PHY aPHY[1];
1498 } fields;
1499 } u;
1500} MptConfigurationPageManufacturing7, *PMptConfigurationPageManufacturing7;
1501AssertCompileSize(MptConfigurationPageManufacturing7, 36+sizeof(MptConfigurationPageManufacturing7PHY));
1502
1503#define LSILOGICSCSI_MANUFACTURING7_GET_SIZE(ports) (sizeof(MptConfigurationPageManufacturing7) + ((ports) - 1) * sizeof(MptConfigurationPageManufacturing7PHY))
1504
1505/** Flags for the flags field */
1506#define LSILOGICSCSI_MANUFACTURING7_FLAGS_USE_PROVIDED_INFORMATION RT_BIT(0)
1507
1508/** Flags for the pinout field */
1509#define LSILOGICSCSI_MANUFACTURING7_PINOUT_UNKNOWN RT_BIT(0)
1510#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8482 RT_BIT(1)
1511#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE1 RT_BIT(8)
1512#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE2 RT_BIT(9)
1513#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE3 RT_BIT(10)
1514#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8470_LANE4 RT_BIT(11)
1515#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE1 RT_BIT(16)
1516#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE2 RT_BIT(17)
1517#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE3 RT_BIT(18)
1518#define LSILOGICSCSI_MANUFACTURING7_PINOUT_SFF8484_LANE4 RT_BIT(19)
1519
1520/** Flags for the location field */
1521#define LSILOGICSCSI_MANUFACTURING7_LOCATION_UNKNOWN 0x01
1522#define LSILOGICSCSI_MANUFACTURING7_LOCATION_INTERNAL 0x02
1523#define LSILOGICSCSI_MANUFACTURING7_LOCATION_EXTERNAL 0x04
1524#define LSILOGICSCSI_MANUFACTURING7_LOCATION_SWITCHABLE 0x08
1525#define LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO 0x10
1526#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_PRESENT 0x20
1527#define LSILOGICSCSI_MANUFACTURING7_LOCATION_NOT_CONNECTED 0x80
1528
1529/**
1530 * Manufacturing page 8 - Readonly.
1531 */
1532typedef struct MptConfigurationPageManufacturing8
1533{
1534 /** Union. */
1535 union
1536 {
1537 /** Byte view. */
1538 uint8_t abPageData[4];
1539 /** Field view. */
1540 struct
1541 {
1542 /** The omnipresent header. */
1543 MptConfigurationPageHeader Header;
1544 /** Product specific information */
1545 } fields;
1546 } u;
1547} MptConfigurationPageManufacturing8, *PMptConfigurationPageManufacturing8;
1548AssertCompileSize(MptConfigurationPageManufacturing8, 4);
1549
1550/**
1551 * Manufacturing page 9 - Readonly.
1552 */
1553typedef struct MptConfigurationPageManufacturing9
1554{
1555 /** Union. */
1556 union
1557 {
1558 /** Byte view. */
1559 uint8_t abPageData[4];
1560 /** Field view. */
1561 struct
1562 {
1563 /** The omnipresent header. */
1564 MptConfigurationPageHeader Header;
1565 /** Product specific information */
1566 } fields;
1567 } u;
1568} MptConfigurationPageManufacturing9, *PMptConfigurationPageManufacturing9;
1569AssertCompileSize(MptConfigurationPageManufacturing9, 4);
1570
1571/**
1572 * Manufacturing page 10 - Readonly.
1573 */
1574typedef struct MptConfigurationPageManufacturing10
1575{
1576 /** Union. */
1577 union
1578 {
1579 /** Byte view. */
1580 uint8_t abPageData[4];
1581 /** Field view. */
1582 struct
1583 {
1584 /** The omnipresent header. */
1585 MptConfigurationPageHeader Header;
1586 /** Product specific information */
1587 } fields;
1588 } u;
1589} MptConfigurationPageManufacturing10, *PMptConfigurationPageManufacturing10;
1590AssertCompileSize(MptConfigurationPageManufacturing10, 4);
1591
1592/**
1593 * IO Unit page 0. - Readonly.
1594 */
1595#pragma pack(1) /* u64UniqueIdentifier is at offset 4, which isn't natural for uint64_t. */
1596typedef struct MptConfigurationPageIOUnit0
1597{
1598 /** Union. */
1599 union
1600 {
1601 /** Byte view. */
1602 uint8_t abPageData[12];
1603 /** Field view. */
1604 struct
1605 {
1606 /** The omnipresent header. */
1607 MptConfigurationPageHeader Header;
1608 /** A unique identifier. */
1609 uint64_t u64UniqueIdentifier;
1610 } fields;
1611 } u;
1612} MptConfigurationPageIOUnit0, *PMptConfigurationPageIOUnit0;
1613#pragma pack()
1614AssertCompileSize(MptConfigurationPageIOUnit0, 12);
1615
1616/**
1617 * IO Unit page 1. - Read/Write.
1618 */
1619typedef struct MptConfigurationPageIOUnit1
1620{
1621 /** Union. */
1622 union
1623 {
1624 /** Byte view. */
1625 uint8_t abPageData[8];
1626 /** Field view. */
1627 struct
1628 {
1629 /** The omnipresent header. */
1630 MptConfigurationPageHeader Header;
1631 /** Flag whether this is a single function PCI device. */
1632 unsigned fSingleFunction: 1;
1633 /** Flag whether all possible paths to a device are mapped. */
1634 unsigned fAllPathsMapped: 1;
1635 /** Reserved. */
1636 unsigned u4Reserved: 4;
1637 /** Flag whether all RAID functionality is disabled. */
1638 unsigned fIntegratedRAIDDisabled: 1;
1639 /** Flag whether 32bit PCI accesses are forced. */
1640 unsigned f32BitAccessForced: 1;
1641 /** Reserved. */
1642 unsigned abReserved: 24;
1643 } fields;
1644 } u;
1645} MptConfigurationPageIOUnit1, *PMptConfigurationPageIOUnit1;
1646AssertCompileSize(MptConfigurationPageIOUnit1, 8);
1647
1648/**
1649 * Adapter Ordering.
1650 */
1651typedef struct MptConfigurationPageIOUnit2AdapterOrdering
1652{
1653 /** PCI bus number. */
1654 unsigned u8PCIBusNumber: 8;
1655 /** PCI device and function number. */
1656 unsigned u8PCIDevFn: 8;
1657 /** Flag whether the adapter is embedded. */
1658 unsigned fAdapterEmbedded: 1;
1659 /** Flag whether the adapter is enabled. */
1660 unsigned fAdapterEnabled: 1;
1661 /** Reserved. */
1662 unsigned u6Reserved: 6;
1663 /** Reserved. */
1664 unsigned u8Reserved: 8;
1665} MptConfigurationPageIOUnit2AdapterOrdering, *PMptConfigurationPageIOUnit2AdapterOrdering;
1666AssertCompileSize(MptConfigurationPageIOUnit2AdapterOrdering, 4);
1667
1668/**
1669 * IO Unit page 2. - Read/Write.
1670 */
1671typedef struct MptConfigurationPageIOUnit2
1672{
1673 /** Union. */
1674 union
1675 {
1676 /** Byte view. */
1677 uint8_t abPageData[28];
1678 /** Field view. */
1679 struct
1680 {
1681 /** The omnipresent header. */
1682 MptConfigurationPageHeader Header;
1683 /** Reserved. */
1684 unsigned fReserved: 1;
1685 /** Flag whether Pause on error is enabled. */
1686 unsigned fPauseOnError: 1;
1687 /** Flag whether verbose mode is enabled. */
1688 unsigned fVerboseModeEnabled: 1;
1689 /** Set to disable color video. */
1690 unsigned fDisableColorVideo: 1;
1691 /** Flag whether int 40h is hooked. */
1692 unsigned fNotHookInt40h: 1;
1693 /** Reserved. */
1694 unsigned u3Reserved: 3;
1695 /** Reserved. */
1696 unsigned abReserved: 24;
1697 /** BIOS version. */
1698 uint32_t u32BIOSVersion;
1699 /** Adapter ordering. */
1700 MptConfigurationPageIOUnit2AdapterOrdering aAdapterOrder[4];
1701 } fields;
1702 } u;
1703} MptConfigurationPageIOUnit2, *PMptConfigurationPageIOUnit2;
1704AssertCompileSize(MptConfigurationPageIOUnit2, 28);
1705
1706/*
1707 * IO Unit page 3. - Read/Write.
1708 */
1709typedef struct MptConfigurationPageIOUnit3
1710{
1711 /** Union. */
1712 union
1713 {
1714 /** Byte view. */
1715 uint8_t abPageData[8];
1716 /** Field view. */
1717 struct
1718 {
1719 /** The omnipresent header. */
1720 MptConfigurationPageHeader Header;
1721 /** Number of GPIO values. */
1722 uint8_t u8GPIOCount;
1723 /** Reserved. */
1724 uint8_t abReserved[3];
1725 } fields;
1726 } u;
1727} MptConfigurationPageIOUnit3, *PMptConfigurationPageIOUnit3;
1728AssertCompileSize(MptConfigurationPageIOUnit3, 8);
1729
1730/*
1731 * IO Unit page 4. - Readonly for everyone except the BIOS.
1732 */
1733typedef struct MptConfigurationPageIOUnit4
1734{
1735 /** Union. */
1736 union
1737 {
1738 /** Byte view. */
1739 uint8_t abPageData[20];
1740 /** Field view. */
1741 struct
1742 {
1743 /** The omnipresent header. */
1744 MptConfigurationPageHeader Header;
1745 /** Reserved */
1746 uint32_t u32Reserved;
1747 /** SG entry describing the Firmware location. */
1748 MptSGEntrySimple64 FWImageSGE;
1749 } fields;
1750 } u;
1751} MptConfigurationPageIOUnit4, *PMptConfigurationPageIOUnit4;
1752AssertCompileSize(MptConfigurationPageIOUnit4, 20);
1753
1754/**
1755 * IOC page 0. - Readonly
1756 */
1757typedef struct MptConfigurationPageIOC0
1758{
1759 /** Union. */
1760 union
1761 {
1762 /** Byte view. */
1763 uint8_t abPageData[28];
1764 /** Field view. */
1765 struct
1766 {
1767 /** The omnipresent header. */
1768 MptConfigurationPageHeader Header;
1769 /** Total amount of NV memory in bytes. */
1770 uint32_t u32TotalNVStore;
1771 /** Number of free bytes in the NV store. */
1772 uint32_t u32FreeNVStore;
1773 /** PCI vendor ID. */
1774 uint16_t u16VendorId;
1775 /** PCI device ID. */
1776 uint16_t u16DeviceId;
1777 /** PCI revision ID. */
1778 uint8_t u8RevisionId;
1779 /** Reserved. */
1780 uint8_t abReserved[3];
1781 /** PCI class code. */
1782 uint32_t u32ClassCode;
1783 /** Subsystem vendor Id. */
1784 uint16_t u16SubsystemVendorId;
1785 /** Subsystem Id. */
1786 uint16_t u16SubsystemId;
1787 } fields;
1788 } u;
1789} MptConfigurationPageIOC0, *PMptConfigurationPageIOC0;
1790AssertCompileSize(MptConfigurationPageIOC0, 28);
1791
1792/**
1793 * IOC page 1. - Read/Write
1794 */
1795typedef struct MptConfigurationPageIOC1
1796{
1797 /** Union. */
1798 union
1799 {
1800 /** Byte view. */
1801 uint8_t abPageData[16];
1802 /** Field view. */
1803 struct
1804 {
1805 /** The omnipresent header. */
1806 MptConfigurationPageHeader Header;
1807 /** Flag whether reply coalescing is enabled. */
1808 unsigned fReplyCoalescingEnabled: 1;
1809 /** Reserved. */
1810 unsigned u31Reserved: 31;
1811 /** Coalescing Timeout in microseconds. */
1812 unsigned u32CoalescingTimeout: 32;
1813 /** Coalescing depth. */
1814 unsigned u8CoalescingDepth: 8;
1815 /** Reserved. */
1816 unsigned u8Reserved0: 8;
1817 unsigned u8Reserved1: 8;
1818 unsigned u8Reserved2: 8;
1819 } fields;
1820 } u;
1821} MptConfigurationPageIOC1, *PMptConfigurationPageIOC1;
1822AssertCompileSize(MptConfigurationPageIOC1, 16);
1823
1824/**
1825 * IOC page 2. - Readonly
1826 */
1827typedef struct MptConfigurationPageIOC2
1828{
1829 /** Union. */
1830 union
1831 {
1832 /** Byte view. */
1833 uint8_t abPageData[12];
1834 /** Field view. */
1835 struct
1836 {
1837 /** The omnipresent header. */
1838 MptConfigurationPageHeader Header;
1839 /** Flag whether striping is supported. */
1840 unsigned fStripingSupported: 1;
1841 /** Flag whether enhanced mirroring is supported. */
1842 unsigned fEnhancedMirroringSupported: 1;
1843 /** Flag whether mirroring is supported. */
1844 unsigned fMirroringSupported: 1;
1845 /** Reserved. */
1846 unsigned u26Reserved: 26;
1847 /** Flag whether SES is supported. */
1848 unsigned fSESSupported: 1;
1849 /** Flag whether SAF-TE is supported. */
1850 unsigned fSAFTESupported: 1;
1851 /** Flag whether cross channel volumes are supported. */
1852 unsigned fCrossChannelVolumesSupported: 1;
1853 /** Number of active integrated RAID volumes. */
1854 unsigned u8NumActiveVolumes: 8;
1855 /** Maximum number of integrated RAID volumes supported. */
1856 unsigned u8MaxVolumes: 8;
1857 /** Number of active integrated RAID physical disks. */
1858 unsigned u8NumActivePhysDisks: 8;
1859 /** Maximum number of integrated RAID physical disks supported. */
1860 unsigned u8MaxPhysDisks: 8;
1861 /** RAID volumes... - not supported. */
1862 } fields;
1863 } u;
1864} MptConfigurationPageIOC2, *PMptConfigurationPageIOC2;
1865AssertCompileSize(MptConfigurationPageIOC2, 12);
1866
1867/**
1868 * IOC page 3. - Readonly
1869 */
1870typedef struct MptConfigurationPageIOC3
1871{
1872 /** Union. */
1873 union
1874 {
1875 /** Byte view. */
1876 uint8_t abPageData[8];
1877 /** Field view. */
1878 struct
1879 {
1880 /** The omnipresent header. */
1881 MptConfigurationPageHeader Header;
1882 /** Number of active integrated RAID physical disks. */
1883 uint8_t u8NumPhysDisks;
1884 /** Reserved. */
1885 uint8_t abReserved[3];
1886 } fields;
1887 } u;
1888} MptConfigurationPageIOC3, *PMptConfigurationPageIOC3;
1889AssertCompileSize(MptConfigurationPageIOC3, 8);
1890
1891/**
1892 * IOC page 4. - Read/Write
1893 */
1894typedef struct MptConfigurationPageIOC4
1895{
1896 /** Union. */
1897 union
1898 {
1899 /** Byte view. */
1900 uint8_t abPageData[8];
1901 /** Field view. */
1902 struct
1903 {
1904 /** The omnipresent header. */
1905 MptConfigurationPageHeader Header;
1906 /** Number of SEP entries in this page. */
1907 uint8_t u8ActiveSEP;
1908 /** Maximum number of SEp entries supported. */
1909 uint8_t u8MaxSEP;
1910 /** Reserved. */
1911 uint16_t u16Reserved;
1912 /** SEP entries... - not supported. */
1913 } fields;
1914 } u;
1915} MptConfigurationPageIOC4, *PMptConfigurationPageIOC4;
1916AssertCompileSize(MptConfigurationPageIOC4, 8);
1917
1918/**
1919 * IOC page 6. - Read/Write
1920 */
1921typedef struct MptConfigurationPageIOC6
1922{
1923 /** Union. */
1924 union
1925 {
1926 /** Byte view. */
1927 uint8_t abPageData[60];
1928 /** Field view. */
1929 struct
1930 {
1931 /** The omnipresent header. */
1932 MptConfigurationPageHeader Header;
1933 uint32_t u32CapabilitiesFlags;
1934 uint8_t u8MaxDrivesIS;
1935 uint8_t u8MaxDrivesIM;
1936 uint8_t u8MaxDrivesIME;
1937 uint8_t u8Reserved1;
1938 uint8_t u8MinDrivesIS;
1939 uint8_t u8MinDrivesIM;
1940 uint8_t u8MinDrivesIME;
1941 uint8_t u8Reserved2;
1942 uint8_t u8MaxGlobalHotSpares;
1943 uint8_t u8Reserved3;
1944 uint16_t u16Reserved4;
1945 uint32_t u32Reserved5;
1946 uint32_t u32SupportedStripeSizeMapIS;
1947 uint32_t u32SupportedStripeSizeMapIME;
1948 uint32_t u32Reserved6;
1949 uint8_t u8MetadataSize;
1950 uint8_t u8Reserved7;
1951 uint16_t u16Reserved8;
1952 uint16_t u16MaxBadBlockTableEntries;
1953 uint16_t u16Reserved9;
1954 uint16_t u16IRNvsramUsage;
1955 uint16_t u16Reserved10;
1956 uint32_t u32IRNvsramVersion;
1957 uint32_t u32Reserved11;
1958 } fields;
1959 } u;
1960} MptConfigurationPageIOC6, *PMptConfigurationPageIOC6;
1961AssertCompileSize(MptConfigurationPageIOC6, 60);
1962
1963/**
1964 * BIOS page 1 - Read/write.
1965 */
1966typedef struct MptConfigurationPageBIOS1
1967{
1968 /** Union. */
1969 union
1970 {
1971 /** Byte view. */
1972 uint8_t abPageData[48];
1973 /** Field view. */
1974 struct
1975 {
1976 /** The omnipresent header. */
1977 MptConfigurationPageHeader Header;
1978 /** BIOS options */
1979 uint32_t u32BiosOptions;
1980 /** IOC settings */
1981 uint32_t u32IOCSettings;
1982 /** Reserved */
1983 uint32_t u32Reserved;
1984 /** Device settings */
1985 uint32_t u32DeviceSettings;
1986 /** Number of devices */
1987 uint16_t u16NumberOfDevices;
1988 /** Expander spinup */
1989 uint8_t u8ExpanderSpinup;
1990 /** Reserved */
1991 uint8_t u8Reserved;
1992 /** I/O timeout of block devices without removable media */
1993 uint16_t u16IOTimeoutBlockDevicesNonRM;
1994 /** I/O timeout sequential */
1995 uint16_t u16IOTimeoutSequential;
1996 /** I/O timeout other */
1997 uint16_t u16IOTimeoutOther;
1998 /** I/O timeout of block devices with removable media */
1999 uint16_t u16IOTimeoutBlockDevicesRM;
2000 } fields;
2001 } u;
2002} MptConfigurationPageBIOS1, *PMptConfigurationPageBIOS1;
2003AssertCompileSize(MptConfigurationPageBIOS1, 48);
2004
2005#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_DISABLE RT_BIT(0)
2006#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_SCAN_FROM_HIGH_TO_LOW RT_BIT(1)
2007#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SAS_SUPPORT RT_BIT(8)
2008#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_FC_SUPPORT RT_BIT(9)
2009#define LSILOGICSCSI_BIOS1_BIOSOPTIONS_BIOS_EXTENDED_SPI_SUPPORT RT_BIT(10)
2010
2011#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ALTERNATE_CHS RT_BIT(3)
2012
2013#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_SET(x) ((x) << 4)
2014#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_DISABLED 0x00
2015#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BIOS_ONLY 0x01
2016#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_OS_ONLY 0x02
2017#define LSILOGICSCSI_BIOS1_IOCSETTINGS_ADAPTER_SUPPORT_BOT 0x03
2018
2019#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_SET(x) ((x) << 6)
2020#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_NO_INT13H 0x00
2021#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_BOOT_MEDIA_INT13H 0x01
2022#define LSILOGICSCSI_BIOS1_IOCSETTINGS_REMOVABLE_MEDIA_INT13H 0x02
2023
2024#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_SET(x) ((x & 0xF) << 8)
2025#define LSILOGICSCSI_BIOS1_IOCSETTINGS_SPINUP_DELAY_GET(x) ((x >> 8) & 0x0F)
2026#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_SET(x) ((x & 0xF) << 12)
2027#define LSILOGICSCSI_BIOS1_IOCSETTINGS_MAX_TARGET_SPINUP_GET(x) ((x >> 12) & 0x0F)
2028
2029#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SET(x) (((x) & 0x3) << 16)
2030#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_ENCLOSURE 0x0
2031#define LSILOGICSCSI_BIOS1_IOCSETTINGS_BOOT_PREFERENCE_SAS_ADDRESS 0x1
2032
2033#define LSILOGICSCSI_BIOS1_IOCSETTINGS_DIRECT_ATTACH_SPINUP_MODE_ALL RT_BIT(18)
2034#define LSILOGICSCSI_BIOS1_IOCSETTINGS_AUTO_PORT_ENABLE RT_BIT(19)
2035
2036#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_SET(x) (((x) & 0xF) << 20)
2037#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_REPLY_DELAY_GET(x) ((x >> 20) & 0x0F)
2038
2039#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_SET(x) (((x) & 0xF) << 24)
2040#define LSILOGICSCSI_BIOS1_IOCSETTINGS_PORT_ENABLE_SPINUP_DELAY_GET(x) ((x >> 24) & 0x0F)
2041
2042#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS RT_BIT(0)
2043#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_NON_REMOVABLE_DEVICES RT_BIT(1)
2044#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS_FOR_REMOVABLE_DEVICES RT_BIT(2)
2045#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_LUN_SCANS2 RT_BIT(3)
2046#define LSILOGICSCSI_BIOS1_DEVICESETTINGS_DISABLE_SMART_POLLING RT_BIT(4)
2047
2048#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_SET(x) ((x) & 0x0F)
2049#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_SPINUP_DELAY_GET(x) ((x) & 0x0F)
2050#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_SET(x) (((x) & 0x0F) << 4)
2051#define LSILOGICSCSI_BIOS1_EXPANDERSPINUP_MAX_SPINUP_DELAY_GET(x) ((x >> 4) & 0x0F)
2052
2053/**
2054 * BIOS page 2 - Read/write.
2055 */
2056typedef struct MptConfigurationPageBIOS2
2057{
2058 /** Union. */
2059 union
2060 {
2061 /** Byte view. */
2062 uint8_t abPageData[384];
2063 /** Field view. */
2064 struct
2065 {
2066 /** The omnipresent header. */
2067 MptConfigurationPageHeader Header;
2068 /** Reserved */
2069 uint32_t au32Reserved[6];
2070 /** Format of the boot device field. */
2071 uint8_t u8BootDeviceForm;
2072 /** Previous format of the boot device field. */
2073 uint8_t u8PrevBootDeviceForm;
2074 /** Reserved */
2075 uint16_t u16Reserved;
2076 /** Boot device fields - dependent on the format */
2077 union
2078 {
2079 /** Device for AdapterNumber:Bus:Target:LUN */
2080 struct
2081 {
2082 /** Target ID */
2083 uint8_t u8TargetID;
2084 /** Bus */
2085 uint8_t u8Bus;
2086 /** Adapter Number */
2087 uint8_t u8AdapterNumber;
2088 /** Reserved */
2089 uint8_t u8Reserved;
2090 /** Reserved */
2091 uint32_t au32Reserved[3];
2092 /** LUN */
2093 uint32_t aLUN[5];
2094 /** Reserved */
2095 uint32_t au32Reserved2[56];
2096 } AdapterNumberBusTargetLUN;
2097 /** Device for PCIAddress:Bus:Target:LUN */
2098 struct
2099 {
2100 /** Target ID */
2101 uint8_t u8TargetID;
2102 /** Bus */
2103 uint8_t u8Bus;
2104 /** Adapter Number */
2105 uint16_t u16PCIAddress;
2106 /** Reserved */
2107 uint32_t au32Reserved[3];
2108 /** LUN */
2109 uint32_t aLUN[5];
2110 /** Reserved */
2111 uint32_t au32Reserved2[56];
2112 } PCIAddressBusTargetLUN;
2113#if 0 /** @todo r=bird: The u16PCISlotNo member looks like it has the wrong type, but I cannot immediately locate specs and check. */
2114 /** Device for PCISlotNo:Bus:Target:LUN */
2115 struct
2116 {
2117 /** Target ID */
2118 uint8_t u8TargetID;
2119 /** Bus */
2120 uint8_t u8Bus;
2121 /** PCI Slot Number */
2122 uint8_t u16PCISlotNo;
2123 /** Reserved */
2124 uint32_t au32Reserved[3];
2125 /** LUN */
2126 uint32_t aLUN[5];
2127 /** Reserved */
2128 uint32_t au32Reserved2[56];
2129 } PCIAddressBusSlotLUN;
2130#endif
2131 /** Device for FC channel world wide name */
2132 struct
2133 {
2134 /** World wide port name low */
2135 uint32_t u32WorldWidePortNameLow;
2136 /** World wide port name high */
2137 uint32_t u32WorldWidePortNameHigh;
2138 /** Reserved */
2139 uint32_t au32Reserved[3];
2140 /** LUN */
2141 uint32_t aLUN[5];
2142 /** Reserved */
2143 uint32_t au32Reserved2[56];
2144 } FCWorldWideName;
2145 /** Device for FC channel world wide name */
2146 struct
2147 {
2148 /** SAS address */
2149 SASADDRESS SASAddress;
2150 /** Reserved */
2151 uint32_t au32Reserved[3];
2152 /** LUN */
2153 uint32_t aLUN[5];
2154 /** Reserved */
2155 uint32_t au32Reserved2[56];
2156 } SASWorldWideName;
2157 /** Device for Enclosure/Slot */
2158 struct
2159 {
2160 /** Enclosure logical ID */
2161 uint64_t u64EnclosureLogicalID;
2162 /** Reserved */
2163 uint32_t au32Reserved[3];
2164 /** LUN */
2165 uint32_t aLUN[5];
2166 /** Reserved */
2167 uint32_t au32Reserved2[56];
2168 } EnclosureSlot;
2169 } BootDevice;
2170 } fields;
2171 } u;
2172} MptConfigurationPageBIOS2, *PMptConfigurationPageBIOS2;
2173AssertCompileMemberAlignment(MptConfigurationPageBIOS2, u.fields, 8);
2174AssertCompileSize(MptConfigurationPageBIOS2, 384);
2175
2176#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SET(x) ((x) & 0x0F)
2177#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FIRST 0x0
2178#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ADAPTER_BUS_TARGET_LUN 0x1
2179#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCIADDR_BUS_TARGET_LUN 0x2
2180#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_PCISLOT_BUS_TARGET_LUN 0x3
2181#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_FC_WWN 0x4
2182#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_SAS_WWN 0x5
2183#define LSILOGICSCSI_BIOS2_BOOT_DEVICE_FORM_ENCLOSURE_SLOT 0x6
2184
2185/**
2186 * BIOS page 4 - Read/Write (Where is 3? - not defined in the spec)
2187 */
2188#pragma pack(1) /* u64ReassignmentBaseWWID starts at offset 4, which isn't normally natural for uint64_t. */
2189typedef struct MptConfigurationPageBIOS4
2190{
2191 /** Union. */
2192 union
2193 {
2194 /** Byte view. */
2195 uint8_t abPageData[12];
2196 /** Field view. */
2197 struct
2198 {
2199 /** The omnipresent header. */
2200 MptConfigurationPageHeader Header;
2201 /** Reassignment Base WWID */
2202 uint64_t u64ReassignmentBaseWWID;
2203 } fields;
2204 } u;
2205} MptConfigurationPageBIOS4, *PMptConfigurationPageBIOS4;
2206#pragma pack()
2207AssertCompileSize(MptConfigurationPageBIOS4, 12);
2208
2209/**
2210 * SCSI-SPI port page 0. - Readonly
2211 */
2212typedef struct MptConfigurationPageSCSISPIPort0
2213{
2214 /** Union. */
2215 union
2216 {
2217 /** Byte view. */
2218 uint8_t abPageData[12];
2219 /** Field view. */
2220 struct
2221 {
2222 /** The omnipresent header. */
2223 MptConfigurationPageHeader Header;
2224 /** Flag whether this port is information unit transfers capable. */
2225 unsigned fInformationUnitTransfersCapable: 1;
2226 /** Flag whether the port is DT (Dual Transfer) capable. */
2227 unsigned fDTCapable: 1;
2228 /** Flag whether the port is QAS (Quick Arbitrate and Select) capable. */
2229 unsigned fQASCapable: 1;
2230 /** Reserved. */
2231 unsigned u5Reserved1: 5;
2232 /** Minimum Synchronous transfer period. */
2233 unsigned u8MinimumSynchronousTransferPeriod: 8;
2234 /** Maximum synchronous offset. */
2235 unsigned u8MaximumSynchronousOffset: 8;
2236 /** Reserved. */
2237 unsigned u5Reserved2: 5;
2238 /** Flag whether indicating the width of the bus - 0 narrow and 1 for wide. */
2239 unsigned fWide: 1;
2240 /** Reserved */
2241 unsigned fReserved: 1;
2242 /** Flag whether the port is AIP (Asynchronous Information Protection) capable. */
2243 unsigned fAIPCapable: 1;
2244 /** Signaling Type. */
2245 unsigned u2SignalingType: 2;
2246 /** Reserved. */
2247 unsigned u30Reserved: 30;
2248 } fields;
2249 } u;
2250} MptConfigurationPageSCSISPIPort0, *PMptConfigurationPageSCSISPIPort0;
2251AssertCompileSize(MptConfigurationPageSCSISPIPort0, 12);
2252
2253/**
2254 * SCSI-SPI port page 1. - Read/Write
2255 */
2256typedef struct MptConfigurationPageSCSISPIPort1
2257{
2258 /** Union. */
2259 union
2260 {
2261 /** Byte view. */
2262 uint8_t abPageData[12];
2263 /** Field view. */
2264 struct
2265 {
2266 /** The omnipresent header. */
2267 MptConfigurationPageHeader Header;
2268 /** The SCSI ID of the port. */
2269 uint8_t u8SCSIID;
2270 /** Reserved. */
2271 uint8_t u8Reserved;
2272 /** Port response IDs Bit mask field. */
2273 uint16_t u16PortResponseIDsBitmask;
2274 /** Value for the on BUS timer. */
2275 uint32_t u32OnBusTimerValue;
2276 } fields;
2277 } u;
2278} MptConfigurationPageSCSISPIPort1, *PMptConfigurationPageSCSISPIPort1;
2279AssertCompileSize(MptConfigurationPageSCSISPIPort1, 12);
2280
2281/**
2282 * Device settings for one device.
2283 */
2284typedef struct MptDeviceSettings
2285{
2286 /** Timeout for I/O in seconds. */
2287 unsigned u8Timeout: 8;
2288 /** Minimum synchronous factor. */
2289 unsigned u8SyncFactor: 8;
2290 /** Flag whether disconnect is enabled. */
2291 unsigned fDisconnectEnable: 1;
2292 /** Flag whether Scan ID is enabled. */
2293 unsigned fScanIDEnable: 1;
2294 /** Flag whether Scan LUNs is enabled. */
2295 unsigned fScanLUNEnable: 1;
2296 /** Flag whether tagged queuing is enabled. */
2297 unsigned fTaggedQueuingEnabled: 1;
2298 /** Flag whether wide is enabled. */
2299 unsigned fWideDisable: 1;
2300 /** Flag whether this device is bootable. */
2301 unsigned fBootChoice: 1;
2302 /** Reserved. */
2303 unsigned u10Reserved: 10;
2304} MptDeviceSettings, *PMptDeviceSettings;
2305AssertCompileSize(MptDeviceSettings, 4);
2306
2307/**
2308 * SCSI-SPI port page 2. - Read/Write for the BIOS
2309 */
2310typedef struct MptConfigurationPageSCSISPIPort2
2311{
2312 /** Union. */
2313 union
2314 {
2315 /** Byte view. */
2316 uint8_t abPageData[76];
2317 /** Field view. */
2318 struct
2319 {
2320 /** The omnipresent header. */
2321 MptConfigurationPageHeader Header;
2322 /** Flag indicating the bus scan order. */
2323 unsigned fBusScanOrderHighToLow: 1;
2324 /** Reserved. */
2325 unsigned fReserved: 1;
2326 /** Flag whether SCSI Bus resets are avoided. */
2327 unsigned fAvoidSCSIBusResets: 1;
2328 /** Flag whether alternate CHS is used. */
2329 unsigned fAlternateCHS: 1;
2330 /** Flag whether termination is disabled. */
2331 unsigned fTerminationDisabled: 1;
2332 /** Reserved. */
2333 unsigned u27Reserved: 27;
2334 /** Host SCSI ID. */
2335 unsigned u4HostSCSIID: 4;
2336 /** Initialize HBA. */
2337 unsigned u2InitializeHBA: 2;
2338 /** Removeable media setting. */
2339 unsigned u2RemovableMediaSetting: 2;
2340 /** Spinup delay. */
2341 unsigned u4SpinupDelay: 4;
2342 /** Negotiating settings. */
2343 unsigned u2NegotitatingSettings: 2;
2344 /** Reserved. */
2345 unsigned u18Reserved: 18;
2346 /** Device Settings. */
2347 MptDeviceSettings aDeviceSettings[16];
2348 } fields;
2349 } u;
2350} MptConfigurationPageSCSISPIPort2, *PMptConfigurationPageSCSISPIPort2;
2351AssertCompileSize(MptConfigurationPageSCSISPIPort2, 76);
2352
2353/**
2354 * SCSI-SPI device page 0. - Readonly
2355 */
2356typedef struct MptConfigurationPageSCSISPIDevice0
2357{
2358 /** Union. */
2359 union
2360 {
2361 /** Byte view. */
2362 uint8_t abPageData[12];
2363 /** Field view. */
2364 struct
2365 {
2366 /** The omnipresent header. */
2367 MptConfigurationPageHeader Header;
2368 /** Negotiated Parameters. */
2369 /** Information Units enabled. */
2370 unsigned fInformationUnitsEnabled: 1;
2371 /** Dual Transfers Enabled. */
2372 unsigned fDTEnabled: 1;
2373 /** QAS enabled. */
2374 unsigned fQASEnabled: 1;
2375 /** Reserved. */
2376 unsigned u5Reserved1: 5;
2377 /** Synchronous Transfer period. */
2378 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2379 /** Synchronous offset. */
2380 unsigned u8NegotiatedSynchronousOffset: 8;
2381 /** Reserved. */
2382 unsigned u5Reserved2: 5;
2383 /** Width - 0 for narrow and 1 for wide. */
2384 unsigned fWide: 1;
2385 /** Reserved. */
2386 unsigned fReserved: 1;
2387 /** AIP enabled. */
2388 unsigned fAIPEnabled: 1;
2389 /** Flag whether negotiation occurred. */
2390 unsigned fNegotationOccured: 1;
2391 /** Flag whether a SDTR message was rejected. */
2392 unsigned fSDTRRejected: 1;
2393 /** Flag whether a WDTR message was rejected. */
2394 unsigned fWDTRRejected: 1;
2395 /** Flag whether a PPR message was rejected. */
2396 unsigned fPPRRejected: 1;
2397 /** Reserved. */
2398 unsigned u28Reserved: 28;
2399 } fields;
2400 } u;
2401} MptConfigurationPageSCSISPIDevice0, *PMptConfigurationPageSCSISPIDevice0;
2402AssertCompileSize(MptConfigurationPageSCSISPIDevice0, 12);
2403
2404/**
2405 * SCSI-SPI device page 1. - Read/Write
2406 */
2407typedef struct MptConfigurationPageSCSISPIDevice1
2408{
2409 /** Union. */
2410 union
2411 {
2412 /** Byte view. */
2413 uint8_t abPageData[16];
2414 /** Field view. */
2415 struct
2416 {
2417 /** The omnipresent header. */
2418 MptConfigurationPageHeader Header;
2419 /** Requested Parameters. */
2420 /** Information Units enable. */
2421 unsigned fInformationUnitsEnable: 1;
2422 /** Dual Transfers Enable. */
2423 unsigned fDTEnable: 1;
2424 /** QAS enable. */
2425 unsigned fQASEnable: 1;
2426 /** Reserved. */
2427 unsigned u5Reserved1: 5;
2428 /** Synchronous Transfer period. */
2429 unsigned u8NegotiatedSynchronousTransferPeriod: 8;
2430 /** Synchronous offset. */
2431 unsigned u8NegotiatedSynchronousOffset: 8;
2432 /** Reserved. */
2433 unsigned u5Reserved2: 5;
2434 /** Width - 0 for narrow and 1 for wide. */
2435 unsigned fWide: 1;
2436 /** Reserved. */
2437 unsigned fReserved1: 1;
2438 /** AIP enable. */
2439 unsigned fAIPEnable: 1;
2440 /** Reserved. */
2441 unsigned fReserved2: 1;
2442 /** WDTR disallowed. */
2443 unsigned fWDTRDisallowed: 1;
2444 /** SDTR disallowed. */
2445 unsigned fSDTRDisallowed: 1;
2446 /** Reserved. */
2447 unsigned u29Reserved: 29;
2448 } fields;
2449 } u;
2450} MptConfigurationPageSCSISPIDevice1, *PMptConfigurationPageSCSISPIDevice1;
2451AssertCompileSize(MptConfigurationPageSCSISPIDevice1, 16);
2452
2453/**
2454 * SCSI-SPI device page 2. - Read/Write
2455 */
2456typedef struct MptConfigurationPageSCSISPIDevice2
2457{
2458 /** Union. */
2459 union
2460 {
2461 /** Byte view. */
2462 uint8_t abPageData[16];
2463 /** Field view. */
2464 struct
2465 {
2466 /** The omnipresent header. */
2467 MptConfigurationPageHeader Header;
2468 /** Reserved. */
2469 unsigned u4Reserved: 4;
2470 /** ISI enable. */
2471 unsigned fISIEnable: 1;
2472 /** Secondary driver enable. */
2473 unsigned fSecondaryDriverEnable: 1;
2474 /** Reserved. */
2475 unsigned fReserved: 1;
2476 /** Slew create controller. */
2477 unsigned u3SlewRateControler: 3;
2478 /** Primary drive strength controller. */
2479 unsigned u3PrimaryDriveStrengthControl: 3;
2480 /** Secondary drive strength controller. */
2481 unsigned u3SecondaryDriveStrengthControl: 3;
2482 /** Reserved. */
2483 unsigned u12Reserved: 12;
2484 /** XCLKH_ST. */
2485 unsigned fXCLKH_ST: 1;
2486 /** XCLKS_ST. */
2487 unsigned fXCLKS_ST: 1;
2488 /** XCLKH_DT. */
2489 unsigned fXCLKH_DT: 1;
2490 /** XCLKS_DT. */
2491 unsigned fXCLKS_DT: 1;
2492 /** Parity pipe select. */
2493 unsigned u2ParityPipeSelect: 2;
2494 /** Reserved. */
2495 unsigned u30Reserved: 30;
2496 /** Data bit pipeline select. */
2497 unsigned u32DataPipelineSelect: 32;
2498 } fields;
2499 } u;
2500} MptConfigurationPageSCSISPIDevice2, *PMptConfigurationPageSCSISPIDevice2;
2501AssertCompileSize(MptConfigurationPageSCSISPIDevice2, 16);
2502
2503/**
2504 * SCSI-SPI device page 3 (Revision G). - Readonly
2505 */
2506typedef struct MptConfigurationPageSCSISPIDevice3
2507{
2508 /** Union. */
2509 union
2510 {
2511 /** Byte view. */
2512 uint8_t abPageData[1];
2513 /** Field view. */
2514 struct
2515 {
2516 /** The omnipresent header. */
2517 MptConfigurationPageHeader Header;
2518 /** Number of times the IOC rejected a message because it doesn't support the operation. */
2519 uint16_t u16MsgRejectCount;
2520 /** Number of times the SCSI bus entered an invalid operation state. */
2521 uint16_t u16PhaseErrorCount;
2522 /** Number of parity errors. */
2523 uint16_t u16ParityCount;
2524 /** Reserved. */
2525 uint16_t u16Reserved;
2526 } fields;
2527 } u;
2528} MptConfigurationPageSCSISPIDevice3, *PMptConfigurationPageSCSISPIDevice3;
2529AssertCompileSize(MptConfigurationPageSCSISPIDevice3, 12);
2530
2531/**
2532 * PHY entry for the SAS I/O unit page 0
2533 */
2534typedef struct MptConfigurationPageSASIOUnit0PHY
2535{
2536 /** Port number */
2537 uint8_t u8Port;
2538 /** Port flags */
2539 uint8_t u8PortFlags;
2540 /** Phy flags */
2541 uint8_t u8PhyFlags;
2542 /** negotiated link rate */
2543 uint8_t u8NegotiatedLinkRate;
2544 /** Controller phy device info */
2545 uint32_t u32ControllerPhyDeviceInfo;
2546 /** Attached device handle */
2547 uint16_t u16AttachedDevHandle;
2548 /** Controller device handle */
2549 uint16_t u16ControllerDevHandle;
2550 /** Discovery status */
2551 uint32_t u32DiscoveryStatus;
2552} MptConfigurationPageSASIOUnit0PHY, *PMptConfigurationPageSASIOUnit0PHY;
2553AssertCompileSize(MptConfigurationPageSASIOUnit0PHY, 16);
2554
2555/**
2556 * SAS I/O Unit page 0 - Readonly
2557 */
2558typedef struct MptConfigurationPageSASIOUnit0
2559{
2560 /** Union. */
2561 union
2562 {
2563 /** Byte view - variable. */
2564 uint8_t abPageData[1];
2565 /** Field view. */
2566 struct
2567 {
2568 /** The omnipresent header. */
2569 MptExtendedConfigurationPageHeader ExtHeader;
2570 /** Nvdata version default */
2571 uint16_t u16NvdataVersionDefault;
2572 /** Nvdata version persistent */
2573 uint16_t u16NvdataVersionPersistent;
2574 /** Number of physical ports */
2575 uint8_t u8NumPhys;
2576 /** Reserved */
2577 uint8_t au8Reserved[3];
2578 /** Content for each physical port - variable depending on the amount of ports. */
2579 MptConfigurationPageSASIOUnit0PHY aPHY[1];
2580 } fields;
2581 } u;
2582} MptConfigurationPageSASIOUnit0, *PMptConfigurationPageSASIOUnit0;
2583AssertCompileSize(MptConfigurationPageSASIOUnit0, 8+2+2+1+3+sizeof(MptConfigurationPageSASIOUnit0PHY));
2584
2585#define LSILOGICSCSI_SASIOUNIT0_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit0) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit0PHY))
2586
2587#define LSILOGICSCSI_SASIOUNIT0_PORT_CONFIGURATION_AUTO RT_BIT(0)
2588#define LSILOGICSCSI_SASIOUNIT0_PORT_TARGET_IOC RT_BIT(2)
2589#define LSILOGICSCSI_SASIOUNIT0_PORT_DISCOVERY_IN_STATUS RT_BIT(3)
2590
2591#define LSILOGICSCSI_SASIOUNIT0_PHY_RX_INVERTED RT_BIT(0)
2592#define LSILOGICSCSI_SASIOUNIT0_PHY_TX_INVERTED RT_BIT(1)
2593#define LSILOGICSCSI_SASIOUNIT0_PHY_DISABLED RT_BIT(2)
2594
2595#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(x) ((x) & 0x0F)
2596#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_GET(x) ((x) & 0x0F)
2597#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_UNKNOWN 0x00
2598#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_DISABLED 0x01
2599#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED 0x02
2600#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SATA_OOB 0x03
2601#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_15GB 0x08
2602#define LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB 0x09
2603
2604#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(x) ((x) & 0x3)
2605#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO 0x0
2606#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END 0x1
2607#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_EDGE_EXPANDER 0x2
2608#define LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2609
2610#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA_HOST RT_BIT(3)
2611#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_INITIATOR RT_BIT(4)
2612#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_INITIATOR RT_BIT(5)
2613#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_INITIATOR RT_BIT(6)
2614#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SATA RT_BIT(7)
2615#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SMP_TARGET RT_BIT(8)
2616#define LSILOGICSCSI_SASIOUNIT0_DEVICE_STP_TARGET RT_BIT(9)
2617#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET RT_BIT(10)
2618#define LSILOGICSCSI_SASIOUNIT0_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2619#define LSILOGICSCSI_SASIOUNIT0_DEVICE_LSI RT_BIT(12)
2620#define LSILOGICSCSI_SASIOUNIT0_DEVICE_ATAPI_DEVICE RT_BIT(13)
2621#define LSILOGICSCSI_SASIOUNIT0_DEVICE_SEP_DEVICE RT_BIT(14)
2622
2623#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_LOOP RT_BIT(0)
2624#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNADDRESSABLE RT_BIT(1)
2625#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SAME_SAS_ADDR RT_BIT(2)
2626#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXPANDER_ERROR RT_BIT(3)
2627#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_TIMEOUT RT_BIT(4)
2628#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_OOE RT_BIT(5)
2629#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_EXP_ROUTE_IDX RT_BIT(6)
2630#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_FUNC_FAILED RT_BIT(7)
2631#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SMP_CRC_ERROR RT_BIT(8)
2632#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_SUBTRSCTIVE_LNK RT_BIT(9)
2633#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_TBL_LNK RT_BIT(10)
2634#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_UNSUPPORTED_DEV RT_BIT(11)
2635#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MAX_SATA_TGTS RT_BIT(12)
2636#define LSILOGICSCSI_SASIOUNIT0_DISCOVERY_STATUS_MULT_CTRLS RT_BIT(13)
2637
2638/**
2639 * PHY entry for the SAS I/O unit page 1
2640 */
2641typedef struct MptConfigurationPageSASIOUnit1PHY
2642{
2643 /** Port number */
2644 uint8_t u8Port;
2645 /** Port flags */
2646 uint8_t u8PortFlags;
2647 /** Phy flags */
2648 uint8_t u8PhyFlags;
2649 /** Max link rate */
2650 uint8_t u8MaxMinLinkRate;
2651 /** Controller phy device info */
2652 uint32_t u32ControllerPhyDeviceInfo;
2653 /** Maximum target port connect time */
2654 uint16_t u16MaxTargetPortConnectTime;
2655 /** Reserved */
2656 uint16_t u16Reserved;
2657} MptConfigurationPageSASIOUnit1PHY, *PMptConfigurationPageSASIOUnit1PHY;
2658AssertCompileSize(MptConfigurationPageSASIOUnit1PHY, 12);
2659
2660/**
2661 * SAS I/O Unit page 1 - Read/Write
2662 */
2663typedef struct MptConfigurationPageSASIOUnit1
2664{
2665 /** Union. */
2666 union
2667 {
2668 /** Byte view - variable. */
2669 uint8_t abPageData[1];
2670 /** Field view. */
2671 struct
2672 {
2673 /** The omnipresent header. */
2674 MptExtendedConfigurationPageHeader ExtHeader;
2675 /** Control flags */
2676 uint16_t u16ControlFlags;
2677 /** maximum number of SATA targets */
2678 uint16_t u16MaxNumSATATargets;
2679 /** additional control flags */
2680 uint16_t u16AdditionalControlFlags;
2681 /** Reserved */
2682 uint16_t u16Reserved;
2683 /** Number of PHYs */
2684 uint8_t u8NumPhys;
2685 /** maximum SATA queue depth */
2686 uint8_t u8SATAMaxQDepth;
2687 /** Delay for reporting missing devices. */
2688 uint8_t u8ReportDeviceMissingDelay;
2689 /** I/O device missing delay */
2690 uint8_t u8IODeviceMissingDelay;
2691 /** Content for each physical port - variable depending on the number of ports */
2692 MptConfigurationPageSASIOUnit1PHY aPHY[1];
2693 } fields;
2694 } u;
2695} MptConfigurationPageSASIOUnit1, *PMptConfigurationPageSASIOUnit1;
2696AssertCompileSize(MptConfigurationPageSASIOUnit1, 8+12+sizeof(MptConfigurationPageSASIOUnit1PHY));
2697
2698#define LSILOGICSCSI_SASIOUNIT1_GET_SIZE(ports) (sizeof(MptConfigurationPageSASIOUnit1) + ((ports) - 1) * sizeof(MptConfigurationPageSASIOUnit1PHY))
2699
2700#define LSILOGICSCSI_SASIOUNIT1_CONTROL_CLEAR_SATA_AFFILIATION RT_BIT(0)
2701#define LSILOGICSCSI_SASIOUNIT1_CONTROL_FIRST_LEVEL_DISCOVERY_ONLY RT_BIT(1)
2702#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SUBTRACTIVE_LNK_ILLEGAL RT_BIT(2)
2703#define LSILOGICSCSI_SASIOUNIT1_CONTROL_IOC_ENABLE_HIGH_PHY RT_BIT(3)
2704#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED RT_BIT(4)
2705#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED RT_BIT(5)
2706#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED RT_BIT(6)
2707#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LBA48_REQUIRED RT_BIT(7)
2708#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_INIT_POSTPONED RT_BIT(8)
2709
2710#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SET(x) (((x) & 0x3) << 9)
2711#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_GET(x) (((x) >> 9) & 0x3)
2712#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS_AND_SATA 0x00
2713#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SAS 0x01
2714#define LSILOGICSCSI_SASIOUNIT1_CONTROL_DEVICE_SUPPORT_SATA 0x02
2715
2716#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_EXP_ADDR RT_BIT(11)
2717#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_SETTINGS_PRESERV_REQUIRED RT_BIT(12)
2718#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_15GB RT_BIT(13)
2719#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SATA_LIMIT_RATE_30GB RT_BIT(14)
2720#define LSILOGICSCSI_SASIOUNIT1_CONTROL_SAS_SELF_TEST_ENABLED RT_BIT(15)
2721
2722#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_TBL_LNKS_ALLOW RT_BIT(0)
2723#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_NO_AFFIL RT_BIT(1)
2724#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_SELF_AFFIL RT_BIT(2)
2725#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_OTHER_AFFIL RT_BIT(3)
2726#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_RST_PORT_EN_ONLY RT_BIT(4)
2727#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_HIDE_NON_ZERO_PHYS RT_BIT(5)
2728#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_SATA_ASYNC_NOTIF RT_BIT(6)
2729#define LSILOGICSCSI_SASIOUNIT1_ADDITIONAL_CONTROL_MULT_PORTS_ILL_SAME_DOMAIN RT_BIT(7)
2730
2731#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_UNITS_16_SEC RT_BIT(7)
2732#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_SET(x) ((x) & 0x7F)
2733#define LSILOGICSCSI_SASIOUNIT1_MISSING_DEVICE_DELAY_GET(x) ((x) & 0x7F)
2734
2735#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_AUTO RT_BIT(0)
2736#define LSILOGICSCSI_SASIOUNIT1_PORT_CONFIGURATION_IOC1 RT_BIT(2)
2737
2738#define LSILOGICSCSI_SASIOUNIT1_PHY_RX_INVERT RT_BIT(0)
2739#define LSILOGICSCSI_SASIOUNIT1_PHY_TX_INVERT RT_BIT(1)
2740#define LSILOGICSCSI_SASIOUNIT1_PHY_DISABLE RT_BIT(2)
2741
2742#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(x) ((x) & 0x0F)
2743#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_GET(x) ((x) & 0x0F)
2744#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(x) (((x) & 0x0F) << 4)
2745#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_GET(x) ((x >> 4) & 0x0F)
2746#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB 0x8
2747#define LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB 0x9
2748
2749#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_SET(x) ((x) & 0x3)
2750#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_GET(x) ((x) & 0x3)
2751#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_NO 0x0
2752#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_END 0x1
2753#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_EDGE_EXPANDER 0x2
2754#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2755#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_INITIATOR RT_BIT(4)
2756#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_INITIATOR RT_BIT(5)
2757#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_INITIATOR RT_BIT(6)
2758#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SMP_TARGET RT_BIT(8)
2759#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_STP_TARGET RT_BIT(9)
2760#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SSP_TARGET RT_BIT(10)
2761#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2762#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_LSI RT_BIT(12)
2763#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_ATAPI RT_BIT(13)
2764#define LSILOGICSCSI_SASIOUNIT1_CTL_PHY_DEVICE_SEP RT_BIT(14)
2765
2766/**
2767 * SAS I/O unit page 2 - Read/Write
2768 */
2769typedef struct MptConfigurationPageSASIOUnit2
2770{
2771 /** Union. */
2772 union
2773 {
2774 /** Byte view - variable. */
2775 uint8_t abPageData[1];
2776 /** Field view. */
2777 struct
2778 {
2779 /** The omnipresent header. */
2780 MptExtendedConfigurationPageHeader ExtHeader;
2781 /** Device numbers per enclosure */
2782 uint8_t u8NumDevsPerEnclosure;
2783 /** Boot device wait time */
2784 uint8_t u8BootDeviceWaitTime;
2785 /** Reserved */
2786 uint16_t u16Reserved;
2787 /** Maximum number of persistent Bus and target ID mappings */
2788 uint16_t u16MaxPersistentIDs;
2789 /** Number of persistent IDs used */
2790 uint16_t u16NumPersistentIDsUsed;
2791 /** Status */
2792 uint8_t u8Status;
2793 /** Flags */
2794 uint8_t u8Flags;
2795 /** Maximum number of physical mapped IDs */
2796 uint16_t u16MaxNumPhysicalMappedIDs;
2797 } fields;
2798 } u;
2799} MptConfigurationPageSASIOUnit2, *PMptConfigurationPageSASIOUnit2;
2800AssertCompileSize(MptConfigurationPageSASIOUnit2, 20);
2801
2802#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_TBL_FULL RT_BIT(0)
2803#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_MAP_DISABLED RT_BIT(1)
2804#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_ENC_DEV_UNMAPPED RT_BIT(2)
2805#define LSILOGICSCSI_SASIOUNIT2_STATUS_PERSISTENT_DEV_LIMIT_EXCEEDED RT_BIT(3)
2806
2807#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_MAP_DISABLE RT_BIT(0)
2808#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_SET(x) ((x & 0x7) << 1)
2809#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_GET(x) ((x >> 1) & 0x7)
2810#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_NO 0x0
2811#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_DIRECT_ATTACHED 0x1
2812#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_ENC 0x2
2813#define LSILOGICSCSI_SASIOUNIT2_FLAGS_PERSISTENT_PHYS_MAP_MODE_HOST 0x7
2814#define LSILOGICSCSI_SASIOUNIT2_FLAGS_RESERVE_TARGET_ID_ZERO RT_BIT(4)
2815#define LSILOGICSCSI_SASIOUNIT2_FLAGS_START_SLOT_NUMBER_ONE RT_BIT(5)
2816
2817/**
2818 * SAS I/O unit page 3 - Read/Write
2819 */
2820typedef struct MptConfigurationPageSASIOUnit3
2821{
2822 /** Union. */
2823 union
2824 {
2825 /** Byte view - variable. */
2826 uint8_t abPageData[1];
2827 /** Field view. */
2828 struct
2829 {
2830 /** The omnipresent header. */
2831 MptExtendedConfigurationPageHeader ExtHeader;
2832 /** Reserved */
2833 uint32_t u32Reserved;
2834 uint32_t u32MaxInvalidDwordCount;
2835 uint32_t u32InvalidDwordCountTime;
2836 uint32_t u32MaxRunningDisparityErrorCount;
2837 uint32_t u32RunningDisparityErrorTime;
2838 uint32_t u32MaxLossDwordSynchCount;
2839 uint32_t u32LossDwordSynchCountTime;
2840 uint32_t u32MaxPhysResetProblemCount;
2841 uint32_t u32PhyResetProblemTime;
2842 } fields;
2843 } u;
2844} MptConfigurationPageSASIOUnit3, *PMptConfigurationPageSASIOUnit3;
2845AssertCompileSize(MptConfigurationPageSASIOUnit3, 44);
2846
2847/**
2848 * SAS PHY page 0 - Readonly
2849 */
2850#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
2851typedef struct MptConfigurationPageSASPHY0
2852{
2853 /** Union. */
2854 union
2855 {
2856 /** Byte view - variable. */
2857 uint8_t abPageData[1];
2858 /** Field view. */
2859 struct
2860 {
2861 /** The omnipresent header. */
2862 MptExtendedConfigurationPageHeader ExtHeader;
2863 /** Owner dev handle. */
2864 uint16_t u16OwnerDevHandle;
2865 /** Reserved */
2866 uint16_t u16Reserved0;
2867 /** SAS address */
2868 SASADDRESS SASAddress;
2869 /** Attached device handle */
2870 uint16_t u16AttachedDevHandle;
2871 /** Attached phy identifier */
2872 uint8_t u8AttachedPhyIdentifier;
2873 /** Reserved */
2874 uint8_t u8Reserved1;
2875 /** Attached device information */
2876 uint32_t u32AttachedDeviceInfo;
2877 /** Programmed link rate */
2878 uint8_t u8ProgrammedLinkRate;
2879 /** Hardware link rate */
2880 uint8_t u8HwLinkRate;
2881 /** Change count */
2882 uint8_t u8ChangeCount;
2883 /** Flags */
2884 uint8_t u8Flags;
2885 /** Phy information */
2886 uint32_t u32PhyInfo;
2887 } fields;
2888 } u;
2889} MptConfigurationPageSASPHY0, *PMptConfigurationPageSASPHY0;
2890#pragma pack()
2891AssertCompileSize(MptConfigurationPageSASPHY0, 36);
2892
2893#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2894#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2895#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO 0x0
2896#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END 0x1
2897#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2898#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2899#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2900#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2901#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2902#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2903#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2904#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2905#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2906#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_LSI RT_BIT(12)
2907#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
2908#define LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_SEP RT_BIT(14)
2909
2910/**
2911 * SAS PHY page 1 - Readonly
2912 */
2913typedef struct MptConfigurationPageSASPHY1
2914{
2915 /** Union. */
2916 union
2917 {
2918 /** Byte view - variable. */
2919 uint8_t abPageData[1];
2920 /** Field view. */
2921 struct
2922 {
2923 /** The omnipresent header. */
2924 MptExtendedConfigurationPageHeader ExtHeader;
2925 /** Reserved */
2926 uint32_t u32Reserved0;
2927 uint32_t u32InvalidDwordCound;
2928 uint32_t u32RunningDisparityErrorCount;
2929 uint32_t u32LossDwordSynchCount;
2930 uint32_t u32PhyResetProblemCount;
2931 } fields;
2932 } u;
2933} MptConfigurationPageSASPHY1, *PMptConfigurationPageSASPHY1;
2934AssertCompileSize(MptConfigurationPageSASPHY1, 28);
2935
2936/**
2937 * SAS Device page 0 - Readonly
2938 */
2939#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
2940typedef struct MptConfigurationPageSASDevice0
2941{
2942 /** Union. */
2943 union
2944 {
2945 /** Byte view - variable. */
2946 uint8_t abPageData[1];
2947 /** Field view. */
2948 struct
2949 {
2950 /** The omnipresent header. */
2951 MptExtendedConfigurationPageHeader ExtHeader;
2952 /** Slot number */
2953 uint16_t u16Slot;
2954 /** Enclosure handle. */
2955 uint16_t u16EnclosureHandle;
2956 /** SAS address */
2957 SASADDRESS SASAddress;
2958 /** Parent device handle */
2959 uint16_t u16ParentDevHandle;
2960 /** Phy number */
2961 uint8_t u8PhyNum;
2962 /** Access status */
2963 uint8_t u8AccessStatus;
2964 /** Device handle */
2965 uint16_t u16DevHandle;
2966 /** Target ID */
2967 uint8_t u8TargetID;
2968 /** Bus */
2969 uint8_t u8Bus;
2970 /** Device info */
2971 uint32_t u32DeviceInfo;
2972 /** Flags */
2973 uint16_t u16Flags;
2974 /** Physical port */
2975 uint8_t u8PhysicalPort;
2976 /** Reserved */
2977 uint8_t u8Reserved0;
2978 } fields;
2979 } u;
2980} MptConfigurationPageSASDevice0, *PMptConfigurationPageSASDevice0;
2981#pragma pack()
2982AssertCompileSize(MptConfigurationPageSASDevice0, 36);
2983
2984#define LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS (0x00)
2985
2986#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_SET(x) ((x) & 0x3)
2987#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_GET(x) ((x) & 0x3)
2988#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_NO 0x0
2989#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_END 0x1
2990#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_EDGE_EXPANDER 0x2
2991#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_TYPE_FANOUT_EXPANDER 0x3
2992#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_INITIATOR RT_BIT(4)
2993#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_INITIATOR RT_BIT(5)
2994#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_INITIATOR RT_BIT(6)
2995#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SMP_TARGET RT_BIT(8)
2996#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_STP_TARGET RT_BIT(9)
2997#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SSP_TARGET RT_BIT(10)
2998#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_DIRECT_ATTACHED RT_BIT(11)
2999#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_LSI RT_BIT(12)
3000#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_ATAPI RT_BIT(13)
3001#define LSILOGICSCSI_SASDEVICE0_DEV_INFO_DEVICE_SEP RT_BIT(14)
3002
3003#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT (RT_BIT(0))
3004#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID (RT_BIT(1))
3005#define LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT (RT_BIT(2))
3006
3007/**
3008 * SAS Device page 1 - Readonly
3009 */
3010#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
3011typedef struct MptConfigurationPageSASDevice1
3012{
3013 /** Union. */
3014 union
3015 {
3016 /** Byte view - variable. */
3017 uint8_t abPageData[1];
3018 /** Field view. */
3019 struct
3020 {
3021 /** The omnipresent header. */
3022 MptExtendedConfigurationPageHeader ExtHeader;
3023 /** Reserved */
3024 uint32_t u32Reserved0;
3025 /** SAS address */
3026 SASADDRESS SASAddress;
3027 /** Reserved */
3028 uint32_t u32Reserved;
3029 /** Device handle */
3030 uint16_t u16DevHandle;
3031 /** Target ID */
3032 uint8_t u8TargetID;
3033 /** Bus */
3034 uint8_t u8Bus;
3035 /** Initial REgister device FIS */
3036 uint32_t au32InitialRegDeviceFIS[5];
3037 } fields;
3038 } u;
3039} MptConfigurationPageSASDevice1, *PMptConfigurationPageSASDevice1;
3040#pragma pack()
3041AssertCompileSize(MptConfigurationPageSASDevice1, 48);
3042
3043/**
3044 * SAS Device page 2 - Read/Write persistent
3045 */
3046#pragma pack(1) /* Because of a uint64_t inside SASAddress, the struct size would be 24 without packing. */
3047typedef struct MptConfigurationPageSASDevice2
3048{
3049 /** Union. */
3050 union
3051 {
3052 /** Byte view - variable. */
3053 uint8_t abPageData[1];
3054 /** Field view. */
3055 struct
3056 {
3057 /** The omnipresent header. */
3058 MptExtendedConfigurationPageHeader ExtHeader;
3059 /** Physical identifier */
3060 SASADDRESS SASAddress;
3061 /** Enclosure mapping */
3062 uint32_t u32EnclosureMapping;
3063 } fields;
3064 } u;
3065} MptConfigurationPageSASDevice2, *PMptConfigurationPageSASDevice2;
3066#pragma pack()
3067AssertCompileSize(MptConfigurationPageSASDevice2, 20);
3068
3069/**
3070 * A device entitiy containing all pages.
3071 */
3072typedef struct MptSASDevice
3073{
3074 /** Pointer to the next device if any. */
3075 struct MptSASDevice *pNext;
3076 /** Pointer to the previous device if any. */
3077 struct MptSASDevice *pPrev;
3078
3079 MptConfigurationPageSASDevice0 SASDevicePage0;
3080 MptConfigurationPageSASDevice1 SASDevicePage1;
3081 MptConfigurationPageSASDevice2 SASDevicePage2;
3082} MptSASDevice, *PMptSASDevice;
3083
3084/**
3085 * SAS Expander page 0 - Readonly
3086 */
3087#pragma pack(1) /* SASAddress starts at offset 12, which isn't typically natural for uint64_t (inside it). */
3088typedef struct MptConfigurationPageSASExpander0
3089{
3090 /** Union. */
3091 union
3092 {
3093 /** Byte view - variable. */
3094 uint8_t abPageData[1];
3095 /** Field view. */
3096 struct
3097 {
3098 /** The omnipresent header. */
3099 MptExtendedConfigurationPageHeader ExtHeader;
3100 /** Physical port */
3101 uint8_t u8PhysicalPort;
3102 /** Reserved */
3103 uint8_t u8Reserved0;
3104 /** Enclosure handle */
3105 uint16_t u16EnclosureHandle;
3106 /** SAS address */
3107 SASADDRESS SASAddress;
3108 /** Discovery status */
3109 uint32_t u32DiscoveryStatus;
3110 /** Device handle. */
3111 uint16_t u16DevHandle;
3112 /** Parent device handle */
3113 uint16_t u16ParentDevHandle;
3114 /** Expander change count */
3115 uint16_t u16ExpanderChangeCount;
3116 /** Expander route indexes */
3117 uint16_t u16ExpanderRouteIndexes;
3118 /** Number of PHys in this expander */
3119 uint8_t u8NumPhys;
3120 /** SAS level */
3121 uint8_t u8SASLevel;
3122 /** Flags */
3123 uint8_t u8Flags;
3124 /** Reserved */
3125 uint8_t u8Reserved1;
3126 } fields;
3127 } u;
3128} MptConfigurationPageSASExpander0, *PMptConfigurationPageSASExpander0;
3129#pragma pack()
3130AssertCompileSize(MptConfigurationPageSASExpander0, 36);
3131
3132/**
3133 * SAS Expander page 1 - Readonly
3134 */
3135typedef struct MptConfigurationPageSASExpander1
3136{
3137 /** Union. */
3138 union
3139 {
3140 /** Byte view - variable. */
3141 uint8_t abPageData[1];
3142 /** Field view. */
3143 struct
3144 {
3145 /** The omnipresent header. */
3146 MptExtendedConfigurationPageHeader ExtHeader;
3147 /** Physical port */
3148 uint8_t u8PhysicalPort;
3149 /** Reserved */
3150 uint8_t u8Reserved0[3];
3151 /** Number of PHYs */
3152 uint8_t u8NumPhys;
3153 /** Number of the Phy the information in this page is for. */
3154 uint8_t u8Phy;
3155 /** Number of routing table entries */
3156 uint16_t u16NumTableEntriesProgrammed;
3157 /** Programmed link rate */
3158 uint8_t u8ProgrammedLinkRate;
3159 /** Hardware link rate */
3160 uint8_t u8HwLinkRate;
3161 /** Attached device handle */
3162 uint16_t u16AttachedDevHandle;
3163 /** Phy information */
3164 uint32_t u32PhyInfo;
3165 /** Attached device information */
3166 uint32_t u32AttachedDeviceInfo;
3167 /** Owner device handle. */
3168 uint16_t u16OwnerDevHandle;
3169 /** Change count */
3170 uint8_t u8ChangeCount;
3171 /** Negotiated link rate */
3172 uint8_t u8NegotiatedLinkRate;
3173 /** Phy identifier */
3174 uint8_t u8PhyIdentifier;
3175 /** Attached phy identifier */
3176 uint8_t u8AttachedPhyIdentifier;
3177 /** Reserved */
3178 uint8_t u8Reserved1;
3179 /** Discovery information */
3180 uint8_t u8DiscoveryInfo;
3181 /** Reserved */
3182 uint32_t u32Reserved;
3183 } fields;
3184 } u;
3185} MptConfigurationPageSASExpander1, *PMptConfigurationPageSASExpander1;
3186AssertCompileSize(MptConfigurationPageSASExpander1, 40);
3187
3188/**
3189 * Structure of all supported pages for the SCSI SPI controller.
3190 * Used to load the device state from older versions.
3191 */
3192typedef struct MptConfigurationPagesSupported_SSM_V2
3193{
3194 MptConfigurationPageManufacturing0 ManufacturingPage0;
3195 MptConfigurationPageManufacturing1 ManufacturingPage1;
3196 MptConfigurationPageManufacturing2 ManufacturingPage2;
3197 MptConfigurationPageManufacturing3 ManufacturingPage3;
3198 MptConfigurationPageManufacturing4 ManufacturingPage4;
3199 MptConfigurationPageIOUnit0 IOUnitPage0;
3200 MptConfigurationPageIOUnit1 IOUnitPage1;
3201 MptConfigurationPageIOUnit2 IOUnitPage2;
3202 MptConfigurationPageIOUnit3 IOUnitPage3;
3203 MptConfigurationPageIOC0 IOCPage0;
3204 MptConfigurationPageIOC1 IOCPage1;
3205 MptConfigurationPageIOC2 IOCPage2;
3206 MptConfigurationPageIOC3 IOCPage3;
3207 MptConfigurationPageIOC4 IOCPage4;
3208 MptConfigurationPageIOC6 IOCPage6;
3209 struct
3210 {
3211 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3212 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3213 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3214 } aPortPages[1]; /* Currently only one port supported. */
3215 struct
3216 {
3217 struct
3218 {
3219 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3220 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3221 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3222 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3223 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3224 } aBuses[1]; /* Only one bus at the moment. */
3225} MptConfigurationPagesSupported_SSM_V2, *PMptConfigurationPagesSupported_SSM_V2;
3226
3227typedef struct MptConfigurationPagesSpi
3228{
3229 struct
3230 {
3231 MptConfigurationPageSCSISPIPort0 SCSISPIPortPage0;
3232 MptConfigurationPageSCSISPIPort1 SCSISPIPortPage1;
3233 MptConfigurationPageSCSISPIPort2 SCSISPIPortPage2;
3234 } aPortPages[1]; /* Currently only one port supported. */
3235 struct
3236 {
3237 struct
3238 {
3239 MptConfigurationPageSCSISPIDevice0 SCSISPIDevicePage0;
3240 MptConfigurationPageSCSISPIDevice1 SCSISPIDevicePage1;
3241 MptConfigurationPageSCSISPIDevice2 SCSISPIDevicePage2;
3242 MptConfigurationPageSCSISPIDevice3 SCSISPIDevicePage3;
3243 } aDevicePages[LSILOGICSCSI_PCI_SPI_DEVICES_MAX];
3244 } aBuses[1]; /* Only one bus at the moment. */
3245} MptConfigurationPagesSpi, *PMptConfigurationPagesSpi;
3246
3247typedef struct MptPHY
3248{
3249 MptConfigurationPageSASPHY0 SASPHYPage0;
3250 MptConfigurationPageSASPHY1 SASPHYPage1;
3251} MptPHY, *PMptPHY;
3252
3253typedef struct MptConfigurationPagesSas
3254{
3255 /** Pointer to the manufacturing page 7 */
3256 PMptConfigurationPageManufacturing7 pManufacturingPage7;
3257 /** Size of the manufacturing page 7 */
3258 uint32_t cbManufacturingPage7;
3259 /** Size of the I/O unit page 0 */
3260 uint32_t cbSASIOUnitPage0;
3261 /** Pointer to the I/O unit page 0 */
3262 PMptConfigurationPageSASIOUnit0 pSASIOUnitPage0;
3263 /** Pointer to the I/O unit page 1 */
3264 PMptConfigurationPageSASIOUnit1 pSASIOUnitPage1;
3265 /** Size of the I/O unit page 1 */
3266 uint32_t cbSASIOUnitPage1;
3267 /** I/O unit page 2 */
3268 MptConfigurationPageSASIOUnit2 SASIOUnitPage2;
3269 /** I/O unit page 3 */
3270 MptConfigurationPageSASIOUnit3 SASIOUnitPage3;
3271
3272 /** Number of PHYs in the array. */
3273 uint32_t cPHYs;
3274 /** Pointer to an array of per PHYS pages. */
3275 R3PTRTYPE(PMptPHY) paPHYs;
3276
3277 /** Number of devices detected. */
3278 uint32_t cDevices;
3279 uint32_t u32Padding;
3280 /** Pointer to the first SAS device. */
3281 R3PTRTYPE(PMptSASDevice) pSASDeviceHead;
3282 /** Pointer to the last SAS device. */
3283 R3PTRTYPE(PMptSASDevice) pSASDeviceTail;
3284} MptConfigurationPagesSas, *PMptConfigurationPagesSas;
3285AssertCompile(RTASSERT_OFFSET_OF(MptConfigurationPagesSas,cbSASIOUnitPage0) + 4 == RTASSERT_OFFSET_OF(MptConfigurationPagesSas, pSASIOUnitPage0));
3286AssertCompile(RTASSERT_OFFSET_OF(MptConfigurationPagesSas,cPHYs) + 4 == RTASSERT_OFFSET_OF(MptConfigurationPagesSas, paPHYs));
3287AssertCompile(RTASSERT_OFFSET_OF(MptConfigurationPagesSas,cDevices) + 8 == RTASSERT_OFFSET_OF(MptConfigurationPagesSas, pSASDeviceHead));
3288
3289
3290/**
3291 * Structure of all supported pages for both controllers.
3292 */
3293typedef struct MptConfigurationPagesSupported
3294{
3295 MptConfigurationPageManufacturing0 ManufacturingPage0;
3296 MptConfigurationPageManufacturing1 ManufacturingPage1;
3297 MptConfigurationPageManufacturing2 ManufacturingPage2;
3298 MptConfigurationPageManufacturing3 ManufacturingPage3;
3299 MptConfigurationPageManufacturing4 ManufacturingPage4;
3300 MptConfigurationPageManufacturing5 ManufacturingPage5;
3301 MptConfigurationPageManufacturing6 ManufacturingPage6;
3302 MptConfigurationPageManufacturing8 ManufacturingPage8;
3303 MptConfigurationPageManufacturing9 ManufacturingPage9;
3304 MptConfigurationPageManufacturing10 ManufacturingPage10;
3305 MptConfigurationPageIOUnit0 IOUnitPage0;
3306 MptConfigurationPageIOUnit1 IOUnitPage1;
3307 MptConfigurationPageIOUnit2 IOUnitPage2;
3308 MptConfigurationPageIOUnit3 IOUnitPage3;
3309 MptConfigurationPageIOUnit4 IOUnitPage4;
3310 MptConfigurationPageIOC0 IOCPage0;
3311 MptConfigurationPageIOC1 IOCPage1;
3312 MptConfigurationPageIOC2 IOCPage2;
3313 MptConfigurationPageIOC3 IOCPage3;
3314 MptConfigurationPageIOC4 IOCPage4;
3315 MptConfigurationPageIOC6 IOCPage6;
3316 /* BIOS page 0 is not described */
3317 MptConfigurationPageBIOS1 BIOSPage1;
3318 MptConfigurationPageBIOS2 BIOSPage2;
3319 /* BIOS page 3 is not described */
3320 MptConfigurationPageBIOS4 BIOSPage4;
3321
3322 /** Controller dependent data. */
3323 union
3324 {
3325 MptConfigurationPagesSpi SpiPages;
3326 MptConfigurationPagesSas SasPages;
3327 } u;
3328} MptConfigurationPagesSupported, *PMptConfigurationPagesSupported;
3329
3330/**
3331 * Initializes a page header.
3332 */
3333#define MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags) \
3334 (pg)->u.fields.Header.u8PageType = (flags); \
3335 (pg)->u.fields.Header.u8PageNumber = (nr); \
3336 (pg)->u.fields.Header.u8PageLength = sizeof(type) / 4
3337
3338#define MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pg, type, nr, flags) \
3339 RT_ZERO(*pg); \
3340 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING)
3341
3342#define MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(pg, type, nr, flags) \
3343 RT_ZERO(*pg); \
3344 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT)
3345
3346#define MPT_CONFIG_PAGE_HEADER_INIT_IOC(pg, type, nr, flags) \
3347 RT_ZERO(*pg); \
3348 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_IOC)
3349
3350#define MPT_CONFIG_PAGE_HEADER_INIT_BIOS(pg, type, nr, flags) \
3351 RT_ZERO(*pg); \
3352 MPT_CONFIG_PAGE_HEADER_INIT(pg, type, nr, flags | MPT_CONFIGURATION_PAGE_TYPE_BIOS)
3353
3354/**
3355 * Initializes a extended page header.
3356 */
3357#define MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pg, cb, nr, flags, exttype) \
3358 RT_BZERO(pg, cb); \
3359 (pg)->u.fields.ExtHeader.u8PageType = (flags) | MPT_CONFIGURATION_PAGE_TYPE_EXTENDED; \
3360 (pg)->u.fields.ExtHeader.u8PageNumber = (nr); \
3361 (pg)->u.fields.ExtHeader.u8ExtPageType = (exttype); \
3362 (pg)->u.fields.ExtHeader.u16ExtPageLength = (cb) / 4
3363
3364/**
3365 * Possible SG element types.
3366 */
3367enum MPTSGENTRYTYPE
3368{
3369 MPTSGENTRYTYPE_TRANSACTION_CONTEXT = 0x00,
3370 MPTSGENTRYTYPE_SIMPLE = 0x01,
3371 MPTSGENTRYTYPE_CHAIN = 0x03
3372};
3373
3374/**
3375 * Register interface.
3376 */
3377
3378/**
3379 * Defined states that the SCSI controller can have.
3380 */
3381typedef enum LSILOGICSTATE
3382{
3383 /** Reset state. */
3384 LSILOGICSTATE_RESET = 0x00,
3385 /** Ready state. */
3386 LSILOGICSTATE_READY = 0x01,
3387 /** Operational state. */
3388 LSILOGICSTATE_OPERATIONAL = 0x02,
3389 /** Fault state. */
3390 LSILOGICSTATE_FAULT = 0x04,
3391 /** 32bit size hack */
3392 LSILOGICSTATE_32BIT_HACK = 0x7fffffff
3393} LSILOGICSTATE;
3394
3395/**
3396 * Which entity needs to initialize the controller
3397 * to get into the operational state.
3398 */
3399typedef enum LSILOGICWHOINIT
3400{
3401 /** Not initialized. */
3402 LSILOGICWHOINIT_NOT_INITIALIZED = 0x00,
3403 /** System BIOS. */
3404 LSILOGICWHOINIT_SYSTEM_BIOS = 0x01,
3405 /** ROM Bios. */
3406 LSILOGICWHOINIT_ROM_BIOS = 0x02,
3407 /** PCI Peer. */
3408 LSILOGICWHOINIT_PCI_PEER = 0x03,
3409 /** Host driver. */
3410 LSILOGICWHOINIT_HOST_DRIVER = 0x04,
3411 /** Manufacturing. */
3412 LSILOGICWHOINIT_MANUFACTURING = 0x05,
3413 /** 32bit size hack. */
3414 LSILOGICWHOINIT_32BIT_HACK = 0x7fffffff
3415} LSILOGICWHOINIT;
3416
3417
3418/**
3419 * Doorbell state.
3420 */
3421typedef enum LSILOGICDOORBELLSTATE
3422{
3423 /** Invalid value. */
3424 LSILOGICDOORBELLSTATE_INVALID = 0,
3425 /** Doorbell not in use. */
3426 LSILOGICDOORBELLSTATE_NOT_IN_USE,
3427 /** Reply frame removal, transfer number of entries, low 16bits. */
3428 LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW,
3429 /** Reply frame removal, transfer number of entries, high 16bits. */
3430 LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH,
3431 /** Reply frame removal, remove next free frame, low part. */
3432 LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW,
3433 /** Reply frame removal, remove next free frame, high part. */
3434 LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH,
3435 /** Function handshake. */
3436 LSILOGICDOORBELLSTATE_FN_HANDSHAKE,
3437 /** 32bit hack. */
3438 LSILOGICDOORBELLSTATE_32BIT_HACK = 0x7fffffff
3439} LSILOGICDOORBELLSTATE;
3440/** Pointer to a doorbell state. */
3441typedef LSILOGICDOORBELLSTATE *PLSILOGICDOORBELLSTATE;
3442
3443
3444/**
3445 * IOC status codes.
3446 */
3447#define LSILOGIC_IOCSTATUS_SUCCESS 0x0000
3448#define LSILOGIC_IOCSTATUS_INVALID_FUNCTION 0x0001
3449#define LSILOGIC_IOCSTATUS_BUSY 0x0002
3450#define LSILOGIC_IOCSTATUS_INVALID_SGL 0x0003
3451#define LSILOGIC_IOCSTATUS_INTERNAL_ERROR 0x0004
3452#define LSILOGIC_IOCSTATUS_RESERVED 0x0005
3453#define LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES 0x0006
3454#define LSILOGIC_IOCSTATUS_INVALID_FIELD 0x0007
3455#define LSILOGIC_IOCSTATUS_INVALID_STATE 0x0008
3456#define LSILOGIC_IOCSTATUS_OP_STATE_NOT_SUPPOTED 0x0009
3457
3458/**
3459 * Size of the I/O and MMIO space.
3460 */
3461#define LSILOGIC_PCI_SPACE_IO_SIZE 256
3462#define LSILOGIC_PCI_SPACE_MEM_SIZE 128 * _1K
3463
3464/**
3465 * Doorbell register - Used to get the status of the controller and
3466 * initialise it.
3467 */
3468#define LSILOGIC_REG_DOORBELL 0x00
3469# define LSILOGIC_REG_DOORBELL_SET_STATE(enmState) (((enmState) & 0x0f) << 28)
3470# define LSILOGIC_REG_DOORBELL_SET_USED(enmDoorbell) (((enmDoorbell != LSILOGICDOORBELLSTATE_NOT_IN_USE) ? 1 : 0) << 27)
3471# define LSILOGIC_REG_DOORBELL_SET_WHOINIT(enmWhoInit) (((enmWhoInit) & 0x07) << 24)
3472# define LSILOGIC_REG_DOORBELL_SET_FAULT_CODE(u16Code) (u16Code)
3473# define LSILOGIC_REG_DOORBELL_GET_FUNCTION(x) (((x) & 0xff000000) >> 24)
3474# define LSILOGIC_REG_DOORBELL_GET_SIZE(x) (((x) & 0x00ff0000) >> 16)
3475
3476/**
3477 * Functions which can be passed through the system doorbell.
3478 */
3479#define LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET 0x40
3480#define LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET 0x41
3481#define LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE 0x42
3482#define LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL 0x43
3483
3484/**
3485 * Write sequence register for the diagnostic register.
3486 */
3487#define LSILOGIC_REG_WRITE_SEQUENCE 0x04
3488
3489/**
3490 * Diagnostic register - used to reset the controller.
3491 */
3492#define LSILOGIC_REG_HOST_DIAGNOSTIC 0x08
3493# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_MEM_ENABLE (RT_BIT(0))
3494# define LSILOGIC_REG_HOST_DIAGNOSTIC_DISABLE_ARM (RT_BIT(1))
3495# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER (RT_BIT(2))
3496# define LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE (RT_BIT(4))
3497# define LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_HISTORY (RT_BIT(5))
3498# define LSILOGIC_REG_HOST_DIAGNOSTIC_FLASH_BAD_SIG (RT_BIT(6))
3499# define LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE (RT_BIT(7))
3500# define LSILOGIC_REG_HOST_DIAGNOSTIC_PREVENT_IOC_BOOT (RT_BIT(9))
3501# define LSILOGIC_REG_HOST_DIAGNOSTIC_CLEAR_FLASH_BAD_SIG (RT_BIT(10))
3502
3503#define LSILOGIC_REG_TEST_BASE_ADDRESS 0x0c
3504#define LSILOGIC_REG_DIAG_RW_DATA 0x10
3505#define LSILOGIC_REG_DIAG_RW_ADDRESS 0x14
3506
3507/**
3508 * Interrupt status register.
3509 */
3510#define LSILOGIC_REG_HOST_INTR_STATUS 0x30
3511# define LSILOGIC_REG_HOST_INTR_STATUS_W_MASK (RT_BIT(3))
3512# define LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS (RT_BIT(31))
3513# define LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR (RT_BIT(3))
3514# define LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL (RT_BIT(0))
3515
3516/**
3517 * Interrupt mask register.
3518 */
3519#define LSILOGIC_REG_HOST_INTR_MASK 0x34
3520# define LSILOGIC_REG_HOST_INTR_MASK_W_MASK (RT_BIT(0) | RT_BIT(3) | RT_BIT(8) | RT_BIT(9))
3521# define LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING (RT_BIT(8) | RT_BIT(9))
3522# define LSILOGIC_REG_HOST_INTR_MASK_DOORBELL RT_BIT(0)
3523# define LSILOGIC_REG_HOST_INTR_MASK_REPLY RT_BIT(3)
3524
3525/**
3526 * Queue registers.
3527 */
3528#define LSILOGIC_REG_REQUEST_QUEUE 0x40
3529#define LSILOGIC_REG_REPLY_QUEUE 0x44
3530
3531#endif /* !VBOX_INCLUDED_SRC_Storage_DevLsiLogicSCSI_h */
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