VirtualBox

About
Screenshots
Downloads
Documentation
End-user docs
Technical docs
Contribute
Community

Browse Source

Context Navigation

source: vbox/trunk/src/VBox/Devices/Storage/DevLsiLogicSCSI.cpp@ 60404

Last change on this file since 60404 was 60057, checked in by vboxsync, 8 years ago
Storage/LsiLogic: Missing case
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 237.9 KB

Line
1	/* $Id: DevLsiLogicSCSI.cpp 60057 2016-03-16 09:19:25Z vboxsync $ */
2	/** @file
3	* DevLsiLogicSCSI - LsiLogic LSI53c1030 SCSI controller.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_LSILOGICSCSI
23	#include <VBox/vmm/pdmdev.h>
24	#include <VBox/vmm/pdmstorageifs.h>
25	#include <VBox/vmm/pdmqueue.h>
26	#include <VBox/vmm/pdmthread.h>
27	#include <VBox/vmm/pdmcritsect.h>
28	#include <VBox/scsi.h>
29	#include <VBox/sup.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm.h>
32	#include <iprt/string.h>
33	#include <iprt/list.h>
34	#ifdef IN_RING3
35	# include <iprt/memcache.h>
36	# include <iprt/mem.h>
37	# include <iprt/param.h>
38	# include <iprt/uuid.h>
39	# include <iprt/time.h>
40	#endif
41
42	#include "DevLsiLogicSCSI.h"
43	#include "VBoxSCSI.h"
44
45	#include "VBoxDD.h"
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	/** The current saved state version. */
52	#define LSILOGIC_SAVED_STATE_VERSION 5
53	/** The saved state version used by VirtualBox before the diagnostic
54	* memory access was implemented. */
55	#define LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM 4
56	/** The saved state version used by VirtualBox before the doorbell status flag
57	* was changed from bool to a 32bit enum. */
58	#define LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL 3
59	/** The saved state version used by VirtualBox before SAS support was added. */
60	#define LSILOGIC_SAVED_STATE_VERSION_PRE_SAS 2
61	/** The saved state version used by VirtualBox 3.0 and earlier. It does not
62	* include the device config part. */
63	#define LSILOGIC_SAVED_STATE_VERSION_VBOX_30 1
64
65	/** Maximum number of entries in the release log. */
66	#define MAX_REL_LOG_ERRORS 1024
67
68	#define LSILOGIC_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
69
70	/** Upper number a buffer is freed if it was too big before. */
71	#define LSILOGIC_MAX_ALLOC_TOO_MUCH 20
72
73	/** Maximum size of the memory regions (prevents teh guest from DOSing the host by
74	* allocating loadds of memory). */
75	#define LSILOGIC_MEMORY_REGIONS_MAX (_1M)
76
77
78	/*********************************************************************************************************************************
79	* Structures and Typedefs *
80	*********************************************************************************************************************************/
81
82	/**
83	* I/O buffer copy worker.
84	*
85	* @returns nothing.
86	* @param pDevIns Device instance data.
87	* @param GCPhysIoBuf Guest physical address of the I/O buffer.
88	* @param pvBuf R3 buffer pointer.
89	* @param cbCopy How much to copy.
90	*/
91	typedef DECLCALLBACK(void) FNLSILOGICIOBUFCOPY(PPDMDEVINS pDevIns, RTGCPHYS GCPhysIoBuf,
92	void *pvBuf, size_t cbCopy);
93	/** Pointer to a I/O buffer copy worker. */
94	typedef FNLSILOGICIOBUFCOPY *PFNLSILOGICIOBUFCOPY;
95
96	/**
97	* Reply data.
98	*/
99	typedef struct LSILOGICSCSIREPLY
100	{
101	/** Lower 32 bits of the reply address in memory. */
102	uint32_t u32HostMFALowAddress;
103	/** Full address of the reply in guest memory. */
104	RTGCPHYS GCPhysReplyAddress;
105	/** Size of the reply. */
106	uint32_t cbReply;
107	/** Different views to the reply depending on the request type. */
108	MptReplyUnion Reply;
109	} LSILOGICSCSIREPLY;
110	/** Pointer to reply data. */
111	typedef LSILOGICSCSIREPLY *PLSILOGICSCSIREPLY;
112
113	/**
114	* Memory region of the IOC.
115	*/
116	typedef struct LSILOGICMEMREGN
117	{
118	/** List node. */
119	RTLISTNODE NodeList;
120	/** 32bit address the region starts to describe. */
121	uint32_t u32AddrStart;
122	/** 32bit address the region ends (inclusive). */
123	uint32_t u32AddrEnd;
124	/** Data for this region - variable. */
125	uint32_t au32Data[1];
126	} LSILOGICMEMREGN;
127	/** Pointer to a memory region. */
128	typedef LSILOGICMEMREGN *PLSILOGICMEMREGN;
129
130	/**
131	* State of a device attached to the buslogic host adapter.
132	*
133	* @implements PDMIBASE
134	* @implements PDMISCSIPORT
135	* @implements PDMILEDPORTS
136	*/
137	typedef struct LSILOGICDEVICE
138	{
139	/** Pointer to the owning lsilogic device instance. - R3 pointer */
140	R3PTRTYPE(struct LSILOGICSCSI *) pLsiLogicR3;
141
142	/** LUN of the device. */
143	uint32_t iLUN;
144	/** Number of outstanding tasks on the port. */
145	volatile uint32_t cOutstandingRequests;
146
147	#if HC_ARCH_BITS == 64
148	uint32_t Alignment0;
149	#endif
150
151	/** Our base interface. */
152	PDMIBASE IBase;
153	/** SCSI port interface. */
154	PDMISCSIPORT ISCSIPort;
155	/** Led interface. */
156	PDMILEDPORTS ILed;
157	/** Pointer to the attached driver's base interface. */
158	R3PTRTYPE(PPDMIBASE) pDrvBase;
159	/** Pointer to the underlying SCSI connector interface. */
160	R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;
161	/** The status LED state for this device. */
162	PDMLED Led;
163
164	} LSILOGICDEVICE;
165	/** Pointer to a device state. */
166	typedef LSILOGICDEVICE *PLSILOGICDEVICE;
167
168	/** Pointer to a task state. */
169	typedef struct LSILOGICREQ *PLSILOGICREQ;
170
171	/**
172	* Device instance data for the emulated SCSI controller.
173	*/
174	typedef struct LSILOGICSCSI
175	{
176	/** PCI device structure. */
177	PCIDEVICE PciDev;
178	/** Pointer to the device instance. - R3 ptr. */
179	PPDMDEVINSR3 pDevInsR3;
180	/** Pointer to the device instance. - R0 ptr. */
181	PPDMDEVINSR0 pDevInsR0;
182	/** Pointer to the device instance. - RC ptr. */
183	PPDMDEVINSRC pDevInsRC;
184
185	/** Flag whether the GC part of the device is enabled. */
186	bool fGCEnabled;
187	/** Flag whether the R0 part of the device is enabled. */
188	bool fR0Enabled;
189
190	/** The state the controller is currently in. */
191	LSILOGICSTATE enmState;
192	/** Who needs to init the driver to get into operational state. */
193	LSILOGICWHOINIT enmWhoInit;
194	/** Flag whether we are in doorbell function. */
195	LSILOGICDOORBELLSTATE enmDoorbellState;
196	/** Flag whether diagnostic access is enabled. */
197	bool fDiagnosticEnabled;
198	/** Flag whether a notification was send to R3. */
199	bool fNotificationSent;
200	/** Flag whether the guest enabled event notification from the IOC. */
201	bool fEventNotificationEnabled;
202	/** Flag whether the diagnostic address and RW registers are enabled. */
203	bool fDiagRegsEnabled;
204
205	/** Queue to send tasks to R3. - R3 ptr */
206	R3PTRTYPE(PPDMQUEUE) pNotificationQueueR3;
207	/** Queue to send tasks to R3. - R0 ptr */
208	R0PTRTYPE(PPDMQUEUE) pNotificationQueueR0;
209	/** Queue to send tasks to R3. - RC ptr */
210	RCPTRTYPE(PPDMQUEUE) pNotificationQueueRC;
211
212	/** Number of device states allocated. */
213	uint32_t cDeviceStates;
214
215	/** States for attached devices. */
216	R3PTRTYPE(PLSILOGICDEVICE) paDeviceStates;
217	#if HC_ARCH_BITS == 32
218	RTR3PTR R3PtrPadding0;
219	#endif
220
221	/** Interrupt mask. */
222	volatile uint32_t uInterruptMask;
223	/** Interrupt status register. */
224	volatile uint32_t uInterruptStatus;
225
226	/** Buffer for messages which are passed through the doorbell using the
227	* handshake method. */
228	uint32_t aMessage[sizeof(MptConfigurationRequest)]; /** @todo r=bird: Looks like 4 tims the required size? Please explain in comment if this correct... */
229	/** Actual position in the buffer. */
230	uint32_t iMessage;
231	/** Size of the message which is given in the doorbell message in dwords. */
232	uint32_t cMessage;
233
234	/** Reply buffer.
235	* @note 60 bytes */
236	MptReplyUnion ReplyBuffer;
237	/** Next entry to read. */
238	uint32_t uNextReplyEntryRead;
239	/** Size of the reply in the buffer in 16bit words. */
240	uint32_t cReplySize;
241
242	/** The fault code of the I/O controller if we are in the fault state. */
243	uint16_t u16IOCFaultCode;
244
245	/** I/O port address the device is mapped to. */
246	RTIOPORT IOPortBase;
247	/** MMIO address the device is mapped to. */
248	RTGCPHYS GCPhysMMIOBase;
249
250	/** Upper 32 bits of the message frame address to locate requests in guest memory. */
251	uint32_t u32HostMFAHighAddr;
252	/** Upper 32 bits of the sense buffer address. */
253	uint32_t u32SenseBufferHighAddr;
254	/** Maximum number of devices the driver reported he can handle. */
255	uint8_t cMaxDevices;
256	/** Maximum number of buses the driver reported he can handle. */
257	uint8_t cMaxBuses;
258	/** Current size of reply message frames in the guest. */
259	uint16_t cbReplyFrame;
260
261	/** Next key to write in the sequence to get access
262	* to diagnostic memory. */
263	uint32_t iDiagnosticAccess;
264
265	/** Number entries allocated for the reply queue. */
266	uint32_t cReplyQueueEntries;
267	/** Number entries allocated for the outstanding request queue. */
268	uint32_t cRequestQueueEntries;
269
270
271	/** Critical section protecting the reply post queue. */
272	PDMCRITSECT ReplyPostQueueCritSect;
273	/** Critical section protecting the reply free queue. */
274	PDMCRITSECT ReplyFreeQueueCritSect;
275
276	/** Pointer to the start of the reply free queue - R3. */
277	R3PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR3;
278	/** Pointer to the start of the reply post queue - R3. */
279	R3PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR3;
280	/** Pointer to the start of the request queue - R3. */
281	R3PTRTYPE(volatile uint32_t *) pRequestQueueBaseR3;
282
283	/** Pointer to the start of the reply queue - R0. */
284	R0PTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseR0;
285	/** Pointer to the start of the reply queue - R0. */
286	R0PTRTYPE(volatile uint32_t *) pReplyPostQueueBaseR0;
287	/** Pointer to the start of the request queue - R0. */
288	R0PTRTYPE(volatile uint32_t *) pRequestQueueBaseR0;
289
290	/** Pointer to the start of the reply queue - RC. */
291	RCPTRTYPE(volatile uint32_t *) pReplyFreeQueueBaseRC;
292	/** Pointer to the start of the reply queue - RC. */
293	RCPTRTYPE(volatile uint32_t *) pReplyPostQueueBaseRC;
294	/** Pointer to the start of the request queue - RC. */
295	RCPTRTYPE(volatile uint32_t *) pRequestQueueBaseRC;
296	/** End these RC pointers on a 64-bit boundrary. */
297	RTRCPTR RCPtrPadding1;
298
299	/** Next free entry in the reply queue the guest can write a address to. */
300	volatile uint32_t uReplyFreeQueueNextEntryFreeWrite;
301	/** Next valid entry the controller can read a valid address for reply frames from. */
302	volatile uint32_t uReplyFreeQueueNextAddressRead;
303
304	/** Next free entry in the reply queue the guest can write a address to. */
305	volatile uint32_t uReplyPostQueueNextEntryFreeWrite;
306	/** Next valid entry the controller can read a valid address for reply frames from. */
307	volatile uint32_t uReplyPostQueueNextAddressRead;
308
309	/** Next free entry the guest can write a address to a request frame to. */
310	volatile uint32_t uRequestQueueNextEntryFreeWrite;
311	/** Next valid entry the controller can read a valid address for request frames from. */
312	volatile uint32_t uRequestQueueNextAddressRead;
313
314	/** Emulated controller type */
315	LSILOGICCTRLTYPE enmCtrlType;
316	/** Handle counter */
317	uint16_t u16NextHandle;
318
319	/** Number of ports this controller has. */
320	uint8_t cPorts;
321
322	/** BIOS emulation. */
323	VBOXSCSI VBoxSCSI;
324
325	/** Cache for allocated tasks. */
326	R3PTRTYPE(RTMEMCACHE) hTaskCache;
327	/** Status LUN: The base interface. */
328	PDMIBASE IBase;
329	/** Status LUN: Leds interface. */
330	PDMILEDPORTS ILeds;
331	/** Status LUN: Partner of ILeds. */
332	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
333	/** Pointer to the configuration page area. */
334	R3PTRTYPE(PMptConfigurationPagesSupported) pConfigurationPages;
335
336	/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
337	* a port is entering the idle state. */
338	bool volatile fSignalIdle;
339	/** Flag whether we have tasks which need to be processed again- */
340	bool volatile fRedo;
341	/** Flag whether the worker thread is sleeping. */
342	volatile bool fWrkThreadSleeping;
343	/** Flag whether a request from the BIOS is pending which the
344	* worker thread needs to process. */
345	volatile bool fBiosReqPending;
346	#if HC_ARCH_BITS == 64
347	/** Alignment padding. */
348	bool afPadding2[4];
349	#endif
350	/** List of tasks which can be redone. */
351	R3PTRTYPE(volatile PLSILOGICREQ) pTasksRedoHead;
352
353	/** Current address to read from or write to in the diagnostic memory region. */
354	uint32_t u32DiagMemAddr;
355	/** Current size of the memory regions. */
356	uint32_t cbMemRegns;
357
358	#if HC_ARCH_BITS ==32
359	uint32_t u32Padding3;
360	#endif
361
362	union
363	{
364	/** List of memory regions - PLSILOGICMEMREGN. */
365	RTLISTANCHOR ListMemRegns;
366	uint8_t u8Padding[2 * sizeof(RTUINTPTR)];
367	};
368
369	/** The support driver session handle. */
370	R3R0PTRTYPE(PSUPDRVSESSION) pSupDrvSession;
371	/** Worker thread. */
372	R3PTRTYPE(PPDMTHREAD) pThreadWrk;
373	/** The event semaphore the processing thread waits on. */
374	SUPSEMEVENT hEvtProcess;
375
376	} LSILOGISCSI;
377	/** Pointer to the device instance data of the LsiLogic emulation. */
378	typedef LSILOGICSCSI *PLSILOGICSCSI;
379
380	/**
381	* Task state object which holds all necessary data while
382	* processing the request from the guest.
383	*/
384	typedef struct LSILOGICREQ
385	{
386	/** Next in the redo list. */
387	PLSILOGICREQ pRedoNext;
388	/** Target device. */
389	PLSILOGICDEVICE pTargetDevice;
390	/** The message request from the guest. */
391	MptRequestUnion GuestRequest;
392	/** Reply message if the request produces one. */
393	MptReplyUnion IOCReply;
394	/** SCSI request structure for the SCSI driver. */
395	PDMSCSIREQUEST PDMScsiRequest;
396	/** Address of the message request frame in guests memory.
397	* Used to read the S/G entries in the second step. */
398	RTGCPHYS GCPhysMessageFrameAddr;
399	/** Physical start address of the S/G list. */
400	RTGCPHYS GCPhysSgStart;
401	/** Chain offset */
402	uint32_t cChainOffset;
403	/** Segment describing the I/O buffer. */
404	RTSGSEG SegIoBuf;
405	/** Additional memory allocation for this task. */
406	void *pvAlloc;
407	/** Siize of the allocation. */
408	size_t cbAlloc;
409	/** Number of times we had too much memory allocated for the request. */
410	unsigned cAllocTooMuch;
411	/** Pointer to the sense buffer. */
412	uint8_t abSenseBuffer[18];
413	/** Flag whether the request was issued from the BIOS. */
414	bool fBIOS;
415	} LSILOGICREQ;
416
417
418	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
419
420
421	/*********************************************************************************************************************************
422	* Internal Functions *
423	*********************************************************************************************************************************/
424	RT_C_DECLS_BEGIN
425	#ifdef IN_RING3
426	static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis);
427	static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis);
428	static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
429	PMptConfigurationReply pReply);
430	#endif
431	RT_C_DECLS_END
432
433
434	/*********************************************************************************************************************************
435	* Global Variables *
436	*********************************************************************************************************************************/
437	/** Key sequence the guest has to write to enable access
438	* to diagnostic memory. */
439	static const uint8_t g_lsilogicDiagnosticAccess[] = {0x04, 0x0b, 0x02, 0x07, 0x0d};
440
441	/**
442	* Updates the status of the interrupt pin of the device.
443	*
444	* @returns nothing.
445	* @param pThis Pointer to the LsiLogic device state.
446	*/
447	static void lsilogicUpdateInterrupt(PLSILOGICSCSI pThis)
448	{
449	uint32_t uIntSts;
450
451	LogFlowFunc(("Updating interrupts\n"));
452
453	/* Mask out doorbell status so that it does not affect interrupt updating. */
454	uIntSts = (ASMAtomicReadU32(&pThis->uInterruptStatus) & ~LSILOGIC_REG_HOST_INTR_STATUS_DOORBELL_STS);
455	/* Check maskable interrupts. */
456	uIntSts &= ~(ASMAtomicReadU32(&pThis->uInterruptMask) & ~LSILOGIC_REG_HOST_INTR_MASK_IRQ_ROUTING);
457
458	if (uIntSts)
459	{
460	LogFlowFunc(("Setting interrupt\n"));
461	PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
462	}
463	else
464	{
465	LogFlowFunc(("Clearing interrupt\n"));
466	PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
467	}
468	}
469
470	/**
471	* Sets a given interrupt status bit in the status register and
472	* updates the interrupt status.
473	*
474	* @returns nothing.
475	* @param pThis Pointer to the LsiLogic device state.
476	* @param uStatus The status bit to set.
477	*/
478	DECLINLINE(void) lsilogicSetInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
479	{
480	ASMAtomicOrU32(&pThis->uInterruptStatus, uStatus);
481	lsilogicUpdateInterrupt(pThis);
482	}
483
484	/**
485	* Clears a given interrupt status bit in the status register and
486	* updates the interrupt status.
487	*
488	* @returns nothing.
489	* @param pThis Pointer to the LsiLogic device state.
490	* @param uStatus The status bit to set.
491	*/
492	DECLINLINE(void) lsilogicClearInterrupt(PLSILOGICSCSI pThis, uint32_t uStatus)
493	{
494	ASMAtomicAndU32(&pThis->uInterruptStatus, ~uStatus);
495	lsilogicUpdateInterrupt(pThis);
496	}
497
498	/**
499	* Sets the I/O controller into fault state and sets the fault code.
500	*
501	* @returns nothing
502	* @param pThis Pointer to the LsiLogic device state.
503	* @param uIOCFaultCode Fault code to set.
504	*/
505	DECLINLINE(void) lsilogicSetIOCFaultCode(PLSILOGICSCSI pThis, uint16_t uIOCFaultCode)
506	{
507	if (pThis->enmState != LSILOGICSTATE_FAULT)
508	{
509	LogFunc(("Setting I/O controller into FAULT state: uIOCFaultCode=%u\n", uIOCFaultCode));
510	pThis->enmState = LSILOGICSTATE_FAULT;
511	pThis->u16IOCFaultCode = uIOCFaultCode;
512	}
513	else
514	LogFunc(("We are already in FAULT state\n"));
515	}
516
517	/**
518	* Returns the number of frames in the reply free queue.
519	*
520	* @returns Number of frames in the reply free queue.
521	* @param pThis Pointer to the LsiLogic device state.
522	*/
523	DECLINLINE(uint32_t) lsilogicReplyFreeQueueGetFrameCount(PLSILOGICSCSI pThis)
524	{
525	uint32_t cReplyFrames = 0;
526
527	if (pThis->uReplyFreeQueueNextAddressRead <= pThis->uReplyFreeQueueNextEntryFreeWrite)
528	cReplyFrames = pThis->uReplyFreeQueueNextEntryFreeWrite - pThis->uReplyFreeQueueNextAddressRead;
529	else
530	cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyFreeQueueNextAddressRead + pThis->uReplyFreeQueueNextEntryFreeWrite;
531
532	return cReplyFrames;
533	}
534
535	/**
536	* Returns the number of free entries in the reply post queue.
537	*
538	* @returns Number of frames in the reply free queue.
539	* @param pThis Pointer to the LsiLogic device state.
540	*/
541	DECLINLINE(uint32_t) lsilogicReplyPostQueueGetFrameCount(PLSILOGICSCSI pThis)
542	{
543	uint32_t cReplyFrames = 0;
544
545	if (pThis->uReplyPostQueueNextAddressRead <= pThis->uReplyPostQueueNextEntryFreeWrite)
546	cReplyFrames = pThis->cReplyQueueEntries - pThis->uReplyPostQueueNextEntryFreeWrite + pThis->uReplyPostQueueNextAddressRead;
547	else
548	cReplyFrames = pThis->uReplyPostQueueNextEntryFreeWrite - pThis->uReplyPostQueueNextAddressRead;
549
550	return cReplyFrames;
551	}
552
553	#ifdef IN_RING3
554
555	/**
556	* Performs a hard reset on the controller.
557	*
558	* @returns VBox status code.
559	* @param pThis Pointer to the LsiLogic device state.
560	*/
561	static int lsilogicR3HardReset(PLSILOGICSCSI pThis)
562	{
563	pThis->enmState = LSILOGICSTATE_RESET;
564	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
565
566	/* The interrupts are masked out. */
567	pThis->uInterruptMask \|= LSILOGIC_REG_HOST_INTR_MASK_DOORBELL
568	\| LSILOGIC_REG_HOST_INTR_MASK_REPLY;
569	/* Reset interrupt states. */
570	pThis->uInterruptStatus = 0;
571	lsilogicUpdateInterrupt(pThis);
572
573	/* Reset the queues. */
574	pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
575	pThis->uReplyFreeQueueNextAddressRead = 0;
576	pThis->uReplyPostQueueNextEntryFreeWrite = 0;
577	pThis->uReplyPostQueueNextAddressRead = 0;
578	pThis->uRequestQueueNextEntryFreeWrite = 0;
579	pThis->uRequestQueueNextAddressRead = 0;
580
581	/* Disable diagnostic access. */
582	pThis->iDiagnosticAccess = 0;
583	pThis->fDiagnosticEnabled = false;
584	pThis->fDiagRegsEnabled = false;
585
586	/* Set default values. */
587	pThis->cMaxDevices = pThis->cDeviceStates;
588	pThis->cMaxBuses = 1;
589	pThis->cbReplyFrame = 128; /* @todo Figure out where it is needed. */
590	pThis->u16NextHandle = 1;
591	pThis->u32DiagMemAddr = 0;
592
593	lsilogicR3ConfigurationPagesFree(pThis);
594	lsilogicR3InitializeConfigurationPages(pThis);
595
596	/* Mark that we finished performing the reset. */
597	pThis->enmState = LSILOGICSTATE_READY;
598	return VINF_SUCCESS;
599	}
600
601	/**
602	* Frees the configuration pages if allocated.
603	*
604	* @returns nothing.
605	* @param pThis The LsiLogic controller instance
606	*/
607	static void lsilogicR3ConfigurationPagesFree(PLSILOGICSCSI pThis)
608	{
609
610	if (pThis->pConfigurationPages)
611	{
612	/* Destroy device list if we emulate a SAS controller. */
613	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
614	{
615	PMptConfigurationPagesSas pSasPages = &pThis->pConfigurationPages->u.SasPages;
616	PMptSASDevice pSASDeviceCurr = pSasPages->pSASDeviceHead;
617
618	while (pSASDeviceCurr)
619	{
620	PMptSASDevice pFree = pSASDeviceCurr;
621
622	pSASDeviceCurr = pSASDeviceCurr->pNext;
623	RTMemFree(pFree);
624	}
625	if (pSasPages->paPHYs)
626	RTMemFree(pSasPages->paPHYs);
627	if (pSasPages->pManufacturingPage7)
628	RTMemFree(pSasPages->pManufacturingPage7);
629	if (pSasPages->pSASIOUnitPage0)
630	RTMemFree(pSasPages->pSASIOUnitPage0);
631	if (pSasPages->pSASIOUnitPage1)
632	RTMemFree(pSasPages->pSASIOUnitPage1);
633	}
634
635	RTMemFree(pThis->pConfigurationPages);
636	}
637	}
638
639	/**
640	* Finishes a context reply.
641	*
642	* @returns nothing
643	* @param pThis Pointer to the LsiLogic device state.
644	* @param u32MessageContext The message context ID to post.
645	*/
646	static void lsilogicR3FinishContextReply(PLSILOGICSCSI pThis, uint32_t u32MessageContext)
647	{
648	int rc;
649
650	LogFlowFunc(("pThis=%#p u32MessageContext=%#x\n", pThis, u32MessageContext));
651
652	AssertMsg(pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE, ("We are in a doorbell function\n"));
653
654	/* Write message context ID into reply post queue. */
655	rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
656	AssertRC(rc);
657
658	/* Check for a entry in the queue. */
659	if (!lsilogicReplyPostQueueGetFrameCount(pThis))
660	{
661	/* Set error code. */
662	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
663	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
664	return;
665	}
666
667	/* We have a context reply. */
668	ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite], u32MessageContext);
669	ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
670	pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
671
672	/* Set interrupt. */
673	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
674
675	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
676	}
677
678	#endif /* IN_RING3 */
679
680	/**
681	* Takes necessary steps to finish a reply frame.
682	*
683	* @returns nothing
684	* @param pThis Pointer to the LsiLogic device state.
685	* @param pReply Pointer to the reply message.
686	* @param fForceReplyFifo Flag whether the use of the reply post fifo is forced.
687	*/
688	static void lsilogicFinishAddressReply(PLSILOGICSCSI pThis, PMptReplyUnion pReply, bool fForceReplyFifo)
689	{
690	/*
691	* If we are in a doorbell function we set the reply size now and
692	* set the system doorbell status interrupt to notify the guest that
693	* we are ready to send the reply.
694	*/
695	if (pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE && !fForceReplyFifo)
696	{
697	/* Set size of the reply in 16bit words. The size in the reply is in 32bit dwords. */
698	pThis->cReplySize = pReply->Header.u8MessageLength * 2;
699	Log(("%s: cReplySize=%u\n", __FUNCTION__, pThis->cReplySize));
700	pThis->uNextReplyEntryRead = 0;
701	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
702	}
703	else
704	{
705	/*
706	* The reply queues are only used if the request was fetched from the request queue.
707	* Requests from the request queue are always transferred to R3. So it is not possible
708	* that this case happens in R0 or GC.
709	*/
710	#ifdef IN_RING3
711	int rc;
712	/* Grab a free reply message from the queue. */
713	rc = PDMCritSectEnter(&pThis->ReplyFreeQueueCritSect, VINF_SUCCESS);
714	AssertRC(rc);
715
716	/* Check for a free reply frame. */
717	if (!lsilogicReplyFreeQueueGetFrameCount(pThis))
718	{
719	/* Set error code. */
720	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
721	PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
722	return;
723	}
724
725	uint32_t u32ReplyFrameAddressLow = pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead];
726
727	pThis->uReplyFreeQueueNextAddressRead++;
728	pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
729
730	PDMCritSectLeave(&pThis->ReplyFreeQueueCritSect);
731
732	/* Build 64bit physical address. */
733	RTGCPHYS GCPhysReplyMessage = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr, u32ReplyFrameAddressLow);
734	size_t cbReplyCopied = (pThis->cbReplyFrame < sizeof(MptReplyUnion)) ? pThis->cbReplyFrame : sizeof(MptReplyUnion);
735
736	/* Write reply to guest memory. */
737	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysReplyMessage, pReply, cbReplyCopied);
738
739	/* Write low 32bits of reply frame into post reply queue. */
740	rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_SUCCESS);
741	AssertRC(rc);
742
743	/* Check for a entry in the queue. */
744	if (!lsilogicReplyPostQueueGetFrameCount(pThis))
745	{
746	/* Set error code. */
747	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INSUFFICIENT_RESOURCES);
748	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
749	return;
750	}
751
752	/* We have a address reply. Set the 31th bit to indicate that. */
753	ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyPostQueueBase)[pThis->uReplyPostQueueNextEntryFreeWrite],
754	RT_BIT(31) \| (u32ReplyFrameAddressLow >> 1));
755	ASMAtomicIncU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
756	pThis->uReplyPostQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
757
758	if (fForceReplyFifo)
759	{
760	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
761	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
762	}
763
764	/* Set interrupt. */
765	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
766
767	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
768	#else
769	AssertMsgFailed(("This is not allowed to happen.\n"));
770	#endif
771	}
772	}
773
774	#ifdef IN_RING3
775
776	/**
777	* Tries to find a memory region which covers the given address.
778	*
779	* @returns Pointer to memory region or NULL if not found.
780	* @param pThis Pointer to the LsiLogic device state.
781	* @param u32Addr The 32bit address to search for.
782	*/
783	static PLSILOGICMEMREGN lsilogicR3MemRegionFindByAddr(PLSILOGICSCSI pThis, uint32_t u32Addr)
784	{
785	PLSILOGICMEMREGN pIt;
786	PLSILOGICMEMREGN pRegion = NULL;
787
788	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
789	{
790	if ( u32Addr >= pIt->u32AddrStart
791	&& u32Addr <= pIt->u32AddrEnd)
792	{
793	pRegion = pIt;
794	break;
795	}
796	}
797
798	return pRegion;
799	}
800
801	/**
802	* Frees all allocated memory regions.
803	*
804	* @returns nothing.
805	* @param pThis Pointer to the LsiLogic device state.
806	*/
807	static void lsilogicR3MemRegionsFree(PLSILOGICSCSI pThis)
808	{
809	PLSILOGICMEMREGN pIt;
810	PLSILOGICMEMREGN pItNext;
811
812	RTListForEachSafe(&pThis->ListMemRegns, pIt, pItNext, LSILOGICMEMREGN, NodeList)
813	{
814	RTListNodeRemove(&pIt->NodeList);
815	RTMemFree(pIt);
816	}
817	pThis->cbMemRegns = 0;
818	}
819
820	/**
821	* Inserts a given memory region into the list.
822	*
823	* @returns nothing.
824	* @param pThis Pointer to the LsiLogic device state.
825	* @param pRegion The region to insert.
826	*/
827	static void lsilogicR3MemRegionInsert(PLSILOGICSCSI pThis, PLSILOGICMEMREGN pRegion)
828	{
829	PLSILOGICMEMREGN pIt;
830	bool fInserted = false;
831
832	/* Insert at the right position. */
833	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
834	{
835	if (pRegion->u32AddrEnd < pIt->u32AddrStart)
836	{
837	RTListNodeInsertBefore(&pIt->NodeList, &pRegion->NodeList);
838	fInserted = true;
839	break;
840	}
841	}
842	if (!fInserted)
843	RTListAppend(&pThis->ListMemRegns, &pRegion->NodeList);
844	}
845
846	/**
847	* Count number of memory regions.
848	*
849	* @returns Number of memory regions.
850	* @param pThis Pointer to the LsiLogic device state.
851	*/
852	static uint32_t lsilogicR3MemRegionsCount(PLSILOGICSCSI pThis)
853	{
854	uint32_t cRegions = 0;
855	PLSILOGICMEMREGN pIt;
856
857	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
858	{
859	cRegions++;
860	}
861
862	return cRegions;
863	}
864
865	/**
866	* Handles a write to the diagnostic data register.
867	*
868	* @returns nothing.
869	* @param pThis Pointer to the LsiLogic device state.
870	* @param u32Data Data to write.
871	*/
872	static void lsilogicR3DiagRegDataWrite(PLSILOGICSCSI pThis, uint32_t u32Data)
873	{
874	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
875
876	if (pRegion)
877	{
878	uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
879
880	AssertMsg( offRegion % 4 == 0
881	&& pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
882	("Region offset not on a word boundary or crosses memory region\n"));
883
884	offRegion /= 4;
885	pRegion->au32Data[offRegion] = u32Data;
886	}
887	else
888	{
889	PLSILOGICMEMREGN pIt;
890
891	pRegion = NULL;
892
893	/* Create new region, first check whether we can extend another region. */
894	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
895	{
896	if (pThis->u32DiagMemAddr == pIt->u32AddrEnd + sizeof(uint32_t))
897	{
898	pRegion = pIt;
899	break;
900	}
901	}
902
903	if (pRegion)
904	{
905	/* Reallocate. */
906	RTListNodeRemove(&pRegion->NodeList);
907
908	uint32_t cRegionSizeOld = (pRegion->u32AddrEnd - pRegion->u32AddrStart) / 4 + 1;
909	uint32_t cRegionSizeNew = cRegionSizeOld + 512;
910
911	if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
912	{
913	PLSILOGICMEMREGN pRegionNew = (PLSILOGICMEMREGN)RTMemRealloc(pRegion, RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegionSizeNew]));
914
915	if (pRegionNew)
916	{
917	pRegion = pRegionNew;
918	memset(&pRegion->au32Data[cRegionSizeOld], 0, 512 * sizeof(uint32_t));
919	pRegion->au32Data[cRegionSizeOld] = u32Data;
920	pRegion->u32AddrEnd = pRegion->u32AddrStart + (cRegionSizeNew - 1) * sizeof(uint32_t);
921	pThis->cbMemRegns += 512 * sizeof(uint32_t);
922	}
923	/* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
924
925	lsilogicR3MemRegionInsert(pThis, pRegion);
926	}
927	}
928	else
929	{
930	if (pThis->cbMemRegns + 512 * sizeof(uint32_t) < LSILOGIC_MEMORY_REGIONS_MAX)
931	{
932	/* Create completely new. */
933	pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[512]));
934	if (pRegion)
935	{
936	pRegion->u32AddrStart = pThis->u32DiagMemAddr;
937	pRegion->u32AddrEnd = pRegion->u32AddrStart + (512 - 1) * sizeof(uint32_t);
938	pRegion->au32Data[0] = u32Data;
939	pThis->cbMemRegns += 512 * sizeof(uint32_t);
940
941	lsilogicR3MemRegionInsert(pThis, pRegion);
942	}
943	/* else: Silently fail, there is nothing we can do here and the guest might work nevertheless. */
944	}
945	}
946
947	}
948
949	/* Memory access is always 32bit big. */
950	pThis->u32DiagMemAddr += sizeof(uint32_t);
951	}
952
953	/**
954	* Handles a read from the diagnostic data register.
955	*
956	* @returns nothing.
957	* @param pThis Pointer to the LsiLogic device state.
958	* @param pu32Data Where to store the data.
959	*/
960	static void lsilogicR3DiagRegDataRead(PLSILOGICSCSI pThis, uint32_t *pu32Data)
961	{
962	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, pThis->u32DiagMemAddr);
963
964	if (pRegion)
965	{
966	uint32_t offRegion = pThis->u32DiagMemAddr - pRegion->u32AddrStart;
967
968	AssertMsg( offRegion % 4 == 0
969	&& pThis->u32DiagMemAddr <= pRegion->u32AddrEnd,
970	("Region offset not on a word boundary or crosses memory region\n"));
971
972	offRegion /= 4;
973	*pu32Data = pRegion->au32Data[offRegion];
974	}
975	else /* No region, default value 0. */
976	*pu32Data = 0;
977
978	/* Memory access is always 32bit big. */
979	pThis->u32DiagMemAddr += sizeof(uint32_t);
980	}
981
982	/**
983	* Handles a write to the diagnostic memory address register.
984	*
985	* @returns nothing.
986	* @param pThis Pointer to the LsiLogic device state.
987	* @param u32Addr Address to write.
988	*/
989	static void lsilogicR3DiagRegAddressWrite(PLSILOGICSCSI pThis, uint32_t u32Addr)
990	{
991	pThis->u32DiagMemAddr = u32Addr & ~UINT32_C(0x3); /* 32bit alignment. */
992	}
993
994	/**
995	* Handles a read from the diagnostic memory address register.
996	*
997	* @returns nothing.
998	* @param pThis Pointer to the LsiLogic device state.
999	* @param pu32Addr Where to store the current address.
1000	*/
1001	static void lsilogicR3DiagRegAddressRead(PLSILOGICSCSI pThis, uint32_t *pu32Addr)
1002	{
1003	*pu32Addr = pThis->u32DiagMemAddr;
1004	}
1005
1006	/**
1007	* Processes a given Request from the guest
1008	*
1009	* @returns VBox status code.
1010	* @param pThis Pointer to the LsiLogic device state.
1011	* @param pMessageHdr Pointer to the message header of the request.
1012	* @param pReply Pointer to the reply.
1013	*/
1014	static int lsilogicR3ProcessMessageRequest(PLSILOGICSCSI pThis, PMptMessageHdr pMessageHdr, PMptReplyUnion pReply)
1015	{
1016	int rc = VINF_SUCCESS;
1017	bool fForceReplyPostFifo = false;
1018
1019	# ifdef LOG_ENABLED
1020	if (pMessageHdr->u8Function < RT_ELEMENTS(g_apszMPTFunctionNames))
1021	Log(("Message request function: %s\n", g_apszMPTFunctionNames[pMessageHdr->u8Function]));
1022	else
1023	Log(("Message request function: <unknown>\n"));
1024	# endif
1025
1026	memset(pReply, 0, sizeof(MptReplyUnion));
1027
1028	switch (pMessageHdr->u8Function)
1029	{
1030	case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
1031	{
1032	PMptSCSITaskManagementRequest pTaskMgmtReq = (PMptSCSITaskManagementRequest)pMessageHdr;
1033
1034	LogFlow(("u8TaskType=%u\n", pTaskMgmtReq->u8TaskType));
1035	LogFlow(("u32TaskMessageContext=%#x\n", pTaskMgmtReq->u32TaskMessageContext));
1036
1037	pReply->SCSITaskManagement.u8MessageLength = 6; /* 6 32bit dwords. */
1038	pReply->SCSITaskManagement.u8TaskType = pTaskMgmtReq->u8TaskType;
1039	pReply->SCSITaskManagement.u32TerminationCount = 0;
1040	fForceReplyPostFifo = true;
1041	break;
1042	}
1043	case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
1044	{
1045	/*
1046	* This request sets the I/O controller to the
1047	* operational state.
1048	*/
1049	PMptIOCInitRequest pIOCInitReq = (PMptIOCInitRequest)pMessageHdr;
1050
1051	/* Update configuration values. */
1052	pThis->enmWhoInit = (LSILOGICWHOINIT)pIOCInitReq->u8WhoInit;
1053	pThis->cbReplyFrame = pIOCInitReq->u16ReplyFrameSize;
1054	pThis->cMaxBuses = pIOCInitReq->u8MaxBuses;
1055	pThis->cMaxDevices = pIOCInitReq->u8MaxDevices;
1056	pThis->u32HostMFAHighAddr = pIOCInitReq->u32HostMfaHighAddr;
1057	pThis->u32SenseBufferHighAddr = pIOCInitReq->u32SenseBufferHighAddr;
1058
1059	if (pThis->enmState == LSILOGICSTATE_READY)
1060	{
1061	pThis->enmState = LSILOGICSTATE_OPERATIONAL;
1062	}
1063
1064	/* Return reply. */
1065	pReply->IOCInit.u8MessageLength = 5;
1066	pReply->IOCInit.u8WhoInit = pThis->enmWhoInit;
1067	pReply->IOCInit.u8MaxDevices = pThis->cMaxDevices;
1068	pReply->IOCInit.u8MaxBuses = pThis->cMaxBuses;
1069	break;
1070	}
1071	case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
1072	{
1073	pReply->IOCFacts.u8MessageLength = 15; /* 15 32bit dwords. */
1074
1075	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1076	{
1077	pReply->IOCFacts.u16MessageVersion = 0x0102; /* Version from the specification. */
1078	pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1079	}
1080	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1081	{
1082	pReply->IOCFacts.u16MessageVersion = 0x0105; /* Version from the specification. */
1083	pReply->IOCFacts.u8NumberOfPorts = pThis->cPorts;
1084	}
1085	else
1086	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1087
1088	pReply->IOCFacts.u8IOCNumber = 0; /* PCI function number. */
1089	pReply->IOCFacts.u16IOCExceptions = 0;
1090	pReply->IOCFacts.u8MaxChainDepth = LSILOGICSCSI_MAXIMUM_CHAIN_DEPTH;
1091	pReply->IOCFacts.u8WhoInit = pThis->enmWhoInit;
1092	pReply->IOCFacts.u8BlockSize = 12; /* Block size in 32bit dwords. This is the largest request we can get (SCSI I/O). */
1093	pReply->IOCFacts.u8Flags = 0; /* Bit 0 is set if the guest must upload the FW prior to using the controller. Obviously not needed here. */
1094	pReply->IOCFacts.u16ReplyQueueDepth = pThis->cReplyQueueEntries - 1; /* One entry is always free. */
1095	pReply->IOCFacts.u16RequestFrameSize = 128; /* @todo Figure out where it is needed. */
1096	pReply->IOCFacts.u32CurrentHostMFAHighAddr = pThis->u32HostMFAHighAddr;
1097	pReply->IOCFacts.u16GlobalCredits = pThis->cRequestQueueEntries - 1; /* One entry is always free. */
1098
1099	pReply->IOCFacts.u8EventState = 0; /* Event notifications not enabled. */
1100	pReply->IOCFacts.u32CurrentSenseBufferHighAddr = pThis->u32SenseBufferHighAddr;
1101	pReply->IOCFacts.u16CurReplyFrameSize = pThis->cbReplyFrame;
1102	pReply->IOCFacts.u8MaxDevices = pThis->cMaxDevices;
1103	pReply->IOCFacts.u8MaxBuses = pThis->cMaxBuses;
1104
1105	/* Check for a valid firmware image in the IOC memory which was downlaoded by tzhe guest earlier. */
1106	PLSILOGICMEMREGN pRegion = lsilogicR3MemRegionFindByAddr(pThis, LSILOGIC_FWIMGHDR_LOAD_ADDRESS);
1107
1108	if (pRegion)
1109	{
1110	uint32_t offImgHdr = (LSILOGIC_FWIMGHDR_LOAD_ADDRESS - pRegion->u32AddrStart) / 4;
1111	PFwImageHdr pFwImgHdr = (PFwImageHdr)&pRegion->au32Data[offImgHdr];
1112
1113	/* Check for the signature. */
1114	/** @todo: Checksum validation. */
1115	if ( pFwImgHdr->u32Signature1 == LSILOGIC_FWIMGHDR_SIGNATURE1
1116	&& pFwImgHdr->u32Signature2 == LSILOGIC_FWIMGHDR_SIGNATURE2
1117	&& pFwImgHdr->u32Signature3 == LSILOGIC_FWIMGHDR_SIGNATURE3)
1118	{
1119	LogFlowFunc(("IOC Facts: Found valid firmware image header in memory, using version (%#x), size (%d) and product ID (%#x) from there\n",
1120	pFwImgHdr->u32FwVersion, pFwImgHdr->u32ImageSize, pFwImgHdr->u16ProductId));
1121
1122	pReply->IOCFacts.u16ProductID = pFwImgHdr->u16ProductId;
1123	pReply->IOCFacts.u32FwImageSize = pFwImgHdr->u32ImageSize;
1124	pReply->IOCFacts.u32FWVersion = pFwImgHdr->u32FwVersion;
1125	}
1126	}
1127	else
1128	{
1129	pReply->IOCFacts.u16ProductID = 0xcafe; /* Our own product ID :) */
1130	pReply->IOCFacts.u32FwImageSize = 0; /* No image needed. */
1131	pReply->IOCFacts.u32FWVersion = 0;
1132	}
1133	break;
1134	}
1135	case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
1136	{
1137	PMptPortFactsRequest pPortFactsReq = (PMptPortFactsRequest)pMessageHdr;
1138
1139	pReply->PortFacts.u8MessageLength = 10;
1140	pReply->PortFacts.u8PortNumber = pPortFactsReq->u8PortNumber;
1141
1142	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
1143	{
1144	/* This controller only supports one bus with bus number 0. */
1145	if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1146	{
1147	pReply->PortFacts.u8PortType = 0; /* Not existant. */
1148	}
1149	else
1150	{
1151	pReply->PortFacts.u8PortType = 0x01; /* SCSI Port. */
1152	pReply->PortFacts.u16MaxDevices = LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
1153	pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) \| RT_BIT(0); /* SCSI initiator and LUN supported. */
1154	pReply->PortFacts.u16PortSCSIID = 7; /* Default */
1155	pReply->PortFacts.u16MaxPersistentIDs = 0;
1156	pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1157	pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1158	}
1159	}
1160	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
1161	{
1162	if (pPortFactsReq->u8PortNumber >= pThis->cPorts)
1163	{
1164	pReply->PortFacts.u8PortType = 0; /* Not existant. */
1165	}
1166	else
1167	{
1168	pReply->PortFacts.u8PortType = 0x30; /* SAS Port. */
1169	pReply->PortFacts.u16MaxDevices = pThis->cPorts;
1170	pReply->PortFacts.u16ProtocolFlags = RT_BIT(3) \| RT_BIT(0); /* SCSI initiator and LUN supported. */
1171	pReply->PortFacts.u16PortSCSIID = pThis->cPorts;
1172	pReply->PortFacts.u16MaxPersistentIDs = 0;
1173	pReply->PortFacts.u16MaxPostedCmdBuffers = 0; /* Only applies for target mode which we dont support. */
1174	pReply->PortFacts.u16MaxLANBuckets = 0; /* Only for the LAN controller. */
1175	}
1176	}
1177	else
1178	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
1179	break;
1180	}
1181	case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
1182	{
1183	/*
1184	* The port enable request notifies the IOC to make the port available and perform
1185	* appropriate discovery on the associated link.
1186	*/
1187	PMptPortEnableRequest pPortEnableReq = (PMptPortEnableRequest)pMessageHdr;
1188
1189	pReply->PortEnable.u8MessageLength = 5;
1190	pReply->PortEnable.u8PortNumber = pPortEnableReq->u8PortNumber;
1191	break;
1192	}
1193	case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
1194	{
1195	PMptEventNotificationRequest pEventNotificationReq = (PMptEventNotificationRequest)pMessageHdr;
1196
1197	if (pEventNotificationReq->u8Switch)
1198	pThis->fEventNotificationEnabled = true;
1199	else
1200	pThis->fEventNotificationEnabled = false;
1201
1202	pReply->EventNotification.u16EventDataLength = 1; /* 1 32bit D-Word. */
1203	pReply->EventNotification.u8MessageLength = 8;
1204	pReply->EventNotification.u8MessageFlags = (1 << 7);
1205	pReply->EventNotification.u8AckRequired = 0;
1206	pReply->EventNotification.u32Event = MPT_EVENT_EVENT_CHANGE;
1207	pReply->EventNotification.u32EventContext = 0;
1208	pReply->EventNotification.u32EventData = pThis->fEventNotificationEnabled ? 1 : 0;
1209
1210	break;
1211	}
1212	case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
1213	{
1214	AssertMsgFailed(("todo"));
1215	break;
1216	}
1217	case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
1218	{
1219	PMptConfigurationRequest pConfigurationReq = (PMptConfigurationRequest)pMessageHdr;
1220
1221	rc = lsilogicR3ProcessConfigurationRequest(pThis, pConfigurationReq, &pReply->Configuration);
1222	AssertRC(rc);
1223	break;
1224	}
1225	case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
1226	{
1227	PMptFWUploadRequest pFWUploadReq = (PMptFWUploadRequest)pMessageHdr;
1228
1229	pReply->FWUpload.u8ImageType = pFWUploadReq->u8ImageType;
1230	pReply->FWUpload.u8MessageLength = 6;
1231	pReply->FWUpload.u32ActualImageSize = 0;
1232	break;
1233	}
1234	case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
1235	{
1236	//PMptFWDownloadRequest pFWDownloadReq = (PMptFWDownloadRequest)pMessageHdr;
1237
1238	pReply->FWDownload.u8MessageLength = 5;
1239	LogFlowFunc(("FW Download request issued\n"));
1240	break;
1241	}
1242	case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST: /* Should be handled already. */
1243	default:
1244	AssertMsgFailed(("Invalid request function %#x\n", pMessageHdr->u8Function));
1245	}
1246
1247	/* Copy common bits from request message frame to reply. */
1248	pReply->Header.u8Function = pMessageHdr->u8Function;
1249	pReply->Header.u32MessageContext = pMessageHdr->u32MessageContext;
1250
1251	lsilogicFinishAddressReply(pThis, pReply, fForceReplyPostFifo);
1252	return rc;
1253	}
1254
1255	#endif /* IN_RING3 */
1256
1257	/**
1258	* Writes a value to a register at a given offset.
1259	*
1260	* @returns VBox status code.
1261	* @param pThis Pointer to the LsiLogic device state.
1262	* @param offReg Offset of the register to write.
1263	* @param u32 The value being written.
1264	*/
1265	static int lsilogicRegisterWrite(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t u32)
1266	{
1267	LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1268	switch (offReg)
1269	{
1270	case LSILOGIC_REG_REPLY_QUEUE:
1271	{
1272	/* Add the entry to the reply free queue. */
1273	ASMAtomicWriteU32(&pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextEntryFreeWrite], u32);
1274	pThis->uReplyFreeQueueNextEntryFreeWrite++;
1275	pThis->uReplyFreeQueueNextEntryFreeWrite %= pThis->cReplyQueueEntries;
1276	break;
1277	}
1278	case LSILOGIC_REG_REQUEST_QUEUE:
1279	{
1280	uint32_t uNextWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
1281
1282	ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[uNextWrite], u32);
1283
1284	/*
1285	* Don't update the value in place. It can happen that we get preempted
1286	* after the increment but before the modulo.
1287	* Another EMT will read the wrong value when processing the queues
1288	* and hang in an endless loop creating thousands of requests.
1289	*/
1290	uNextWrite++;
1291	uNextWrite %= pThis->cRequestQueueEntries;
1292	ASMAtomicWriteU32(&pThis->uRequestQueueNextEntryFreeWrite, uNextWrite);
1293
1294	/* Send notification to R3 if there is not one sent already. Do this
1295	* only if the worker thread is not sleeping or might go sleeping. */
1296	if (!ASMAtomicXchgBool(&pThis->fNotificationSent, true))
1297	{
1298	if (ASMAtomicReadBool(&pThis->fWrkThreadSleeping))
1299	{
1300	#ifdef IN_RC
1301	PPDMQUEUEITEMCORE pNotificationItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
1302	AssertPtr(pNotificationItem);
1303	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), pNotificationItem);
1304	#else
1305	LogFlowFunc(("Signal event semaphore\n"));
1306	int rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
1307	AssertRC(rc);
1308	#endif
1309	}
1310	}
1311	break;
1312	}
1313	case LSILOGIC_REG_DOORBELL:
1314	{
1315	/*
1316	* When the guest writes to this register a real device would set the
1317	* doorbell status bit in the interrupt status register to indicate that the IOP
1318	* has still to process the message.
1319	* The guest needs to wait with posting new messages here until the bit is cleared.
1320	* Because the guest is not continuing execution while we are here we can skip this.
1321	*/
1322	if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_NOT_IN_USE)
1323	{
1324	uint32_t uFunction = LSILOGIC_REG_DOORBELL_GET_FUNCTION(u32);
1325
1326	switch (uFunction)
1327	{
1328	case LSILOGIC_DOORBELL_FUNCTION_IO_UNIT_RESET:
1329	case LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET:
1330	{
1331	/*
1332	* The I/O unit reset does much more on real hardware like
1333	* reloading the firmware, nothing we need to do here,
1334	* so this is like the IOC message unit reset.
1335	*/
1336	pThis->enmState = LSILOGICSTATE_RESET;
1337
1338	/* Reset interrupt status. */
1339	pThis->uInterruptStatus = 0;
1340	lsilogicUpdateInterrupt(pThis);
1341
1342	/* Reset the queues. */
1343	pThis->uReplyFreeQueueNextEntryFreeWrite = 0;
1344	pThis->uReplyFreeQueueNextAddressRead = 0;
1345	pThis->uReplyPostQueueNextEntryFreeWrite = 0;
1346	pThis->uReplyPostQueueNextAddressRead = 0;
1347	pThis->uRequestQueueNextEntryFreeWrite = 0;
1348	pThis->uRequestQueueNextAddressRead = 0;
1349
1350	/* Only the IOC message unit reset transisionts to the ready state. */
1351	if (uFunction == LSILOGIC_DOORBELL_FUNCTION_IOC_MSG_UNIT_RESET)
1352	pThis->enmState = LSILOGICSTATE_READY;
1353	break;
1354	}
1355	case LSILOGIC_DOORBELL_FUNCTION_HANDSHAKE:
1356	{
1357	pThis->cMessage = LSILOGIC_REG_DOORBELL_GET_SIZE(u32);
1358	pThis->iMessage = 0;
1359	AssertMsg(pThis->cMessage <= RT_ELEMENTS(pThis->aMessage),
1360	("Message doesn't fit into the buffer, cMessage=%u", pThis->cMessage));
1361	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
1362	/* Update the interrupt status to notify the guest that a doorbell function was started. */
1363	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1364	break;
1365	}
1366	case LSILOGIC_DOORBELL_FUNCTION_REPLY_FRAME_REMOVAL:
1367	{
1368	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW;
1369	/* Update the interrupt status to notify the guest that a doorbell function was started. */
1370	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1371	break;
1372	}
1373	default:
1374	AssertMsgFailed(("Unknown function %u to perform\n", uFunction));
1375	}
1376	}
1377	else if (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1378	{
1379	/*
1380	* We are already performing a doorbell function.
1381	* Get the remaining parameters.
1382	*/
1383	AssertMsg(pThis->iMessage < RT_ELEMENTS(pThis->aMessage), ("Message is too big to fit into the buffer\n"));
1384	/*
1385	* If the last byte of the message is written, force a switch to R3 because some requests might force
1386	* a reply through the FIFO which cannot be handled in GC or R0.
1387	*/
1388	#ifndef IN_RING3
1389	if (pThis->iMessage == pThis->cMessage - 1)
1390	return VINF_IOM_R3_MMIO_WRITE;
1391	#endif
1392	pThis->aMessage[pThis->iMessage++] = u32;
1393	#ifdef IN_RING3
1394	if (pThis->iMessage == pThis->cMessage)
1395	{
1396	int rc = lsilogicR3ProcessMessageRequest(pThis, (PMptMessageHdr)pThis->aMessage, &pThis->ReplyBuffer);
1397	AssertRC(rc);
1398	}
1399	#endif
1400	}
1401	break;
1402	}
1403	case LSILOGIC_REG_HOST_INTR_STATUS:
1404	{
1405	/*
1406	* Clear the bits the guest wants except the system doorbell interrupt and the IO controller
1407	* status bit.
1408	* The former bit is always cleared no matter what the guest writes to the register and
1409	* the latter one is read only.
1410	*/
1411	ASMAtomicAndU32(&pThis->uInterruptStatus, ~LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1412
1413	/*
1414	* Check if there is still a doorbell function in progress. Set the
1415	* system doorbell interrupt bit again if it is.
1416	* We do not use lsilogicSetInterrupt here because the interrupt status
1417	* is updated afterwards anyway.
1418	*/
1419	if ( (pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1420	&& (pThis->cMessage == pThis->iMessage))
1421	{
1422	if (pThis->uNextReplyEntryRead == pThis->cReplySize)
1423	{
1424	/* Reply finished. Reset doorbell in progress status. */
1425	Log(("%s: Doorbell function finished\n", __FUNCTION__));
1426	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1427	}
1428	ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1429	}
1430	else if ( pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_NOT_IN_USE
1431	&& pThis->enmDoorbellState != LSILOGICDOORBELLSTATE_FN_HANDSHAKE)
1432	{
1433	/* Reply frame removal, check whether the reply free queue is empty. */
1434	if ( pThis->uReplyFreeQueueNextAddressRead == pThis->uReplyFreeQueueNextEntryFreeWrite
1435	&& pThis->enmDoorbellState == LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW)
1436	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
1437	ASMAtomicOrU32(&pThis->uInterruptStatus, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1438	}
1439
1440	lsilogicUpdateInterrupt(pThis);
1441	break;
1442	}
1443	case LSILOGIC_REG_HOST_INTR_MASK:
1444	{
1445	ASMAtomicWriteU32(&pThis->uInterruptMask, u32 & LSILOGIC_REG_HOST_INTR_MASK_W_MASK);
1446	lsilogicUpdateInterrupt(pThis);
1447	break;
1448	}
1449	case LSILOGIC_REG_WRITE_SEQUENCE:
1450	{
1451	if (pThis->fDiagnosticEnabled)
1452	{
1453	/* Any value will cause a reset and disabling access. */
1454	pThis->fDiagnosticEnabled = false;
1455	pThis->iDiagnosticAccess = 0;
1456	pThis->fDiagRegsEnabled = false;
1457	}
1458	else if ((u32 & 0xf) == g_lsilogicDiagnosticAccess[pThis->iDiagnosticAccess])
1459	{
1460	pThis->iDiagnosticAccess++;
1461	if (pThis->iDiagnosticAccess == RT_ELEMENTS(g_lsilogicDiagnosticAccess))
1462	{
1463	/*
1464	* Key sequence successfully written. Enable access to diagnostic
1465	* memory and register.
1466	*/
1467	pThis->fDiagnosticEnabled = true;
1468	}
1469	}
1470	else
1471	{
1472	/* Wrong value written - reset to beginning. */
1473	pThis->iDiagnosticAccess = 0;
1474	}
1475	break;
1476	}
1477	case LSILOGIC_REG_HOST_DIAGNOSTIC:
1478	{
1479	if (pThis->fDiagnosticEnabled)
1480	{
1481	#ifndef IN_RING3
1482	return VINF_IOM_R3_MMIO_WRITE;
1483	#else
1484	if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_RESET_ADAPTER)
1485	lsilogicR3HardReset(pThis);
1486	else if (u32 & LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE)
1487	pThis->fDiagRegsEnabled = true;
1488	#endif
1489	}
1490	break;
1491	}
1492	case LSILOGIC_REG_DIAG_RW_DATA:
1493	{
1494	if (pThis->fDiagRegsEnabled)
1495	{
1496	#ifndef IN_RING3
1497	return VINF_IOM_R3_MMIO_WRITE;
1498	#else
1499	lsilogicR3DiagRegDataWrite(pThis, u32);
1500	#endif
1501	}
1502	break;
1503	}
1504	case LSILOGIC_REG_DIAG_RW_ADDRESS:
1505	{
1506	if (pThis->fDiagRegsEnabled)
1507	{
1508	#ifndef IN_RING3
1509	return VINF_IOM_R3_MMIO_WRITE;
1510	#else
1511	lsilogicR3DiagRegAddressWrite(pThis, u32);
1512	#endif
1513	}
1514	break;
1515	}
1516	default: /* Ignore. */
1517	{
1518	break;
1519	}
1520	}
1521	return VINF_SUCCESS;
1522	}
1523
1524	/**
1525	* Reads the content of a register at a given offset.
1526	*
1527	* @returns VBox status code.
1528	* @param pThis Pointer to the LsiLogic device state.
1529	* @param offReg Offset of the register to read.
1530	* @param pu32 Where to store the content of the register.
1531	*/
1532	static int lsilogicRegisterRead(PLSILOGICSCSI pThis, uint32_t offReg, uint32_t *pu32)
1533	{
1534	int rc = VINF_SUCCESS;
1535	uint32_t u32 = 0;
1536	Assert(!(offReg & 3));
1537
1538	/* Align to a 4 byte offset. */
1539	switch (offReg)
1540	{
1541	case LSILOGIC_REG_REPLY_QUEUE:
1542	{
1543	rc = PDMCritSectEnter(&pThis->ReplyPostQueueCritSect, VINF_IOM_R3_MMIO_READ);
1544	if (rc != VINF_SUCCESS)
1545	break;
1546
1547	uint32_t idxReplyPostQueueWrite = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextEntryFreeWrite);
1548	uint32_t idxReplyPostQueueRead = ASMAtomicUoReadU32(&pThis->uReplyPostQueueNextAddressRead);
1549
1550	if (idxReplyPostQueueWrite != idxReplyPostQueueRead)
1551	{
1552	u32 = pThis->CTX_SUFF(pReplyPostQueueBase)[idxReplyPostQueueRead];
1553	idxReplyPostQueueRead++;
1554	idxReplyPostQueueRead %= pThis->cReplyQueueEntries;
1555	ASMAtomicWriteU32(&pThis->uReplyPostQueueNextAddressRead, idxReplyPostQueueRead);
1556	}
1557	else
1558	{
1559	/* The reply post queue is empty. Reset interrupt. */
1560	u32 = UINT32_C(0xffffffff);
1561	lsilogicClearInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_REPLY_INTR);
1562	}
1563	PDMCritSectLeave(&pThis->ReplyPostQueueCritSect);
1564
1565	Log(("%s: Returning address %#x\n", __FUNCTION__, u32));
1566	break;
1567	}
1568	case LSILOGIC_REG_DOORBELL:
1569	{
1570	u32 = LSILOGIC_REG_DOORBELL_SET_STATE(pThis->enmState);
1571	u32 \|= LSILOGIC_REG_DOORBELL_SET_USED(pThis->enmDoorbellState);
1572	u32 \|= LSILOGIC_REG_DOORBELL_SET_WHOINIT(pThis->enmWhoInit);
1573	/*
1574	* If there is a doorbell function in progress we pass the return value
1575	* instead of the status code. We transfer 16bit of the reply
1576	* during one read.
1577	*/
1578	switch (pThis->enmDoorbellState)
1579	{
1580	case LSILOGICDOORBELLSTATE_NOT_IN_USE:
1581	/* We return the status code of the I/O controller. */
1582	u32 \|= pThis->u16IOCFaultCode;
1583	break;
1584	case LSILOGICDOORBELLSTATE_FN_HANDSHAKE:
1585	/* Return next 16bit value. */
1586	u32 \|= pThis->ReplyBuffer.au16Reply[pThis->uNextReplyEntryRead++];
1587	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1588	break;
1589	case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_LOW:
1590	{
1591	uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1592
1593	u32 \|= cReplyFrames & UINT32_C(0xffff);
1594	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH;
1595	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1596	break;
1597	}
1598	case LSILOGICDOORBELLSTATE_RFR_FRAME_COUNT_HIGH:
1599	{
1600	uint32_t cReplyFrames = lsilogicReplyFreeQueueGetFrameCount(pThis);
1601
1602	u32 \|= cReplyFrames >> 16;
1603	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1604	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1605	break;
1606	}
1607	case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW:
1608	if (pThis->uReplyFreeQueueNextEntryFreeWrite != pThis->uReplyFreeQueueNextAddressRead)
1609	{
1610	u32 \|= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] & UINT32_C(0xffff);
1611	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH;
1612	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1613	}
1614	break;
1615	case LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_HIGH:
1616	u32 \|= pThis->CTX_SUFF(pReplyFreeQueueBase)[pThis->uReplyFreeQueueNextAddressRead] >> 16;
1617	pThis->uReplyFreeQueueNextAddressRead++;
1618	pThis->uReplyFreeQueueNextAddressRead %= pThis->cReplyQueueEntries;
1619	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_RFR_NEXT_FRAME_LOW;
1620	lsilogicSetInterrupt(pThis, LSILOGIC_REG_HOST_INTR_STATUS_SYSTEM_DOORBELL);
1621	break;
1622	default:
1623	AssertMsgFailed(("Invalid doorbell state %d\n", pThis->enmDoorbellState));
1624	}
1625
1626	break;
1627	}
1628	case LSILOGIC_REG_HOST_INTR_STATUS:
1629	{
1630	u32 = ASMAtomicReadU32(&pThis->uInterruptStatus);
1631	break;
1632	}
1633	case LSILOGIC_REG_HOST_INTR_MASK:
1634	{
1635	u32 = ASMAtomicReadU32(&pThis->uInterruptMask);
1636	break;
1637	}
1638	case LSILOGIC_REG_HOST_DIAGNOSTIC:
1639	{
1640	if (pThis->fDiagnosticEnabled)
1641	u32 \|= LSILOGIC_REG_HOST_DIAGNOSTIC_DRWE;
1642	if (pThis->fDiagRegsEnabled)
1643	u32 \|= LSILOGIC_REG_HOST_DIAGNOSTIC_DIAG_RW_ENABLE;
1644	break;
1645	}
1646	case LSILOGIC_REG_DIAG_RW_DATA:
1647	{
1648	if (pThis->fDiagRegsEnabled)
1649	{
1650	#ifndef IN_RING3
1651	return VINF_IOM_R3_MMIO_READ;
1652	#else
1653	lsilogicR3DiagRegDataRead(pThis, &u32);
1654	#endif
1655	}
1656	}
1657	case LSILOGIC_REG_DIAG_RW_ADDRESS:
1658	{
1659	if (pThis->fDiagRegsEnabled)
1660	{
1661	#ifndef IN_RING3
1662	return VINF_IOM_R3_MMIO_READ;
1663	#else
1664	lsilogicR3DiagRegAddressRead(pThis, &u32);
1665	#endif
1666	}
1667	}
1668	case LSILOGIC_REG_TEST_BASE_ADDRESS: /* The spec doesn't say anything about these registers, so we just ignore them */
1669	default: /* Ignore. */
1670	{
1671	/** @todo LSILOGIC_REG_DIAG_* should return all F's when accessed by MMIO. We
1672	* return 0. Likely to apply to undefined offsets as well. */
1673	break;
1674	}
1675	}
1676
1677	*pu32 = u32;
1678	LogFlowFunc(("pThis=%#p offReg=%#x u32=%#x\n", pThis, offReg, u32));
1679	return rc;
1680	}
1681
1682	/**
1683	* @callback_method_impl{FNIOMIOPORTOUT}
1684	*/
1685	PDMBOTHCBDECL(int) lsilogicIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1686	{
1687	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1688	uint32_t offReg = Port - pThis->IOPortBase;
1689	int rc;
1690
1691	if (!(offReg & 3))
1692	{
1693	rc = lsilogicRegisterWrite(pThis, offReg, u32);
1694	if (rc == VINF_IOM_R3_MMIO_WRITE)
1695	rc = VINF_IOM_R3_IOPORT_WRITE;
1696	}
1697	else
1698	{
1699	Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1700	rc = VINF_SUCCESS;
1701	}
1702
1703	return rc;
1704	}
1705
1706	/**
1707	* @callback_method_impl{FNIOMIOPORTIN}
1708	*/
1709	PDMBOTHCBDECL(int) lsilogicIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
1710	{
1711	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1712	uint32_t offReg = Port - pThis->IOPortBase;
1713
1714	int rc = lsilogicRegisterRead(pThis, offReg & ~(uint32_t)3, pu32);
1715	if (rc == VINF_IOM_R3_MMIO_READ)
1716	rc = VINF_IOM_R3_IOPORT_READ;
1717
1718	return rc;
1719	}
1720
1721	/**
1722	* @callback_method_impl{FNIOMMMIOWRITE}
1723	*/
1724	PDMBOTHCBDECL(int) lsilogicMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
1725	{
1726	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1727	uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1728	uint32_t u32;
1729	int rc;
1730
1731	/* See comments in lsilogicR3Map regarding size and alignment. */
1732	if (cb == 4)
1733	u32 = (uint32_t const )pv;
1734	else
1735	{
1736	if (cb > 4)
1737	u32 = (uint32_t const )pv;
1738	else if (cb >= 2)
1739	u32 = (uint16_t const )pv;
1740	else
1741	u32 = (uint8_t const )pv;
1742	Log(("lsilogicMMIOWrite: Non-DWORD write access - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1743	}
1744
1745	if (!(offReg & 3))
1746	rc = lsilogicRegisterWrite(pThis, offReg, u32);
1747	else
1748	{
1749	Log(("lsilogicIOPortWrite: Ignoring misaligned write - offReg=%#x u32=%#x cb=%#x\n", offReg, u32, cb));
1750	rc = VINF_SUCCESS;
1751	}
1752	return rc;
1753	}
1754
1755	/**
1756	* @callback_method_impl{FNIOMMMIOREAD}
1757	*/
1758	PDMBOTHCBDECL(int) lsilogicMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
1759	{
1760	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1761	uint32_t offReg = GCPhysAddr - pThis->GCPhysMMIOBase;
1762	Assert(!(offReg & 3)); Assert(cb == 4);
1763
1764	return lsilogicRegisterRead(pThis, offReg, (uint32_t *)pv);
1765	}
1766
1767	PDMBOTHCBDECL(int) lsilogicDiagnosticWrite(PPDMDEVINS pDevIns, void *pvUser,
1768	RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
1769	{
1770	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1771
1772	LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1773
1774	return VINF_SUCCESS;
1775	}
1776
1777	PDMBOTHCBDECL(int) lsilogicDiagnosticRead(PPDMDEVINS pDevIns, void *pvUser,
1778	RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
1779	{
1780	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
1781
1782	LogFlowFunc(("pThis=%#p GCPhysAddr=%RGp pv=%#p{%.*Rhxs} cb=%u\n", pThis, GCPhysAddr, pv, cb, pv, cb));
1783
1784	return VINF_SUCCESS;
1785	}
1786
1787	#ifdef IN_RING3
1788
1789	# ifdef LOG_ENABLED
1790	/**
1791	* Dump an SG entry.
1792	*
1793	* @returns nothing.
1794	* @param pSGEntry Pointer to the SG entry to dump
1795	*/
1796	static void lsilogicDumpSGEntry(PMptSGEntryUnion pSGEntry)
1797	{
1798	if (LogIsEnabled())
1799	{
1800	switch (pSGEntry->Simple32.u2ElementType)
1801	{
1802	case MPTSGENTRYTYPE_SIMPLE:
1803	{
1804	Log(("%s: Dumping info for SIMPLE SG entry:\n", __FUNCTION__));
1805	Log(("%s: u24Length=%u\n", __FUNCTION__, pSGEntry->Simple32.u24Length));
1806	Log(("%s: fEndOfList=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfList));
1807	Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.f64BitAddress));
1808	Log(("%s: fBufferContainsData=%d\n", __FUNCTION__, pSGEntry->Simple32.fBufferContainsData));
1809	Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Simple32.fLocalAddress));
1810	Log(("%s: fEndOfBuffer=%d\n", __FUNCTION__, pSGEntry->Simple32.fEndOfBuffer));
1811	Log(("%s: fLastElement=%d\n", __FUNCTION__, pSGEntry->Simple32.fLastElement));
1812	Log(("%s: u32DataBufferAddressLow=%u\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1813	if (pSGEntry->Simple32.f64BitAddress)
1814	{
1815	Log(("%s: u32DataBufferAddressHigh=%u\n", __FUNCTION__, pSGEntry->Simple64.u32DataBufferAddressHigh));
1816	Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__,
1817	((uint64_t)pSGEntry->Simple64.u32DataBufferAddressHigh << 32)
1818	\| pSGEntry->Simple64.u32DataBufferAddressLow));
1819	}
1820	else
1821	Log(("%s: GCDataBufferAddress=%RGp\n", __FUNCTION__, pSGEntry->Simple32.u32DataBufferAddressLow));
1822
1823	break;
1824	}
1825	case MPTSGENTRYTYPE_CHAIN:
1826	{
1827	Log(("%s: Dumping info for CHAIN SG entry:\n", __FUNCTION__));
1828	Log(("%s: u16Length=%u\n", __FUNCTION__, pSGEntry->Chain.u16Length));
1829	Log(("%s: u8NExtChainOffset=%d\n", __FUNCTION__, pSGEntry->Chain.u8NextChainOffset));
1830	Log(("%s: f64BitAddress=%d\n", __FUNCTION__, pSGEntry->Chain.f64BitAddress));
1831	Log(("%s: fLocalAddress=%d\n", __FUNCTION__, pSGEntry->Chain.fLocalAddress));
1832	Log(("%s: u32SegmentAddressLow=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1833	Log(("%s: u32SegmentAddressHigh=%u\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressHigh));
1834	if (pSGEntry->Chain.f64BitAddress)
1835	Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__,
1836	((uint64_t)pSGEntry->Chain.u32SegmentAddressHigh << 32) \| pSGEntry->Chain.u32SegmentAddressLow));
1837	else
1838	Log(("%s: GCSegmentAddress=%RGp\n", __FUNCTION__, pSGEntry->Chain.u32SegmentAddressLow));
1839	break;
1840	}
1841	}
1842	}
1843	}
1844	# endif /* LOG_ENABLED */
1845
1846	/**
1847	* Walks the guest S/G buffer calling the given copy worker for every buffer.
1848	*
1849	* @returns nothing.
1850	* @param pDevIns Device instance data.
1851	* @param pLsiReq LSI request state.
1852	* @param cbCopy How much bytes to copy.
1853	* @param pfnIoBufCopy Copy worker to call.
1854	*/
1855	static void lsilogicSgBufWalker(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq, size_t cbCopy,
1856	PFNLSILOGICIOBUFCOPY pfnIoBufCopy)
1857	{
1858	bool fEndOfList = false;
1859	RTGCPHYS GCPhysSgEntryNext = pLsiReq->GCPhysSgStart;
1860	RTGCPHYS GCPhysSegmentStart = pLsiReq->GCPhysSgStart;
1861	uint32_t cChainOffsetNext = pLsiReq->cChainOffset;
1862	uint8_t pbBuf = (uint8_t )pLsiReq->SegIoBuf.pvSeg;
1863
1864	/* Go through the list until we reach the end. */
1865	while ( !fEndOfList
1866	&& cbCopy)
1867	{
1868	bool fEndOfSegment = false;
1869
1870	while ( !fEndOfSegment
1871	&& cbCopy)
1872	{
1873	MptSGEntryUnion SGEntry;
1874
1875	Log(("%s: Reading SG entry from %RGp\n", __FUNCTION__, GCPhysSgEntryNext));
1876
1877	/* Read the entry. */
1878	PDMDevHlpPhysRead(pDevIns, GCPhysSgEntryNext, &SGEntry, sizeof(MptSGEntryUnion));
1879
1880	# ifdef LOG_ENABLED
1881	lsilogicDumpSGEntry(&SGEntry);
1882	# endif
1883
1884	AssertMsg(SGEntry.Simple32.u2ElementType == MPTSGENTRYTYPE_SIMPLE, ("Invalid SG entry type\n"));
1885
1886	/* Check if this is a zero element and abort. */
1887	if ( !SGEntry.Simple32.u24Length
1888	&& SGEntry.Simple32.fEndOfList
1889	&& SGEntry.Simple32.fEndOfBuffer)
1890	return;
1891
1892	uint32_t cbCopyThis = SGEntry.Simple32.u24Length;
1893	RTGCPHYS GCPhysAddrDataBuffer = SGEntry.Simple32.u32DataBufferAddressLow;
1894
1895	if (SGEntry.Simple32.f64BitAddress)
1896	{
1897	GCPhysAddrDataBuffer \|= ((uint64_t)SGEntry.Simple64.u32DataBufferAddressHigh) << 32;
1898	GCPhysSgEntryNext += sizeof(MptSGEntrySimple64);
1899	}
1900	else
1901	GCPhysSgEntryNext += sizeof(MptSGEntrySimple32);
1902
1903
1904	pfnIoBufCopy(pDevIns, GCPhysAddrDataBuffer, pbBuf, cbCopyThis);
1905	pbBuf += cbCopyThis;
1906	cbCopy -= cbCopyThis;
1907
1908	/* Check if we reached the end of the list. */
1909	if (SGEntry.Simple32.fEndOfList)
1910	{
1911	/* We finished. */
1912	fEndOfSegment = true;
1913	fEndOfList = true;
1914	}
1915	else if (SGEntry.Simple32.fLastElement)
1916	fEndOfSegment = true;
1917	} /* while (!fEndOfSegment) */
1918
1919	/* Get next chain element. */
1920	if (cChainOffsetNext)
1921	{
1922	MptSGEntryChain SGEntryChain;
1923
1924	PDMDevHlpPhysRead(pDevIns, GCPhysSegmentStart + cChainOffsetNext, &SGEntryChain, sizeof(MptSGEntryChain));
1925
1926	AssertMsg(SGEntryChain.u2ElementType == MPTSGENTRYTYPE_CHAIN, ("Invalid SG entry type\n"));
1927
1928	/* Set the next address now. */
1929	GCPhysSgEntryNext = SGEntryChain.u32SegmentAddressLow;
1930	if (SGEntryChain.f64BitAddress)
1931	GCPhysSgEntryNext \|= ((uint64_t)SGEntryChain.u32SegmentAddressHigh) << 32;
1932
1933	GCPhysSegmentStart = GCPhysSgEntryNext;
1934	cChainOffsetNext = SGEntryChain.u8NextChainOffset * sizeof(uint32_t);
1935	}
1936	} /* while (!fEndOfList) */
1937	}
1938
1939	static DECLCALLBACK(void) lsilogicCopyFromGuest(PPDMDEVINS pDevIns, RTGCPHYS GCPhysIoBuf,
1940	void *pvBuf, size_t cbCopy)
1941	{
1942	PDMDevHlpPhysRead(pDevIns, GCPhysIoBuf, pvBuf, cbCopy);
1943	}
1944
1945	static DECLCALLBACK(void) lsilogicCopyToGuest(PPDMDEVINS pDevIns, RTGCPHYS GCPhysIoBuf,
1946	void *pvBuf, size_t cbCopy)
1947	{
1948	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysIoBuf, pvBuf, cbCopy);
1949	}
1950
1951	/**
1952	* Copy from a guest S/G buffer to the I/O buffer.
1953	*
1954	* @returns nothing.
1955	* @param pDevIns Device instance data.
1956	* @param pLsiReq Request data.
1957	* @param cbCopy How much to copy over.
1958	*/
1959	DECLINLINE(void) lsilogicCopyFromSgBuf(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq, size_t cbCopy)
1960	{
1961	lsilogicSgBufWalker(pDevIns, pLsiReq, cbCopy, lsilogicCopyFromGuest);
1962	}
1963
1964	/**
1965	* Copy from an I/O buffer to the guest S/G buffer.
1966	*
1967	* @returns nothing.
1968	* @param pDevIns Device instance data.
1969	* @param pLsiReq Request data.
1970	* @param cbCopy How much to copy over.
1971	*/
1972	DECLINLINE(void) lsilogicCopyToSgBuf(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq, size_t cbCopy)
1973	{
1974	lsilogicSgBufWalker(pDevIns, pLsiReq, cbCopy, lsilogicCopyToGuest);
1975	}
1976
1977	/**
1978	* Allocates memory for the given request using already allocated memory if possible.
1979	*
1980	* @returns Pointer to the memory or NULL on failure
1981	* @param pLsiReq The request to allocate memory for.
1982	* @param cb The amount of memory to allocate.
1983	*/
1984	static void *lsilogicReqMemAlloc(PLSILOGICREQ pLsiReq, size_t cb)
1985	{
1986	if (pLsiReq->cbAlloc > cb)
1987	pLsiReq->cAllocTooMuch++;
1988	else if (pLsiReq->cbAlloc < cb)
1989	{
1990	if (pLsiReq->cbAlloc)
1991	RTMemPageFree(pLsiReq->pvAlloc, pLsiReq->cbAlloc);
1992
1993	pLsiReq->cbAlloc = RT_ALIGN_Z(cb, _4K);
1994	pLsiReq->pvAlloc = RTMemPageAlloc(pLsiReq->cbAlloc);
1995	pLsiReq->cAllocTooMuch = 0;
1996	if (RT_UNLIKELY(!pLsiReq->pvAlloc))
1997	pLsiReq->cbAlloc = 0;
1998	}
1999
2000	return pLsiReq->pvAlloc;
2001	}
2002
2003	/**
2004	* Frees memory allocated for the given request.
2005	*
2006	* @returns nothing.
2007	* @param pLsiReq The request.
2008	*/
2009	static void lsilogicReqMemFree(PLSILOGICREQ pLsiReq)
2010	{
2011	if (pLsiReq->cAllocTooMuch >= LSILOGIC_MAX_ALLOC_TOO_MUCH)
2012	{
2013	RTMemPageFree(pLsiReq->pvAlloc, pLsiReq->cbAlloc);
2014	pLsiReq->cbAlloc = 0;
2015	pLsiReq->cAllocTooMuch = 0;
2016	}
2017	}
2018
2019	/**
2020	* Allocate I/O memory and copies the guest buffer for writes.
2021	*
2022	* @returns VBox status code.
2023	* @param pDevIns The device instance.
2024	* @param pLsiReq The request state.
2025	* @param cbTransfer Amount of bytes to allocate.
2026	*/
2027	static int lsilogicIoBufAllocate(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq,
2028	size_t cbTransfer)
2029	{
2030	uint8_t uTxDir = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2031
2032	AssertMsg( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE
2033	\|\| uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ
2034	\|\| uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE,
2035	("Allocating I/O memory for a non I/O request is not allowed\n"));
2036
2037	pLsiReq->SegIoBuf.pvSeg = lsilogicReqMemAlloc(pLsiReq, cbTransfer);
2038	if (!pLsiReq->SegIoBuf.pvSeg)
2039	return VERR_NO_MEMORY;
2040
2041	pLsiReq->SegIoBuf.cbSeg = cbTransfer;
2042	if ( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE
2043	\|\| uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2044	lsilogicCopyFromSgBuf(pDevIns, pLsiReq, cbTransfer);
2045
2046	return VINF_SUCCESS;
2047	}
2048
2049	/**
2050	* Frees the I/O memory of the given request and updates the guest buffer if necessary.
2051	*
2052	* @returns nothing.
2053	* @param pDevIns The device instance.
2054	* @param pLsiReq The request state.
2055	* @param fCopyToGuest Flag whether to update the guest buffer if necessary.
2056	* Nothing is copied if false even if the request was a read.
2057	*/
2058	static void lsilogicIoBufFree(PPDMDEVINS pDevIns, PLSILOGICREQ pLsiReq,
2059	bool fCopyToGuest)
2060	{
2061	uint8_t uTxDir = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2062
2063	AssertMsg( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE
2064	\|\| uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ
2065	\|\| uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE,
2066	("Allocating I/O memory for a non I/O request is not allowed\n"));
2067
2068	if ( ( uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ
2069	\|\| uTxDir == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2070	&& fCopyToGuest)
2071	lsilogicCopyToSgBuf(pDevIns, pLsiReq, pLsiReq->SegIoBuf.cbSeg);
2072
2073	lsilogicReqMemFree(pLsiReq);
2074	pLsiReq->SegIoBuf.pvSeg = NULL;
2075	pLsiReq->SegIoBuf.cbSeg = 0;
2076	}
2077
2078	# ifdef LOG_ENABLED
2079	static void lsilogicR3DumpSCSIIORequest(PMptSCSIIORequest pSCSIIORequest)
2080	{
2081	if (LogIsEnabled())
2082	{
2083	Log(("%s: u8TargetID=%d\n", __FUNCTION__, pSCSIIORequest->u8TargetID));
2084	Log(("%s: u8Bus=%d\n", __FUNCTION__, pSCSIIORequest->u8Bus));
2085	Log(("%s: u8ChainOffset=%d\n", __FUNCTION__, pSCSIIORequest->u8ChainOffset));
2086	Log(("%s: u8Function=%d\n", __FUNCTION__, pSCSIIORequest->u8Function));
2087	Log(("%s: u8CDBLength=%d\n", __FUNCTION__, pSCSIIORequest->u8CDBLength));
2088	Log(("%s: u8SenseBufferLength=%d\n", __FUNCTION__, pSCSIIORequest->u8SenseBufferLength));
2089	Log(("%s: u8MessageFlags=%d\n", __FUNCTION__, pSCSIIORequest->u8MessageFlags));
2090	Log(("%s: u32MessageContext=%#x\n", __FUNCTION__, pSCSIIORequest->u32MessageContext));
2091	for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8LUN); i++)
2092	Log(("%s: u8LUN[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8LUN[i]));
2093	Log(("%s: u32Control=%#x\n", __FUNCTION__, pSCSIIORequest->u32Control));
2094	for (unsigned i = 0; i < RT_ELEMENTS(pSCSIIORequest->au8CDB); i++)
2095	Log(("%s: u8CDB[%d]=%d\n", __FUNCTION__, i, pSCSIIORequest->au8CDB[i]));
2096	Log(("%s: u32DataLength=%#x\n", __FUNCTION__, pSCSIIORequest->u32DataLength));
2097	Log(("%s: u32SenseBufferLowAddress=%#x\n", __FUNCTION__, pSCSIIORequest->u32SenseBufferLowAddress));
2098	}
2099	}
2100	# endif
2101
2102	static void lsilogicR3WarningDiskFull(PPDMDEVINS pDevIns)
2103	{
2104	int rc;
2105	LogRel(("LsiLogic#%d: Host disk full\n", pDevIns->iInstance));
2106	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_DISKFULL",
2107	N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
2108	AssertRC(rc);
2109	}
2110
2111	static void lsilogicR3WarningFileTooBig(PPDMDEVINS pDevIns)
2112	{
2113	int rc;
2114	LogRel(("LsiLogic#%d: File too big\n", pDevIns->iInstance));
2115	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_FILETOOBIG",
2116	N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
2117	AssertRC(rc);
2118	}
2119
2120	static void lsilogicR3WarningISCSI(PPDMDEVINS pDevIns)
2121	{
2122	int rc;
2123	LogRel(("LsiLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));
2124	rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_ISCSIDOWN",
2125	N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
2126	AssertRC(rc);
2127	}
2128
2129	static void lsilogicR3WarningUnknown(PPDMDEVINS pDevIns, int rc)
2130	{
2131	int rc2;
2132	LogRel(("LsiLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));
2133	rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND \| VMSETRTERR_FLAGS_NO_WAIT, "DevLsiLogic_UNKNOWN",
2134	N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);
2135	AssertRC(rc2);
2136	}
2137
2138	static void lsilogicR3RedoSetWarning(PLSILOGICSCSI pThis, int rc)
2139	{
2140	if (rc == VERR_DISK_FULL)
2141	lsilogicR3WarningDiskFull(pThis->CTX_SUFF(pDevIns));
2142	else if (rc == VERR_FILE_TOO_BIG)
2143	lsilogicR3WarningFileTooBig(pThis->CTX_SUFF(pDevIns));
2144	else if (rc == VERR_BROKEN_PIPE \|\| rc == VERR_NET_CONNECTION_REFUSED)
2145	{
2146	/* iSCSI connection abort (first error) or failure to reestablish
2147	* connection (second error). Pause VM. On resume we'll retry. */
2148	lsilogicR3WarningISCSI(pThis->CTX_SUFF(pDevIns));
2149	}
2150	else if (rc != VERR_VD_DEK_MISSING)
2151	lsilogicR3WarningUnknown(pThis->CTX_SUFF(pDevIns), rc);
2152	}
2153
2154	/**
2155	* Processes a SCSI I/O request by setting up the request
2156	* and sending it to the underlying SCSI driver.
2157	* Steps needed to complete request are done in the
2158	* callback called by the driver below upon completion of
2159	* the request.
2160	*
2161	* @returns VBox status code.
2162	* @param pThis Pointer to the LsiLogic device state.
2163	* @param pLsiReq Pointer to the task state data.
2164	*/
2165	static int lsilogicR3ProcessSCSIIORequest(PLSILOGICSCSI pThis, PLSILOGICREQ pLsiReq)
2166	{
2167	int rc = VINF_SUCCESS;
2168
2169	# ifdef LOG_ENABLED
2170	lsilogicR3DumpSCSIIORequest(&pLsiReq->GuestRequest.SCSIIO);
2171	# endif
2172
2173	pLsiReq->fBIOS = false;
2174	pLsiReq->GCPhysSgStart = pLsiReq->GCPhysMessageFrameAddr + sizeof(MptSCSIIORequest);
2175	pLsiReq->cChainOffset = pLsiReq->GuestRequest.SCSIIO.u8ChainOffset;
2176	if (pLsiReq->cChainOffset)
2177	pLsiReq->cChainOffset = pLsiReq->cChainOffset * sizeof(uint32_t) - sizeof(MptSCSIIORequest);
2178
2179	if (RT_LIKELY( (pLsiReq->GuestRequest.SCSIIO.u8TargetID < pThis->cDeviceStates)
2180	&& (pLsiReq->GuestRequest.SCSIIO.u8Bus == 0)))
2181	{
2182	PLSILOGICDEVICE pTargetDevice;
2183	pTargetDevice = &pThis->paDeviceStates[pLsiReq->GuestRequest.SCSIIO.u8TargetID];
2184
2185	if (pTargetDevice->pDrvBase)
2186	{
2187
2188	if (pLsiReq->GuestRequest.SCSIIO.u32DataLength)
2189	{
2190
2191	rc = lsilogicIoBufAllocate(pThis->CTX_SUFF(pDevIns), pLsiReq,
2192	pLsiReq->GuestRequest.SCSIIO.u32DataLength);
2193	AssertRC(rc); /** @todo: Insufficient resources error. */
2194	}
2195
2196	/* Setup the SCSI request. */
2197	pLsiReq->pTargetDevice = pTargetDevice;
2198	pLsiReq->PDMScsiRequest.uLogicalUnit = pLsiReq->GuestRequest.SCSIIO.au8LUN[1];
2199
2200	uint8_t uDataDirection = MPT_SCSIIO_REQUEST_CONTROL_TXDIR_GET(pLsiReq->GuestRequest.SCSIIO.u32Control);
2201
2202	if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_NONE)
2203	pLsiReq->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;
2204	else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_WRITE)
2205	pLsiReq->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;
2206	else if (uDataDirection == MPT_SCSIIO_REQUEST_CONTROL_TXDIR_READ)
2207	pLsiReq->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;
2208
2209	pLsiReq->PDMScsiRequest.cbCDB = pLsiReq->GuestRequest.SCSIIO.u8CDBLength;
2210	pLsiReq->PDMScsiRequest.pbCDB = pLsiReq->GuestRequest.SCSIIO.au8CDB;
2211	pLsiReq->PDMScsiRequest.cbScatterGather = pLsiReq->GuestRequest.SCSIIO.u32DataLength;
2212	if (pLsiReq->PDMScsiRequest.cbScatterGather)
2213	{
2214	pLsiReq->PDMScsiRequest.cScatterGatherEntries = 1;
2215	pLsiReq->PDMScsiRequest.paScatterGatherHead = &pLsiReq->SegIoBuf;
2216	}
2217	else
2218	{
2219	pLsiReq->PDMScsiRequest.cScatterGatherEntries = 0;
2220	pLsiReq->PDMScsiRequest.paScatterGatherHead = NULL;
2221	}
2222	pLsiReq->PDMScsiRequest.cbSenseBuffer = sizeof(pLsiReq->abSenseBuffer);
2223	memset(pLsiReq->abSenseBuffer, 0, pLsiReq->PDMScsiRequest.cbSenseBuffer);
2224	pLsiReq->PDMScsiRequest.pbSenseBuffer = pLsiReq->abSenseBuffer;
2225	pLsiReq->PDMScsiRequest.pvUser = pLsiReq;
2226
2227	ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);
2228	rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pLsiReq->PDMScsiRequest);
2229	AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));
2230	return VINF_SUCCESS;
2231	}
2232	else
2233	{
2234	/* Device is not present report SCSI selection timeout. */
2235	pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_DEVICE_NOT_THERE;
2236	}
2237	}
2238	else
2239	{
2240	/* Report out of bounds target ID or bus. */
2241	if (pLsiReq->GuestRequest.SCSIIO.u8Bus != 0)
2242	pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_BUS;
2243	else
2244	pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = MPT_SCSI_IO_ERROR_IOCSTATUS_INVALID_TARGETID;
2245	}
2246
2247	static int g_cLogged = 0;
2248
2249	if (g_cLogged++ < MAX_REL_LOG_ERRORS)
2250	{
2251	LogRel(("LsiLogic#%d: %d/%d (Bus/Target) doesn't exist\n", pThis->CTX_SUFF(pDevIns)->iInstance,
2252	pLsiReq->GuestRequest.SCSIIO.u8TargetID, pLsiReq->GuestRequest.SCSIIO.u8Bus));
2253	/* Log the CDB too */
2254	LogRel(("LsiLogic#%d: Guest issued CDB {%#x",
2255	pThis->CTX_SUFF(pDevIns)->iInstance, pLsiReq->GuestRequest.SCSIIO.au8CDB[0]));
2256	for (unsigned i = 1; i < pLsiReq->GuestRequest.SCSIIO.u8CDBLength; i++)
2257	LogRel((", %#x", pLsiReq->GuestRequest.SCSIIO.au8CDB[i]));
2258	LogRel(("}\n"));
2259	}
2260
2261	/* The rest is equal to both errors. */
2262	pLsiReq->IOCReply.SCSIIOError.u8TargetID = pLsiReq->GuestRequest.SCSIIO.u8TargetID;
2263	pLsiReq->IOCReply.SCSIIOError.u8Bus = pLsiReq->GuestRequest.SCSIIO.u8Bus;
2264	pLsiReq->IOCReply.SCSIIOError.u8MessageLength = sizeof(MptSCSIIOErrorReply) / 4;
2265	pLsiReq->IOCReply.SCSIIOError.u8Function = pLsiReq->GuestRequest.SCSIIO.u8Function;
2266	pLsiReq->IOCReply.SCSIIOError.u8CDBLength = pLsiReq->GuestRequest.SCSIIO.u8CDBLength;
2267	pLsiReq->IOCReply.SCSIIOError.u8SenseBufferLength = pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2268	pLsiReq->IOCReply.SCSIIOError.u32MessageContext = pLsiReq->GuestRequest.SCSIIO.u32MessageContext;
2269	pLsiReq->IOCReply.SCSIIOError.u8SCSIStatus = SCSI_STATUS_OK;
2270	pLsiReq->IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_TERMINATED;
2271	pLsiReq->IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2272	pLsiReq->IOCReply.SCSIIOError.u32TransferCount = 0;
2273	pLsiReq->IOCReply.SCSIIOError.u32SenseCount = 0;
2274	pLsiReq->IOCReply.SCSIIOError.u32ResponseInfo = 0;
2275
2276	lsilogicFinishAddressReply(pThis, &pLsiReq->IOCReply, false);
2277	RTMemCacheFree(pThis->hTaskCache, pLsiReq);
2278
2279	return rc;
2280	}
2281
2282
2283	/**
2284	* @interface_method_impl{PDMISCSIPORT,pfnSCSIRequestCompleted}
2285	*/
2286	static DECLCALLBACK(int) lsilogicR3DeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,
2287	int rcCompletion, bool fRedo, int rcReq)
2288	{
2289	PLSILOGICREQ pLsiReq = (PLSILOGICREQ)pSCSIRequest->pvUser;
2290	PLSILOGICDEVICE pLsiLogicDevice = pLsiReq->pTargetDevice;
2291	PLSILOGICSCSI pThis = pLsiLogicDevice->CTX_SUFF(pLsiLogic);
2292
2293	/* If the task failed but it is possible to redo it again after a suspend
2294	* add it to the list. */
2295	if (fRedo)
2296	{
2297	if (!pLsiReq->fBIOS && pLsiReq->PDMScsiRequest.cbScatterGather)
2298	lsilogicIoBufFree(pThis->CTX_SUFF(pDevIns), pLsiReq, false /* fCopyToGuest */);
2299
2300	/* Add to the list. */
2301	do
2302	{
2303	pLsiReq->pRedoNext = ASMAtomicReadPtrT(&pThis->pTasksRedoHead, PLSILOGICREQ);
2304	} while (!ASMAtomicCmpXchgPtr(&pThis->pTasksRedoHead, pLsiReq, pLsiReq->pRedoNext));
2305
2306	/* Suspend the VM if not done already. */
2307	if (!ASMAtomicXchgBool(&pThis->fRedo, true))
2308	lsilogicR3RedoSetWarning(pThis, rcReq);
2309	}
2310	else
2311	{
2312	if (RT_UNLIKELY(pLsiReq->fBIOS))
2313	{
2314	int rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, pSCSIRequest, rcCompletion);
2315	AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));
2316	}
2317	else
2318	{
2319	RTGCPHYS GCPhysAddrSenseBuffer;
2320
2321	GCPhysAddrSenseBuffer = pLsiReq->GuestRequest.SCSIIO.u32SenseBufferLowAddress;
2322	GCPhysAddrSenseBuffer \|= ((uint64_t)pThis->u32SenseBufferHighAddr << 32);
2323
2324	/* Copy the sense buffer over. */
2325	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrSenseBuffer, pLsiReq->abSenseBuffer,
2326	RT_UNLIKELY( pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength
2327	< pLsiReq->PDMScsiRequest.cbSenseBuffer)
2328	? pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength
2329	: pLsiReq->PDMScsiRequest.cbSenseBuffer);
2330
2331	if (pLsiReq->PDMScsiRequest.cbScatterGather)
2332	lsilogicIoBufFree(pThis->CTX_SUFF(pDevIns), pLsiReq, true /* fCopyToGuest */);
2333
2334
2335	if (RT_LIKELY(rcCompletion == SCSI_STATUS_OK))
2336	lsilogicR3FinishContextReply(pThis, pLsiReq->GuestRequest.SCSIIO.u32MessageContext);
2337	else
2338	{
2339	/* The SCSI target encountered an error during processing post a reply. */
2340	memset(&pLsiReq->IOCReply, 0, sizeof(MptReplyUnion));
2341	pLsiReq->IOCReply.SCSIIOError.u8TargetID = pLsiReq->GuestRequest.SCSIIO.u8TargetID;
2342	pLsiReq->IOCReply.SCSIIOError.u8Bus = pLsiReq->GuestRequest.SCSIIO.u8Bus;
2343	pLsiReq->IOCReply.SCSIIOError.u8MessageLength = 8;
2344	pLsiReq->IOCReply.SCSIIOError.u8Function = pLsiReq->GuestRequest.SCSIIO.u8Function;
2345	pLsiReq->IOCReply.SCSIIOError.u8CDBLength = pLsiReq->GuestRequest.SCSIIO.u8CDBLength;
2346	pLsiReq->IOCReply.SCSIIOError.u8SenseBufferLength = pLsiReq->GuestRequest.SCSIIO.u8SenseBufferLength;
2347	pLsiReq->IOCReply.SCSIIOError.u8MessageFlags = pLsiReq->GuestRequest.SCSIIO.u8MessageFlags;
2348	pLsiReq->IOCReply.SCSIIOError.u32MessageContext = pLsiReq->GuestRequest.SCSIIO.u32MessageContext;
2349	pLsiReq->IOCReply.SCSIIOError.u8SCSIStatus = rcCompletion;
2350	pLsiReq->IOCReply.SCSIIOError.u8SCSIState = MPT_SCSI_IO_ERROR_SCSI_STATE_AUTOSENSE_VALID;
2351	pLsiReq->IOCReply.SCSIIOError.u16IOCStatus = 0;
2352	pLsiReq->IOCReply.SCSIIOError.u32IOCLogInfo = 0;
2353	pLsiReq->IOCReply.SCSIIOError.u32TransferCount = 0;
2354	pLsiReq->IOCReply.SCSIIOError.u32SenseCount = sizeof(pLsiReq->abSenseBuffer);
2355	pLsiReq->IOCReply.SCSIIOError.u32ResponseInfo = 0;
2356
2357	lsilogicFinishAddressReply(pThis, &pLsiReq->IOCReply, false);
2358	}
2359	}
2360
2361	RTMemCacheFree(pThis->hTaskCache, pLsiReq);
2362	}
2363
2364	ASMAtomicDecU32(&pLsiLogicDevice->cOutstandingRequests);
2365
2366	if (pLsiLogicDevice->cOutstandingRequests == 0 && pThis->fSignalIdle)
2367	PDMDevHlpAsyncNotificationCompleted(pThis->pDevInsR3);
2368
2369	return VINF_SUCCESS;
2370	}
2371
2372	/**
2373	* @interface_method_impl{PDMISCSIPORT,pfnQueryDeviceLocation}
2374	*/
2375	static DECLCALLBACK(int) lsilogicR3QueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,
2376	uint32_t piInstance, uint32_t piLUN)
2377	{
2378	PLSILOGICDEVICE pLsiLogicDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ISCSIPort);
2379	PPDMDEVINS pDevIns = pLsiLogicDevice->CTX_SUFF(pLsiLogic)->CTX_SUFF(pDevIns);
2380
2381	AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
2382	AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
2383	AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
2384
2385	*ppcszController = pDevIns->pReg->szName;
2386	*piInstance = pDevIns->iInstance;
2387	*piLUN = pLsiLogicDevice->iLUN;
2388
2389	return VINF_SUCCESS;
2390	}
2391
2392	/**
2393	* Return the configuration page header and data
2394	* which matches the given page type and number.
2395	*
2396	* @returns VINF_SUCCESS if successful
2397	* VERR_NOT_FOUND if the requested page could be found.
2398	* @param u8PageNumber Number of the page to get.
2399	* @param ppPageHeader Where to store the pointer to the page header.
2400	* @param ppbPageData Where to store the pointer to the page data.
2401	*/
2402	static int lsilogicR3ConfigurationIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2403	PMptConfigurationPagesSupported pPages,
2404	uint8_t u8PageNumber,
2405	PMptConfigurationPageHeader *ppPageHeader,
2406	uint8_t *ppbPageData, size_t pcbPage)
2407	{
2408	int rc = VINF_SUCCESS;
2409
2410	AssertPtr(ppPageHeader); Assert(ppbPageData);
2411
2412	switch (u8PageNumber)
2413	{
2414	case 0:
2415	*ppPageHeader = &pPages->IOUnitPage0.u.fields.Header;
2416	*ppbPageData = pPages->IOUnitPage0.u.abPageData;
2417	*pcbPage = sizeof(pPages->IOUnitPage0);
2418	break;
2419	case 1:
2420	*ppPageHeader = &pPages->IOUnitPage1.u.fields.Header;
2421	*ppbPageData = pPages->IOUnitPage1.u.abPageData;
2422	*pcbPage = sizeof(pPages->IOUnitPage1);
2423	break;
2424	case 2:
2425	*ppPageHeader = &pPages->IOUnitPage2.u.fields.Header;
2426	*ppbPageData = pPages->IOUnitPage2.u.abPageData;
2427	*pcbPage = sizeof(pPages->IOUnitPage2);
2428	break;
2429	case 3:
2430	*ppPageHeader = &pPages->IOUnitPage3.u.fields.Header;
2431	*ppbPageData = pPages->IOUnitPage3.u.abPageData;
2432	*pcbPage = sizeof(pPages->IOUnitPage3);
2433	break;
2434	case 4:
2435	*ppPageHeader = &pPages->IOUnitPage4.u.fields.Header;
2436	*ppbPageData = pPages->IOUnitPage4.u.abPageData;
2437	*pcbPage = sizeof(pPages->IOUnitPage4);
2438	break;
2439	default:
2440	rc = VERR_NOT_FOUND;
2441	}
2442
2443	return rc;
2444	}
2445
2446	/**
2447	* Return the configuration page header and data
2448	* which matches the given page type and number.
2449	*
2450	* @returns VINF_SUCCESS if successful
2451	* VERR_NOT_FOUND if the requested page could be found.
2452	* @param u8PageNumber Number of the page to get.
2453	* @param ppPageHeader Where to store the pointer to the page header.
2454	* @param ppbPageData Where to store the pointer to the page data.
2455	*/
2456	static int lsilogicR3ConfigurationIOCPageGetFromNumber(PLSILOGICSCSI pThis,
2457	PMptConfigurationPagesSupported pPages,
2458	uint8_t u8PageNumber,
2459	PMptConfigurationPageHeader *ppPageHeader,
2460	uint8_t *ppbPageData, size_t pcbPage)
2461	{
2462	int rc = VINF_SUCCESS;
2463
2464	AssertPtr(ppPageHeader); Assert(ppbPageData);
2465
2466	switch (u8PageNumber)
2467	{
2468	case 0:
2469	*ppPageHeader = &pPages->IOCPage0.u.fields.Header;
2470	*ppbPageData = pPages->IOCPage0.u.abPageData;
2471	*pcbPage = sizeof(pPages->IOCPage0);
2472	break;
2473	case 1:
2474	*ppPageHeader = &pPages->IOCPage1.u.fields.Header;
2475	*ppbPageData = pPages->IOCPage1.u.abPageData;
2476	*pcbPage = sizeof(pPages->IOCPage1);
2477	break;
2478	case 2:
2479	*ppPageHeader = &pPages->IOCPage2.u.fields.Header;
2480	*ppbPageData = pPages->IOCPage2.u.abPageData;
2481	*pcbPage = sizeof(pPages->IOCPage2);
2482	break;
2483	case 3:
2484	*ppPageHeader = &pPages->IOCPage3.u.fields.Header;
2485	*ppbPageData = pPages->IOCPage3.u.abPageData;
2486	*pcbPage = sizeof(pPages->IOCPage3);
2487	break;
2488	case 4:
2489	*ppPageHeader = &pPages->IOCPage4.u.fields.Header;
2490	*ppbPageData = pPages->IOCPage4.u.abPageData;
2491	*pcbPage = sizeof(pPages->IOCPage4);
2492	break;
2493	case 6:
2494	*ppPageHeader = &pPages->IOCPage6.u.fields.Header;
2495	*ppbPageData = pPages->IOCPage6.u.abPageData;
2496	*pcbPage = sizeof(pPages->IOCPage6);
2497	break;
2498	default:
2499	rc = VERR_NOT_FOUND;
2500	}
2501
2502	return rc;
2503	}
2504
2505	/**
2506	* Return the configuration page header and data
2507	* which matches the given page type and number.
2508	*
2509	* @returns VINF_SUCCESS if successful
2510	* VERR_NOT_FOUND if the requested page could be found.
2511	* @param u8PageNumber Number of the page to get.
2512	* @param ppPageHeader Where to store the pointer to the page header.
2513	* @param ppbPageData Where to store the pointer to the page data.
2514	*/
2515	static int lsilogicR3ConfigurationManufacturingPageGetFromNumber(PLSILOGICSCSI pThis,
2516	PMptConfigurationPagesSupported pPages,
2517	uint8_t u8PageNumber,
2518	PMptConfigurationPageHeader *ppPageHeader,
2519	uint8_t *ppbPageData, size_t pcbPage)
2520	{
2521	int rc = VINF_SUCCESS;
2522
2523	AssertPtr(ppPageHeader); Assert(ppbPageData);
2524
2525	switch (u8PageNumber)
2526	{
2527	case 0:
2528	*ppPageHeader = &pPages->ManufacturingPage0.u.fields.Header;
2529	*ppbPageData = pPages->ManufacturingPage0.u.abPageData;
2530	*pcbPage = sizeof(pPages->ManufacturingPage0);
2531	break;
2532	case 1:
2533	*ppPageHeader = &pPages->ManufacturingPage1.u.fields.Header;
2534	*ppbPageData = pPages->ManufacturingPage1.u.abPageData;
2535	*pcbPage = sizeof(pPages->ManufacturingPage1);
2536	break;
2537	case 2:
2538	*ppPageHeader = &pPages->ManufacturingPage2.u.fields.Header;
2539	*ppbPageData = pPages->ManufacturingPage2.u.abPageData;
2540	*pcbPage = sizeof(pPages->ManufacturingPage2);
2541	break;
2542	case 3:
2543	*ppPageHeader = &pPages->ManufacturingPage3.u.fields.Header;
2544	*ppbPageData = pPages->ManufacturingPage3.u.abPageData;
2545	*pcbPage = sizeof(pPages->ManufacturingPage3);
2546	break;
2547	case 4:
2548	*ppPageHeader = &pPages->ManufacturingPage4.u.fields.Header;
2549	*ppbPageData = pPages->ManufacturingPage4.u.abPageData;
2550	*pcbPage = sizeof(pPages->ManufacturingPage4);
2551	break;
2552	case 5:
2553	*ppPageHeader = &pPages->ManufacturingPage5.u.fields.Header;
2554	*ppbPageData = pPages->ManufacturingPage5.u.abPageData;
2555	*pcbPage = sizeof(pPages->ManufacturingPage5);
2556	break;
2557	case 6:
2558	*ppPageHeader = &pPages->ManufacturingPage6.u.fields.Header;
2559	*ppbPageData = pPages->ManufacturingPage6.u.abPageData;
2560	*pcbPage = sizeof(pPages->ManufacturingPage6);
2561	break;
2562	case 7:
2563	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
2564	{
2565	*ppPageHeader = &pPages->u.SasPages.pManufacturingPage7->u.fields.Header;
2566	*ppbPageData = pPages->u.SasPages.pManufacturingPage7->u.abPageData;
2567	*pcbPage = pPages->u.SasPages.cbManufacturingPage7;
2568	}
2569	else
2570	rc = VERR_NOT_FOUND;
2571	break;
2572	case 8:
2573	*ppPageHeader = &pPages->ManufacturingPage8.u.fields.Header;
2574	*ppbPageData = pPages->ManufacturingPage8.u.abPageData;
2575	*pcbPage = sizeof(pPages->ManufacturingPage8);
2576	break;
2577	case 9:
2578	*ppPageHeader = &pPages->ManufacturingPage9.u.fields.Header;
2579	*ppbPageData = pPages->ManufacturingPage9.u.abPageData;
2580	*pcbPage = sizeof(pPages->ManufacturingPage9);
2581	break;
2582	case 10:
2583	*ppPageHeader = &pPages->ManufacturingPage10.u.fields.Header;
2584	*ppbPageData = pPages->ManufacturingPage10.u.abPageData;
2585	*pcbPage = sizeof(pPages->ManufacturingPage10);
2586	break;
2587	default:
2588	rc = VERR_NOT_FOUND;
2589	}
2590
2591	return rc;
2592	}
2593
2594	/**
2595	* Return the configuration page header and data
2596	* which matches the given page type and number.
2597	*
2598	* @returns VINF_SUCCESS if successful
2599	* VERR_NOT_FOUND if the requested page could be found.
2600	* @param u8PageNumber Number of the page to get.
2601	* @param ppPageHeader Where to store the pointer to the page header.
2602	* @param ppbPageData Where to store the pointer to the page data.
2603	*/
2604	static int lsilogicR3ConfigurationBiosPageGetFromNumber(PLSILOGICSCSI pThis,
2605	PMptConfigurationPagesSupported pPages,
2606	uint8_t u8PageNumber,
2607	PMptConfigurationPageHeader *ppPageHeader,
2608	uint8_t *ppbPageData, size_t pcbPage)
2609	{
2610	int rc = VINF_SUCCESS;
2611
2612	AssertPtr(ppPageHeader); Assert(ppbPageData);
2613
2614	switch (u8PageNumber)
2615	{
2616	case 1:
2617	*ppPageHeader = &pPages->BIOSPage1.u.fields.Header;
2618	*ppbPageData = pPages->BIOSPage1.u.abPageData;
2619	*pcbPage = sizeof(pPages->BIOSPage1);
2620	break;
2621	case 2:
2622	*ppPageHeader = &pPages->BIOSPage2.u.fields.Header;
2623	*ppbPageData = pPages->BIOSPage2.u.abPageData;
2624	*pcbPage = sizeof(pPages->BIOSPage2);
2625	break;
2626	case 4:
2627	*ppPageHeader = &pPages->BIOSPage4.u.fields.Header;
2628	*ppbPageData = pPages->BIOSPage4.u.abPageData;
2629	*pcbPage = sizeof(pPages->BIOSPage4);
2630	break;
2631	default:
2632	rc = VERR_NOT_FOUND;
2633	}
2634
2635	return rc;
2636	}
2637
2638	/**
2639	* Return the configuration page header and data
2640	* which matches the given page type and number.
2641	*
2642	* @returns VINF_SUCCESS if successful
2643	* VERR_NOT_FOUND if the requested page could be found.
2644	* @param u8PageNumber Number of the page to get.
2645	* @param ppPageHeader Where to store the pointer to the page header.
2646	* @param ppbPageData Where to store the pointer to the page data.
2647	*/
2648	static int lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(PLSILOGICSCSI pThis,
2649	PMptConfigurationPagesSupported pPages,
2650	uint8_t u8Port,
2651	uint8_t u8PageNumber,
2652	PMptConfigurationPageHeader *ppPageHeader,
2653	uint8_t *ppbPageData, size_t pcbPage)
2654	{
2655	int rc = VINF_SUCCESS;
2656	AssertPtr(ppPageHeader); Assert(ppbPageData);
2657
2658
2659	if (u8Port >= RT_ELEMENTS(pPages->u.SpiPages.aPortPages))
2660	return VERR_NOT_FOUND;
2661
2662	switch (u8PageNumber)
2663	{
2664	case 0:
2665	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.fields.Header;
2666	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0.u.abPageData;
2667	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage0);
2668	break;
2669	case 1:
2670	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.fields.Header;
2671	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1.u.abPageData;
2672	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage1);
2673	break;
2674	case 2:
2675	*ppPageHeader = &pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.fields.Header;
2676	*ppbPageData = pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2.u.abPageData;
2677	*pcbPage = sizeof(pPages->u.SpiPages.aPortPages[u8Port].SCSISPIPortPage2);
2678	break;
2679	default:
2680	rc = VERR_NOT_FOUND;
2681	}
2682
2683	return rc;
2684	}
2685
2686	/**
2687	* Return the configuration page header and data
2688	* which matches the given page type and number.
2689	*
2690	* @returns VINF_SUCCESS if successful
2691	* VERR_NOT_FOUND if the requested page could be found.
2692	* @param u8PageNumber Number of the page to get.
2693	* @param ppPageHeader Where to store the pointer to the page header.
2694	* @param ppbPageData Where to store the pointer to the page data.
2695	*/
2696	static int lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2697	PMptConfigurationPagesSupported pPages,
2698	uint8_t u8Bus,
2699	uint8_t u8TargetID, uint8_t u8PageNumber,
2700	PMptConfigurationPageHeader *ppPageHeader,
2701	uint8_t *ppbPageData, size_t pcbPage)
2702	{
2703	int rc = VINF_SUCCESS;
2704	AssertPtr(ppPageHeader); Assert(ppbPageData);
2705
2706	if (u8Bus >= RT_ELEMENTS(pPages->u.SpiPages.aBuses))
2707	return VERR_NOT_FOUND;
2708
2709	if (u8TargetID >= RT_ELEMENTS(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages))
2710	return VERR_NOT_FOUND;
2711
2712	switch (u8PageNumber)
2713	{
2714	case 0:
2715	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.fields.Header;
2716	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0.u.abPageData;
2717	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage0);
2718	break;
2719	case 1:
2720	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.fields.Header;
2721	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1.u.abPageData;
2722	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage1);
2723	break;
2724	case 2:
2725	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.fields.Header;
2726	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2.u.abPageData;
2727	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage2);
2728	break;
2729	case 3:
2730	*ppPageHeader = &pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.fields.Header;
2731	*ppbPageData = pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3.u.abPageData;
2732	*pcbPage = sizeof(pPages->u.SpiPages.aBuses[u8Bus].aDevicePages[u8TargetID].SCSISPIDevicePage3);
2733	break;
2734	default:
2735	rc = VERR_NOT_FOUND;
2736	}
2737
2738	return rc;
2739	}
2740
2741	static int lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(PLSILOGICSCSI pThis,
2742	PMptConfigurationPagesSupported pPages,
2743	uint8_t u8PageNumber,
2744	PMptExtendedConfigurationPageHeader *ppPageHeader,
2745	uint8_t *ppbPageData, size_t pcbPage)
2746	{
2747	int rc = VINF_SUCCESS;
2748
2749	switch (u8PageNumber)
2750	{
2751	case 0:
2752	*ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage0->u.fields.ExtHeader;
2753	*ppbPageData = pPages->u.SasPages.pSASIOUnitPage0->u.abPageData;
2754	*pcbPage = pPages->u.SasPages.cbSASIOUnitPage0;
2755	break;
2756	case 1:
2757	*ppPageHeader = &pPages->u.SasPages.pSASIOUnitPage1->u.fields.ExtHeader;
2758	*ppbPageData = pPages->u.SasPages.pSASIOUnitPage1->u.abPageData;
2759	*pcbPage = pPages->u.SasPages.cbSASIOUnitPage1;
2760	break;
2761	case 2:
2762	*ppPageHeader = &pPages->u.SasPages.SASIOUnitPage2.u.fields.ExtHeader;
2763	*ppbPageData = pPages->u.SasPages.SASIOUnitPage2.u.abPageData;
2764	*pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage2);
2765	break;
2766	case 3:
2767	*ppPageHeader = &pPages->u.SasPages.SASIOUnitPage3.u.fields.ExtHeader;
2768	*ppbPageData = pPages->u.SasPages.SASIOUnitPage3.u.abPageData;
2769	*pcbPage = sizeof(pPages->u.SasPages.SASIOUnitPage3);
2770	break;
2771	default:
2772	rc = VERR_NOT_FOUND;
2773	}
2774
2775	return rc;
2776	}
2777
2778	static int lsilogicR3ConfigurationSASPHYPageGetFromNumber(PLSILOGICSCSI pThis,
2779	PMptConfigurationPagesSupported pPages,
2780	uint8_t u8PageNumber,
2781	MptConfigurationPageAddress PageAddress,
2782	PMptExtendedConfigurationPageHeader *ppPageHeader,
2783	uint8_t *ppbPageData, size_t pcbPage)
2784	{
2785	int rc = VINF_SUCCESS;
2786	uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2787	PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2788	PMptPHY pPHYPages = NULL;
2789
2790	Log(("Address form %d\n", uAddressForm));
2791
2792	if (uAddressForm == 0) /* PHY number */
2793	{
2794	uint8_t u8PhyNumber = PageAddress.SASPHY.Form0.u8PhyNumber;
2795
2796	Log(("PHY number %d\n", u8PhyNumber));
2797
2798	if (u8PhyNumber >= pPagesSas->cPHYs)
2799	return VERR_NOT_FOUND;
2800
2801	pPHYPages = &pPagesSas->paPHYs[u8PhyNumber];
2802	}
2803	else if (uAddressForm == 1) /* Index form */
2804	{
2805	uint16_t u16Index = PageAddress.SASPHY.Form1.u16Index;
2806
2807	Log(("PHY index %d\n", u16Index));
2808
2809	if (u16Index >= pPagesSas->cPHYs)
2810	return VERR_NOT_FOUND;
2811
2812	pPHYPages = &pPagesSas->paPHYs[u16Index];
2813	}
2814	else
2815	rc = VERR_NOT_FOUND; /* Correct? */
2816
2817	if (pPHYPages)
2818	{
2819	switch (u8PageNumber)
2820	{
2821	case 0:
2822	*ppPageHeader = &pPHYPages->SASPHYPage0.u.fields.ExtHeader;
2823	*ppbPageData = pPHYPages->SASPHYPage0.u.abPageData;
2824	*pcbPage = sizeof(pPHYPages->SASPHYPage0);
2825	break;
2826	case 1:
2827	*ppPageHeader = &pPHYPages->SASPHYPage1.u.fields.ExtHeader;
2828	*ppbPageData = pPHYPages->SASPHYPage1.u.abPageData;
2829	*pcbPage = sizeof(pPHYPages->SASPHYPage1);
2830	break;
2831	default:
2832	rc = VERR_NOT_FOUND;
2833	}
2834	}
2835	else
2836	rc = VERR_NOT_FOUND;
2837
2838	return rc;
2839	}
2840
2841	static int lsilogicR3ConfigurationSASDevicePageGetFromNumber(PLSILOGICSCSI pThis,
2842	PMptConfigurationPagesSupported pPages,
2843	uint8_t u8PageNumber,
2844	MptConfigurationPageAddress PageAddress,
2845	PMptExtendedConfigurationPageHeader *ppPageHeader,
2846	uint8_t *ppbPageData, size_t pcbPage)
2847	{
2848	int rc = VINF_SUCCESS;
2849	uint8_t uAddressForm = MPT_CONFIGURATION_PAGE_ADDRESS_GET_SAS_FORM(PageAddress);
2850	PMptConfigurationPagesSas pPagesSas = &pPages->u.SasPages;
2851	PMptSASDevice pSASDevice = NULL;
2852
2853	Log(("Address form %d\n", uAddressForm));
2854
2855	if (uAddressForm == 0)
2856	{
2857	uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2858
2859	Log(("Get next handle %#x\n", u16Handle));
2860
2861	pSASDevice = pPagesSas->pSASDeviceHead;
2862
2863	/* Get the first device? */
2864	if (u16Handle != 0xffff)
2865	{
2866	/* No, search for the right one. */
2867
2868	while ( pSASDevice
2869	&& pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2870	pSASDevice = pSASDevice->pNext;
2871
2872	if (pSASDevice)
2873	pSASDevice = pSASDevice->pNext;
2874	}
2875	}
2876	else if (uAddressForm == 1)
2877	{
2878	uint8_t u8TargetID = PageAddress.SASDevice.Form1.u8TargetID;
2879	uint8_t u8Bus = PageAddress.SASDevice.Form1.u8Bus;
2880
2881	Log(("u8TargetID=%d u8Bus=%d\n", u8TargetID, u8Bus));
2882
2883	pSASDevice = pPagesSas->pSASDeviceHead;
2884
2885	while ( pSASDevice
2886	&& ( pSASDevice->SASDevicePage0.u.fields.u8TargetID != u8TargetID
2887	\|\| pSASDevice->SASDevicePage0.u.fields.u8Bus != u8Bus))
2888	pSASDevice = pSASDevice->pNext;
2889	}
2890	else if (uAddressForm == 2)
2891	{
2892	uint16_t u16Handle = PageAddress.SASDevice.Form0And2.u16Handle;
2893
2894	Log(("Handle %#x\n", u16Handle));
2895
2896	pSASDevice = pPagesSas->pSASDeviceHead;
2897
2898	while ( pSASDevice
2899	&& pSASDevice->SASDevicePage0.u.fields.u16DevHandle != u16Handle)
2900	pSASDevice = pSASDevice->pNext;
2901	}
2902
2903	if (pSASDevice)
2904	{
2905	switch (u8PageNumber)
2906	{
2907	case 0:
2908	*ppPageHeader = &pSASDevice->SASDevicePage0.u.fields.ExtHeader;
2909	*ppbPageData = pSASDevice->SASDevicePage0.u.abPageData;
2910	*pcbPage = sizeof(pSASDevice->SASDevicePage0);
2911	break;
2912	case 1:
2913	*ppPageHeader = &pSASDevice->SASDevicePage1.u.fields.ExtHeader;
2914	*ppbPageData = pSASDevice->SASDevicePage1.u.abPageData;
2915	*pcbPage = sizeof(pSASDevice->SASDevicePage1);
2916	break;
2917	case 2:
2918	*ppPageHeader = &pSASDevice->SASDevicePage2.u.fields.ExtHeader;
2919	*ppbPageData = pSASDevice->SASDevicePage2.u.abPageData;
2920	*pcbPage = sizeof(pSASDevice->SASDevicePage2);
2921	break;
2922	default:
2923	rc = VERR_NOT_FOUND;
2924	}
2925	}
2926	else
2927	rc = VERR_NOT_FOUND;
2928
2929	return rc;
2930	}
2931
2932	/**
2933	* Returns the extended configuration page header and data.
2934	* @returns VINF_SUCCESS if successful
2935	* VERR_NOT_FOUND if the requested page could be found.
2936	* @param pThis Pointer to the LsiLogic device state.
2937	* @param pConfigurationReq The configuration request.
2938	* @param u8PageNumber Number of the page to get.
2939	* @param ppPageHeader Where to store the pointer to the page header.
2940	* @param ppbPageData Where to store the pointer to the page data.
2941	*/
2942	static int lsilogicR3ConfigurationPageGetExtended(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
2943	PMptExtendedConfigurationPageHeader *ppPageHeader,
2944	uint8_t *ppbPageData, size_t pcbPage)
2945	{
2946	int rc = VINF_SUCCESS;
2947
2948	Log(("Extended page requested:\n"));
2949	Log(("u8ExtPageType=%#x\n", pConfigurationReq->u8ExtPageType));
2950	Log(("u8ExtPageLength=%d\n", pConfigurationReq->u16ExtPageLength));
2951
2952	switch (pConfigurationReq->u8ExtPageType)
2953	{
2954	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT:
2955	{
2956	rc = lsilogicR3ConfigurationSASIOUnitPageGetFromNumber(pThis,
2957	pThis->pConfigurationPages,
2958	pConfigurationReq->u8PageNumber,
2959	ppPageHeader, ppbPageData, pcbPage);
2960	break;
2961	}
2962	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS:
2963	{
2964	rc = lsilogicR3ConfigurationSASPHYPageGetFromNumber(pThis,
2965	pThis->pConfigurationPages,
2966	pConfigurationReq->u8PageNumber,
2967	pConfigurationReq->PageAddress,
2968	ppPageHeader, ppbPageData, pcbPage);
2969	break;
2970	}
2971	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE:
2972	{
2973	rc = lsilogicR3ConfigurationSASDevicePageGetFromNumber(pThis,
2974	pThis->pConfigurationPages,
2975	pConfigurationReq->u8PageNumber,
2976	pConfigurationReq->PageAddress,
2977	ppPageHeader, ppbPageData, pcbPage);
2978	break;
2979	}
2980	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASEXPANDER: /* No expanders supported */
2981	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_ENCLOSURE: /* No enclosures supported */
2982	default:
2983	rc = VERR_NOT_FOUND;
2984	}
2985
2986	return rc;
2987	}
2988
2989	/**
2990	* Processes a Configuration request.
2991	*
2992	* @returns VBox status code.
2993	* @param pThis Pointer to the LsiLogic device state.
2994	* @param pConfigurationReq Pointer to the request structure.
2995	* @param pReply Pointer to the reply message frame
2996	*/
2997	static int lsilogicR3ProcessConfigurationRequest(PLSILOGICSCSI pThis, PMptConfigurationRequest pConfigurationReq,
2998	PMptConfigurationReply pReply)
2999	{
3000	int rc = VINF_SUCCESS;
3001	uint8_t *pbPageData = NULL;
3002	PMptConfigurationPageHeader pPageHeader = NULL;
3003	PMptExtendedConfigurationPageHeader pExtPageHeader = NULL;
3004	uint8_t u8PageType;
3005	uint8_t u8PageAttribute;
3006	size_t cbPage = 0;
3007
3008	LogFlowFunc(("pThis=%#p\n", pThis));
3009
3010	u8PageType = MPT_CONFIGURATION_PAGE_TYPE_GET(pConfigurationReq->u8PageType);
3011	u8PageAttribute = MPT_CONFIGURATION_PAGE_ATTRIBUTE_GET(pConfigurationReq->u8PageType);
3012
3013	Log(("GuestRequest:\n"));
3014	Log(("u8Action=%#x\n", pConfigurationReq->u8Action));
3015	Log(("u8PageType=%#x\n", u8PageType));
3016	Log(("u8PageNumber=%d\n", pConfigurationReq->u8PageNumber));
3017	Log(("u8PageLength=%d\n", pConfigurationReq->u8PageLength));
3018	Log(("u8PageVersion=%d\n", pConfigurationReq->u8PageVersion));
3019
3020	/* Copy common bits from the request into the reply. */
3021	pReply->u8MessageLength = 6; /* 6 32bit D-Words. */
3022	pReply->u8Action = pConfigurationReq->u8Action;
3023	pReply->u8Function = pConfigurationReq->u8Function;
3024	pReply->u32MessageContext = pConfigurationReq->u32MessageContext;
3025
3026	switch (u8PageType)
3027	{
3028	case MPT_CONFIGURATION_PAGE_TYPE_IO_UNIT:
3029	{
3030	/* Get the page data. */
3031	rc = lsilogicR3ConfigurationIOUnitPageGetFromNumber(pThis,
3032	pThis->pConfigurationPages,
3033	pConfigurationReq->u8PageNumber,
3034	&pPageHeader, &pbPageData, &cbPage);
3035	break;
3036	}
3037	case MPT_CONFIGURATION_PAGE_TYPE_IOC:
3038	{
3039	/* Get the page data. */
3040	rc = lsilogicR3ConfigurationIOCPageGetFromNumber(pThis,
3041	pThis->pConfigurationPages,
3042	pConfigurationReq->u8PageNumber,
3043	&pPageHeader, &pbPageData, &cbPage);
3044	break;
3045	}
3046	case MPT_CONFIGURATION_PAGE_TYPE_MANUFACTURING:
3047	{
3048	/* Get the page data. */
3049	rc = lsilogicR3ConfigurationManufacturingPageGetFromNumber(pThis,
3050	pThis->pConfigurationPages,
3051	pConfigurationReq->u8PageNumber,
3052	&pPageHeader, &pbPageData, &cbPage);
3053	break;
3054	}
3055	case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT:
3056	{
3057	/* Get the page data. */
3058	rc = lsilogicR3ConfigurationSCSISPIPortPageGetFromNumber(pThis,
3059	pThis->pConfigurationPages,
3060	pConfigurationReq->PageAddress.MPIPortNumber.u8PortNumber,
3061	pConfigurationReq->u8PageNumber,
3062	&pPageHeader, &pbPageData, &cbPage);
3063	break;
3064	}
3065	case MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE:
3066	{
3067	/* Get the page data. */
3068	rc = lsilogicR3ConfigurationSCSISPIDevicePageGetFromNumber(pThis,
3069	pThis->pConfigurationPages,
3070	pConfigurationReq->PageAddress.BusAndTargetId.u8Bus,
3071	pConfigurationReq->PageAddress.BusAndTargetId.u8TargetID,
3072	pConfigurationReq->u8PageNumber,
3073	&pPageHeader, &pbPageData, &cbPage);
3074	break;
3075	}
3076	case MPT_CONFIGURATION_PAGE_TYPE_BIOS:
3077	{
3078	rc = lsilogicR3ConfigurationBiosPageGetFromNumber(pThis,
3079	pThis->pConfigurationPages,
3080	pConfigurationReq->u8PageNumber,
3081	&pPageHeader, &pbPageData, &cbPage);
3082	break;
3083	}
3084	case MPT_CONFIGURATION_PAGE_TYPE_EXTENDED:
3085	{
3086	rc = lsilogicR3ConfigurationPageGetExtended(pThis,
3087	pConfigurationReq,
3088	&pExtPageHeader, &pbPageData, &cbPage);
3089	break;
3090	}
3091	default:
3092	rc = VERR_NOT_FOUND;
3093	}
3094
3095	if (rc == VERR_NOT_FOUND)
3096	{
3097	Log(("Page not found\n"));
3098	pReply->u8PageType = pConfigurationReq->u8PageType;
3099	pReply->u8PageNumber = pConfigurationReq->u8PageNumber;
3100	pReply->u8PageLength = pConfigurationReq->u8PageLength;
3101	pReply->u8PageVersion = pConfigurationReq->u8PageVersion;
3102	pReply->u16IOCStatus = MPT_IOCSTATUS_CONFIG_INVALID_PAGE;
3103	return VINF_SUCCESS;
3104	}
3105
3106	if (u8PageType == MPT_CONFIGURATION_PAGE_TYPE_EXTENDED)
3107	{
3108	pReply->u8PageType = pExtPageHeader->u8PageType;
3109	pReply->u8PageNumber = pExtPageHeader->u8PageNumber;
3110	pReply->u8PageVersion = pExtPageHeader->u8PageVersion;
3111	pReply->u8ExtPageType = pExtPageHeader->u8ExtPageType;
3112	pReply->u16ExtPageLength = pExtPageHeader->u16ExtPageLength;
3113
3114	for (int i = 0; i < pExtPageHeader->u16ExtPageLength; i++)
3115	LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3116	}
3117	else
3118	{
3119	pReply->u8PageType = pPageHeader->u8PageType;
3120	pReply->u8PageNumber = pPageHeader->u8PageNumber;
3121	pReply->u8PageLength = pPageHeader->u8PageLength;
3122	pReply->u8PageVersion = pPageHeader->u8PageVersion;
3123
3124	for (int i = 0; i < pReply->u8PageLength; i++)
3125	LogFlowFunc(("PageData[%d]=%#x\n", i, ((uint32_t *)pbPageData)[i]));
3126	}
3127
3128	/*
3129	* Don't use the scatter gather handling code as the configuration request always have only one
3130	* simple element.
3131	*/
3132	switch (pConfigurationReq->u8Action)
3133	{
3134	case MPT_CONFIGURATION_REQUEST_ACTION_DEFAULT: /* Nothing to do. We are always using the defaults. */
3135	case MPT_CONFIGURATION_REQUEST_ACTION_HEADER:
3136	{
3137	/* Already copied above nothing to do. */
3138	break;
3139	}
3140	case MPT_CONFIGURATION_REQUEST_ACTION_READ_NVRAM:
3141	case MPT_CONFIGURATION_REQUEST_ACTION_READ_CURRENT:
3142	case MPT_CONFIGURATION_REQUEST_ACTION_READ_DEFAULT:
3143	{
3144	uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3145	if (cbBuffer != 0)
3146	{
3147	RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3148	if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3149	GCPhysAddrPageBuffer \|= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3150
3151	PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData, RT_MIN(cbBuffer, cbPage));
3152	}
3153	break;
3154	}
3155	case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_CURRENT:
3156	case MPT_CONFIGURATION_REQUEST_ACTION_WRITE_NVRAM:
3157	{
3158	uint32_t cbBuffer = pConfigurationReq->SimpleSGElement.u24Length;
3159	if (cbBuffer != 0)
3160	{
3161	RTGCPHYS GCPhysAddrPageBuffer = pConfigurationReq->SimpleSGElement.u32DataBufferAddressLow;
3162	if (pConfigurationReq->SimpleSGElement.f64BitAddress)
3163	GCPhysAddrPageBuffer \|= (uint64_t)pConfigurationReq->SimpleSGElement.u32DataBufferAddressHigh << 32;
3164
3165	LogFlow(("cbBuffer=%u cbPage=%u\n", cbBuffer, cbPage));
3166
3167	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysAddrPageBuffer, pbPageData,
3168	RT_MIN(cbBuffer, cbPage));
3169	}
3170	break;
3171	}
3172	default:
3173	AssertMsgFailed(("todo\n"));
3174	}
3175
3176	return VINF_SUCCESS;
3177	}
3178
3179	/**
3180	* Initializes the configuration pages for the SPI SCSI controller.
3181	*
3182	* @returns nothing
3183	* @param pThis Pointer to the LsiLogic device state.
3184	*/
3185	static void lsilogicR3InitializeConfigurationPagesSpi(PLSILOGICSCSI pThis)
3186	{
3187	PMptConfigurationPagesSpi pPages = &pThis->pConfigurationPages->u.SpiPages;
3188
3189	AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI, ("Controller is not the SPI SCSI one\n"));
3190
3191	LogFlowFunc(("pThis=%#p\n", pThis));
3192
3193	/* Clear everything first. */
3194	memset(pPages, 0, sizeof(MptConfigurationPagesSpi));
3195
3196	for (unsigned i = 0; i < RT_ELEMENTS(pPages->aPortPages); i++)
3197	{
3198	/* SCSI-SPI port page 0. */
3199	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3200	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3201	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageNumber = 0;
3202	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort0) / 4;
3203	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fInformationUnitTransfersCapable = true;
3204	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fDTCapable = true;
3205	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fQASCapable = true;
3206	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MinimumSynchronousTransferPeriod = 0;
3207	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u8MaximumSynchronousOffset = 0xff;
3208	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fWide = true;
3209	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.fAIPCapable = true;
3210	pPages->aPortPages[i].SCSISPIPortPage0.u.fields.u2SignalingType = 0x3; /* Single Ended. */
3211
3212	/* SCSI-SPI port page 1. */
3213	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3214	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3215	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageNumber = 1;
3216	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort1) / 4;
3217	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u8SCSIID = 7;
3218	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u16PortResponseIDsBitmask = (1 << 7);
3219	pPages->aPortPages[i].SCSISPIPortPage1.u.fields.u32OnBusTimerValue = 0;
3220
3221	/* SCSI-SPI port page 2. */
3222	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3223	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_PORT;
3224	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageNumber = 2;
3225	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIPort2) / 4;
3226	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u4HostSCSIID = 7;
3227	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.u2InitializeHBA = 0x3;
3228	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.fTerminationDisabled = true;
3229	for (unsigned iDevice = 0; iDevice < RT_ELEMENTS(pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings); iDevice++)
3230	{
3231	pPages->aPortPages[i].SCSISPIPortPage2.u.fields.aDeviceSettings[iDevice].fBootChoice = true;
3232	}
3233	/* Everything else 0 for now. */
3234	}
3235
3236	for (unsigned uBusCurr = 0; uBusCurr < RT_ELEMENTS(pPages->aBuses); uBusCurr++)
3237	{
3238	for (unsigned uDeviceCurr = 0; uDeviceCurr < RT_ELEMENTS(pPages->aBuses[uBusCurr].aDevicePages); uDeviceCurr++)
3239	{
3240	/* SCSI-SPI device page 0. */
3241	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3242	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3243	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageNumber = 0;
3244	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage0.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice0) / 4;
3245	/* Everything else 0 for now. */
3246
3247	/* SCSI-SPI device page 1. */
3248	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3249	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3250	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageNumber = 1;
3251	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage1.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice1) / 4;
3252	/* Everything else 0 for now. */
3253
3254	/* SCSI-SPI device page 2. */
3255	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE
3256	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3257	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageNumber = 2;
3258	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage2.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice2) / 4;
3259	/* Everything else 0 for now. */
3260
3261	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3262	\| MPT_CONFIGURATION_PAGE_TYPE_SCSI_SPI_DEVICE;
3263	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageNumber = 3;
3264	pPages->aBuses[uBusCurr].aDevicePages[uDeviceCurr].SCSISPIDevicePage3.u.fields.Header.u8PageLength = sizeof(MptConfigurationPageSCSISPIDevice3) / 4;
3265	/* Everything else 0 for now. */
3266	}
3267	}
3268	}
3269
3270	/**
3271	* Generates a handle.
3272	*
3273	* @returns the handle.
3274	* @param pThis Pointer to the LsiLogic device state.
3275	*/
3276	DECLINLINE(uint16_t) lsilogicGetHandle(PLSILOGICSCSI pThis)
3277	{
3278	uint16_t u16Handle = pThis->u16NextHandle++;
3279	return u16Handle;
3280	}
3281
3282	/**
3283	* Generates a SAS address (WWID)
3284	*
3285	* @returns nothing.
3286	* @param pSASAddress Pointer to an unitialised SAS address.
3287	* @param iId iId which will go into the address.
3288	*
3289	* @todo Generate better SAS addresses. (Request a block from SUN probably)
3290	*/
3291	void lsilogicSASAddressGenerate(PSASADDRESS pSASAddress, unsigned iId)
3292	{
3293	pSASAddress->u8Address[0] = (0x5 << 5);
3294	pSASAddress->u8Address[1] = 0x01;
3295	pSASAddress->u8Address[2] = 0x02;
3296	pSASAddress->u8Address[3] = 0x03;
3297	pSASAddress->u8Address[4] = 0x04;
3298	pSASAddress->u8Address[5] = 0x05;
3299	pSASAddress->u8Address[6] = 0x06;
3300	pSASAddress->u8Address[7] = iId;
3301	}
3302
3303	/**
3304	* Initializes the configuration pages for the SAS SCSI controller.
3305	*
3306	* @returns nothing
3307	* @param pThis Pointer to the LsiLogic device state.
3308	*/
3309	static void lsilogicR3InitializeConfigurationPagesSas(PLSILOGICSCSI pThis)
3310	{
3311	PMptConfigurationPagesSas pPages = &pThis->pConfigurationPages->u.SasPages;
3312
3313	AssertMsg(pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS, ("Controller is not the SAS SCSI one\n"));
3314
3315	LogFlowFunc(("pThis=%#p\n", pThis));
3316
3317	/* Manufacturing Page 7 - Connector settings. */
3318	pPages->cbManufacturingPage7 = LSILOGICSCSI_MANUFACTURING7_GET_SIZE(pThis->cPorts);
3319	PMptConfigurationPageManufacturing7 pManufacturingPage7 = (PMptConfigurationPageManufacturing7)RTMemAllocZ(pPages->cbManufacturingPage7);
3320	AssertPtr(pManufacturingPage7);
3321	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(pManufacturingPage7,
3322	0, 7,
3323	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3324	/* Set size manually. */
3325	if (pPages->cbManufacturingPage7 / 4 > 255)
3326	pManufacturingPage7->u.fields.Header.u8PageLength = 255;
3327	else
3328	pManufacturingPage7->u.fields.Header.u8PageLength = pPages->cbManufacturingPage7 / 4;
3329	pManufacturingPage7->u.fields.u8NumPhys = pThis->cPorts;
3330	pPages->pManufacturingPage7 = pManufacturingPage7;
3331
3332	/* SAS I/O unit page 0 - Port specific information. */
3333	pPages->cbSASIOUnitPage0 = LSILOGICSCSI_SASIOUNIT0_GET_SIZE(pThis->cPorts);
3334	PMptConfigurationPageSASIOUnit0 pSASPage0 = (PMptConfigurationPageSASIOUnit0)RTMemAllocZ(pPages->cbSASIOUnitPage0);
3335	AssertPtr(pSASPage0);
3336
3337	MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage0, pPages->cbSASIOUnitPage0,
3338	0, MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY,
3339	MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3340	pSASPage0->u.fields.u8NumPhys = pThis->cPorts;
3341	pPages->pSASIOUnitPage0 = pSASPage0;
3342
3343	/* SAS I/O unit page 1 - Port specific settings. */
3344	pPages->cbSASIOUnitPage1 = LSILOGICSCSI_SASIOUNIT1_GET_SIZE(pThis->cPorts);
3345	PMptConfigurationPageSASIOUnit1 pSASPage1 = (PMptConfigurationPageSASIOUnit1)RTMemAllocZ(pPages->cbSASIOUnitPage1);
3346	AssertPtr(pSASPage1);
3347
3348	MPT_CONFIG_EXTENDED_PAGE_HEADER_INIT(pSASPage1, pPages->cbSASIOUnitPage1,
3349	1, MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE,
3350	MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT);
3351	pSASPage1->u.fields.u8NumPhys = pSASPage0->u.fields.u8NumPhys;
3352	pSASPage1->u.fields.u16ControlFlags = 0;
3353	pSASPage1->u.fields.u16AdditionalControlFlags = 0;
3354	pPages->pSASIOUnitPage1 = pSASPage1;
3355
3356	/* SAS I/O unit page 2 - Port specific information. */
3357	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3358	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3359	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8PageNumber = 2;
3360	pPages->SASIOUnitPage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3361	pPages->SASIOUnitPage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit2) / 4;
3362
3363	/* SAS I/O unit page 3 - Port specific information. */
3364	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3365	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3366	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8PageNumber = 3;
3367	pPages->SASIOUnitPage3.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASIOUNIT;
3368	pPages->SASIOUnitPage3.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASIOUnit3) / 4;
3369
3370	pPages->cPHYs = pThis->cPorts;
3371	pPages->paPHYs = (PMptPHY)RTMemAllocZ(pPages->cPHYs * sizeof(MptPHY));
3372	AssertPtr(pPages->paPHYs);
3373
3374	/* Initialize the PHY configuration */
3375	for (unsigned i = 0; i < pThis->cPorts; i++)
3376	{
3377	PMptPHY pPHYPages = &pPages->paPHYs[i];
3378	uint16_t u16ControllerHandle = lsilogicGetHandle(pThis);
3379
3380	pManufacturingPage7->u.fields.aPHY[i].u8Location = LSILOGICSCSI_MANUFACTURING7_LOCATION_AUTO;
3381
3382	pSASPage0->u.fields.aPHY[i].u8Port = i;
3383	pSASPage0->u.fields.aPHY[i].u8PortFlags = 0;
3384	pSASPage0->u.fields.aPHY[i].u8PhyFlags = 0;
3385	pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_FAILED;
3386	pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3387	pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16ControllerHandle;
3388	pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = 0; /* No device attached. */
3389	pSASPage0->u.fields.aPHY[i].u32DiscoveryStatus = 0; /* No errors */
3390
3391	pSASPage1->u.fields.aPHY[i].u8Port = i;
3392	pSASPage1->u.fields.aPHY[i].u8PortFlags = 0;
3393	pSASPage1->u.fields.aPHY[i].u8PhyFlags = 0;
3394	pSASPage1->u.fields.aPHY[i].u8MaxMinLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3395	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3396	pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_NO);
3397
3398	/* SAS PHY page 0. */
3399	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3400	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3401	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8PageNumber = 0;
3402	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3403	pPHYPages->SASPHYPage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY0) / 4;
3404	pPHYPages->SASPHYPage0.u.fields.u8AttachedPhyIdentifier = i;
3405	pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_NO);
3406	pPHYPages->SASPHYPage0.u.fields.u8ProgrammedLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3407	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3408	pPHYPages->SASPHYPage0.u.fields.u8HwLinkRate = LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MIN_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_15GB)
3409	\| LSILOGICSCSI_SASIOUNIT1_LINK_RATE_MAX_SET(LSILOGICSCSI_SASIOUNIT1_LINK_RATE_30GB);
3410
3411	/* SAS PHY page 1. */
3412	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3413	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3414	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8PageNumber = 1;
3415	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASPHYS;
3416	pPHYPages->SASPHYPage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASPHY1) / 4;
3417
3418	/* Settings for present devices. */
3419	if (pThis->paDeviceStates[i].pDrvBase)
3420	{
3421	uint16_t u16DeviceHandle = lsilogicGetHandle(pThis);
3422	SASADDRESS SASAddress;
3423	PMptSASDevice pSASDevice = (PMptSASDevice)RTMemAllocZ(sizeof(MptSASDevice));
3424	AssertPtr(pSASDevice);
3425
3426	memset(&SASAddress, 0, sizeof(SASADDRESS));
3427	lsilogicSASAddressGenerate(&SASAddress, i);
3428
3429	pSASPage0->u.fields.aPHY[i].u8NegotiatedLinkRate = LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_SET(LSILOGICSCSI_SASIOUNIT0_NEGOTIATED_RATE_30GB);
3430	pSASPage0->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3431	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3432	pSASPage0->u.fields.aPHY[i].u16AttachedDevHandle = u16DeviceHandle;
3433	pSASPage1->u.fields.aPHY[i].u32ControllerPhyDeviceInfo = LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_SET(LSILOGICSCSI_SASIOUNIT0_DEVICE_TYPE_END)
3434	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3435	pSASPage0->u.fields.aPHY[i].u16ControllerDevHandle = u16DeviceHandle;
3436
3437	pPHYPages->SASPHYPage0.u.fields.u32AttachedDeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END);
3438	pPHYPages->SASPHYPage0.u.fields.SASAddress = SASAddress;
3439	pPHYPages->SASPHYPage0.u.fields.u16OwnerDevHandle = u16DeviceHandle;
3440	pPHYPages->SASPHYPage0.u.fields.u16AttachedDevHandle = u16DeviceHandle;
3441
3442	/* SAS device page 0. */
3443	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3444	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3445	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8PageNumber = 0;
3446	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3447	pSASDevice->SASDevicePage0.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice0) / 4;
3448	pSASDevice->SASDevicePage0.u.fields.SASAddress = SASAddress;
3449	pSASDevice->SASDevicePage0.u.fields.u16ParentDevHandle = u16ControllerHandle;
3450	pSASDevice->SASDevicePage0.u.fields.u8PhyNum = i;
3451	pSASDevice->SASDevicePage0.u.fields.u8AccessStatus = LSILOGICSCSI_SASDEVICE0_STATUS_NO_ERRORS;
3452	pSASDevice->SASDevicePage0.u.fields.u16DevHandle = u16DeviceHandle;
3453	pSASDevice->SASDevicePage0.u.fields.u8TargetID = i;
3454	pSASDevice->SASDevicePage0.u.fields.u8Bus = 0;
3455	pSASDevice->SASDevicePage0.u.fields.u32DeviceInfo = LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_SET(LSILOGICSCSI_SASPHY0_DEV_INFO_DEVICE_TYPE_END)
3456	\| LSILOGICSCSI_SASIOUNIT0_DEVICE_SSP_TARGET;
3457	pSASDevice->SASDevicePage0.u.fields.u16Flags = LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_PRESENT
3458	\| LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPED_TO_BUS_AND_TARGET_ID
3459	\| LSILOGICSCSI_SASDEVICE0_FLAGS_DEVICE_MAPPING_PERSISTENT;
3460	pSASDevice->SASDevicePage0.u.fields.u8PhysicalPort = i;
3461
3462	/* SAS device page 1. */
3463	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3464	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3465	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8PageNumber = 1;
3466	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3467	pSASDevice->SASDevicePage1.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice1) / 4;
3468	pSASDevice->SASDevicePage1.u.fields.SASAddress = SASAddress;
3469	pSASDevice->SASDevicePage1.u.fields.u16DevHandle = u16DeviceHandle;
3470	pSASDevice->SASDevicePage1.u.fields.u8TargetID = i;
3471	pSASDevice->SASDevicePage1.u.fields.u8Bus = 0;
3472
3473	/* SAS device page 2. */
3474	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageType = MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY
3475	\| MPT_CONFIGURATION_PAGE_TYPE_EXTENDED;
3476	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8PageNumber = 2;
3477	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u8ExtPageType = MPT_CONFIGURATION_PAGE_TYPE_EXTENDED_SASDEVICE;
3478	pSASDevice->SASDevicePage2.u.fields.ExtHeader.u16ExtPageLength = sizeof(MptConfigurationPageSASDevice2) / 4;
3479	pSASDevice->SASDevicePage2.u.fields.SASAddress = SASAddress;
3480
3481	/* Link into device list. */
3482	if (!pPages->cDevices)
3483	{
3484	pPages->pSASDeviceHead = pSASDevice;
3485	pPages->pSASDeviceTail = pSASDevice;
3486	pPages->cDevices = 1;
3487	}
3488	else
3489	{
3490	pSASDevice->pPrev = pPages->pSASDeviceTail;
3491	pPages->pSASDeviceTail->pNext = pSASDevice;
3492	pPages->pSASDeviceTail = pSASDevice;
3493	pPages->cDevices++;
3494	}
3495	}
3496	}
3497	}
3498
3499	/**
3500	* Initializes the configuration pages.
3501	*
3502	* @returns nothing
3503	* @param pThis Pointer to the LsiLogic device state.
3504	*/
3505	static void lsilogicR3InitializeConfigurationPages(PLSILOGICSCSI pThis)
3506	{
3507	/* Initialize the common pages. */
3508	PMptConfigurationPagesSupported pPages = (PMptConfigurationPagesSupported)RTMemAllocZ(sizeof(MptConfigurationPagesSupported));
3509
3510	pThis->pConfigurationPages = pPages;
3511
3512	LogFlowFunc(("pThis=%#p\n", pThis));
3513
3514	/* Clear everything first. */
3515	memset(pPages, 0, sizeof(MptConfigurationPagesSupported));
3516
3517	/* Manufacturing Page 0. */
3518	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage0,
3519	MptConfigurationPageManufacturing0, 0,
3520	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3521	strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipName, "VBox MPT Fusion", 16);
3522	strncpy((char *)pPages->ManufacturingPage0.u.fields.abChipRevision, "1.0", 8);
3523	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardName, "VBox MPT Fusion", 16);
3524	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardAssembly, "SUN", 8);
3525	strncpy((char *)pPages->ManufacturingPage0.u.fields.abBoardTracerNumber, "CAFECAFECAFECAFE", 16);
3526
3527	/* Manufacturing Page 1 - I don't know what this contains so we leave it 0 for now. */
3528	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage1,
3529	MptConfigurationPageManufacturing1, 1,
3530	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3531
3532	/* Manufacturing Page 2. */
3533	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage2,
3534	MptConfigurationPageManufacturing2, 2,
3535	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3536
3537	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3538	{
3539	pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3540	pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3541	}
3542	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3543	{
3544	pPages->ManufacturingPage2.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3545	pPages->ManufacturingPage2.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3546	}
3547
3548	/* Manufacturing Page 3. */
3549	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage3,
3550	MptConfigurationPageManufacturing3, 3,
3551	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3552
3553	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3554	{
3555	pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3556	pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3557	}
3558	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3559	{
3560	pPages->ManufacturingPage3.u.fields.u16PCIDeviceID = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3561	pPages->ManufacturingPage3.u.fields.u8PCIRevisionID = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3562	}
3563
3564	/* Manufacturing Page 4 - I don't know what this contains so we leave it 0 for now. */
3565	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage4,
3566	MptConfigurationPageManufacturing4, 4,
3567	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3568
3569	/* Manufacturing Page 5 - WWID settings. */
3570	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage5,
3571	MptConfigurationPageManufacturing5, 5,
3572	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT_READONLY);
3573
3574	/* Manufacturing Page 6 - Product specific settings. */
3575	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage6,
3576	MptConfigurationPageManufacturing6, 6,
3577	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3578
3579	/* Manufacturing Page 8 - Product specific settings. */
3580	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage8,
3581	MptConfigurationPageManufacturing8, 8,
3582	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3583
3584	/* Manufacturing Page 9 - Product specific settings. */
3585	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage9,
3586	MptConfigurationPageManufacturing9, 9,
3587	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3588
3589	/* Manufacturing Page 10 - Product specific settings. */
3590	MPT_CONFIG_PAGE_HEADER_INIT_MANUFACTURING(&pPages->ManufacturingPage10,
3591	MptConfigurationPageManufacturing10, 10,
3592	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3593
3594	/* I/O Unit page 0. */
3595	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage0,
3596	MptConfigurationPageIOUnit0, 0,
3597	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3598	pPages->IOUnitPage0.u.fields.u64UniqueIdentifier = 0xcafe;
3599
3600	/* I/O Unit page 1. */
3601	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage1,
3602	MptConfigurationPageIOUnit1, 1,
3603	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3604	pPages->IOUnitPage1.u.fields.fSingleFunction = true;
3605	pPages->IOUnitPage1.u.fields.fAllPathsMapped = false;
3606	pPages->IOUnitPage1.u.fields.fIntegratedRAIDDisabled = true;
3607	pPages->IOUnitPage1.u.fields.f32BitAccessForced = false;
3608
3609	/* I/O Unit page 2. */
3610	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage2,
3611	MptConfigurationPageIOUnit2, 2,
3612	MPT_CONFIGURATION_PAGE_ATTRIBUTE_PERSISTENT);
3613	pPages->IOUnitPage2.u.fields.fPauseOnError = false;
3614	pPages->IOUnitPage2.u.fields.fVerboseModeEnabled = false;
3615	pPages->IOUnitPage2.u.fields.fDisableColorVideo = false;
3616	pPages->IOUnitPage2.u.fields.fNotHookInt40h = false;
3617	pPages->IOUnitPage2.u.fields.u32BIOSVersion = 0xcafecafe;
3618	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEnabled = true;
3619	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].fAdapterEmbedded = true;
3620	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIBusNumber = 0;
3621	pPages->IOUnitPage2.u.fields.aAdapterOrder[0].u8PCIDevFn = pThis->PciDev.devfn;
3622
3623	/* I/O Unit page 3. */
3624	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage3,
3625	MptConfigurationPageIOUnit3, 3,
3626	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3627	pPages->IOUnitPage3.u.fields.u8GPIOCount = 0;
3628
3629	/* I/O Unit page 4. */
3630	MPT_CONFIG_PAGE_HEADER_INIT_IO_UNIT(&pPages->IOUnitPage4,
3631	MptConfigurationPageIOUnit4, 4,
3632	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3633
3634	/* IOC page 0. */
3635	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage0,
3636	MptConfigurationPageIOC0, 0,
3637	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3638	pPages->IOCPage0.u.fields.u32TotalNVStore = 0;
3639	pPages->IOCPage0.u.fields.u32FreeNVStore = 0;
3640
3641	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3642	{
3643	pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3644	pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SPI_DEVICE_ID;
3645	pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SPI_REVISION_ID;
3646	pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SPI_CLASS_CODE;
3647	pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID;
3648	pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID;
3649	}
3650	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3651	{
3652	pPages->IOCPage0.u.fields.u16VendorId = LSILOGICSCSI_PCI_VENDOR_ID;
3653	pPages->IOCPage0.u.fields.u16DeviceId = LSILOGICSCSI_PCI_SAS_DEVICE_ID;
3654	pPages->IOCPage0.u.fields.u8RevisionId = LSILOGICSCSI_PCI_SAS_REVISION_ID;
3655	pPages->IOCPage0.u.fields.u32ClassCode = LSILOGICSCSI_PCI_SAS_CLASS_CODE;
3656	pPages->IOCPage0.u.fields.u16SubsystemVendorId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID;
3657	pPages->IOCPage0.u.fields.u16SubsystemId = LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID;
3658	}
3659
3660	/* IOC page 1. */
3661	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage1,
3662	MptConfigurationPageIOC1, 1,
3663	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3664	pPages->IOCPage1.u.fields.fReplyCoalescingEnabled = false;
3665	pPages->IOCPage1.u.fields.u32CoalescingTimeout = 0;
3666	pPages->IOCPage1.u.fields.u8CoalescingDepth = 0;
3667
3668	/* IOC page 2. */
3669	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage2,
3670	MptConfigurationPageIOC2, 2,
3671	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3672	/* Everything else here is 0. */
3673
3674	/* IOC page 3. */
3675	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage3,
3676	MptConfigurationPageIOC3, 3,
3677	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3678	/* Everything else here is 0. */
3679
3680	/* IOC page 4. */
3681	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage4,
3682	MptConfigurationPageIOC4, 4,
3683	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3684	/* Everything else here is 0. */
3685
3686	/* IOC page 6. */
3687	MPT_CONFIG_PAGE_HEADER_INIT_IOC(&pPages->IOCPage6,
3688	MptConfigurationPageIOC6, 6,
3689	MPT_CONFIGURATION_PAGE_ATTRIBUTE_READONLY);
3690	/* Everything else here is 0. */
3691
3692	/* BIOS page 1. */
3693	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage1,
3694	MptConfigurationPageBIOS1, 1,
3695	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3696
3697	/* BIOS page 2. */
3698	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage2,
3699	MptConfigurationPageBIOS2, 2,
3700	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3701
3702	/* BIOS page 4. */
3703	MPT_CONFIG_PAGE_HEADER_INIT_BIOS(&pPages->BIOSPage4,
3704	MptConfigurationPageBIOS4, 4,
3705	MPT_CONFIGURATION_PAGE_ATTRIBUTE_CHANGEABLE);
3706
3707	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
3708	lsilogicR3InitializeConfigurationPagesSpi(pThis);
3709	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
3710	lsilogicR3InitializeConfigurationPagesSas(pThis);
3711	else
3712	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
3713	}
3714
3715	/**
3716	* @callback_method_impl{FNPDMQUEUEDEV, Transmit queue consumer.}
3717	*/
3718	static DECLCALLBACK(bool) lsilogicR3NotifyQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3719	{
3720	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3721	int rc = VINF_SUCCESS;
3722
3723	LogFlowFunc(("pDevIns=%#p pItem=%#p\n", pDevIns, pItem));
3724
3725	rc = SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
3726	AssertRC(rc);
3727
3728	return true;
3729	}
3730
3731	/**
3732	* Sets the emulated controller type from a given string.
3733	*
3734	* @returns VBox status code.
3735	*
3736	* @param pThis Pointer to the LsiLogic device state.
3737	* @param pcszCtrlType The string to use.
3738	*/
3739	static int lsilogicR3GetCtrlTypeFromString(PLSILOGICSCSI pThis, const char *pcszCtrlType)
3740	{
3741	int rc = VERR_INVALID_PARAMETER;
3742
3743	if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME))
3744	{
3745	pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SPI;
3746	rc = VINF_SUCCESS;
3747	}
3748	else if (!RTStrCmp(pcszCtrlType, LSILOGICSCSI_PCI_SAS_CTRLNAME))
3749	{
3750	pThis->enmCtrlType = LSILOGICCTRLTYPE_SCSI_SAS;
3751	rc = VINF_SUCCESS;
3752	}
3753
3754	return rc;
3755	}
3756
3757	/**
3758	* @callback_method_impl{FNIOMIOPORTIN, Legacy ISA port.}
3759	*/
3760	static DECLCALLBACK(int) lsilogicR3IsaIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
3761	{
3762	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3763
3764	Assert(cb == 1);
3765
3766	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3767	? Port - LSILOGIC_BIOS_IO_PORT
3768	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3769	int rc = vboxscsiReadRegister(&pThis->VBoxSCSI, iRegister, pu32);
3770
3771	Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",
3772	__FUNCTION__, pu32, 1, pu32, iRegister, rc));
3773
3774	return rc;
3775	}
3776
3777	/**
3778	* Prepares a request from the BIOS.
3779	*
3780	* @returns VBox status code.
3781	* @param pThis Pointer to the LsiLogic device state.
3782	*/
3783	static int lsilogicR3PrepareBiosScsiRequest(PLSILOGICSCSI pThis)
3784	{
3785	int rc;
3786	PLSILOGICREQ pLsiReq;
3787	uint32_t uTargetDevice;
3788
3789	rc = RTMemCacheAllocEx(pThis->hTaskCache, (void **)&pLsiReq);
3790	AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);
3791
3792	pLsiReq->fBIOS = true;
3793
3794	rc = vboxscsiSetupRequest(&pThis->VBoxSCSI, &pLsiReq->PDMScsiRequest, &uTargetDevice);
3795	AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);
3796
3797	pLsiReq->PDMScsiRequest.pvUser = pLsiReq;
3798
3799	if (uTargetDevice < pThis->cDeviceStates)
3800	{
3801	pLsiReq->pTargetDevice = &pThis->paDeviceStates[uTargetDevice];
3802
3803	if (pLsiReq->pTargetDevice->pDrvBase)
3804	{
3805	ASMAtomicIncU32(&pLsiReq->pTargetDevice->cOutstandingRequests);
3806
3807	rc = pLsiReq->pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pLsiReq->pTargetDevice->pDrvSCSIConnector,
3808	&pLsiReq->PDMScsiRequest);
3809	AssertMsgRCReturn(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc), rc);
3810	return VINF_SUCCESS;
3811	}
3812	}
3813
3814	/* Device is not present. */
3815	AssertMsg(pLsiReq->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,
3816	("Device is not present but command is not inquiry\n"));
3817
3818	SCSIINQUIRYDATA ScsiInquiryData;
3819
3820	memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));
3821	ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;
3822	ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;
3823
3824	memcpy(pThis->VBoxSCSI.pbBuf, &ScsiInquiryData, 5);
3825
3826	rc = vboxscsiRequestFinished(&pThis->VBoxSCSI, &pLsiReq->PDMScsiRequest, SCSI_STATUS_OK);
3827	AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);
3828
3829	RTMemCacheFree(pThis->hTaskCache, pLsiReq);
3830	return rc;
3831	}
3832
3833	/**
3834	* @callback_method_impl{FNIOMIOPORTOUT, Legacy ISA port.}
3835	*/
3836	static DECLCALLBACK(int) lsilogicR3IsaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3837	{
3838	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3839	Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));
3840
3841	Assert(cb == 1);
3842
3843	/*
3844	* If there is already a request form the BIOS pending ignore this write
3845	* because it should not happen.
3846	*/
3847	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
3848	return VINF_SUCCESS;
3849
3850	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3851	? Port - LSILOGIC_BIOS_IO_PORT
3852	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3853	int rc = vboxscsiWriteRegister(&pThis->VBoxSCSI, iRegister, (uint8_t)u32);
3854	if (rc == VERR_MORE_DATA)
3855	{
3856	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3857	/* Send a notifier to the PDM queue that there are pending requests. */
3858	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3859	AssertMsg(pItem, ("Allocating item for queue failed\n"));
3860	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3861	}
3862	else if (RT_FAILURE(rc))
3863	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3864
3865	return VINF_SUCCESS;
3866	}
3867
3868	/**
3869	* @callback_method_impl{FNIOMIOPORTOUTSTRING,
3870	* Port I/O Handler for primary port range OUT string operations.}
3871	*/
3872	static DECLCALLBACK(int) lsilogicR3IsaIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3873	uint8_t const pbSrc, uint32_t pcTransfers, unsigned cb)
3874	{
3875	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3876	Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3877
3878	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3879	? Port - LSILOGIC_BIOS_IO_PORT
3880	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3881	int rc = vboxscsiWriteString(pDevIns, &pThis->VBoxSCSI, iRegister, pbSrc, pcTransfers, cb);
3882	if (rc == VERR_MORE_DATA)
3883	{
3884	ASMAtomicXchgBool(&pThis->fBiosReqPending, true);
3885	/* Send a notifier to the PDM queue that there are pending requests. */
3886	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
3887	AssertMsg(pItem, ("Allocating item for queue failed\n"));
3888	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
3889	}
3890	else if (RT_FAILURE(rc))
3891	AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));
3892
3893	return rc;
3894	}
3895
3896	/**
3897	* @callback_method_impl{FNIOMIOPORTINSTRING,
3898	* Port I/O Handler for primary port range IN string operations.}
3899	*/
3900	static DECLCALLBACK(int) lsilogicR3IsaIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port,
3901	uint8_t pbDst, uint32_t pcTransfers, unsigned cb)
3902	{
3903	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3904	LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n", pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));
3905
3906	uint8_t iRegister = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3907	? Port - LSILOGIC_BIOS_IO_PORT
3908	: Port - LSILOGIC_SAS_BIOS_IO_PORT;
3909	return vboxscsiReadString(pDevIns, &pThis->VBoxSCSI, iRegister, pbDst, pcTransfers, cb);
3910	}
3911
3912	/**
3913	* @callback_method_impl{FNPCIIOREGIONMAP}
3914	*/
3915	static DECLCALLBACK(int) lsilogicR3Map(PPCIDEVICE pPciDev, /unsigned/ int iRegion,
3916	RTGCPHYS GCPhysAddress, uint32_t cb,
3917	PCIADDRESSSPACE enmType)
3918	{
3919	PPDMDEVINS pDevIns = pPciDev->pDevIns;
3920	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
3921	int rc = VINF_SUCCESS;
3922	const char *pcszCtrl = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3923	? "LsiLogic"
3924	: "LsiLogicSas";
3925	const char *pcszDiag = pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
3926	? "LsiLogicDiag"
3927	: "LsiLogicSasDiag";
3928
3929	Log2(("%s: registering area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
3930
3931	AssertMsg( (enmType == PCI_ADDRESS_SPACE_MEM && cb >= LSILOGIC_PCI_SPACE_MEM_SIZE)
3932	\|\| (enmType == PCI_ADDRESS_SPACE_IO && cb >= LSILOGIC_PCI_SPACE_IO_SIZE),
3933	("PCI region type and size do not match\n"));
3934
3935	if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 1)
3936	{
3937	/*
3938	* Non-4-byte read access to LSILOGIC_REG_REPLY_QUEUE may cause real strange behavior
3939	* because the data is part of a physical guest address. But some drivers use 1-byte
3940	* access to scan for SCSI controllers. So, we simplify our code by telling IOM to
3941	* read DWORDs.
3942	*
3943	* Regarding writes, we couldn't find anything specific in the specs about what should
3944	* happen. So far we've ignored unaligned writes and assumed the missing bytes of
3945	* byte and word access to be zero. We suspect that IOMMMIO_FLAGS_WRITE_ONLY_DWORD
3946	* or IOMMMIO_FLAGS_WRITE_DWORD_ZEROED would be the most appropriate here, but since we
3947	* don't have real hw to test one, the old behavior is kept exactly like it used to be.
3948	*/
3949	/** @todo Check out unaligned writes and non-dword writes on real LsiLogic
3950	* hardware. */
3951	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3952	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3953	lsilogicMMIOWrite, lsilogicMMIORead, pcszCtrl);
3954	if (RT_FAILURE(rc))
3955	return rc;
3956
3957	if (pThis->fR0Enabled)
3958	{
3959	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3960	"lsilogicMMIOWrite", "lsilogicMMIORead");
3961	if (RT_FAILURE(rc))
3962	return rc;
3963	}
3964
3965	if (pThis->fGCEnabled)
3966	{
3967	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3968	"lsilogicMMIOWrite", "lsilogicMMIORead");
3969	if (RT_FAILURE(rc))
3970	return rc;
3971	}
3972
3973	pThis->GCPhysMMIOBase = GCPhysAddress;
3974	}
3975	else if (enmType == PCI_ADDRESS_SPACE_MEM && iRegion == 2)
3976	{
3977	/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
3978	rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3979	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3980	lsilogicDiagnosticWrite, lsilogicDiagnosticRead, pcszDiag);
3981	if (RT_FAILURE(rc))
3982	return rc;
3983
3984	if (pThis->fR0Enabled)
3985	{
3986	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3987	"lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
3988	if (RT_FAILURE(rc))
3989	return rc;
3990	}
3991
3992	if (pThis->fGCEnabled)
3993	{
3994	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3995	"lsilogicDiagnosticWrite", "lsilogicDiagnosticRead");
3996	if (RT_FAILURE(rc))
3997	return rc;
3998	}
3999	}
4000	else if (enmType == PCI_ADDRESS_SPACE_IO)
4001	{
4002	rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4003	NULL, lsilogicIOPortWrite, lsilogicIOPortRead, NULL, NULL, pcszCtrl);
4004	if (RT_FAILURE(rc))
4005	return rc;
4006
4007	if (pThis->fR0Enabled)
4008	{
4009	rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4010	0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4011	if (RT_FAILURE(rc))
4012	return rc;
4013	}
4014
4015	if (pThis->fGCEnabled)
4016	{
4017	rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, LSILOGIC_PCI_SPACE_IO_SIZE,
4018	0, "lsilogicIOPortWrite", "lsilogicIOPortRead", NULL, NULL, pcszCtrl);
4019	if (RT_FAILURE(rc))
4020	return rc;
4021	}
4022
4023	pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
4024	}
4025	else
4026	AssertMsgFailed(("Invalid enmType=%d iRegion=%d\n", enmType, iRegion));
4027
4028	return rc;
4029	}
4030
4031	/**
4032	* @callback_method_impl{PFNDBGFHANDLERDEV}
4033	*/
4034	static DECLCALLBACK(void) lsilogicR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4035	{
4036	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4037	bool fVerbose = false;
4038
4039	/*
4040	* Parse args.
4041	*/
4042	if (pszArgs)
4043	fVerbose = strstr(pszArgs, "verbose") != NULL;
4044
4045	/*
4046	* Show info.
4047	*/
4048	pHlp->pfnPrintf(pHlp,
4049	"%s#%d: port=%RTiop mmio=%RGp max-devices=%u GC=%RTbool R0=%RTbool\n",
4050	pDevIns->pReg->szName,
4051	pDevIns->iInstance,
4052	pThis->IOPortBase, pThis->GCPhysMMIOBase,
4053	pThis->cDeviceStates,
4054	pThis->fGCEnabled ? true : false,
4055	pThis->fR0Enabled ? true : false);
4056
4057	/*
4058	* Show general state.
4059	*/
4060	pHlp->pfnPrintf(pHlp, "enmState=%u\n", pThis->enmState);
4061	pHlp->pfnPrintf(pHlp, "enmWhoInit=%u\n", pThis->enmWhoInit);
4062	pHlp->pfnPrintf(pHlp, "enmDoorbellState=%d\n", pThis->enmDoorbellState);
4063	pHlp->pfnPrintf(pHlp, "fDiagnosticEnabled=%RTbool\n", pThis->fDiagnosticEnabled);
4064	pHlp->pfnPrintf(pHlp, "fNotificationSent=%RTbool\n", pThis->fNotificationSent);
4065	pHlp->pfnPrintf(pHlp, "fEventNotificationEnabled=%RTbool\n", pThis->fEventNotificationEnabled);
4066	pHlp->pfnPrintf(pHlp, "uInterruptMask=%#x\n", pThis->uInterruptMask);
4067	pHlp->pfnPrintf(pHlp, "uInterruptStatus=%#x\n", pThis->uInterruptStatus);
4068	pHlp->pfnPrintf(pHlp, "u16IOCFaultCode=%#06x\n", pThis->u16IOCFaultCode);
4069	pHlp->pfnPrintf(pHlp, "u32HostMFAHighAddr=%#x\n", pThis->u32HostMFAHighAddr);
4070	pHlp->pfnPrintf(pHlp, "u32SenseBufferHighAddr=%#x\n", pThis->u32SenseBufferHighAddr);
4071	pHlp->pfnPrintf(pHlp, "cMaxDevices=%u\n", pThis->cMaxDevices);
4072	pHlp->pfnPrintf(pHlp, "cMaxBuses=%u\n", pThis->cMaxBuses);
4073	pHlp->pfnPrintf(pHlp, "cbReplyFrame=%u\n", pThis->cbReplyFrame);
4074	pHlp->pfnPrintf(pHlp, "cReplyQueueEntries=%u\n", pThis->cReplyQueueEntries);
4075	pHlp->pfnPrintf(pHlp, "cRequestQueueEntries=%u\n", pThis->cRequestQueueEntries);
4076	pHlp->pfnPrintf(pHlp, "cPorts=%u\n", pThis->cPorts);
4077
4078	/*
4079	* Show queue status.
4080	*/
4081	pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextEntryFreeWrite=%u\n", pThis->uReplyFreeQueueNextEntryFreeWrite);
4082	pHlp->pfnPrintf(pHlp, "uReplyFreeQueueNextAddressRead=%u\n", pThis->uReplyFreeQueueNextAddressRead);
4083	pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextEntryFreeWrite=%u\n", pThis->uReplyPostQueueNextEntryFreeWrite);
4084	pHlp->pfnPrintf(pHlp, "uReplyPostQueueNextAddressRead=%u\n", pThis->uReplyPostQueueNextAddressRead);
4085	pHlp->pfnPrintf(pHlp, "uRequestQueueNextEntryFreeWrite=%u\n", pThis->uRequestQueueNextEntryFreeWrite);
4086	pHlp->pfnPrintf(pHlp, "uRequestQueueNextAddressRead=%u\n", pThis->uRequestQueueNextAddressRead);
4087
4088	/*
4089	* Show queue content if verbose
4090	*/
4091	if (fVerbose)
4092	{
4093	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4094	pHlp->pfnPrintf(pHlp, "RFQ[%u]=%#x\n", i, pThis->pReplyFreeQueueBaseR3[i]);
4095
4096	pHlp->pfnPrintf(pHlp, "\n");
4097
4098	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4099	pHlp->pfnPrintf(pHlp, "RPQ[%u]=%#x\n", i, pThis->pReplyPostQueueBaseR3[i]);
4100
4101	pHlp->pfnPrintf(pHlp, "\n");
4102
4103	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4104	pHlp->pfnPrintf(pHlp, "ReqQ[%u]=%#x\n", i, pThis->pRequestQueueBaseR3[i]);
4105	}
4106
4107	/*
4108	* Print the device status.
4109	*/
4110	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4111	{
4112	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4113
4114	pHlp->pfnPrintf(pHlp, "\n");
4115
4116	pHlp->pfnPrintf(pHlp, "Device[%u]: device-attached=%RTbool cOutstandingRequests=%u\n",
4117	i, pDevice->pDrvBase != NULL, pDevice->cOutstandingRequests);
4118	}
4119	}
4120
4121	/**
4122	* Allocate the queues.
4123	*
4124	* @returns VBox status code.
4125	*
4126	* @param pThis Pointer to the LsiLogic device state.
4127	*/
4128	static int lsilogicR3QueuesAlloc(PLSILOGICSCSI pThis)
4129	{
4130	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4131	uint32_t cbQueues;
4132
4133	Assert(!pThis->pReplyFreeQueueBaseR3);
4134
4135	cbQueues = 2pThis->cReplyQueueEntries sizeof(uint32_t);
4136	cbQueues += pThis->cRequestQueueEntries * sizeof(uint32_t);
4137	int rc = MMHyperAlloc(pVM, cbQueues, 1, MM_TAG_PDM_DEVICE_USER,
4138	(void **)&pThis->pReplyFreeQueueBaseR3);
4139	if (RT_FAILURE(rc))
4140	return VERR_NO_MEMORY;
4141	pThis->pReplyFreeQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4142	pThis->pReplyFreeQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4143
4144	pThis->pReplyPostQueueBaseR3 = pThis->pReplyFreeQueueBaseR3 + pThis->cReplyQueueEntries;
4145	pThis->pReplyPostQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4146	pThis->pReplyPostQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pReplyPostQueueBaseR3);
4147
4148	pThis->pRequestQueueBaseR3 = pThis->pReplyPostQueueBaseR3 + pThis->cReplyQueueEntries;
4149	pThis->pRequestQueueBaseR0 = MMHyperR3ToR0(pVM, (void *)pThis->pRequestQueueBaseR3);
4150	pThis->pRequestQueueBaseRC = MMHyperR3ToRC(pVM, (void *)pThis->pRequestQueueBaseR3);
4151
4152	return VINF_SUCCESS;
4153	}
4154
4155	/**
4156	* Free the hyper memory used or the queues.
4157	*
4158	* @returns nothing.
4159	*
4160	* @param pThis Pointer to the LsiLogic device state.
4161	*/
4162	static void lsilogicR3QueuesFree(PLSILOGICSCSI pThis)
4163	{
4164	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4165	int rc = VINF_SUCCESS;
4166
4167	AssertPtr(pThis->pReplyFreeQueueBaseR3);
4168
4169	rc = MMHyperFree(pVM, (void *)pThis->pReplyFreeQueueBaseR3);
4170	AssertRC(rc);
4171
4172	pThis->pReplyFreeQueueBaseR3 = NULL;
4173	pThis->pReplyPostQueueBaseR3 = NULL;
4174	pThis->pRequestQueueBaseR3 = NULL;
4175	}
4176
4177
4178	/* The worker thread. */
4179	static DECLCALLBACK(int) lsilogicR3Worker(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4180	{
4181	PLSILOGICSCSI pThis = (PLSILOGICSCSI)pThread->pvUser;
4182	int rc = VINF_SUCCESS;
4183
4184	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4185	return VINF_SUCCESS;
4186
4187	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4188	{
4189	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, true);
4190	bool fNotificationSent = ASMAtomicXchgBool(&pThis->fNotificationSent, false);
4191	if (!fNotificationSent)
4192	{
4193	Assert(ASMAtomicReadBool(&pThis->fWrkThreadSleeping));
4194	rc = SUPSemEventWaitNoResume(pThis->pSupDrvSession, pThis->hEvtProcess, RT_INDEFINITE_WAIT);
4195	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4196	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4197	break;
4198	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4199	ASMAtomicWriteBool(&pThis->fNotificationSent, false);
4200	}
4201
4202	ASMAtomicWriteBool(&pThis->fWrkThreadSleeping, false);
4203
4204	/* Check whether there is a BIOS request pending and process it first. */
4205	if (ASMAtomicReadBool(&pThis->fBiosReqPending))
4206	{
4207	rc = lsilogicR3PrepareBiosScsiRequest(pThis);
4208	AssertRC(rc);
4209	ASMAtomicXchgBool(&pThis->fBiosReqPending, false);
4210	}
4211
4212	/* Only process request which arrived before we received the notification. */
4213	uint32_t uRequestQueueNextEntryWrite = ASMAtomicReadU32(&pThis->uRequestQueueNextEntryFreeWrite);
4214
4215	/* Go through the messages now and process them. */
4216	while ( RT_LIKELY(pThis->enmState == LSILOGICSTATE_OPERATIONAL)
4217	&& (pThis->uRequestQueueNextAddressRead != uRequestQueueNextEntryWrite))
4218	{
4219	uint32_t u32RequestMessageFrameDesc = pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextAddressRead];
4220	RTGCPHYS GCPhysMessageFrameAddr = LSILOGIC_RTGCPHYS_FROM_U32(pThis->u32HostMFAHighAddr,
4221	(u32RequestMessageFrameDesc & ~0x07));
4222
4223	PLSILOGICREQ pLsiReq;
4224
4225	/* Get new task state. */
4226	rc = RTMemCacheAllocEx(pThis->hTaskCache, (void **)&pLsiReq);
4227	AssertRC(rc);
4228
4229	pLsiReq->GCPhysMessageFrameAddr = GCPhysMessageFrameAddr;
4230
4231	/* Read the message header from the guest first. */
4232	PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &pLsiReq->GuestRequest, sizeof(MptMessageHdr));
4233
4234	/* Determine the size of the request. */
4235	uint32_t cbRequest = 0;
4236
4237	switch (pLsiReq->GuestRequest.Header.u8Function)
4238	{
4239	case MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST:
4240	cbRequest = sizeof(MptSCSIIORequest);
4241	break;
4242	case MPT_MESSAGE_HDR_FUNCTION_SCSI_TASK_MGMT:
4243	cbRequest = sizeof(MptSCSITaskManagementRequest);
4244	break;
4245	case MPT_MESSAGE_HDR_FUNCTION_IOC_INIT:
4246	cbRequest = sizeof(MptIOCInitRequest);
4247	break;
4248	case MPT_MESSAGE_HDR_FUNCTION_IOC_FACTS:
4249	cbRequest = sizeof(MptIOCFactsRequest);
4250	break;
4251	case MPT_MESSAGE_HDR_FUNCTION_CONFIG:
4252	cbRequest = sizeof(MptConfigurationRequest);
4253	break;
4254	case MPT_MESSAGE_HDR_FUNCTION_PORT_FACTS:
4255	cbRequest = sizeof(MptPortFactsRequest);
4256	break;
4257	case MPT_MESSAGE_HDR_FUNCTION_PORT_ENABLE:
4258	cbRequest = sizeof(MptPortEnableRequest);
4259	break;
4260	case MPT_MESSAGE_HDR_FUNCTION_EVENT_NOTIFICATION:
4261	cbRequest = sizeof(MptEventNotificationRequest);
4262	break;
4263	case MPT_MESSAGE_HDR_FUNCTION_EVENT_ACK:
4264	AssertMsgFailed(("todo\n"));
4265	//cbRequest = sizeof(MptEventAckRequest);
4266	break;
4267	case MPT_MESSAGE_HDR_FUNCTION_FW_DOWNLOAD:
4268	cbRequest = sizeof(MptFWDownloadRequest);
4269	break;
4270	case MPT_MESSAGE_HDR_FUNCTION_FW_UPLOAD:
4271	cbRequest = sizeof(MptFWUploadRequest);
4272	break;
4273	default:
4274	AssertMsgFailed(("Unknown function issued %u\n", pLsiReq->GuestRequest.Header.u8Function));
4275	lsilogicSetIOCFaultCode(pThis, LSILOGIC_IOCSTATUS_INVALID_FUNCTION);
4276	}
4277
4278	if (cbRequest != 0)
4279	{
4280	/* Read the complete message frame from guest memory now. */
4281	PDMDevHlpPhysRead(pDevIns, GCPhysMessageFrameAddr, &pLsiReq->GuestRequest, cbRequest);
4282
4283	/* Handle SCSI I/O requests now. */
4284	if (pLsiReq->GuestRequest.Header.u8Function == MPT_MESSAGE_HDR_FUNCTION_SCSI_IO_REQUEST)
4285	{
4286	rc = lsilogicR3ProcessSCSIIORequest(pThis, pLsiReq);
4287	AssertRC(rc);
4288	}
4289	else
4290	{
4291	MptReplyUnion Reply;
4292	rc = lsilogicR3ProcessMessageRequest(pThis, &pLsiReq->GuestRequest.Header, &Reply);
4293	AssertRC(rc);
4294	RTMemCacheFree(pThis->hTaskCache, pLsiReq);
4295	}
4296
4297	pThis->uRequestQueueNextAddressRead++;
4298	pThis->uRequestQueueNextAddressRead %= pThis->cRequestQueueEntries;
4299	}
4300	} /* While request frames available. */
4301	} /* While running */
4302
4303	return VINF_SUCCESS;
4304	}
4305
4306
4307	/**
4308	* Unblock the worker thread so it can respond to a state change.
4309	*
4310	* @returns VBox status code.
4311	* @param pDevIns The pcnet device instance.
4312	* @param pThread The send thread.
4313	*/
4314	static DECLCALLBACK(int) lsilogicR3WorkerWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4315	{
4316	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4317	return SUPSemEventSignal(pThis->pSupDrvSession, pThis->hEvtProcess);
4318	}
4319
4320
4321	/**
4322	* Kicks the controller to process pending tasks after the VM was resumed
4323	* or loaded from a saved state.
4324	*
4325	* @returns nothing.
4326	* @param pThis Pointer to the LsiLogic device state.
4327	*/
4328	static void lsilogicR3Kick(PLSILOGICSCSI pThis)
4329	{
4330	if ( pThis->VBoxSCSI.fBusy
4331	&& !pThis->fBiosReqPending)
4332	pThis->fBiosReqPending = true;
4333
4334	if (pThis->fNotificationSent)
4335	{
4336	/* Send a notifier to the PDM queue that there are pending requests. */
4337	PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pNotificationQueue));
4338	AssertMsg(pItem, ("Allocating item for queue failed\n"));
4339	PDMQueueInsert(pThis->CTX_SUFF(pNotificationQueue), (PPDMQUEUEITEMCORE)pItem);
4340	}
4341	}
4342
4343
4344	/*
4345	* Saved state.
4346	*/
4347
4348	/**
4349	* @callback_method_impl{FNSSMDEVLIVEEXEC}
4350	*/
4351	static DECLCALLBACK(int) lsilogicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4352	{
4353	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4354
4355	SSMR3PutU32(pSSM, pThis->enmCtrlType);
4356	SSMR3PutU32(pSSM, pThis->cDeviceStates);
4357	SSMR3PutU32(pSSM, pThis->cPorts);
4358
4359	/* Save the device config. */
4360	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4361	SSMR3PutBool(pSSM, pThis->paDeviceStates[i].pDrvBase != NULL);
4362
4363	return VINF_SSM_DONT_CALL_AGAIN;
4364	}
4365
4366	/**
4367	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4368	*/
4369	static DECLCALLBACK(int) lsilogicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4370	{
4371	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4372
4373	/* Every device first. */
4374	lsilogicR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
4375	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4376	{
4377	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4378
4379	AssertMsg(!pDevice->cOutstandingRequests,
4380	("There are still outstanding requests on this device\n"));
4381	SSMR3PutU32(pSSM, pDevice->cOutstandingRequests);
4382	}
4383	/* Now the main device state. */
4384	SSMR3PutU32 (pSSM, pThis->enmState);
4385	SSMR3PutU32 (pSSM, pThis->enmWhoInit);
4386	SSMR3PutU32 (pSSM, pThis->enmDoorbellState);
4387	SSMR3PutBool (pSSM, pThis->fDiagnosticEnabled);
4388	SSMR3PutBool (pSSM, pThis->fNotificationSent);
4389	SSMR3PutBool (pSSM, pThis->fEventNotificationEnabled);
4390	SSMR3PutU32 (pSSM, pThis->uInterruptMask);
4391	SSMR3PutU32 (pSSM, pThis->uInterruptStatus);
4392	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4393	SSMR3PutU32 (pSSM, pThis->aMessage[i]);
4394	SSMR3PutU32 (pSSM, pThis->iMessage);
4395	SSMR3PutU32 (pSSM, pThis->cMessage);
4396	SSMR3PutMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4397	SSMR3PutU32 (pSSM, pThis->uNextReplyEntryRead);
4398	SSMR3PutU32 (pSSM, pThis->cReplySize);
4399	SSMR3PutU16 (pSSM, pThis->u16IOCFaultCode);
4400	SSMR3PutU32 (pSSM, pThis->u32HostMFAHighAddr);
4401	SSMR3PutU32 (pSSM, pThis->u32SenseBufferHighAddr);
4402	SSMR3PutU8 (pSSM, pThis->cMaxDevices);
4403	SSMR3PutU8 (pSSM, pThis->cMaxBuses);
4404	SSMR3PutU16 (pSSM, pThis->cbReplyFrame);
4405	SSMR3PutU32 (pSSM, pThis->iDiagnosticAccess);
4406	SSMR3PutU32 (pSSM, pThis->cReplyQueueEntries);
4407	SSMR3PutU32 (pSSM, pThis->cRequestQueueEntries);
4408	SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextEntryFreeWrite);
4409	SSMR3PutU32 (pSSM, pThis->uReplyFreeQueueNextAddressRead);
4410	SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextEntryFreeWrite);
4411	SSMR3PutU32 (pSSM, pThis->uReplyPostQueueNextAddressRead);
4412	SSMR3PutU32 (pSSM, pThis->uRequestQueueNextEntryFreeWrite);
4413	SSMR3PutU32 (pSSM, pThis->uRequestQueueNextAddressRead);
4414
4415	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4416	SSMR3PutU32(pSSM, pThis->pReplyFreeQueueBaseR3[i]);
4417	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4418	SSMR3PutU32(pSSM, pThis->pReplyPostQueueBaseR3[i]);
4419	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4420	SSMR3PutU32(pSSM, pThis->pRequestQueueBaseR3[i]);
4421
4422	SSMR3PutU16 (pSSM, pThis->u16NextHandle);
4423
4424	/* Save diagnostic memory register and data regions. */
4425	SSMR3PutU32 (pSSM, pThis->u32DiagMemAddr);
4426	SSMR3PutU32 (pSSM, lsilogicR3MemRegionsCount(pThis));
4427
4428	PLSILOGICMEMREGN pIt = NULL;
4429	RTListForEach(&pThis->ListMemRegns, pIt, LSILOGICMEMREGN, NodeList)
4430	{
4431	SSMR3PutU32(pSSM, pIt->u32AddrStart);
4432	SSMR3PutU32(pSSM, pIt->u32AddrEnd);
4433	SSMR3PutMem(pSSM, &pIt->au32Data[0], (pIt->u32AddrEnd - pIt->u32AddrStart + 1) * sizeof(uint32_t));
4434	}
4435
4436	PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4437
4438	SSMR3PutMem (pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4439	SSMR3PutMem (pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4440	SSMR3PutMem (pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4441	SSMR3PutMem (pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4442	SSMR3PutMem (pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4443	SSMR3PutMem (pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4444	SSMR3PutMem (pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4445	SSMR3PutMem (pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4446	SSMR3PutMem (pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4447	SSMR3PutMem (pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4448	SSMR3PutMem (pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4449	SSMR3PutMem (pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4450	SSMR3PutMem (pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4451	SSMR3PutMem (pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4452	SSMR3PutMem (pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4453	SSMR3PutMem (pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4454	SSMR3PutMem (pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4455	SSMR3PutMem (pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4456	SSMR3PutMem (pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4457	SSMR3PutMem (pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4458	SSMR3PutMem (pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4459	SSMR3PutMem (pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4460	SSMR3PutMem (pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4461	SSMR3PutMem (pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4462
4463	/* Device dependent pages */
4464	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4465	{
4466	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4467
4468	SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4469	SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4470	SSMR3PutMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4471
4472	for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4473	{
4474	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4475	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4476	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4477	SSMR3PutMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4478	}
4479	}
4480	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4481	{
4482	PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4483
4484	SSMR3PutU32(pSSM, pSasPages->cbManufacturingPage7);
4485	SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage0);
4486	SSMR3PutU32(pSSM, pSasPages->cbSASIOUnitPage1);
4487
4488	SSMR3PutMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4489	SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4490	SSMR3PutMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4491
4492	SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4493	SSMR3PutMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4494
4495	SSMR3PutU32(pSSM, pSasPages->cPHYs);
4496	for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4497	{
4498	SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4499	SSMR3PutMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4500	}
4501
4502	/* The number of devices first. */
4503	SSMR3PutU32(pSSM, pSasPages->cDevices);
4504
4505	PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4506
4507	while (pCurr)
4508	{
4509	SSMR3PutMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4510	SSMR3PutMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4511	SSMR3PutMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4512
4513	pCurr = pCurr->pNext;
4514	}
4515	}
4516	else
4517	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4518
4519	vboxscsiR3SaveExec(&pThis->VBoxSCSI, pSSM);
4520	return SSMR3PutU32(pSSM, ~0);
4521	}
4522
4523	/**
4524	* @callback_method_impl{FNSSMDEVLOADDONE}
4525	*/
4526	static DECLCALLBACK(int) lsilogicR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4527	{
4528	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4529
4530	lsilogicR3Kick(pThis);
4531	return VINF_SUCCESS;
4532	}
4533
4534	/**
4535	* @callback_method_impl{FNSSMDEVLOADEXEC}
4536	*/
4537	static DECLCALLBACK(int) lsilogicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4538	{
4539	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4540	int rc;
4541
4542	if ( uVersion != LSILOGIC_SAVED_STATE_VERSION
4543	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM
4544	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL
4545	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_PRE_SAS
4546	&& uVersion != LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4547	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4548
4549	/* device config */
4550	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4551	{
4552	LSILOGICCTRLTYPE enmCtrlType;
4553	uint32_t cDeviceStates, cPorts;
4554
4555	rc = SSMR3GetU32(pSSM, (uint32_t *)&enmCtrlType);
4556	AssertRCReturn(rc, rc);
4557	rc = SSMR3GetU32(pSSM, &cDeviceStates);
4558	AssertRCReturn(rc, rc);
4559	rc = SSMR3GetU32(pSSM, &cPorts);
4560	AssertRCReturn(rc, rc);
4561
4562	if (enmCtrlType != pThis->enmCtrlType)
4563	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Controller type): config=%d state=%d"),
4564	pThis->enmCtrlType, enmCtrlType);
4565	if (cDeviceStates != pThis->cDeviceStates)
4566	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Device states): config=%u state=%u"),
4567	pThis->cDeviceStates, cDeviceStates);
4568	if (cPorts != pThis->cPorts)
4569	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target config mismatch (Ports): config=%u state=%u"),
4570	pThis->cPorts, cPorts);
4571	}
4572	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_VBOX_30)
4573	{
4574	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4575	{
4576	bool fPresent;
4577	rc = SSMR3GetBool(pSSM, &fPresent);
4578	AssertRCReturn(rc, rc);
4579	if (fPresent != (pThis->paDeviceStates[i].pDrvBase != NULL))
4580	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Target %u config mismatch: config=%RTbool state=%RTbool"),
4581	i, pThis->paDeviceStates[i].pDrvBase != NULL, fPresent);
4582	}
4583	}
4584	if (uPass != SSM_PASS_FINAL)
4585	return VINF_SUCCESS;
4586
4587	/* Every device first. */
4588	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
4589	{
4590	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
4591
4592	AssertMsg(!pDevice->cOutstandingRequests,
4593	("There are still outstanding requests on this device\n"));
4594	SSMR3GetU32(pSSM, (uint32_t *)&pDevice->cOutstandingRequests);
4595	}
4596	/* Now the main device state. */
4597	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmState);
4598	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->enmWhoInit);
4599	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_BOOL_DOORBELL)
4600	{
4601	bool fDoorbellInProgress = false;
4602
4603	/*
4604	* The doorbell status flag distinguishes only between
4605	* doorbell not in use or a Function handshake is currently in progress.
4606	*/
4607	SSMR3GetBool (pSSM, &fDoorbellInProgress);
4608	if (fDoorbellInProgress)
4609	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_FN_HANDSHAKE;
4610	else
4611	pThis->enmDoorbellState = LSILOGICDOORBELLSTATE_NOT_IN_USE;
4612	}
4613	else
4614	SSMR3GetU32(pSSM, (uint32_t *)&pThis->enmDoorbellState);
4615	SSMR3GetBool (pSSM, &pThis->fDiagnosticEnabled);
4616	SSMR3GetBool (pSSM, &pThis->fNotificationSent);
4617	SSMR3GetBool (pSSM, &pThis->fEventNotificationEnabled);
4618	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptMask);
4619	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uInterruptStatus);
4620	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMessage); i++)
4621	SSMR3GetU32 (pSSM, &pThis->aMessage[i]);
4622	SSMR3GetU32 (pSSM, &pThis->iMessage);
4623	SSMR3GetU32 (pSSM, &pThis->cMessage);
4624	SSMR3GetMem (pSSM, &pThis->ReplyBuffer, sizeof(pThis->ReplyBuffer));
4625	SSMR3GetU32 (pSSM, &pThis->uNextReplyEntryRead);
4626	SSMR3GetU32 (pSSM, &pThis->cReplySize);
4627	SSMR3GetU16 (pSSM, &pThis->u16IOCFaultCode);
4628	SSMR3GetU32 (pSSM, &pThis->u32HostMFAHighAddr);
4629	SSMR3GetU32 (pSSM, &pThis->u32SenseBufferHighAddr);
4630	SSMR3GetU8 (pSSM, &pThis->cMaxDevices);
4631	SSMR3GetU8 (pSSM, &pThis->cMaxBuses);
4632	SSMR3GetU16 (pSSM, &pThis->cbReplyFrame);
4633	SSMR3GetU32 (pSSM, &pThis->iDiagnosticAccess);
4634
4635	uint32_t cReplyQueueEntries, cRequestQueueEntries;
4636	SSMR3GetU32 (pSSM, &cReplyQueueEntries);
4637	SSMR3GetU32 (pSSM, &cRequestQueueEntries);
4638
4639	if ( cReplyQueueEntries != pThis->cReplyQueueEntries
4640	\|\| cRequestQueueEntries != pThis->cRequestQueueEntries)
4641	{
4642	LogFlow(("Reallocating queues cReplyQueueEntries=%u cRequestQueuEntries=%u\n",
4643	cReplyQueueEntries, cRequestQueueEntries));
4644	lsilogicR3QueuesFree(pThis);
4645	pThis->cReplyQueueEntries = cReplyQueueEntries;
4646	pThis->cRequestQueueEntries = cRequestQueueEntries;
4647	rc = lsilogicR3QueuesAlloc(pThis);
4648	if (RT_FAILURE(rc))
4649	return rc;
4650	}
4651
4652	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextEntryFreeWrite);
4653	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyFreeQueueNextAddressRead);
4654	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextEntryFreeWrite);
4655	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uReplyPostQueueNextAddressRead);
4656	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextEntryFreeWrite);
4657	SSMR3GetU32 (pSSM, (uint32_t *)&pThis->uRequestQueueNextAddressRead);
4658
4659	PMptConfigurationPagesSupported pPages = pThis->pConfigurationPages;
4660
4661	if (uVersion <= LSILOGIC_SAVED_STATE_VERSION_PRE_SAS)
4662	{
4663	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4664	MptConfigurationPagesSupported_SSM_V2 ConfigPagesV2;
4665
4666	if (pThis->enmCtrlType != LSILOGICCTRLTYPE_SCSI_SPI)
4667	return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Expected SPI SCSI controller"));
4668
4669	SSMR3GetMem(pSSM, &ConfigPagesV2,
4670	sizeof(MptConfigurationPagesSupported_SSM_V2));
4671
4672	pPages->ManufacturingPage0 = ConfigPagesV2.ManufacturingPage0;
4673	pPages->ManufacturingPage1 = ConfigPagesV2.ManufacturingPage1;
4674	pPages->ManufacturingPage2 = ConfigPagesV2.ManufacturingPage2;
4675	pPages->ManufacturingPage3 = ConfigPagesV2.ManufacturingPage3;
4676	pPages->ManufacturingPage4 = ConfigPagesV2.ManufacturingPage4;
4677	pPages->IOUnitPage0 = ConfigPagesV2.IOUnitPage0;
4678	pPages->IOUnitPage1 = ConfigPagesV2.IOUnitPage1;
4679	pPages->IOUnitPage2 = ConfigPagesV2.IOUnitPage2;
4680	pPages->IOUnitPage3 = ConfigPagesV2.IOUnitPage3;
4681	pPages->IOCPage0 = ConfigPagesV2.IOCPage0;
4682	pPages->IOCPage1 = ConfigPagesV2.IOCPage1;
4683	pPages->IOCPage2 = ConfigPagesV2.IOCPage2;
4684	pPages->IOCPage3 = ConfigPagesV2.IOCPage3;
4685	pPages->IOCPage4 = ConfigPagesV2.IOCPage4;
4686	pPages->IOCPage6 = ConfigPagesV2.IOCPage6;
4687
4688	pSpiPages->aPortPages[0].SCSISPIPortPage0 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage0;
4689	pSpiPages->aPortPages[0].SCSISPIPortPage1 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage1;
4690	pSpiPages->aPortPages[0].SCSISPIPortPage2 = ConfigPagesV2.aPortPages[0].SCSISPIPortPage2;
4691
4692	for (unsigned i = 0; i < RT_ELEMENTS(pPages->u.SpiPages.aBuses[0].aDevicePages); i++)
4693	{
4694	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage0;
4695	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage1;
4696	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage2;
4697	pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3 = ConfigPagesV2.aBuses[0].aDevicePages[i].SCSISPIDevicePage3;
4698	}
4699	}
4700	else
4701	{
4702	/* Queue content */
4703	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4704	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyFreeQueueBaseR3[i]);
4705	for (unsigned i = 0; i < pThis->cReplyQueueEntries; i++)
4706	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pReplyPostQueueBaseR3[i]);
4707	for (unsigned i = 0; i < pThis->cRequestQueueEntries; i++)
4708	SSMR3GetU32(pSSM, (uint32_t *)&pThis->pRequestQueueBaseR3[i]);
4709
4710	SSMR3GetU16(pSSM, &pThis->u16NextHandle);
4711
4712	if (uVersion > LSILOGIC_SAVED_STATE_VERSION_PRE_DIAG_MEM)
4713	{
4714	uint32_t cMemRegions = 0;
4715
4716	/* Save diagnostic memory register and data regions. */
4717	SSMR3GetU32 (pSSM, &pThis->u32DiagMemAddr);
4718	SSMR3GetU32 (pSSM, &cMemRegions);
4719
4720	while (cMemRegions)
4721	{
4722	uint32_t u32AddrStart = 0;
4723	uint32_t u32AddrEnd = 0;
4724	uint32_t cRegion = 0;
4725	PLSILOGICMEMREGN pRegion = NULL;
4726
4727	SSMR3GetU32(pSSM, &u32AddrStart);
4728	SSMR3GetU32(pSSM, &u32AddrEnd);
4729
4730	cRegion = u32AddrEnd - u32AddrStart + 1;
4731	pRegion = (PLSILOGICMEMREGN)RTMemAllocZ(RT_OFFSETOF(LSILOGICMEMREGN, au32Data[cRegion]));
4732	if (pRegion)
4733	{
4734	pRegion->u32AddrStart = u32AddrStart;
4735	pRegion->u32AddrEnd = u32AddrEnd;
4736	SSMR3GetMem(pSSM, &pRegion->au32Data[0], cRegion * sizeof(uint32_t));
4737	lsilogicR3MemRegionInsert(pThis, pRegion);
4738	pThis->cbMemRegns += cRegion * sizeof(uint32_t);
4739	}
4740	else
4741	{
4742	/* Leave a log message but continue. */
4743	LogRel(("LsiLogic: Out of memory while restoring the state, might not work as expected\n"));
4744	SSMR3Skip(pSSM, cRegion * sizeof(uint32_t));
4745	}
4746	cMemRegions--;
4747	}
4748	}
4749
4750	/* Configuration pages */
4751	SSMR3GetMem(pSSM, &pPages->ManufacturingPage0, sizeof(MptConfigurationPageManufacturing0));
4752	SSMR3GetMem(pSSM, &pPages->ManufacturingPage1, sizeof(MptConfigurationPageManufacturing1));
4753	SSMR3GetMem(pSSM, &pPages->ManufacturingPage2, sizeof(MptConfigurationPageManufacturing2));
4754	SSMR3GetMem(pSSM, &pPages->ManufacturingPage3, sizeof(MptConfigurationPageManufacturing3));
4755	SSMR3GetMem(pSSM, &pPages->ManufacturingPage4, sizeof(MptConfigurationPageManufacturing4));
4756	SSMR3GetMem(pSSM, &pPages->ManufacturingPage5, sizeof(MptConfigurationPageManufacturing5));
4757	SSMR3GetMem(pSSM, &pPages->ManufacturingPage6, sizeof(MptConfigurationPageManufacturing6));
4758	SSMR3GetMem(pSSM, &pPages->ManufacturingPage8, sizeof(MptConfigurationPageManufacturing8));
4759	SSMR3GetMem(pSSM, &pPages->ManufacturingPage9, sizeof(MptConfigurationPageManufacturing9));
4760	SSMR3GetMem(pSSM, &pPages->ManufacturingPage10, sizeof(MptConfigurationPageManufacturing10));
4761	SSMR3GetMem(pSSM, &pPages->IOUnitPage0, sizeof(MptConfigurationPageIOUnit0));
4762	SSMR3GetMem(pSSM, &pPages->IOUnitPage1, sizeof(MptConfigurationPageIOUnit1));
4763	SSMR3GetMem(pSSM, &pPages->IOUnitPage2, sizeof(MptConfigurationPageIOUnit2));
4764	SSMR3GetMem(pSSM, &pPages->IOUnitPage3, sizeof(MptConfigurationPageIOUnit3));
4765	SSMR3GetMem(pSSM, &pPages->IOUnitPage4, sizeof(MptConfigurationPageIOUnit4));
4766	SSMR3GetMem(pSSM, &pPages->IOCPage0, sizeof(MptConfigurationPageIOC0));
4767	SSMR3GetMem(pSSM, &pPages->IOCPage1, sizeof(MptConfigurationPageIOC1));
4768	SSMR3GetMem(pSSM, &pPages->IOCPage2, sizeof(MptConfigurationPageIOC2));
4769	SSMR3GetMem(pSSM, &pPages->IOCPage3, sizeof(MptConfigurationPageIOC3));
4770	SSMR3GetMem(pSSM, &pPages->IOCPage4, sizeof(MptConfigurationPageIOC4));
4771	SSMR3GetMem(pSSM, &pPages->IOCPage6, sizeof(MptConfigurationPageIOC6));
4772	SSMR3GetMem(pSSM, &pPages->BIOSPage1, sizeof(MptConfigurationPageBIOS1));
4773	SSMR3GetMem(pSSM, &pPages->BIOSPage2, sizeof(MptConfigurationPageBIOS2));
4774	SSMR3GetMem(pSSM, &pPages->BIOSPage4, sizeof(MptConfigurationPageBIOS4));
4775
4776	/* Device dependent pages */
4777	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
4778	{
4779	PMptConfigurationPagesSpi pSpiPages = &pPages->u.SpiPages;
4780
4781	SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage0, sizeof(MptConfigurationPageSCSISPIPort0));
4782	SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage1, sizeof(MptConfigurationPageSCSISPIPort1));
4783	SSMR3GetMem(pSSM, &pSpiPages->aPortPages[0].SCSISPIPortPage2, sizeof(MptConfigurationPageSCSISPIPort2));
4784
4785	for (unsigned i = 0; i < RT_ELEMENTS(pSpiPages->aBuses[0].aDevicePages); i++)
4786	{
4787	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage0, sizeof(MptConfigurationPageSCSISPIDevice0));
4788	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage1, sizeof(MptConfigurationPageSCSISPIDevice1));
4789	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage2, sizeof(MptConfigurationPageSCSISPIDevice2));
4790	SSMR3GetMem(pSSM, &pSpiPages->aBuses[0].aDevicePages[i].SCSISPIDevicePage3, sizeof(MptConfigurationPageSCSISPIDevice3));
4791	}
4792	}
4793	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
4794	{
4795	uint32_t cbPage0, cbPage1, cPHYs, cbManufacturingPage7;
4796	PMptConfigurationPagesSas pSasPages = &pPages->u.SasPages;
4797
4798	SSMR3GetU32(pSSM, &cbManufacturingPage7);
4799	SSMR3GetU32(pSSM, &cbPage0);
4800	SSMR3GetU32(pSSM, &cbPage1);
4801
4802	if ( (cbPage0 != pSasPages->cbSASIOUnitPage0)
4803	\|\| (cbPage1 != pSasPages->cbSASIOUnitPage1)
4804	\|\| (cbManufacturingPage7 != pSasPages->cbManufacturingPage7))
4805	return VERR_SSM_LOAD_CONFIG_MISMATCH;
4806
4807	AssertPtr(pSasPages->pManufacturingPage7);
4808	AssertPtr(pSasPages->pSASIOUnitPage0);
4809	AssertPtr(pSasPages->pSASIOUnitPage1);
4810
4811	SSMR3GetMem(pSSM, pSasPages->pManufacturingPage7, pSasPages->cbManufacturingPage7);
4812	SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage0, pSasPages->cbSASIOUnitPage0);
4813	SSMR3GetMem(pSSM, pSasPages->pSASIOUnitPage1, pSasPages->cbSASIOUnitPage1);
4814
4815	SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage2, sizeof(MptConfigurationPageSASIOUnit2));
4816	SSMR3GetMem(pSSM, &pSasPages->SASIOUnitPage3, sizeof(MptConfigurationPageSASIOUnit3));
4817
4818	SSMR3GetU32(pSSM, &cPHYs);
4819	if (cPHYs != pSasPages->cPHYs)
4820	return VERR_SSM_LOAD_CONFIG_MISMATCH;
4821
4822	AssertPtr(pSasPages->paPHYs);
4823	for (unsigned i = 0; i < pSasPages->cPHYs; i++)
4824	{
4825	SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage0, sizeof(MptConfigurationPageSASPHY0));
4826	SSMR3GetMem(pSSM, &pSasPages->paPHYs[i].SASPHYPage1, sizeof(MptConfigurationPageSASPHY1));
4827	}
4828
4829	/* The number of devices first. */
4830	SSMR3GetU32(pSSM, &pSasPages->cDevices);
4831
4832	PMptSASDevice pCurr = pSasPages->pSASDeviceHead;
4833
4834	for (unsigned i = 0; i < pSasPages->cDevices; i++)
4835	{
4836	SSMR3GetMem(pSSM, &pCurr->SASDevicePage0, sizeof(MptConfigurationPageSASDevice0));
4837	SSMR3GetMem(pSSM, &pCurr->SASDevicePage1, sizeof(MptConfigurationPageSASDevice1));
4838	SSMR3GetMem(pSSM, &pCurr->SASDevicePage2, sizeof(MptConfigurationPageSASDevice2));
4839
4840	pCurr = pCurr->pNext;
4841	}
4842
4843	Assert(!pCurr);
4844	}
4845	else
4846	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
4847	}
4848
4849	rc = vboxscsiR3LoadExec(&pThis->VBoxSCSI, pSSM);
4850	if (RT_FAILURE(rc))
4851	{
4852	LogRel(("LsiLogic: Failed to restore BIOS state: %Rrc.\n", rc));
4853	return PDMDEV_SET_ERROR(pDevIns, rc,
4854	N_("LsiLogic: Failed to restore BIOS state\n"));
4855	}
4856
4857	uint32_t u32;
4858	rc = SSMR3GetU32(pSSM, &u32);
4859	if (RT_FAILURE(rc))
4860	return rc;
4861	AssertMsgReturn(u32 == ~0U, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4862
4863	return VINF_SUCCESS;
4864	}
4865
4866
4867	/*
4868	* The device level IBASE and LED interfaces.
4869	*/
4870
4871	/**
4872	* @interface_method_impl{PDMILEDPORTS,pfnQueryInterface, For a SCSI device.}
4873	*
4874	* @remarks Called by the scsi driver, proxying the main calls.
4875	*/
4876	static DECLCALLBACK(int) lsilogicR3DeviceQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4877	{
4878	PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, ILed);
4879	if (iLUN == 0)
4880	{
4881	*ppLed = &pDevice->Led;
4882	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4883	return VINF_SUCCESS;
4884	}
4885	return VERR_PDM_LUN_NOT_FOUND;
4886	}
4887
4888
4889	/**
4890	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4891	*/
4892	static DECLCALLBACK(void ) lsilogicR3DeviceQueryInterface(PPDMIBASE pInterface, const char pszIID)
4893	{
4894	PLSILOGICDEVICE pDevice = RT_FROM_MEMBER(pInterface, LSILOGICDEVICE, IBase);
4895
4896	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevice->IBase);
4897	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISCSIPORT, &pDevice->ISCSIPort);
4898	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pDevice->ILed);
4899	return NULL;
4900	}
4901
4902
4903	/*
4904	* The controller level IBASE and LED interfaces.
4905	*/
4906
4907	/**
4908	* Gets the pointer to the status LED of a unit.
4909	*
4910	* @returns VBox status code.
4911	* @param pInterface Pointer to the interface structure containing the called function pointer.
4912	* @param iLUN The unit which status LED we desire.
4913	* @param ppLed Where to store the LED pointer.
4914	*/
4915	static DECLCALLBACK(int) lsilogicR3StatusQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4916	{
4917	PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, ILeds);
4918	if (iLUN < pThis->cDeviceStates)
4919	{
4920	*ppLed = &pThis->paDeviceStates[iLUN].Led;
4921	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4922	return VINF_SUCCESS;
4923	}
4924	return VERR_PDM_LUN_NOT_FOUND;
4925	}
4926
4927	/**
4928	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4929	*/
4930	static DECLCALLBACK(void ) lsilogicR3StatusQueryInterface(PPDMIBASE pInterface, const char pszIID)
4931	{
4932	PLSILOGICSCSI pThis = RT_FROM_MEMBER(pInterface, LSILOGICSCSI, IBase);
4933	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4934	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
4935	return NULL;
4936	}
4937
4938
4939	/*
4940	* The PDM device interface and some helpers.
4941	*/
4942
4943	/**
4944	* Checks if all asynchronous I/O is finished.
4945	*
4946	* Used by lsilogicR3Reset, lsilogicR3Suspend and lsilogicR3PowerOff.
4947	*
4948	* @returns true if quiesced, false if busy.
4949	* @param pDevIns The device instance.
4950	*/
4951	static bool lsilogicR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
4952	{
4953	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4954
4955	for (uint32_t i = 0; i < pThis->cDeviceStates; i++)
4956	{
4957	PLSILOGICDEVICE pThisDevice = &pThis->paDeviceStates[i];
4958	if (pThisDevice->pDrvBase)
4959	{
4960	if (pThisDevice->cOutstandingRequests != 0)
4961	return false;
4962	}
4963	}
4964
4965	return true;
4966	}
4967
4968	/**
4969	* @callback_method_impl{FNPDMDEVASYNCNOTIFY,
4970	* Callback employed by lsilogicR3Suspend and lsilogicR3PowerOff.}
4971	*/
4972	static DECLCALLBACK(bool) lsilogicR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
4973	{
4974	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
4975	return false;
4976
4977	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4978	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
4979	return true;
4980	}
4981
4982	/**
4983	* Common worker for ahciR3Suspend and ahciR3PowerOff.
4984	*/
4985	static void lsilogicR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
4986	{
4987	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
4988
4989	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
4990	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
4991	PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncSuspendOrPowerOffDone);
4992	else
4993	{
4994	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
4995
4996	AssertMsg(!pThis->fNotificationSent, ("The PDM Queue should be empty at this point\n"));
4997
4998	if (pThis->fRedo)
4999	{
5000	/*
5001	* We have tasks which we need to redo. Put the message frame addresses
5002	* into the request queue (we save the requests).
5003	* Guest execution is suspended at this point so there is no race between us and
5004	* lsilogicRegisterWrite.
5005	*/
5006	PLSILOGICREQ pLsiReq = pThis->pTasksRedoHead;
5007
5008	pThis->pTasksRedoHead = NULL;
5009
5010	while (pLsiReq)
5011	{
5012	PLSILOGICREQ pFree;
5013
5014	if (!pLsiReq->fBIOS)
5015	{
5016	/* Write only the lower 32bit part of the address. */
5017	ASMAtomicWriteU32(&pThis->CTX_SUFF(pRequestQueueBase)[pThis->uRequestQueueNextEntryFreeWrite],
5018	pLsiReq->GCPhysMessageFrameAddr & UINT32_C(0xffffffff));
5019
5020	pThis->uRequestQueueNextEntryFreeWrite++;
5021	pThis->uRequestQueueNextEntryFreeWrite %= pThis->cRequestQueueEntries;
5022	}
5023	else
5024	{
5025	AssertMsg(!pLsiReq->pRedoNext, ("Only one BIOS task can be active!\n"));
5026	vboxscsiSetRequestRedo(&pThis->VBoxSCSI, &pLsiReq->PDMScsiRequest);
5027	}
5028
5029	pThis->fNotificationSent = true;
5030
5031	pFree = pLsiReq;
5032	pLsiReq = pLsiReq->pRedoNext;
5033
5034	RTMemCacheFree(pThis->hTaskCache, pFree);
5035	}
5036	pThis->fRedo = false;
5037	}
5038	}
5039	}
5040
5041	/**
5042	* @interface_method_impl{PDMDEVREG,pfnSuspend}
5043	*/
5044	static DECLCALLBACK(void) lsilogicR3Suspend(PPDMDEVINS pDevIns)
5045	{
5046	Log(("lsilogicR3Suspend\n"));
5047	lsilogicR3SuspendOrPowerOff(pDevIns);
5048	}
5049
5050	/**
5051	* @interface_method_impl{PDMDEVREG,pfnResume}
5052	*/
5053	static DECLCALLBACK(void) lsilogicR3Resume(PPDMDEVINS pDevIns)
5054	{
5055	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5056
5057	Log(("lsilogicR3Resume\n"));
5058
5059	lsilogicR3Kick(pThis);
5060	}
5061
5062	/**
5063	* @interface_method_impl{PDMDEVREG,pfnDetach}
5064	*
5065	* One harddisk at one port has been unplugged.
5066	* The VM is suspended at this point.
5067	*/
5068	static DECLCALLBACK(void) lsilogicR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5069	{
5070	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5071	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5072
5073	if (iLUN >= pThis->cDeviceStates)
5074	return;
5075
5076	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5077	("LsiLogic: Device does not support hotplugging\n"));
5078
5079	Log(("%s:\n", __FUNCTION__));
5080
5081	/*
5082	* Zero some important members.
5083	*/
5084	pDevice->pDrvBase = NULL;
5085	pDevice->pDrvSCSIConnector = NULL;
5086	}
5087
5088	/**
5089	* @interface_method_impl{PDMDEVREG,pfnAttach}
5090	*/
5091	static DECLCALLBACK(int) lsilogicR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5092	{
5093	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5094	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[iLUN];
5095	int rc;
5096
5097	if (iLUN >= pThis->cDeviceStates)
5098	return VERR_PDM_LUN_NOT_FOUND;
5099
5100	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5101	("LsiLogic: Device does not support hotplugging\n"),
5102	VERR_INVALID_PARAMETER);
5103
5104	/* the usual paranoia */
5105	AssertRelease(!pDevice->pDrvBase);
5106	AssertRelease(!pDevice->pDrvSCSIConnector);
5107	Assert(pDevice->iLUN == iLUN);
5108
5109	/*
5110	* Try attach the block device and get the interfaces,
5111	* required as well as optional.
5112	*/
5113	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, NULL);
5114	if (RT_SUCCESS(rc))
5115	{
5116	/* Get SCSI connector interface. */
5117	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
5118	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
5119	}
5120	else
5121	AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pDevice->iLUN, rc));
5122
5123	if (RT_FAILURE(rc))
5124	{
5125	pDevice->pDrvBase = NULL;
5126	pDevice->pDrvSCSIConnector = NULL;
5127	}
5128	return rc;
5129	}
5130
5131	/**
5132	* Common reset worker.
5133	*
5134	* @param pDevIns The device instance data.
5135	*/
5136	static void lsilogicR3ResetCommon(PPDMDEVINS pDevIns)
5137	{
5138	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5139	int rc;
5140
5141	rc = lsilogicR3HardReset(pThis);
5142	AssertRC(rc);
5143
5144	vboxscsiInitialize(&pThis->VBoxSCSI);
5145	}
5146
5147	/**
5148	* @callback_method_impl{FNPDMDEVASYNCNOTIFY,
5149	* Callback employed by lsilogicR3Reset.}
5150	*/
5151	static DECLCALLBACK(bool) lsilogicR3IsAsyncResetDone(PPDMDEVINS pDevIns)
5152	{
5153	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5154
5155	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5156	return false;
5157	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5158
5159	lsilogicR3ResetCommon(pDevIns);
5160	return true;
5161	}
5162
5163	/**
5164	* @interface_method_impl{PDMDEVREG,pfnReset}
5165	*/
5166	static DECLCALLBACK(void) lsilogicR3Reset(PPDMDEVINS pDevIns)
5167	{
5168	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5169
5170	ASMAtomicWriteBool(&pThis->fSignalIdle, true);
5171	if (!lsilogicR3AllAsyncIOIsFinished(pDevIns))
5172	PDMDevHlpSetAsyncNotification(pDevIns, lsilogicR3IsAsyncResetDone);
5173	else
5174	{
5175	ASMAtomicWriteBool(&pThis->fSignalIdle, false);
5176	lsilogicR3ResetCommon(pDevIns);
5177	}
5178	}
5179
5180	/**
5181	* @interface_method_impl{PDMDEVREG,pfnRelocate}
5182	*/
5183	static DECLCALLBACK(void) lsilogicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5184	{
5185	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5186
5187	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5188	pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5189
5190	/* Relocate queues. */
5191	pThis->pReplyFreeQueueBaseRC += offDelta;
5192	pThis->pReplyPostQueueBaseRC += offDelta;
5193	pThis->pRequestQueueBaseRC += offDelta;
5194	}
5195
5196	/**
5197	* @interface_method_impl{PDMDEVREG,pfnPowerOff}
5198	*/
5199	static DECLCALLBACK(void) lsilogicR3PowerOff(PPDMDEVINS pDevIns)
5200	{
5201	Log(("lsilogicR3PowerOff\n"));
5202	lsilogicR3SuspendOrPowerOff(pDevIns);
5203	}
5204
5205	/**
5206	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5207	*/
5208	static DECLCALLBACK(int) lsilogicR3Destruct(PPDMDEVINS pDevIns)
5209	{
5210	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5211	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5212
5213	PDMR3CritSectDelete(&pThis->ReplyFreeQueueCritSect);
5214	PDMR3CritSectDelete(&pThis->ReplyPostQueueCritSect);
5215
5216	RTMemFree(pThis->paDeviceStates);
5217	pThis->paDeviceStates = NULL;
5218
5219	/* Destroy task cache. */
5220	if (pThis->hTaskCache != NIL_RTMEMCACHE)
5221	{
5222	int rc = RTMemCacheDestroy(pThis->hTaskCache); AssertRC(rc);
5223	pThis->hTaskCache = NIL_RTMEMCACHE;
5224	}
5225
5226	if (pThis->hEvtProcess != NIL_SUPSEMEVENT)
5227	{
5228	SUPSemEventClose(pThis->pSupDrvSession, pThis->hEvtProcess);
5229	pThis->hEvtProcess = NIL_SUPSEMEVENT;
5230	}
5231
5232	lsilogicR3ConfigurationPagesFree(pThis);
5233	lsilogicR3MemRegionsFree(pThis);
5234
5235	return VINF_SUCCESS;
5236	}
5237
5238	/**
5239	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5240	*/
5241	static DECLCALLBACK(int) lsilogicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5242	{
5243	PLSILOGICSCSI pThis = PDMINS_2_DATA(pDevIns, PLSILOGICSCSI);
5244	int rc = VINF_SUCCESS;
5245	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5246
5247	/*
5248	* Initialize enought of the state to make the destructure not trip up.
5249	*/
5250	pThis->hTaskCache = NIL_RTMEMCACHE;
5251	pThis->hEvtProcess = NIL_SUPSEMEVENT;
5252	pThis->fBiosReqPending = false;
5253	RTListInit(&pThis->ListMemRegns);
5254
5255	/*
5256	* Validate and read configuration.
5257	*/
5258	rc = CFGMR3AreValuesValid(pCfg, "GCEnabled\0"
5259	"R0Enabled\0"
5260	"ReplyQueueDepth\0"
5261	"RequestQueueDepth\0"
5262	"ControllerType\0"
5263	"NumPorts\0"
5264	"Bootable\0");
5265	if (RT_FAILURE(rc))
5266	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5267	N_("LsiLogic configuration error: unknown option specified"));
5268	rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fGCEnabled, true);
5269	if (RT_FAILURE(rc))
5270	return PDMDEV_SET_ERROR(pDevIns, rc,
5271	N_("LsiLogic configuration error: failed to read GCEnabled as boolean"));
5272	Log(("%s: fGCEnabled=%d\n", __FUNCTION__, pThis->fGCEnabled));
5273
5274	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
5275	if (RT_FAILURE(rc))
5276	return PDMDEV_SET_ERROR(pDevIns, rc,
5277	N_("LsiLogic configuration error: failed to read R0Enabled as boolean"));
5278	Log(("%s: fR0Enabled=%d\n", __FUNCTION__, pThis->fR0Enabled));
5279
5280	rc = CFGMR3QueryU32Def(pCfg, "ReplyQueueDepth",
5281	&pThis->cReplyQueueEntries,
5282	LSILOGICSCSI_REPLY_QUEUE_DEPTH_DEFAULT);
5283	if (RT_FAILURE(rc))
5284	return PDMDEV_SET_ERROR(pDevIns, rc,
5285	N_("LsiLogic configuration error: failed to read ReplyQueue as integer"));
5286	Log(("%s: ReplyQueueDepth=%u\n", __FUNCTION__, pThis->cReplyQueueEntries));
5287
5288	rc = CFGMR3QueryU32Def(pCfg, "RequestQueueDepth",
5289	&pThis->cRequestQueueEntries,
5290	LSILOGICSCSI_REQUEST_QUEUE_DEPTH_DEFAULT);
5291	if (RT_FAILURE(rc))
5292	return PDMDEV_SET_ERROR(pDevIns, rc,
5293	N_("LsiLogic configuration error: failed to read RequestQueue as integer"));
5294	Log(("%s: RequestQueueDepth=%u\n", __FUNCTION__, pThis->cRequestQueueEntries));
5295
5296	char *pszCtrlType;
5297	rc = CFGMR3QueryStringAllocDef(pCfg, "ControllerType",
5298	&pszCtrlType, LSILOGICSCSI_PCI_SPI_CTRLNAME);
5299	if (RT_FAILURE(rc))
5300	return PDMDEV_SET_ERROR(pDevIns, rc,
5301	N_("LsiLogic configuration error: failed to read ControllerType as string"));
5302	Log(("%s: ControllerType=%s\n", __FUNCTION__, pszCtrlType));
5303
5304	rc = lsilogicR3GetCtrlTypeFromString(pThis, pszCtrlType);
5305	MMR3HeapFree(pszCtrlType);
5306
5307	char szDevTag[20];
5308	RTStrPrintf(szDevTag, sizeof(szDevTag), "LSILOGIC%s-%u",
5309	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI ? "SPI" : "SAS",
5310	iInstance);
5311
5312
5313	if (RT_FAILURE(rc))
5314	return PDMDEV_SET_ERROR(pDevIns, rc,
5315	N_("LsiLogic configuration error: failed to determine controller type from string"));
5316
5317	rc = CFGMR3QueryU8(pCfg, "NumPorts",
5318	&pThis->cPorts);
5319	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5320	{
5321	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5322	pThis->cPorts = LSILOGICSCSI_PCI_SPI_PORTS_MAX;
5323	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5324	pThis->cPorts = LSILOGICSCSI_PCI_SAS_PORTS_DEFAULT;
5325	else
5326	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5327	}
5328	else if (RT_FAILURE(rc))
5329	return PDMDEV_SET_ERROR(pDevIns, rc,
5330	N_("LsiLogic configuration error: failed to read NumPorts as integer"));
5331
5332	bool fBootable;
5333	rc = CFGMR3QueryBoolDef(pCfg, "Bootable", &fBootable, true);
5334	if (RT_FAILURE(rc))
5335	return PDMDEV_SET_ERROR(pDevIns, rc,
5336	N_("LsiLogic configuration error: failed to read Bootable as boolean"));
5337	Log(("%s: Bootable=%RTbool\n", __FUNCTION__, fBootable));
5338
5339	/* Init static parts. */
5340	PCIDevSetVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_VENDOR_ID); /* LsiLogic */
5341
5342	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5343	{
5344	PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_DEVICE_ID); /* LSI53C1030 */
5345	PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_VENDOR_ID);
5346	PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SPI_SUBSYSTEM_ID);
5347	}
5348	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5349	{
5350	PCIDevSetDeviceId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_DEVICE_ID); /* SAS1068 */
5351	PCIDevSetSubSystemVendorId(&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_VENDOR_ID);
5352	PCIDevSetSubSystemId (&pThis->PciDev, LSILOGICSCSI_PCI_SAS_SUBSYSTEM_ID);
5353	}
5354	else
5355	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5356
5357	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* SCSI */
5358	PCIDevSetClassSub (&pThis->PciDev, 0x00); /* SCSI */
5359	PCIDevSetClassBase (&pThis->PciDev, 0x01); /* Mass storage */
5360	PCIDevSetInterruptPin(&pThis->PciDev, 0x01); /* Interrupt pin A */
5361
5362	# ifdef VBOX_WITH_MSI_DEVICES
5363	PCIDevSetStatus(&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST);
5364	PCIDevSetCapabilityList(&pThis->PciDev, 0x80);
5365	# endif
5366
5367	pThis->pDevInsR3 = pDevIns;
5368	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5369	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5370	pThis->pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
5371	pThis->IBase.pfnQueryInterface = lsilogicR3StatusQueryInterface;
5372	pThis->ILeds.pfnQueryStatusLed = lsilogicR3StatusQueryStatusLed;
5373
5374	/*
5375	* Create critical sections protecting the reply post and free queues.
5376	* Note! We do our own syncronization, so NOP the default crit sect for the device.
5377	*/
5378	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5379	AssertRCReturn(rc, rc);
5380
5381	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyFreeQueueCritSect, RT_SRC_POS, "%sRFQ", szDevTag);
5382	if (RT_FAILURE(rc))
5383	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply free queue"));
5384
5385	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->ReplyPostQueueCritSect, RT_SRC_POS, "%sRPQ", szDevTag);
5386	if (RT_FAILURE(rc))
5387	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic: cannot create critical section for reply post queue"));
5388
5389	/*
5390	* Register the PCI device, it's I/O regions.
5391	*/
5392	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5393	if (RT_FAILURE(rc))
5394	return rc;
5395
5396	# ifdef VBOX_WITH_MSI_DEVICES
5397	PDMMSIREG MsiReg;
5398	RT_ZERO(MsiReg);
5399	/* use this code for MSI-X support */
5400	# if 0
5401	MsiReg.cMsixVectors = 1;
5402	MsiReg.iMsixCapOffset = 0x80;
5403	MsiReg.iMsixNextOffset = 0x00;
5404	MsiReg.iMsixBar = 3;
5405	# else
5406	MsiReg.cMsiVectors = 1;
5407	MsiReg.iMsiCapOffset = 0x80;
5408	MsiReg.iMsiNextOffset = 0x00;
5409	# endif
5410	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5411	if (RT_FAILURE (rc))
5412	{
5413	/* That's OK, we can work without MSI */
5414	PCIDevSetCapabilityList(&pThis->PciDev, 0x0);
5415	}
5416	# endif
5417
5418	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, LSILOGIC_PCI_SPACE_IO_SIZE, PCI_ADDRESS_SPACE_IO, lsilogicR3Map);
5419	if (RT_FAILURE(rc))
5420	return rc;
5421
5422	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5423	if (RT_FAILURE(rc))
5424	return rc;
5425
5426	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, LSILOGIC_PCI_SPACE_MEM_SIZE, PCI_ADDRESS_SPACE_MEM, lsilogicR3Map);
5427	if (RT_FAILURE(rc))
5428	return rc;
5429
5430	/* Initialize task queue. (Need two items to handle SMP guest concurrency.) */
5431	char szTaggedText[64];
5432	RTStrPrintf(szTaggedText, sizeof(szTaggedText), "%s-Task", szDevTag);
5433	rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 2, 0,
5434	lsilogicR3NotifyQueueConsumer, true,
5435	szTaggedText,
5436	&pThis->pNotificationQueueR3);
5437	if (RT_FAILURE(rc))
5438	return rc;
5439	pThis->pNotificationQueueR0 = PDMQueueR0Ptr(pThis->pNotificationQueueR3);
5440	pThis->pNotificationQueueRC = PDMQueueRCPtr(pThis->pNotificationQueueR3);
5441
5442	/*
5443	* We need one entry free in the queue.
5444	*/
5445	pThis->cReplyQueueEntries++;
5446	pThis->cRequestQueueEntries++;
5447
5448	/*
5449	* Allocate memory for the queues.
5450	*/
5451	rc = lsilogicR3QueuesAlloc(pThis);
5452	if (RT_FAILURE(rc))
5453	return rc;
5454
5455	/*
5456	* Allocate task cache.
5457	*/
5458	rc = RTMemCacheCreate(&pThis->hTaskCache, sizeof(LSILOGICREQ), 0, UINT32_MAX,
5459	NULL, NULL, NULL, 0);
5460	if (RT_FAILURE(rc))
5461	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Cannot create task cache"));
5462
5463	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5464	pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SPI_DEVICES_PER_BUS_MAX;
5465	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5466	pThis->cDeviceStates = pThis->cPorts * LSILOGICSCSI_PCI_SAS_DEVICES_PER_PORT_MAX;
5467	else
5468	AssertMsgFailed(("Invalid controller type: %d\n", pThis->enmCtrlType));
5469
5470	/*
5471	* Create event semaphore and worker thread.
5472	*/
5473	rc = PDMDevHlpThreadCreate(pDevIns, &pThis->pThreadWrk, pThis, lsilogicR3Worker,
5474	lsilogicR3WorkerWakeUp, 0, RTTHREADTYPE_IO, szDevTag);
5475	if (RT_FAILURE(rc))
5476	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5477	N_("LsiLogic: Failed to create worker thread %s"), szDevTag);
5478
5479	rc = SUPSemEventCreate(pThis->pSupDrvSession, &pThis->hEvtProcess);
5480	if (RT_FAILURE(rc))
5481	return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
5482	N_("LsiLogic: Failed to create SUP event semaphore"));
5483
5484	/*
5485	* Allocate device states.
5486	*/
5487	pThis->paDeviceStates = (PLSILOGICDEVICE)RTMemAllocZ(sizeof(LSILOGICDEVICE) * pThis->cDeviceStates);
5488	if (!pThis->paDeviceStates)
5489	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to allocate memory for device states"));
5490
5491	for (unsigned i = 0; i < pThis->cDeviceStates; i++)
5492	{
5493	char szName[24];
5494	PLSILOGICDEVICE pDevice = &pThis->paDeviceStates[i];
5495
5496	/* Initialize static parts of the device. */
5497	pDevice->iLUN = i;
5498	pDevice->pLsiLogicR3 = pThis;
5499	pDevice->Led.u32Magic = PDMLED_MAGIC;
5500	pDevice->IBase.pfnQueryInterface = lsilogicR3DeviceQueryInterface;
5501	pDevice->ISCSIPort.pfnSCSIRequestCompleted = lsilogicR3DeviceSCSIRequestCompleted;
5502	pDevice->ISCSIPort.pfnQueryDeviceLocation = lsilogicR3QueryDeviceLocation;
5503	pDevice->ILed.pfnQueryStatusLed = lsilogicR3DeviceQueryStatusLed;
5504
5505	RTStrPrintf(szName, sizeof(szName), "Device%u", i);
5506
5507	/* Attach SCSI driver. */
5508	rc = PDMDevHlpDriverAttach(pDevIns, pDevice->iLUN, &pDevice->IBase, &pDevice->pDrvBase, szName);
5509	if (RT_SUCCESS(rc))
5510	{
5511	/* Get SCSI connector interface. */
5512	pDevice->pDrvSCSIConnector = PDMIBASE_QUERY_INTERFACE(pDevice->pDrvBase, PDMISCSICONNECTOR);
5513	AssertMsgReturn(pDevice->pDrvSCSIConnector, ("Missing SCSI interface below\n"), VERR_PDM_MISSING_INTERFACE);
5514	}
5515	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5516	{
5517	pDevice->pDrvBase = NULL;
5518	rc = VINF_SUCCESS;
5519	Log(("LsiLogic: no driver attached to device %s\n", szName));
5520	}
5521	else
5522	{
5523	AssertLogRelMsgFailed(("LsiLogic: Failed to attach %s\n", szName));
5524	return rc;
5525	}
5526	}
5527
5528	/*
5529	* Attach status driver (optional).
5530	*/
5531	PPDMIBASE pBase;
5532	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
5533	if (RT_SUCCESS(rc))
5534	pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5535	else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
5536	{
5537	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
5538	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot attach to status driver"));
5539	}
5540
5541	/* Initialize the SCSI emulation for the BIOS. */
5542	rc = vboxscsiInitialize(&pThis->VBoxSCSI);
5543	AssertRC(rc);
5544
5545	/*
5546	* Register I/O port space in ISA region for BIOS access
5547	* if the controller is marked as bootable.
5548	*/
5549	if (fBootable)
5550	{
5551	if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI)
5552	rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_BIOS_IO_PORT, 4, NULL,
5553	lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5554	lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5555	"LsiLogic BIOS");
5556	else if (pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SAS)
5557	rc = PDMDevHlpIOPortRegister(pDevIns, LSILOGIC_SAS_BIOS_IO_PORT, 4, NULL,
5558	lsilogicR3IsaIOPortWrite, lsilogicR3IsaIOPortRead,
5559	lsilogicR3IsaIOPortWriteStr, lsilogicR3IsaIOPortReadStr,
5560	"LsiLogic SAS BIOS");
5561	else
5562	AssertMsgFailed(("Invalid controller type %d\n", pThis->enmCtrlType));
5563
5564	if (RT_FAILURE(rc))
5565	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register legacy I/O handlers"));
5566	}
5567
5568	/* Register save state handlers. */
5569	rc = PDMDevHlpSSMRegisterEx(pDevIns, LSILOGIC_SAVED_STATE_VERSION, sizeof(*pThis), NULL,
5570	NULL, lsilogicR3LiveExec, NULL,
5571	NULL, lsilogicR3SaveExec, NULL,
5572	NULL, lsilogicR3LoadExec, lsilogicR3LoadDone);
5573	if (RT_FAILURE(rc))
5574	return PDMDEV_SET_ERROR(pDevIns, rc, N_("LsiLogic cannot register save state handlers"));
5575
5576	pThis->enmWhoInit = LSILOGICWHOINIT_SYSTEM_BIOS;
5577
5578	/*
5579	* Register the info item.
5580	*/
5581	char szTmp[128];
5582	RTStrPrintf(szTmp, sizeof(szTmp), "%s%u", pDevIns->pReg->szName, pDevIns->iInstance);
5583	PDMDevHlpDBGFInfoRegister(pDevIns, szTmp,
5584	pThis->enmCtrlType == LSILOGICCTRLTYPE_SCSI_SPI
5585	? "LsiLogic SPI info."
5586	: "LsiLogic SAS info.", lsilogicR3Info);
5587
5588	/* Perform hard reset. */
5589	rc = lsilogicR3HardReset(pThis);
5590	AssertRC(rc);
5591
5592	return rc;
5593	}
5594
5595	/**
5596	* The device registration structure - SPI SCSI controller.
5597	*/
5598	const PDMDEVREG g_DeviceLsiLogicSCSI =
5599	{
5600	/* u32Version */
5601	PDM_DEVREG_VERSION,
5602	/* szName */
5603	"lsilogicscsi",
5604	/* szRCMod */
5605	"VBoxDDRC.rc",
5606	/* szR0Mod */
5607	"VBoxDDR0.r0",
5608	/* pszDescription */
5609	"LSI Logic 53c1030 SCSI controller.\n",
5610	/* fFlags */
5611	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
5612	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
5613	/* fClass */
5614	PDM_DEVREG_CLASS_STORAGE,
5615	/* cMaxInstances */
5616	~0U,
5617	/* cbInstance */
5618	sizeof(LSILOGICSCSI),
5619	/* pfnConstruct */
5620	lsilogicR3Construct,
5621	/* pfnDestruct */
5622	lsilogicR3Destruct,
5623	/* pfnRelocate */
5624	lsilogicR3Relocate,
5625	/* pfnMemSetup */
5626	NULL,
5627	/* pfnPowerOn */
5628	NULL,
5629	/* pfnReset */
5630	lsilogicR3Reset,
5631	/* pfnSuspend */
5632	lsilogicR3Suspend,
5633	/* pfnResume */
5634	lsilogicR3Resume,
5635	/* pfnAttach */
5636	lsilogicR3Attach,
5637	/* pfnDetach */
5638	lsilogicR3Detach,
5639	/* pfnQueryInterface. */
5640	NULL,
5641	/* pfnInitComplete */
5642	NULL,
5643	/* pfnPowerOff */
5644	lsilogicR3PowerOff,
5645	/* pfnSoftReset */
5646	NULL,
5647	/* u32VersionEnd */
5648	PDM_DEVREG_VERSION
5649	};
5650
5651	/**
5652	* The device registration structure - SAS controller.
5653	*/
5654	const PDMDEVREG g_DeviceLsiLogicSAS =
5655	{
5656	/* u32Version */
5657	PDM_DEVREG_VERSION,
5658	/* szName */
5659	"lsilogicsas",
5660	/* szRCMod */
5661	"VBoxDDRC.rc",
5662	/* szR0Mod */
5663	"VBoxDDR0.r0",
5664	/* pszDescription */
5665	"LSI Logic SAS1068 controller.\n",
5666	/* fFlags */
5667	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0 \|
5668	PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION \| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION \|
5669	PDM_DEVREG_FLAGS_FIRST_RESET_NOTIFICATION,
5670	/* fClass */
5671	PDM_DEVREG_CLASS_STORAGE,
5672	/* cMaxInstances */
5673	~0U,
5674	/* cbInstance */
5675	sizeof(LSILOGICSCSI),
5676	/* pfnConstruct */
5677	lsilogicR3Construct,
5678	/* pfnDestruct */
5679	lsilogicR3Destruct,
5680	/* pfnRelocate */
5681	lsilogicR3Relocate,
5682	/* pfnMemSetup */
5683	NULL,
5684	/* pfnPowerOn */
5685	NULL,
5686	/* pfnReset */
5687	lsilogicR3Reset,
5688	/* pfnSuspend */
5689	lsilogicR3Suspend,
5690	/* pfnResume */
5691	lsilogicR3Resume,
5692	/* pfnAttach */
5693	lsilogicR3Attach,
5694	/* pfnDetach */
5695	lsilogicR3Detach,
5696	/* pfnQueryInterface. */
5697	NULL,
5698	/* pfnInitComplete */
5699	NULL,
5700	/* pfnPowerOff */
5701	lsilogicR3PowerOff,
5702	/* pfnSoftReset */
5703	NULL,
5704	/* u32VersionEnd */
5705	PDM_DEVREG_VERSION
5706	};
5707
5708	#endif /* IN_RING3 */
5709	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

© 2023 Oracle
Contact – Privacy policy – Terms of Use