1 | /* $Id: DevAHCI.cpp 106422 2024-10-17 10:07:16Z vboxsync $ */
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2 | /** @file
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3 | * DevAHCI - AHCI controller device (disk and cdrom).
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4 | *
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5 | * Implements the AHCI standard 1.1
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6 | */
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7 |
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8 | /*
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9 | * Copyright (C) 2006-2024 Oracle and/or its affiliates.
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10 | *
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11 | * This file is part of VirtualBox base platform packages, as
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12 | * available from https://www.virtualbox.org.
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13 | *
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14 | * This program is free software; you can redistribute it and/or
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15 | * modify it under the terms of the GNU General Public License
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16 | * as published by the Free Software Foundation, in version 3 of the
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17 | * License.
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18 | *
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19 | * This program is distributed in the hope that it will be useful, but
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20 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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22 | * General Public License for more details.
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23 | *
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24 | * You should have received a copy of the GNU General Public License
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25 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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26 | *
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27 | * SPDX-License-Identifier: GPL-3.0-only
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28 | */
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29 |
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30 | /** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
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31 | *
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32 | * This component implements an AHCI serial ATA controller. The device is split
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33 | * into two parts. The first part implements the register interface for the
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34 | * guest and the second one does the data transfer.
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35 | *
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36 | * The guest can access the controller in two ways. The first one is the native
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37 | * way implementing the registers described in the AHCI specification and is
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38 | * the preferred one. The second implements the I/O ports used for booting from
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39 | * the hard disk and for guests which don't have an AHCI SATA driver.
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40 | *
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41 | * The data is transfered using the extended media interface, asynchronously if
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42 | * it is supported by the driver below otherwise it weill be done synchronous.
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43 | * Either way a thread is used to process new requests from the guest.
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44 | */
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45 |
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46 |
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47 | /*********************************************************************************************************************************
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48 | * Header Files *
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49 | *********************************************************************************************************************************/
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50 | #define LOG_GROUP LOG_GROUP_DEV_AHCI
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51 | #include <VBox/vmm/pdmdev.h>
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52 | #include <VBox/vmm/pdmstorageifs.h>
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53 | #include <VBox/vmm/pdmqueue.h>
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54 | #include <VBox/vmm/pdmthread.h>
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55 | #include <VBox/vmm/pdmcritsect.h>
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56 | #include <VBox/sup.h>
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57 | #include <VBox/scsi.h>
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58 | #include <VBox/ata.h>
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59 | #include <VBox/AssertGuest.h>
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60 | #include <iprt/assert.h>
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61 | #include <iprt/asm.h>
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62 | #include <iprt/string.h>
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63 | #include <iprt/list.h>
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64 | #ifdef IN_RING3
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65 | # include <iprt/param.h>
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66 | # include <iprt/thread.h>
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67 | # include <iprt/semaphore.h>
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68 | # include <iprt/alloc.h>
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69 | # include <iprt/uuid.h>
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70 | # include <iprt/time.h>
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71 | #endif
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72 | #include "VBoxDD.h"
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73 |
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74 | #if defined(VBOX_WITH_DTRACE) \
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75 | && defined(IN_RING3) \
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76 | && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
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77 | # include "dtrace/VBoxDD.h"
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78 | #else
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79 | # define VBOXDD_AHCI_REQ_SUBMIT(a,b,c,d) do { } while (0)
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80 | # define VBOXDD_AHCI_REQ_COMPLETED(a,b,c,d) do { } while (0)
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81 | #endif
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82 |
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83 | /** Maximum number of ports available.
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84 | * Spec defines 32 but we have one allocated for command completion coalescing
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85 | * and another for a reserved future feature.
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86 | */
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87 | #define AHCI_MAX_NR_PORTS_IMPL 30
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88 | /** Maximum number of command slots available. */
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89 | #define AHCI_NR_COMMAND_SLOTS 32
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90 |
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91 | /** The current saved state version. */
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92 | #define AHCI_SAVED_STATE_VERSION 9
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93 | /** The saved state version before the ATAPI emulation was removed and the generic SCSI driver was used. */
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94 | #define AHCI_SAVED_STATE_VERSION_PRE_ATAPI_REMOVE 8
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95 | /** The saved state version before changing the port reset logic in an incompatible way. */
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96 | #define AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES 7
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97 | /** Saved state version before the per port hotplug port was added. */
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98 | #define AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG 6
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99 | /** Saved state version before legacy ATA emulation was dropped. */
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100 | #define AHCI_SAVED_STATE_VERSION_IDE_EMULATION 5
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101 | /** Saved state version before ATAPI support was added. */
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102 | #define AHCI_SAVED_STATE_VERSION_PRE_ATAPI 3
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103 | /** The saved state version use in VirtualBox 3.0 and earlier.
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104 | * This was before the config was added and ahciIOTasks was dropped. */
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105 | #define AHCI_SAVED_STATE_VERSION_VBOX_30 2
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106 | /* for Older ATA state Read handling */
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107 | #define ATA_CTL_SAVED_STATE_VERSION 3
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108 | #define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 1
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109 | #define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 2
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110 |
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111 | /** The maximum number of release log entries per device. */
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112 | #define MAX_LOG_REL_ERRORS 1024
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113 |
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114 | /**
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115 | * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
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116 | * Set to 1 to disable multi-sector read support. According to the ATA
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117 | * specification this must be a power of 2 and it must fit in an 8 bit
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118 | * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
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119 | */
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120 | #define ATA_MAX_MULT_SECTORS 128
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121 |
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122 | /**
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123 | * Fastest PIO mode supported by the drive.
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124 | */
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125 | #define ATA_PIO_MODE_MAX 4
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126 | /**
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127 | * Fastest MDMA mode supported by the drive.
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128 | */
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129 | #define ATA_MDMA_MODE_MAX 2
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130 | /**
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131 | * Fastest UDMA mode supported by the drive.
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132 | */
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133 | #define ATA_UDMA_MODE_MAX 6
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134 |
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135 | /**
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136 | * Length of the configurable VPD data (without termination)
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137 | */
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138 | #define AHCI_SERIAL_NUMBER_LENGTH 20
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139 | #define AHCI_FIRMWARE_REVISION_LENGTH 8
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140 | #define AHCI_MODEL_NUMBER_LENGTH 40
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141 | #define AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH 8
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142 | #define AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH 16
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143 | #define AHCI_ATAPI_INQUIRY_REVISION_LENGTH 4
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144 |
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145 | /** ATAPI sense info size. */
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146 | #define ATAPI_SENSE_SIZE 64
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147 |
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148 | /**
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149 | * Command Header.
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150 | */
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151 | typedef struct
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152 | {
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153 | /** Description Information. */
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154 | uint32_t u32DescInf;
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155 | /** Command status. */
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156 | uint32_t u32PRDBC;
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157 | /** Command Table Base Address. */
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158 | uint32_t u32CmdTblAddr;
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159 | /** Command Table Base Address - upper 32-bits. */
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160 | uint32_t u32CmdTblAddrUp;
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161 | /** Reserved */
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162 | uint32_t u32Reserved[4];
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163 | } CmdHdr;
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164 | AssertCompileSize(CmdHdr, 32);
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165 |
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166 | /* Defines for the command header. */
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167 | #define AHCI_CMDHDR_PRDTL_MASK 0xffff0000
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168 | #define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
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169 | #define AHCI_CMDHDR_C RT_BIT(10)
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170 | #define AHCI_CMDHDR_B RT_BIT(9)
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171 | #define AHCI_CMDHDR_R RT_BIT(8)
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172 | #define AHCI_CMDHDR_P RT_BIT(7)
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173 | #define AHCI_CMDHDR_W RT_BIT(6)
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174 | #define AHCI_CMDHDR_A RT_BIT(5)
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175 | #define AHCI_CMDHDR_CFL_MASK 0x1f
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176 |
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177 | #define AHCI_CMDHDR_PRDT_OFFSET 0x80
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178 | #define AHCI_CMDHDR_ACMD_OFFSET 0x40
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179 |
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180 | /* Defines for the command FIS. */
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181 | /* Defines that are used in the first double word. */
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182 | #define AHCI_CMDFIS_TYPE 0 /* The first byte. */
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183 | # define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
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184 | # define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
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185 | # define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
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186 | # define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
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187 | # define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
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188 | # define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
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189 | # define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
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190 | # define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
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191 | # define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
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192 | # define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
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193 | # define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
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194 | # define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
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195 | # define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
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196 |
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197 | #define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
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198 | #define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
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199 | #define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
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200 | #define AHCI_CMDFIS_D RT_BIT(5)
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201 |
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202 | #define AHCI_CMDFIS_CMD 2
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203 | #define AHCI_CMDFIS_FET 3
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204 |
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205 | #define AHCI_CMDFIS_SECTN 4
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206 | #define AHCI_CMDFIS_CYLL 5
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207 | #define AHCI_CMDFIS_CYLH 6
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208 | #define AHCI_CMDFIS_HEAD 7
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209 |
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210 | #define AHCI_CMDFIS_SECTNEXP 8
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211 | #define AHCI_CMDFIS_CYLLEXP 9
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212 | #define AHCI_CMDFIS_CYLHEXP 10
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213 | #define AHCI_CMDFIS_FETEXP 11
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214 |
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215 | #define AHCI_CMDFIS_SECTC 12
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216 | #define AHCI_CMDFIS_SECTCEXP 13
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217 | #define AHCI_CMDFIS_CTL 15
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218 | # define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
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219 | # define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
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220 |
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221 | /* For D2H FIS */
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222 | #define AHCI_CMDFIS_STS 2
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223 | #define AHCI_CMDFIS_ERR 3
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224 |
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225 | /** Pointer to a task state. */
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226 | typedef struct AHCIREQ *PAHCIREQ;
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227 |
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228 | /** Task encountered a buffer overflow. */
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229 | #define AHCI_REQ_OVERFLOW RT_BIT_32(0)
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230 | /** Request is a PIO data command, if this flag is not set it either is
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231 | * a command which does not transfer data or a DMA command based on the transfer size. */
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232 | #define AHCI_REQ_PIO_DATA RT_BIT_32(1)
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233 | /** The request has the SACT register set. */
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234 | #define AHCI_REQ_CLEAR_SACT RT_BIT_32(2)
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235 | /** Flag whether the request is queued. */
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236 | #define AHCI_REQ_IS_QUEUED RT_BIT_32(3)
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237 | /** Flag whether the request is stored on the stack. */
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238 | #define AHCI_REQ_IS_ON_STACK RT_BIT_32(4)
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239 | /** Flag whether this request transfers data from the device to the HBA or
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240 | * the other way around .*/
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241 | #define AHCI_REQ_XFER_2_HOST RT_BIT_32(5)
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242 |
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243 | /**
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244 | * A task state.
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245 | */
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246 | typedef struct AHCIREQ
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247 | {
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248 | /** The I/O request handle from the driver below associated with this request. */
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249 | PDMMEDIAEXIOREQ hIoReq;
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250 | /** Tag of the task. */
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251 | uint32_t uTag;
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252 | /** The command Fis for this task. */
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253 | uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
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254 | /** The ATAPI command data. */
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255 | uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
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256 | /** Physical address of the command header. - GC */
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257 | RTGCPHYS GCPhysCmdHdrAddr;
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258 | /** Physical address of the PRDT */
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259 | RTGCPHYS GCPhysPrdtl;
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260 | /** Number of entries in the PRDTL. */
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261 | unsigned cPrdtlEntries;
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262 | /** Data direction. */
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263 | PDMMEDIAEXIOREQTYPE enmType;
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264 | /** Start offset. */
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265 | uint64_t uOffset;
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266 | /** Number of bytes to transfer. */
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267 | size_t cbTransfer;
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268 | /** Flags for this task. */
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269 | uint32_t fFlags;
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270 | /** SCSI status code. */
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271 | uint8_t u8ScsiSts;
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272 | /** Flag when the buffer is mapped. */
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273 | bool fMapped;
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274 | /** Page lock when the buffer is mapped. */
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275 | PGMPAGEMAPLOCK PgLck;
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276 | } AHCIREQ;
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277 |
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278 | /**
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279 | * Notifier queue item.
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280 | */
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281 | typedef struct DEVPORTNOTIFIERQUEUEITEM
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282 | {
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283 | /** The core part owned by the queue manager. */
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284 | PDMQUEUEITEMCORE Core;
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285 | /** The port to process. */
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286 | uint8_t iPort;
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287 | } DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
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288 |
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289 |
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290 | /**
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291 | * The shared state of an AHCI port.
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292 | */
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293 | typedef struct AHCIPORT
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294 | {
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295 | /** Command List Base Address. */
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296 | uint32_t regCLB;
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297 | /** Command List Base Address upper bits. */
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298 | uint32_t regCLBU;
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299 | /** FIS Base Address. */
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300 | uint32_t regFB;
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301 | /** FIS Base Address upper bits. */
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302 | uint32_t regFBU;
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303 | /** Interrupt Status. */
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304 | volatile uint32_t regIS;
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305 | /** Interrupt Enable. */
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306 | uint32_t regIE;
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307 | /** Command. */
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308 | uint32_t regCMD;
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309 | /** Task File Data. */
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310 | uint32_t regTFD;
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311 | /** Signature */
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312 | uint32_t regSIG;
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313 | /** Serial ATA Status. */
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314 | uint32_t regSSTS;
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315 | /** Serial ATA Control. */
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316 | uint32_t regSCTL;
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317 | /** Serial ATA Error. */
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318 | uint32_t regSERR;
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319 | /** Serial ATA Active. */
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320 | volatile uint32_t regSACT;
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321 | /** Command Issue. */
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322 | uint32_t regCI;
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323 |
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324 | /** Current number of active tasks. */
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325 | volatile uint32_t cTasksActive;
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326 | uint32_t u32Alignment1;
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327 | /** Command List Base Address */
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328 | volatile RTGCPHYS GCPhysAddrClb;
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329 | /** FIS Base Address */
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330 | volatile RTGCPHYS GCPhysAddrFb;
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331 |
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332 | /** Device is powered on. */
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333 | bool fPoweredOn;
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334 | /** Device has spun up. */
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335 | bool fSpunUp;
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336 | /** First D2H FIS was sent. */
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337 | bool fFirstD2HFisSent;
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338 | /** Attached device is a CD/DVD drive. */
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339 | bool fATAPI;
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340 | /** Flag whether this port is in a reset state. */
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341 | volatile bool fPortReset;
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342 | /** Flag whether TRIM is supported. */
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343 | bool fTrimEnabled;
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344 | /** Flag if we are in a device reset. */
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345 | bool fResetDevice;
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346 | /** Flag whether this port is hot plug capable. */
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347 | bool fHotpluggable;
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348 | /** Flag whether the port is in redo task mode. */
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349 | volatile bool fRedo;
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350 | /** Flag whether the worker thread is sleeping. */
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351 | volatile bool fWrkThreadSleeping;
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352 |
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353 | bool afAlignment1[2];
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354 |
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355 | /** Number of total sectors. */
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356 | uint64_t cTotalSectors;
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357 | /** Size of one sector. */
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358 | uint32_t cbSector;
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359 | /** Currently configured number of sectors in a multi-sector transfer. */
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360 | uint32_t cMultSectors;
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361 | /** The LUN (same as port number). */
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362 | uint32_t iLUN;
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363 | /** Set if there is a device present at the port. */
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364 | bool fPresent;
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365 | /** Currently active transfer mode (MDMA/UDMA) and speed. */
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366 | uint8_t uATATransferMode;
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367 | /** Exponent of logical sectors in a physical sector, number of logical sectors is 2^exp. */
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368 | uint8_t cLogSectorsPerPhysicalExp;
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369 | uint8_t bAlignment2;
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370 | /** ATAPI sense data. */
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371 | uint8_t abATAPISense[ATAPI_SENSE_SIZE];
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372 |
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373 | /** Bitmap for finished tasks (R3 -> Guest). */
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374 | volatile uint32_t u32TasksFinished;
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375 | /** Bitmap for finished queued tasks (R3 -> Guest). */
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376 | volatile uint32_t u32QueuedTasksFinished;
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377 | /** Bitmap for new queued tasks (Guest -> R3). */
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378 | volatile uint32_t u32TasksNew;
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379 | /** Bitmap of tasks which must be redone because of a non fatal error. */
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380 | volatile uint32_t u32TasksRedo;
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381 |
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382 | /** Current command slot processed.
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383 | * Accessed by the guest by reading the CMD register.
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384 | * Holds the command slot of the command processed at the moment. */
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385 | volatile uint32_t u32CurrentCommandSlot;
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386 |
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387 | /** Physical geometry of this image. */
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388 | PDMMEDIAGEOMETRY PCHSGeometry;
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389 |
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390 | /** The status LED state for this drive. */
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391 | PDMLED Led;
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392 |
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393 | /** The event semaphore the processing thread waits on. */
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394 | SUPSEMEVENT hEvtProcess;
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395 |
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396 | /** The serial numnber to use for IDENTIFY DEVICE commands. */
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397 | char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
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398 | /** The firmware revision to use for IDENTIFY DEVICE commands. */
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399 | char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
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400 | /** The model number to use for IDENTIFY DEVICE commands. */
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401 | char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
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402 | /** The vendor identification string for SCSI INQUIRY commands. */
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403 | char szInquiryVendorId[AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
|
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404 | /** The product identification string for SCSI INQUIRY commands. */
|
---|
405 | char szInquiryProductId[AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
|
---|
406 | /** The revision string for SCSI INQUIRY commands. */
|
---|
407 | char szInquiryRevision[AHCI_ATAPI_INQUIRY_REVISION_LENGTH+1];
|
---|
408 | /** Error counter */
|
---|
409 | uint32_t cErrors;
|
---|
410 |
|
---|
411 | uint32_t u32Alignment5;
|
---|
412 | } AHCIPORT;
|
---|
413 | AssertCompileSizeAlignment(AHCIPORT, 8);
|
---|
414 | /** Pointer to the shared state of an AHCI port. */
|
---|
415 | typedef AHCIPORT *PAHCIPORT;
|
---|
416 |
|
---|
417 |
|
---|
418 | /**
|
---|
419 | * The ring-3 state of an AHCI port.
|
---|
420 | *
|
---|
421 | * @implements PDMIBASE
|
---|
422 | * @implements PDMIMEDIAPORT
|
---|
423 | * @implements PDMIMEDIAEXPORT
|
---|
424 | */
|
---|
425 | typedef struct AHCIPORTR3
|
---|
426 | {
|
---|
427 | /** Pointer to the device instance - only to get our bearings in an interface
|
---|
428 | * method, nothing else. */
|
---|
429 | PPDMDEVINSR3 pDevIns;
|
---|
430 |
|
---|
431 | /** The LUN (same as port number). */
|
---|
432 | uint32_t iLUN;
|
---|
433 |
|
---|
434 | /** Device specific settings (R3 only stuff). */
|
---|
435 | /** Pointer to the attached driver's base interface. */
|
---|
436 | R3PTRTYPE(PPDMIBASE) pDrvBase;
|
---|
437 | /** Pointer to the attached driver's block interface. */
|
---|
438 | R3PTRTYPE(PPDMIMEDIA) pDrvMedia;
|
---|
439 | /** Pointer to the attached driver's extended interface. */
|
---|
440 | R3PTRTYPE(PPDMIMEDIAEX) pDrvMediaEx;
|
---|
441 | /** Port description. */
|
---|
442 | char szDesc[8];
|
---|
443 | /** The base interface. */
|
---|
444 | PDMIBASE IBase;
|
---|
445 | /** The block port interface. */
|
---|
446 | PDMIMEDIAPORT IPort;
|
---|
447 | /** The extended media port interface. */
|
---|
448 | PDMIMEDIAEXPORT IMediaExPort;
|
---|
449 |
|
---|
450 | /** Async IO Thread. */
|
---|
451 | R3PTRTYPE(PPDMTHREAD) pAsyncIOThread;
|
---|
452 | /** First task throwing an error. */
|
---|
453 | R3PTRTYPE(volatile PAHCIREQ) pTaskErr;
|
---|
454 |
|
---|
455 | } AHCIPORTR3;
|
---|
456 | AssertCompileSizeAlignment(AHCIPORTR3, 8);
|
---|
457 | /** Pointer to the ring-3 state of an AHCI port. */
|
---|
458 | typedef AHCIPORTR3 *PAHCIPORTR3;
|
---|
459 |
|
---|
460 |
|
---|
461 | /**
|
---|
462 | * Main AHCI device state.
|
---|
463 | *
|
---|
464 | * @implements PDMILEDPORTS
|
---|
465 | */
|
---|
466 | typedef struct AHCI
|
---|
467 | {
|
---|
468 | /** Global Host Control register of the HBA
|
---|
469 | * @todo r=bird: Make this a 'name' doxygen comment with { and add a
|
---|
470 | * corrsponding at-} where appropriate. I cannot tell where to put the
|
---|
471 | * latter. */
|
---|
472 |
|
---|
473 | /** HBA Capabilities - Readonly */
|
---|
474 | uint32_t regHbaCap;
|
---|
475 | /** HBA Control */
|
---|
476 | uint32_t regHbaCtrl;
|
---|
477 | /** Interrupt Status */
|
---|
478 | uint32_t regHbaIs;
|
---|
479 | /** Ports Implemented - Readonly */
|
---|
480 | uint32_t regHbaPi;
|
---|
481 | /** AHCI Version - Readonly */
|
---|
482 | uint32_t regHbaVs;
|
---|
483 | /** Command completion coalescing control */
|
---|
484 | uint32_t regHbaCccCtl;
|
---|
485 | /** Command completion coalescing ports */
|
---|
486 | uint32_t regHbaCccPorts;
|
---|
487 |
|
---|
488 | /** Index register for BIOS access. */
|
---|
489 | uint32_t regIdx;
|
---|
490 |
|
---|
491 | /** Countdown timer for command completion coalescing. */
|
---|
492 | TMTIMERHANDLE hHbaCccTimer;
|
---|
493 |
|
---|
494 | /** Which port number is used to mark an CCC interrupt */
|
---|
495 | uint8_t uCccPortNr;
|
---|
496 | uint8_t abAlignment1[7];
|
---|
497 |
|
---|
498 | /** Timeout value */
|
---|
499 | uint64_t uCccTimeout;
|
---|
500 | /** Number of completions used to assert an interrupt */
|
---|
501 | uint32_t uCccNr;
|
---|
502 | /** Current number of completed commands */
|
---|
503 | uint32_t uCccCurrentNr;
|
---|
504 |
|
---|
505 | /** Register structure per port */
|
---|
506 | AHCIPORT aPorts[AHCI_MAX_NR_PORTS_IMPL];
|
---|
507 |
|
---|
508 | /** The critical section. */
|
---|
509 | PDMCRITSECT lock;
|
---|
510 |
|
---|
511 | /** Bitmask of ports which asserted an interrupt. */
|
---|
512 | volatile uint32_t u32PortsInterrupted;
|
---|
513 | /** Number of I/O threads currently active - used for async controller reset handling. */
|
---|
514 | volatile uint32_t cThreadsActive;
|
---|
515 |
|
---|
516 | /** Flag whether the legacy port reset method should be used to make it work with saved states. */
|
---|
517 | bool fLegacyPortResetMethod;
|
---|
518 | /** Enable tiger (10.4.x) SSTS hack or not. */
|
---|
519 | bool fTigerHack;
|
---|
520 | /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
|
---|
521 | volatile bool f8ByteMMIO4BytesWrittenSuccessfully;
|
---|
522 |
|
---|
523 | /** Device is in a reset state.
|
---|
524 | * @todo r=bird: This isn't actually being modified by anyone... */
|
---|
525 | bool fReset;
|
---|
526 | /** Supports 64bit addressing
|
---|
527 | * @todo r=bird: This isn't really being modified by anyone (always false). */
|
---|
528 | bool f64BitAddr;
|
---|
529 | /** Flag whether the controller has BIOS access enabled.
|
---|
530 | * @todo r=bird: Not used, just queried from CFGM. */
|
---|
531 | bool fBootable;
|
---|
532 |
|
---|
533 | bool afAlignment2[2];
|
---|
534 |
|
---|
535 | /** Number of usable ports on this controller. */
|
---|
536 | uint32_t cPortsImpl;
|
---|
537 | /** Number of usable command slots for each port. */
|
---|
538 | uint32_t cCmdSlotsAvail;
|
---|
539 |
|
---|
540 | /** PCI region \#0: Legacy IDE fake, 8 ports. */
|
---|
541 | IOMIOPORTHANDLE hIoPortsLegacyFake0;
|
---|
542 | /** PCI region \#1: Legacy IDE fake, 1 port. */
|
---|
543 | IOMIOPORTHANDLE hIoPortsLegacyFake1;
|
---|
544 | /** PCI region \#2: Legacy IDE fake, 8 ports. */
|
---|
545 | IOMIOPORTHANDLE hIoPortsLegacyFake2;
|
---|
546 | /** PCI region \#3: Legacy IDE fake, 1 port. */
|
---|
547 | IOMIOPORTHANDLE hIoPortsLegacyFake3;
|
---|
548 | /** PCI region \#4: BMDMA I/O port range, 16 ports, used for the Index/Data
|
---|
549 | * pair register access. */
|
---|
550 | IOMIOPORTHANDLE hIoPortIdxData;
|
---|
551 | /** PCI region \#5: MMIO registers. */
|
---|
552 | IOMMMIOHANDLE hMmio;
|
---|
553 | } AHCI;
|
---|
554 | AssertCompileMemberAlignment(AHCI, aPorts, 8);
|
---|
555 | /** Pointer to the state of an AHCI device. */
|
---|
556 | typedef AHCI *PAHCI;
|
---|
557 |
|
---|
558 |
|
---|
559 | /**
|
---|
560 | * Main AHCI device ring-3 state.
|
---|
561 | *
|
---|
562 | * @implements PDMILEDPORTS
|
---|
563 | */
|
---|
564 | typedef struct AHCIR3
|
---|
565 | {
|
---|
566 | /** Pointer to the device instance - only for getting our bearings in
|
---|
567 | * interface methods. */
|
---|
568 | PPDMDEVINSR3 pDevIns;
|
---|
569 |
|
---|
570 | /** Status LUN: The base interface. */
|
---|
571 | PDMIBASE IBase;
|
---|
572 | /** Status LUN: Leds interface. */
|
---|
573 | PDMILEDPORTS ILeds;
|
---|
574 | /** Status LUN: Partner of ILeds. */
|
---|
575 | R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
|
---|
576 | /** Status LUN: Media Notifys. */
|
---|
577 | R3PTRTYPE(PPDMIMEDIANOTIFY) pMediaNotify;
|
---|
578 |
|
---|
579 | /** Register structure per port */
|
---|
580 | AHCIPORTR3 aPorts[AHCI_MAX_NR_PORTS_IMPL];
|
---|
581 |
|
---|
582 | /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
|
---|
583 | * a port is entering the idle state. */
|
---|
584 | bool volatile fSignalIdle;
|
---|
585 | bool afAlignment7[2+4];
|
---|
586 | } AHCIR3;
|
---|
587 | /** Pointer to the ring-3 state of an AHCI device. */
|
---|
588 | typedef AHCIR3 *PAHCIR3;
|
---|
589 |
|
---|
590 |
|
---|
591 | /**
|
---|
592 | * Main AHCI device ring-0 state.
|
---|
593 | */
|
---|
594 | typedef struct AHCIR0
|
---|
595 | {
|
---|
596 | uint64_t uUnused;
|
---|
597 | } AHCIR0;
|
---|
598 | /** Pointer to the ring-0 state of an AHCI device. */
|
---|
599 | typedef AHCIR0 *PAHCIR0;
|
---|
600 |
|
---|
601 |
|
---|
602 | /**
|
---|
603 | * Main AHCI device raw-mode state.
|
---|
604 | */
|
---|
605 | typedef struct AHCIRC
|
---|
606 | {
|
---|
607 | uint64_t uUnused;
|
---|
608 | } AHCIRC;
|
---|
609 | /** Pointer to the raw-mode state of an AHCI device. */
|
---|
610 | typedef AHCIRC *PAHCIRC;
|
---|
611 |
|
---|
612 |
|
---|
613 | /** Main AHCI device current context state. */
|
---|
614 | typedef CTX_SUFF(AHCI) AHCICC;
|
---|
615 | /** Pointer to the current context state of an AHCI device. */
|
---|
616 | typedef CTX_SUFF(PAHCI) PAHCICC;
|
---|
617 |
|
---|
618 |
|
---|
619 | /**
|
---|
620 | * Scatter gather list entry.
|
---|
621 | */
|
---|
622 | typedef struct
|
---|
623 | {
|
---|
624 | /** Data Base Address. */
|
---|
625 | uint32_t u32DBA;
|
---|
626 | /** Data Base Address - Upper 32-bits. */
|
---|
627 | uint32_t u32DBAUp;
|
---|
628 | /** Reserved */
|
---|
629 | uint32_t u32Reserved;
|
---|
630 | /** Description information. */
|
---|
631 | uint32_t u32DescInf;
|
---|
632 | } SGLEntry;
|
---|
633 | AssertCompileSize(SGLEntry, 16);
|
---|
634 |
|
---|
635 | #ifdef IN_RING3
|
---|
636 | /**
|
---|
637 | * Memory buffer callback.
|
---|
638 | *
|
---|
639 | * @param pDevIns The device instance.
|
---|
640 | * @param GCPhys The guest physical address of the memory buffer.
|
---|
641 | * @param pSgBuf The pointer to the host R3 S/G buffer.
|
---|
642 | * @param cbCopy How many bytes to copy between the two buffers.
|
---|
643 | * @param pcbSkip Initially contains the amount of bytes to skip
|
---|
644 | * starting from the guest physical address before
|
---|
645 | * accessing the S/G buffer and start copying data.
|
---|
646 | * On return this contains the remaining amount if
|
---|
647 | * cbCopy < *pcbSkip or 0 otherwise.
|
---|
648 | */
|
---|
649 | typedef DECLCALLBACKTYPE(void, FNAHCIR3MEMCOPYCALLBACK,(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
|
---|
650 | PRTSGBUF pSgBuf, size_t cbCopy, size_t *pcbSkip));
|
---|
651 | /** Pointer to a memory copy buffer callback. */
|
---|
652 | typedef FNAHCIR3MEMCOPYCALLBACK *PFNAHCIR3MEMCOPYCALLBACK;
|
---|
653 | #endif
|
---|
654 |
|
---|
655 | /** Defines for a scatter gather list entry. */
|
---|
656 | #define SGLENTRY_DBA_READONLY ~(RT_BIT(0))
|
---|
657 | #define SGLENTRY_DESCINF_I RT_BIT(31)
|
---|
658 | #define SGLENTRY_DESCINF_DBC 0x3fffff
|
---|
659 | #define SGLENTRY_DESCINF_READONLY 0x803fffff
|
---|
660 |
|
---|
661 | /* Defines for the global host control registers for the HBA. */
|
---|
662 |
|
---|
663 | #define AHCI_HBA_GLOBAL_SIZE 0x100
|
---|
664 |
|
---|
665 | /* Defines for the HBA Capabilities - Readonly */
|
---|
666 | #define AHCI_HBA_CAP_S64A RT_BIT(31)
|
---|
667 | #define AHCI_HBA_CAP_SNCQ RT_BIT(30)
|
---|
668 | #define AHCI_HBA_CAP_SIS RT_BIT(28)
|
---|
669 | #define AHCI_HBA_CAP_SSS RT_BIT(27)
|
---|
670 | #define AHCI_HBA_CAP_SALP RT_BIT(26)
|
---|
671 | #define AHCI_HBA_CAP_SAL RT_BIT(25)
|
---|
672 | #define AHCI_HBA_CAP_SCLO RT_BIT(24)
|
---|
673 | #define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
|
---|
674 | # define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
|
---|
675 | # define AHCI_HBA_CAP_ISS_GEN1 RT_BIT(0)
|
---|
676 | # define AHCI_HBA_CAP_ISS_GEN2 RT_BIT(1)
|
---|
677 | #define AHCI_HBA_CAP_SNZO RT_BIT(19)
|
---|
678 | #define AHCI_HBA_CAP_SAM RT_BIT(18)
|
---|
679 | #define AHCI_HBA_CAP_SPM RT_BIT(17)
|
---|
680 | #define AHCI_HBA_CAP_PMD RT_BIT(15)
|
---|
681 | #define AHCI_HBA_CAP_SSC RT_BIT(14)
|
---|
682 | #define AHCI_HBA_CAP_PSC RT_BIT(13)
|
---|
683 | #define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
|
---|
684 | #define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
|
---|
685 | #define AHCI_HBA_CAP_CCCS RT_BIT(7)
|
---|
686 | #define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
|
---|
687 | #define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
|
---|
688 |
|
---|
689 | /* Defines for the HBA Control register - Read/Write */
|
---|
690 | #define AHCI_HBA_CTRL_AE RT_BIT(31)
|
---|
691 | #define AHCI_HBA_CTRL_IE RT_BIT(1)
|
---|
692 | #define AHCI_HBA_CTRL_HR RT_BIT(0)
|
---|
693 | #define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
|
---|
694 |
|
---|
695 | /* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
|
---|
696 | #define AHCI_HBA_VS_MJR (1 << 16)
|
---|
697 | #define AHCI_HBA_VS_MNR 0x100
|
---|
698 |
|
---|
699 | /* Defines for the command completion coalescing control register */
|
---|
700 | #define AHCI_HBA_CCC_CTL_TV 0xffff0000
|
---|
701 | #define AHCI_HBA_CCC_CTL_TV_SET(x) (x << 16)
|
---|
702 | #define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
|
---|
703 |
|
---|
704 | #define AHCI_HBA_CCC_CTL_CC 0xff00
|
---|
705 | #define AHCI_HBA_CCC_CTL_CC_SET(x) (x << 8)
|
---|
706 | #define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
|
---|
707 |
|
---|
708 | #define AHCI_HBA_CCC_CTL_INT 0xf8
|
---|
709 | #define AHCI_HBA_CCC_CTL_INT_SET(x) (x << 3)
|
---|
710 | #define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
|
---|
711 |
|
---|
712 | #define AHCI_HBA_CCC_CTL_EN RT_BIT(0)
|
---|
713 |
|
---|
714 | /* Defines for the port registers. */
|
---|
715 |
|
---|
716 | #define AHCI_PORT_REGISTER_SIZE 0x80
|
---|
717 |
|
---|
718 | #define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
|
---|
719 |
|
---|
720 | #define AHCI_PORT_FB_RESERVED 0xffffff00 /* For masking out the reserved bits. */
|
---|
721 |
|
---|
722 | #define AHCI_PORT_IS_CPDS RT_BIT(31)
|
---|
723 | #define AHCI_PORT_IS_TFES RT_BIT(30)
|
---|
724 | #define AHCI_PORT_IS_HBFS RT_BIT(29)
|
---|
725 | #define AHCI_PORT_IS_HBDS RT_BIT(28)
|
---|
726 | #define AHCI_PORT_IS_IFS RT_BIT(27)
|
---|
727 | #define AHCI_PORT_IS_INFS RT_BIT(26)
|
---|
728 | #define AHCI_PORT_IS_OFS RT_BIT(24)
|
---|
729 | #define AHCI_PORT_IS_IPMS RT_BIT(23)
|
---|
730 | #define AHCI_PORT_IS_PRCS RT_BIT(22)
|
---|
731 | #define AHCI_PORT_IS_DIS RT_BIT(7)
|
---|
732 | #define AHCI_PORT_IS_PCS RT_BIT(6)
|
---|
733 | #define AHCI_PORT_IS_DPS RT_BIT(5)
|
---|
734 | #define AHCI_PORT_IS_UFS RT_BIT(4)
|
---|
735 | #define AHCI_PORT_IS_SDBS RT_BIT(3)
|
---|
736 | #define AHCI_PORT_IS_DSS RT_BIT(2)
|
---|
737 | #define AHCI_PORT_IS_PSS RT_BIT(1)
|
---|
738 | #define AHCI_PORT_IS_DHRS RT_BIT(0)
|
---|
739 | #define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
|
---|
740 |
|
---|
741 | #define AHCI_PORT_IE_CPDE RT_BIT(31)
|
---|
742 | #define AHCI_PORT_IE_TFEE RT_BIT(30)
|
---|
743 | #define AHCI_PORT_IE_HBFE RT_BIT(29)
|
---|
744 | #define AHCI_PORT_IE_HBDE RT_BIT(28)
|
---|
745 | #define AHCI_PORT_IE_IFE RT_BIT(27)
|
---|
746 | #define AHCI_PORT_IE_INFE RT_BIT(26)
|
---|
747 | #define AHCI_PORT_IE_OFE RT_BIT(24)
|
---|
748 | #define AHCI_PORT_IE_IPME RT_BIT(23)
|
---|
749 | #define AHCI_PORT_IE_PRCE RT_BIT(22)
|
---|
750 | #define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
|
---|
751 | #define AHCI_PORT_IE_PCE RT_BIT(6)
|
---|
752 | #define AHCI_PORT_IE_DPE RT_BIT(5)
|
---|
753 | #define AHCI_PORT_IE_UFE RT_BIT(4)
|
---|
754 | #define AHCI_PORT_IE_SDBE RT_BIT(3)
|
---|
755 | #define AHCI_PORT_IE_DSE RT_BIT(2)
|
---|
756 | #define AHCI_PORT_IE_PSE RT_BIT(1)
|
---|
757 | #define AHCI_PORT_IE_DHRE RT_BIT(0)
|
---|
758 | #define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
|
---|
759 |
|
---|
760 | #define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
|
---|
761 | #define AHCI_PORT_CMD_ICC_SHIFT(x) ((x) << 28)
|
---|
762 | # define AHCI_PORT_CMD_ICC_IDLE 0x0
|
---|
763 | # define AHCI_PORT_CMD_ICC_ACTIVE 0x1
|
---|
764 | # define AHCI_PORT_CMD_ICC_PARTIAL 0x2
|
---|
765 | # define AHCI_PORT_CMD_ICC_SLUMBER 0x6
|
---|
766 | #define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
|
---|
767 | #define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
|
---|
768 | #define AHCI_PORT_CMD_DLAE RT_BIT(25)
|
---|
769 | #define AHCI_PORT_CMD_ATAPI RT_BIT(24)
|
---|
770 | #define AHCI_PORT_CMD_CPD RT_BIT(20)
|
---|
771 | #define AHCI_PORT_CMD_ISP RT_BIT(19) /* Readonly */
|
---|
772 | #define AHCI_PORT_CMD_HPCP RT_BIT(18)
|
---|
773 | #define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
|
---|
774 | #define AHCI_PORT_CMD_CPS RT_BIT(16)
|
---|
775 | #define AHCI_PORT_CMD_CR RT_BIT(15) /* Readonly */
|
---|
776 | #define AHCI_PORT_CMD_FR RT_BIT(14) /* Readonly */
|
---|
777 | #define AHCI_PORT_CMD_ISS RT_BIT(13) /* Readonly */
|
---|
778 | #define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
|
---|
779 | #define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
|
---|
780 | #define AHCI_PORT_CMD_FRE RT_BIT(4)
|
---|
781 | #define AHCI_PORT_CMD_CLO RT_BIT(3)
|
---|
782 | #define AHCI_PORT_CMD_POD RT_BIT(2)
|
---|
783 | #define AHCI_PORT_CMD_SUD RT_BIT(1)
|
---|
784 | #define AHCI_PORT_CMD_ST RT_BIT(0)
|
---|
785 | #define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
|
---|
786 |
|
---|
787 | #define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
|
---|
788 | #define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
|
---|
789 | #define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
|
---|
790 | #define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
|
---|
791 | #define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
|
---|
792 | #define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
|
---|
793 | #define AHCI_PORT_SCTL_DET_NINIT 0
|
---|
794 | #define AHCI_PORT_SCTL_DET_INIT 1
|
---|
795 | #define AHCI_PORT_SCTL_DET_OFFLINE 4
|
---|
796 | #define AHCI_PORT_SCTL_READONLY 0xfff
|
---|
797 |
|
---|
798 | #define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
|
---|
799 | #define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
|
---|
800 | #define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
|
---|
801 | #define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
|
---|
802 | #define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
|
---|
803 | #define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
|
---|
804 |
|
---|
805 | #define AHCI_PORT_TFD_BSY RT_BIT(7)
|
---|
806 | #define AHCI_PORT_TFD_DRQ RT_BIT(3)
|
---|
807 | #define AHCI_PORT_TFD_ERR RT_BIT(0)
|
---|
808 |
|
---|
809 | #define AHCI_PORT_SERR_X RT_BIT(26)
|
---|
810 | #define AHCI_PORT_SERR_W RT_BIT(18)
|
---|
811 | #define AHCI_PORT_SERR_N RT_BIT(16)
|
---|
812 |
|
---|
813 | /* Signatures for attached storage devices. */
|
---|
814 | #define AHCI_PORT_SIG_DISK 0x00000101
|
---|
815 | #define AHCI_PORT_SIG_ATAPI 0xeb140101
|
---|
816 |
|
---|
817 | /*
|
---|
818 | * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
|
---|
819 | * regFB points to the base of this area.
|
---|
820 | * Every FIS type has an offset where it is posted in this area.
|
---|
821 | */
|
---|
822 | #define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
|
---|
823 | #define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
|
---|
824 | #define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
|
---|
825 | #define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
|
---|
826 | #define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
|
---|
827 |
|
---|
828 | /** Mask to get the LBA value from a LBA range. */
|
---|
829 | #define AHCI_RANGE_LBA_MASK UINT64_C(0xffffffffffff)
|
---|
830 | /** Mas to get the length value from a LBA range. */
|
---|
831 | #define AHCI_RANGE_LENGTH_MASK UINT64_C(0xffff000000000000)
|
---|
832 | /** Returns the length of the range in sectors. */
|
---|
833 | #define AHCI_RANGE_LENGTH_GET(val) (((val) & AHCI_RANGE_LENGTH_MASK) >> 48)
|
---|
834 |
|
---|
835 | /**
|
---|
836 | * AHCI register operator.
|
---|
837 | */
|
---|
838 | typedef struct ahci_opreg
|
---|
839 | {
|
---|
840 | const char *pszName;
|
---|
841 | VBOXSTRICTRC (*pfnRead )(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value);
|
---|
842 | VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t u32Value);
|
---|
843 | } AHCIOPREG;
|
---|
844 |
|
---|
845 | /**
|
---|
846 | * AHCI port register operator.
|
---|
847 | */
|
---|
848 | typedef struct pAhciPort_opreg
|
---|
849 | {
|
---|
850 | const char *pszName;
|
---|
851 | VBOXSTRICTRC (*pfnRead )(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value);
|
---|
852 | VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value);
|
---|
853 | } AHCIPORTOPREG;
|
---|
854 |
|
---|
855 |
|
---|
856 | /*********************************************************************************************************************************
|
---|
857 | * Internal Functions *
|
---|
858 | *********************************************************************************************************************************/
|
---|
859 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
|
---|
860 | RT_C_DECLS_BEGIN
|
---|
861 | #ifdef IN_RING3
|
---|
862 | static void ahciR3HBAReset(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIR3 pThisCC);
|
---|
863 | static int ahciPostFisIntoMemory(PPDMDEVINS pDevIns, PAHCIPORT pAhciPort, unsigned uFisType, uint8_t *pCmdFis);
|
---|
864 | static void ahciPostFirstD2HFisIntoMemory(PPDMDEVINS pDevIns, PAHCIPORT pAhciPort);
|
---|
865 | static size_t ahciR3CopyBufferToPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq, const void *pvSrc, size_t cbSrc, size_t cbSkip);
|
---|
866 | static bool ahciR3CancelActiveTasks(PAHCIPORTR3 pAhciPortR3);
|
---|
867 | #endif
|
---|
868 | RT_C_DECLS_END
|
---|
869 |
|
---|
870 |
|
---|
871 | /*********************************************************************************************************************************
|
---|
872 | * Defined Constants And Macros *
|
---|
873 | *********************************************************************************************************************************/
|
---|
874 | #define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
|
---|
875 |
|
---|
876 | #ifdef IN_RING3
|
---|
877 |
|
---|
878 | # ifdef LOG_USE_C99
|
---|
879 | # define ahciLog(a) \
|
---|
880 | Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
|
---|
881 | # else
|
---|
882 | # define ahciLog(a) \
|
---|
883 | do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
|
---|
884 | # endif
|
---|
885 |
|
---|
886 | #elif defined(IN_RING0)
|
---|
887 |
|
---|
888 | # ifdef LOG_USE_C99
|
---|
889 | # define ahciLog(a) \
|
---|
890 | Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
|
---|
891 | # else
|
---|
892 | # define ahciLog(a) \
|
---|
893 | do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
|
---|
894 | # endif
|
---|
895 |
|
---|
896 | #elif defined(IN_RC)
|
---|
897 |
|
---|
898 | # ifdef LOG_USE_C99
|
---|
899 | # define ahciLog(a) \
|
---|
900 | Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
|
---|
901 | # else
|
---|
902 | # define ahciLog(a) \
|
---|
903 | do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
|
---|
904 | # endif
|
---|
905 |
|
---|
906 | #endif
|
---|
907 |
|
---|
908 |
|
---|
909 |
|
---|
910 | /**
|
---|
911 | * Update PCI IRQ levels
|
---|
912 | */
|
---|
913 | static void ahciHbaClearInterrupt(PPDMDEVINS pDevIns)
|
---|
914 | {
|
---|
915 | Log(("%s: Clearing interrupt\n", __FUNCTION__));
|
---|
916 | PDMDevHlpPCISetIrq(pDevIns, 0, 0);
|
---|
917 | }
|
---|
918 |
|
---|
919 | /**
|
---|
920 | * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
|
---|
921 | */
|
---|
922 | static int ahciHbaSetInterrupt(PPDMDEVINS pDevIns, PAHCI pThis, uint8_t iPort, int rcBusy)
|
---|
923 | {
|
---|
924 | Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
|
---|
925 |
|
---|
926 | int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->lock, rcBusy);
|
---|
927 | if (rc != VINF_SUCCESS)
|
---|
928 | return rc;
|
---|
929 |
|
---|
930 | if (pThis->regHbaCtrl & AHCI_HBA_CTRL_IE)
|
---|
931 | {
|
---|
932 | if ((pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pThis->regHbaCccPorts & (1 << iPort)))
|
---|
933 | {
|
---|
934 | pThis->uCccCurrentNr++;
|
---|
935 | if (pThis->uCccCurrentNr >= pThis->uCccNr)
|
---|
936 | {
|
---|
937 | /* Reset command completion coalescing state. */
|
---|
938 | PDMDevHlpTimerSetMillies(pDevIns, pThis->hHbaCccTimer, pThis->uCccTimeout);
|
---|
939 | pThis->uCccCurrentNr = 0;
|
---|
940 |
|
---|
941 | pThis->u32PortsInterrupted |= (1 << pThis->uCccPortNr);
|
---|
942 | if (!(pThis->u32PortsInterrupted & ~(1 << pThis->uCccPortNr)))
|
---|
943 | {
|
---|
944 | Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
|
---|
945 | PDMDevHlpPCISetIrq(pDevIns, 0, 1);
|
---|
946 | }
|
---|
947 | }
|
---|
948 | }
|
---|
949 | else
|
---|
950 | {
|
---|
951 | /* If only the bit of the actual port is set assert an interrupt
|
---|
952 | * because the interrupt status register was already read by the guest
|
---|
953 | * and we need to send a new notification.
|
---|
954 | * Otherwise an interrupt is still pending.
|
---|
955 | */
|
---|
956 | ASMAtomicOrU32((volatile uint32_t *)&pThis->u32PortsInterrupted, (1 << iPort));
|
---|
957 | if (!(pThis->u32PortsInterrupted & ~(1 << iPort)))
|
---|
958 | {
|
---|
959 | Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
|
---|
960 | PDMDevHlpPCISetIrq(pDevIns, 0, 1);
|
---|
961 | }
|
---|
962 | }
|
---|
963 | }
|
---|
964 |
|
---|
965 | PDMDevHlpCritSectLeave(pDevIns, &pThis->lock);
|
---|
966 | return VINF_SUCCESS;
|
---|
967 | }
|
---|
968 |
|
---|
969 | #ifdef IN_RING3
|
---|
970 |
|
---|
971 | /**
|
---|
972 | * @callback_method_impl{FNTMTIMERDEV, Assert irq when an CCC timeout occurs.}
|
---|
973 | */
|
---|
974 | static DECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
|
---|
975 | {
|
---|
976 | RT_NOREF(pDevIns, hTimer);
|
---|
977 | PAHCI pThis = (PAHCI)pvUser;
|
---|
978 |
|
---|
979 | int rc = ahciHbaSetInterrupt(pDevIns, pThis, pThis->uCccPortNr, VERR_IGNORED);
|
---|
980 | AssertRC(rc);
|
---|
981 | }
|
---|
982 |
|
---|
983 | /**
|
---|
984 | * Finishes the port reset of the given port.
|
---|
985 | *
|
---|
986 | * @param pDevIns The device instance.
|
---|
987 | * @param pThis The shared AHCI state.
|
---|
988 | * @param pAhciPort The port to finish the reset on, shared bits.
|
---|
989 | * @param pAhciPortR3 The port to finish the reset on, ring-3 bits.
|
---|
990 | */
|
---|
991 | static void ahciPortResetFinish(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3)
|
---|
992 | {
|
---|
993 | ahciLog(("%s: Initiated.\n", __FUNCTION__));
|
---|
994 |
|
---|
995 | /* Cancel all tasks first. */
|
---|
996 | bool fAllTasksCanceled = ahciR3CancelActiveTasks(pAhciPortR3);
|
---|
997 | Assert(fAllTasksCanceled); NOREF(fAllTasksCanceled);
|
---|
998 |
|
---|
999 | /* Signature for SATA device. */
|
---|
1000 | if (pAhciPort->fATAPI)
|
---|
1001 | pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
|
---|
1002 | else
|
---|
1003 | pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
|
---|
1004 |
|
---|
1005 | /* We received a COMINIT from the device. Tell the guest. */
|
---|
1006 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
|
---|
1007 | pAhciPort->regSERR |= AHCI_PORT_SERR_X;
|
---|
1008 | pAhciPort->regTFD |= ATA_STAT_BUSY;
|
---|
1009 |
|
---|
1010 | if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSent))
|
---|
1011 | {
|
---|
1012 | ahciPostFirstD2HFisIntoMemory(pDevIns, pAhciPort);
|
---|
1013 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
|
---|
1014 |
|
---|
1015 | if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
|
---|
1016 | {
|
---|
1017 | int rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
1018 | AssertRC(rc);
|
---|
1019 | }
|
---|
1020 | }
|
---|
1021 |
|
---|
1022 | pAhciPort->regSSTS = (0x01 << 8) /* Interface is active. */
|
---|
1023 | | (0x03 << 0); /* Device detected and communication established. */
|
---|
1024 |
|
---|
1025 | /*
|
---|
1026 | * Use the maximum allowed speed.
|
---|
1027 | * (Not that it changes anything really)
|
---|
1028 | */
|
---|
1029 | switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
|
---|
1030 | {
|
---|
1031 | case 0x01:
|
---|
1032 | pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
|
---|
1033 | break;
|
---|
1034 | case 0x02:
|
---|
1035 | case 0x00:
|
---|
1036 | default:
|
---|
1037 | pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
|
---|
1038 | break;
|
---|
1039 | }
|
---|
1040 |
|
---|
1041 | ASMAtomicXchgBool(&pAhciPort->fPortReset, false);
|
---|
1042 | }
|
---|
1043 |
|
---|
1044 | #endif /* IN_RING3 */
|
---|
1045 |
|
---|
1046 | /**
|
---|
1047 | * Kicks the I/O thread from RC or R0.
|
---|
1048 | *
|
---|
1049 | * @param pDevIns The device instance.
|
---|
1050 | * @param pAhciPort The port to kick, shared bits.
|
---|
1051 | */
|
---|
1052 | static void ahciIoThreadKick(PPDMDEVINS pDevIns, PAHCIPORT pAhciPort)
|
---|
1053 | {
|
---|
1054 | LogFlowFunc(("Signal event semaphore\n"));
|
---|
1055 | int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pAhciPort->hEvtProcess);
|
---|
1056 | AssertRC(rc);
|
---|
1057 | }
|
---|
1058 |
|
---|
1059 | static VBOXSTRICTRC PortCmdIssue_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1060 | {
|
---|
1061 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1062 | RT_NOREF(pThis, iReg);
|
---|
1063 |
|
---|
1064 | /* Update the CI register first. */
|
---|
1065 | uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
|
---|
1066 | pAhciPort->regCI &= ~uCIValue;
|
---|
1067 |
|
---|
1068 | if ( (pAhciPort->regCMD & AHCI_PORT_CMD_CR)
|
---|
1069 | && u32Value > 0)
|
---|
1070 | {
|
---|
1071 | /*
|
---|
1072 | * Clear all tasks which are already marked as busy. The guest
|
---|
1073 | * shouldn't write already busy tasks actually.
|
---|
1074 | */
|
---|
1075 | u32Value &= ~pAhciPort->regCI;
|
---|
1076 |
|
---|
1077 | ASMAtomicOrU32(&pAhciPort->u32TasksNew, u32Value);
|
---|
1078 |
|
---|
1079 | /* Send a notification to R3 if u32TasksNew was 0 before our write. */
|
---|
1080 | if (ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
|
---|
1081 | ahciIoThreadKick(pDevIns, pAhciPort);
|
---|
1082 | else
|
---|
1083 | ahciLog(("%s: Worker thread busy, no need to kick.\n", __FUNCTION__));
|
---|
1084 | }
|
---|
1085 | else
|
---|
1086 | ahciLog(("%s: Nothing to do (CMD=%08x).\n", __FUNCTION__, pAhciPort->regCMD));
|
---|
1087 |
|
---|
1088 | pAhciPort->regCI |= u32Value;
|
---|
1089 |
|
---|
1090 | return VINF_SUCCESS;
|
---|
1091 | }
|
---|
1092 |
|
---|
1093 | static VBOXSTRICTRC PortCmdIssue_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1094 | {
|
---|
1095 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1096 |
|
---|
1097 | uint32_t uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
|
---|
1098 | ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
|
---|
1099 |
|
---|
1100 | pAhciPort->regCI &= ~uCIValue;
|
---|
1101 | *pu32Value = pAhciPort->regCI;
|
---|
1102 |
|
---|
1103 | return VINF_SUCCESS;
|
---|
1104 | }
|
---|
1105 |
|
---|
1106 | static VBOXSTRICTRC PortSActive_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1107 | {
|
---|
1108 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1109 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1110 |
|
---|
1111 | pAhciPort->regSACT |= u32Value;
|
---|
1112 |
|
---|
1113 | return VINF_SUCCESS;
|
---|
1114 | }
|
---|
1115 |
|
---|
1116 | static VBOXSTRICTRC PortSActive_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1117 | {
|
---|
1118 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1119 |
|
---|
1120 | uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
|
---|
1121 | pAhciPort->regSACT &= ~u32TasksFinished;
|
---|
1122 |
|
---|
1123 | ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
|
---|
1124 | __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
|
---|
1125 |
|
---|
1126 | *pu32Value = pAhciPort->regSACT;
|
---|
1127 |
|
---|
1128 | return VINF_SUCCESS;
|
---|
1129 | }
|
---|
1130 |
|
---|
1131 | static VBOXSTRICTRC PortSError_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1132 | {
|
---|
1133 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1134 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1135 |
|
---|
1136 | if ( (u32Value & AHCI_PORT_SERR_X)
|
---|
1137 | && (pAhciPort->regSERR & AHCI_PORT_SERR_X))
|
---|
1138 | {
|
---|
1139 | ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
|
---|
1140 | pAhciPort->regTFD |= ATA_STAT_ERR;
|
---|
1141 | pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
|
---|
1142 | }
|
---|
1143 |
|
---|
1144 | if ( (u32Value & AHCI_PORT_SERR_N)
|
---|
1145 | && (pAhciPort->regSERR & AHCI_PORT_SERR_N))
|
---|
1146 | ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PRCS);
|
---|
1147 |
|
---|
1148 | pAhciPort->regSERR &= ~u32Value;
|
---|
1149 |
|
---|
1150 | return VINF_SUCCESS;
|
---|
1151 | }
|
---|
1152 |
|
---|
1153 | static VBOXSTRICTRC PortSError_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1154 | {
|
---|
1155 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1156 | ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
|
---|
1157 | *pu32Value = pAhciPort->regSERR;
|
---|
1158 | return VINF_SUCCESS;
|
---|
1159 | }
|
---|
1160 |
|
---|
1161 | static VBOXSTRICTRC PortSControl_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1162 | {
|
---|
1163 | RT_NOREF(pThis, iReg);
|
---|
1164 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1165 | ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
|
---|
1166 | AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
|
---|
1167 |
|
---|
1168 | #ifndef IN_RING3
|
---|
1169 | RT_NOREF(pDevIns, pAhciPort, u32Value);
|
---|
1170 | return VINF_IOM_R3_MMIO_WRITE;
|
---|
1171 | #else
|
---|
1172 | if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
|
---|
1173 | {
|
---|
1174 | if (!ASMAtomicXchgBool(&pAhciPort->fPortReset, true))
|
---|
1175 | LogRel(("AHCI#%u: Port %d reset\n", pDevIns->iInstance,
|
---|
1176 | pAhciPort->iLUN));
|
---|
1177 |
|
---|
1178 | pAhciPort->regSSTS = 0;
|
---|
1179 | pAhciPort->regSIG = UINT32_MAX;
|
---|
1180 | pAhciPort->regTFD = 0x7f;
|
---|
1181 | pAhciPort->fFirstD2HFisSent = false;
|
---|
1182 | pAhciPort->regSCTL = u32Value;
|
---|
1183 | }
|
---|
1184 | else if ( (u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT
|
---|
1185 | && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT
|
---|
1186 | && pAhciPort->fPresent)
|
---|
1187 | {
|
---|
1188 | /* Do the port reset here, so the guest sees the new status immediately. */
|
---|
1189 | if (pThis->fLegacyPortResetMethod)
|
---|
1190 | {
|
---|
1191 | PAHCIR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAHCICC);
|
---|
1192 | PAHCIPORTR3 pAhciPortR3 = &RT_SAFE_SUBSCRIPT(pThisCC->aPorts, pAhciPort->iLUN);
|
---|
1193 | ahciPortResetFinish(pDevIns, pThis, pAhciPort, pAhciPortR3);
|
---|
1194 | pAhciPort->regSCTL = u32Value; /* Update after finishing the reset, so the I/O thread doesn't get a chance to do the reset. */
|
---|
1195 | }
|
---|
1196 | else
|
---|
1197 | {
|
---|
1198 | if (!pThis->fTigerHack)
|
---|
1199 | pAhciPort->regSSTS = 0x1; /* Indicate device presence detected but communication not established. */
|
---|
1200 | else
|
---|
1201 | pAhciPort->regSSTS = 0x0; /* Indicate no device detected after COMRESET. [tiger hack] */
|
---|
1202 | pAhciPort->regSCTL = u32Value; /* Update before kicking the I/O thread. */
|
---|
1203 |
|
---|
1204 | /* Kick the thread to finish the reset. */
|
---|
1205 | ahciIoThreadKick(pDevIns, pAhciPort);
|
---|
1206 | }
|
---|
1207 | }
|
---|
1208 | else /* Just update the value if there is no device attached. */
|
---|
1209 | pAhciPort->regSCTL = u32Value;
|
---|
1210 |
|
---|
1211 | return VINF_SUCCESS;
|
---|
1212 | #endif
|
---|
1213 | }
|
---|
1214 |
|
---|
1215 | static VBOXSTRICTRC PortSControl_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1216 | {
|
---|
1217 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1218 | ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
|
---|
1219 | ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
|
---|
1220 | AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
|
---|
1221 | AHCI_PORT_SCTL_DET_GET(pAhciPort->regSCTL)));
|
---|
1222 |
|
---|
1223 | *pu32Value = pAhciPort->regSCTL;
|
---|
1224 | return VINF_SUCCESS;
|
---|
1225 | }
|
---|
1226 |
|
---|
1227 | static VBOXSTRICTRC PortSStatus_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1228 | {
|
---|
1229 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1230 | ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
|
---|
1231 | ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
|
---|
1232 | AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
|
---|
1233 | AHCI_PORT_SSTS_DET_GET(pAhciPort->regSSTS)));
|
---|
1234 |
|
---|
1235 | *pu32Value = pAhciPort->regSSTS;
|
---|
1236 | return VINF_SUCCESS;
|
---|
1237 | }
|
---|
1238 |
|
---|
1239 | static VBOXSTRICTRC PortSignature_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1240 | {
|
---|
1241 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1242 | ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
|
---|
1243 | *pu32Value = pAhciPort->regSIG;
|
---|
1244 | return VINF_SUCCESS;
|
---|
1245 | }
|
---|
1246 |
|
---|
1247 | static VBOXSTRICTRC PortTaskFileData_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1248 | {
|
---|
1249 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1250 | ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
|
---|
1251 | ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
|
---|
1252 | (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
|
---|
1253 | (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
|
---|
1254 | *pu32Value = pAhciPort->regTFD;
|
---|
1255 | return VINF_SUCCESS;
|
---|
1256 | }
|
---|
1257 |
|
---|
1258 | /**
|
---|
1259 | * Read from the port command register.
|
---|
1260 | */
|
---|
1261 | static VBOXSTRICTRC PortCmd_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1262 | {
|
---|
1263 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1264 | ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot)));
|
---|
1265 | ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
|
---|
1266 | __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
|
---|
1267 | (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
|
---|
1268 | (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
|
---|
1269 | (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
|
---|
1270 | (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
|
---|
1271 | (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
|
---|
1272 | (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, pAhciPort->u32CurrentCommandSlot,
|
---|
1273 | (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
|
---|
1274 | (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
|
---|
1275 | (pAhciPort->regCMD & AHCI_PORT_CMD_ST)));
|
---|
1276 | *pu32Value = pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot);
|
---|
1277 | return VINF_SUCCESS;
|
---|
1278 | }
|
---|
1279 |
|
---|
1280 | /**
|
---|
1281 | * Write to the port command register.
|
---|
1282 | * This is the register where all the data transfer is started
|
---|
1283 | */
|
---|
1284 | static VBOXSTRICTRC PortCmd_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1285 | {
|
---|
1286 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1287 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1288 | ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
|
---|
1289 | __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
|
---|
1290 | (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
|
---|
1291 | (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
|
---|
1292 | (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
|
---|
1293 | (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
|
---|
1294 | (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
|
---|
1295 | (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
|
---|
1296 | (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
|
---|
1297 | (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
|
---|
1298 | (u32Value & AHCI_PORT_CMD_ST)));
|
---|
1299 |
|
---|
1300 | /* The PxCMD.CCS bits are R/O and maintained separately. */
|
---|
1301 | u32Value &= ~AHCI_PORT_CMD_CCS;
|
---|
1302 |
|
---|
1303 | if (pAhciPort->fPoweredOn && pAhciPort->fSpunUp)
|
---|
1304 | {
|
---|
1305 | if (u32Value & AHCI_PORT_CMD_CLO)
|
---|
1306 | {
|
---|
1307 | ahciLog(("%s: Command list override requested\n", __FUNCTION__));
|
---|
1308 | u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
|
---|
1309 | /* Clear the CLO bit. */
|
---|
1310 | u32Value &= ~(AHCI_PORT_CMD_CLO);
|
---|
1311 | }
|
---|
1312 |
|
---|
1313 | if (u32Value & AHCI_PORT_CMD_ST)
|
---|
1314 | {
|
---|
1315 | /*
|
---|
1316 | * Set engine state to running if there is a device attached and
|
---|
1317 | * IS.PCS is clear.
|
---|
1318 | */
|
---|
1319 | if ( pAhciPort->fPresent
|
---|
1320 | && !(pAhciPort->regIS & AHCI_PORT_IS_PCS))
|
---|
1321 | {
|
---|
1322 | ahciLog(("%s: Engine starts\n", __FUNCTION__));
|
---|
1323 | u32Value |= AHCI_PORT_CMD_CR;
|
---|
1324 |
|
---|
1325 | /* If there is something in CI, kick the I/O thread. */
|
---|
1326 | if ( pAhciPort->regCI > 0
|
---|
1327 | && ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
|
---|
1328 | {
|
---|
1329 | ASMAtomicOrU32(&pAhciPort->u32TasksNew, pAhciPort->regCI);
|
---|
1330 | LogFlowFunc(("Signal event semaphore\n"));
|
---|
1331 | int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pAhciPort->hEvtProcess);
|
---|
1332 | AssertRC(rc);
|
---|
1333 | }
|
---|
1334 | }
|
---|
1335 | else
|
---|
1336 | {
|
---|
1337 | if (!pAhciPort->fPresent)
|
---|
1338 | ahciLog(("%s: No pDrvBase, clearing PxCMD.CR!\n", __FUNCTION__));
|
---|
1339 | else
|
---|
1340 | ahciLog(("%s: PxIS.PCS set (PxIS=%#010x), clearing PxCMD.CR!\n", __FUNCTION__, pAhciPort->regIS));
|
---|
1341 |
|
---|
1342 | u32Value &= ~AHCI_PORT_CMD_CR;
|
---|
1343 | }
|
---|
1344 | }
|
---|
1345 | else
|
---|
1346 | {
|
---|
1347 | ahciLog(("%s: Engine stops\n", __FUNCTION__));
|
---|
1348 | /* Clear command issue register. */
|
---|
1349 | pAhciPort->regCI = 0;
|
---|
1350 | pAhciPort->regSACT = 0;
|
---|
1351 | /* Clear current command slot. */
|
---|
1352 | pAhciPort->u32CurrentCommandSlot = 0;
|
---|
1353 | u32Value &= ~AHCI_PORT_CMD_CR;
|
---|
1354 | }
|
---|
1355 | }
|
---|
1356 | else if (pAhciPort->fPresent)
|
---|
1357 | {
|
---|
1358 | if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
|
---|
1359 | {
|
---|
1360 | ahciLog(("%s: Power on the device\n", __FUNCTION__));
|
---|
1361 | pAhciPort->fPoweredOn = true;
|
---|
1362 |
|
---|
1363 | /*
|
---|
1364 | * Set states in the Port Signature and SStatus registers.
|
---|
1365 | */
|
---|
1366 | if (pAhciPort->fATAPI)
|
---|
1367 | pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
|
---|
1368 | else
|
---|
1369 | pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
|
---|
1370 | pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
|
---|
1371 | (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
|
---|
1372 | (0x03 << 0); /* Device detected and communication established. */
|
---|
1373 |
|
---|
1374 | if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
|
---|
1375 | {
|
---|
1376 | #ifndef IN_RING3
|
---|
1377 | return VINF_IOM_R3_MMIO_WRITE;
|
---|
1378 | #else
|
---|
1379 | ahciPostFirstD2HFisIntoMemory(pDevIns, pAhciPort);
|
---|
1380 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
|
---|
1381 |
|
---|
1382 | if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
|
---|
1383 | {
|
---|
1384 | int rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
1385 | AssertRC(rc);
|
---|
1386 | }
|
---|
1387 | #endif
|
---|
1388 | }
|
---|
1389 | }
|
---|
1390 |
|
---|
1391 | if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
|
---|
1392 | {
|
---|
1393 | ahciLog(("%s: Spin up the device\n", __FUNCTION__));
|
---|
1394 | pAhciPort->fSpunUp = true;
|
---|
1395 | }
|
---|
1396 | }
|
---|
1397 | else
|
---|
1398 | ahciLog(("%s: No pDrvBase, no fPoweredOn + fSpunUp, doing nothing!\n", __FUNCTION__));
|
---|
1399 |
|
---|
1400 | if (u32Value & AHCI_PORT_CMD_FRE)
|
---|
1401 | {
|
---|
1402 | ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
|
---|
1403 |
|
---|
1404 | u32Value |= AHCI_PORT_CMD_FR;
|
---|
1405 |
|
---|
1406 | /* Send the first D2H FIS only if it wasn't already sent. */
|
---|
1407 | if ( !pAhciPort->fFirstD2HFisSent
|
---|
1408 | && pAhciPort->fPresent)
|
---|
1409 | {
|
---|
1410 | #ifndef IN_RING3
|
---|
1411 | return VINF_IOM_R3_MMIO_WRITE;
|
---|
1412 | #else
|
---|
1413 | ahciPostFirstD2HFisIntoMemory(pDevIns, pAhciPort);
|
---|
1414 | pAhciPort->fFirstD2HFisSent = true;
|
---|
1415 | #endif
|
---|
1416 | }
|
---|
1417 | }
|
---|
1418 | else if (!(u32Value & AHCI_PORT_CMD_FRE))
|
---|
1419 | {
|
---|
1420 | ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
|
---|
1421 | u32Value &= ~AHCI_PORT_CMD_FR;
|
---|
1422 | }
|
---|
1423 |
|
---|
1424 | pAhciPort->regCMD = u32Value;
|
---|
1425 |
|
---|
1426 | return VINF_SUCCESS;
|
---|
1427 | }
|
---|
1428 |
|
---|
1429 | /**
|
---|
1430 | * Read from the port interrupt enable register.
|
---|
1431 | */
|
---|
1432 | static VBOXSTRICTRC PortIntrEnable_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1433 | {
|
---|
1434 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1435 | ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
|
---|
1436 | ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
|
---|
1437 | __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
|
---|
1438 | (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
|
---|
1439 | (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
|
---|
1440 | (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
|
---|
1441 | (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
|
---|
1442 | (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
|
---|
1443 | (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
|
---|
1444 | (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
|
---|
1445 | (pAhciPort->regIE & AHCI_PORT_IE_DHRE)));
|
---|
1446 | *pu32Value = pAhciPort->regIE;
|
---|
1447 | return VINF_SUCCESS;
|
---|
1448 | }
|
---|
1449 |
|
---|
1450 | /**
|
---|
1451 | * Write to the port interrupt enable register.
|
---|
1452 | */
|
---|
1453 | static VBOXSTRICTRC PortIntrEnable_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1454 | {
|
---|
1455 | RT_NOREF(iReg);
|
---|
1456 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1457 | ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
|
---|
1458 | __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
|
---|
1459 | (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
|
---|
1460 | (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
|
---|
1461 | (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
|
---|
1462 | (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
|
---|
1463 | (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
|
---|
1464 | (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
|
---|
1465 | (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
|
---|
1466 | (u32Value & AHCI_PORT_IE_DHRE)));
|
---|
1467 |
|
---|
1468 | u32Value &= AHCI_PORT_IE_READONLY;
|
---|
1469 |
|
---|
1470 | /* Check if some a interrupt status bit changed*/
|
---|
1471 | uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
|
---|
1472 |
|
---|
1473 | int rc = VINF_SUCCESS;
|
---|
1474 | if (u32Value & u32IntrStatus)
|
---|
1475 | rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE);
|
---|
1476 |
|
---|
1477 | if (rc == VINF_SUCCESS)
|
---|
1478 | pAhciPort->regIE = u32Value;
|
---|
1479 |
|
---|
1480 | return rc;
|
---|
1481 | }
|
---|
1482 |
|
---|
1483 | /**
|
---|
1484 | * Read from the port interrupt status register.
|
---|
1485 | */
|
---|
1486 | static VBOXSTRICTRC PortIntrSts_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1487 | {
|
---|
1488 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1489 | ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
|
---|
1490 | ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
|
---|
1491 | __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
|
---|
1492 | (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
|
---|
1493 | (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
|
---|
1494 | (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
|
---|
1495 | (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
|
---|
1496 | (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
|
---|
1497 | (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
|
---|
1498 | (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
|
---|
1499 | (pAhciPort->regIS & AHCI_PORT_IS_DHRS)));
|
---|
1500 | *pu32Value = pAhciPort->regIS;
|
---|
1501 | return VINF_SUCCESS;
|
---|
1502 | }
|
---|
1503 |
|
---|
1504 | /**
|
---|
1505 | * Write to the port interrupt status register.
|
---|
1506 | */
|
---|
1507 | static VBOXSTRICTRC PortIntrSts_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1508 | {
|
---|
1509 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1510 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1511 | ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
|
---|
1512 |
|
---|
1513 | return VINF_SUCCESS;
|
---|
1514 | }
|
---|
1515 |
|
---|
1516 | /**
|
---|
1517 | * Read from the port FIS base address upper 32bit register.
|
---|
1518 | */
|
---|
1519 | static VBOXSTRICTRC PortFisAddrUp_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1520 | {
|
---|
1521 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1522 | ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
|
---|
1523 | *pu32Value = pAhciPort->regFBU;
|
---|
1524 | return VINF_SUCCESS;
|
---|
1525 | }
|
---|
1526 |
|
---|
1527 | /**
|
---|
1528 | * Write to the port FIS base address upper 32bit register.
|
---|
1529 | */
|
---|
1530 | static VBOXSTRICTRC PortFisAddrUp_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1531 | {
|
---|
1532 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1533 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1534 |
|
---|
1535 | pAhciPort->regFBU = u32Value;
|
---|
1536 | pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
|
---|
1537 |
|
---|
1538 | return VINF_SUCCESS;
|
---|
1539 | }
|
---|
1540 |
|
---|
1541 | /**
|
---|
1542 | * Read from the port FIS base address register.
|
---|
1543 | */
|
---|
1544 | static VBOXSTRICTRC PortFisAddr_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1545 | {
|
---|
1546 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1547 | ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
|
---|
1548 | *pu32Value = pAhciPort->regFB;
|
---|
1549 | return VINF_SUCCESS;
|
---|
1550 | }
|
---|
1551 |
|
---|
1552 | /**
|
---|
1553 | * Write to the port FIS base address register.
|
---|
1554 | */
|
---|
1555 | static VBOXSTRICTRC PortFisAddr_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1556 | {
|
---|
1557 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1558 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1559 |
|
---|
1560 | Assert(!(u32Value & ~AHCI_PORT_FB_RESERVED));
|
---|
1561 |
|
---|
1562 | pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
|
---|
1563 | pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
|
---|
1564 |
|
---|
1565 | return VINF_SUCCESS;
|
---|
1566 | }
|
---|
1567 |
|
---|
1568 | /**
|
---|
1569 | * Write to the port command list base address upper 32bit register.
|
---|
1570 | */
|
---|
1571 | static VBOXSTRICTRC PortCmdLstAddrUp_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1572 | {
|
---|
1573 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1574 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1575 |
|
---|
1576 | pAhciPort->regCLBU = u32Value;
|
---|
1577 | pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
|
---|
1578 |
|
---|
1579 | return VINF_SUCCESS;
|
---|
1580 | }
|
---|
1581 |
|
---|
1582 | /**
|
---|
1583 | * Read from the port command list base address upper 32bit register.
|
---|
1584 | */
|
---|
1585 | static VBOXSTRICTRC PortCmdLstAddrUp_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1586 | {
|
---|
1587 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1588 | ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
|
---|
1589 | *pu32Value = pAhciPort->regCLBU;
|
---|
1590 | return VINF_SUCCESS;
|
---|
1591 | }
|
---|
1592 |
|
---|
1593 | /**
|
---|
1594 | * Read from the port command list base address register.
|
---|
1595 | */
|
---|
1596 | static VBOXSTRICTRC PortCmdLstAddr_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1597 | {
|
---|
1598 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1599 | ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
|
---|
1600 | *pu32Value = pAhciPort->regCLB;
|
---|
1601 | return VINF_SUCCESS;
|
---|
1602 | }
|
---|
1603 |
|
---|
1604 | /**
|
---|
1605 | * Write to the port command list base address register.
|
---|
1606 | */
|
---|
1607 | static VBOXSTRICTRC PortCmdLstAddr_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1608 | {
|
---|
1609 | RT_NOREF(pDevIns, pThis, iReg);
|
---|
1610 | ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1611 |
|
---|
1612 | Assert(!(u32Value & ~AHCI_PORT_CLB_RESERVED));
|
---|
1613 |
|
---|
1614 | pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
|
---|
1615 | pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
|
---|
1616 |
|
---|
1617 | return VINF_SUCCESS;
|
---|
1618 | }
|
---|
1619 |
|
---|
1620 | /**
|
---|
1621 | * Read from the global Version register.
|
---|
1622 | */
|
---|
1623 | static VBOXSTRICTRC HbaVersion_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1624 | {
|
---|
1625 | RT_NOREF(pDevIns, iReg);
|
---|
1626 | Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, pThis->regHbaVs));
|
---|
1627 | *pu32Value = pThis->regHbaVs;
|
---|
1628 | return VINF_SUCCESS;
|
---|
1629 | }
|
---|
1630 |
|
---|
1631 | /**
|
---|
1632 | * Read from the global Ports implemented register.
|
---|
1633 | */
|
---|
1634 | static VBOXSTRICTRC HbaPortsImplemented_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1635 | {
|
---|
1636 | RT_NOREF(pDevIns, iReg);
|
---|
1637 | Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, pThis->regHbaPi));
|
---|
1638 | *pu32Value = pThis->regHbaPi;
|
---|
1639 | return VINF_SUCCESS;
|
---|
1640 | }
|
---|
1641 |
|
---|
1642 | /**
|
---|
1643 | * Write to the global interrupt status register.
|
---|
1644 | */
|
---|
1645 | static VBOXSTRICTRC HbaInterruptStatus_w(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t u32Value)
|
---|
1646 | {
|
---|
1647 | RT_NOREF(iReg);
|
---|
1648 | Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1649 |
|
---|
1650 | int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->lock, VINF_IOM_R3_MMIO_WRITE);
|
---|
1651 | if (rc != VINF_SUCCESS)
|
---|
1652 | return rc;
|
---|
1653 |
|
---|
1654 | pThis->regHbaIs &= ~(u32Value);
|
---|
1655 |
|
---|
1656 | /*
|
---|
1657 | * Update interrupt status register and check for ports who
|
---|
1658 | * set the interrupt inbetween.
|
---|
1659 | */
|
---|
1660 | bool fClear = true;
|
---|
1661 | pThis->regHbaIs |= ASMAtomicXchgU32(&pThis->u32PortsInterrupted, 0);
|
---|
1662 | if (!pThis->regHbaIs)
|
---|
1663 | {
|
---|
1664 | unsigned i = 0;
|
---|
1665 |
|
---|
1666 | /* Check if the cleared ports have a interrupt status bit set. */
|
---|
1667 | while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
|
---|
1668 | {
|
---|
1669 | if (u32Value & 0x01)
|
---|
1670 | {
|
---|
1671 | PAHCIPORT pAhciPort = &pThis->aPorts[i];
|
---|
1672 |
|
---|
1673 | if (pAhciPort->regIE & pAhciPort->regIS)
|
---|
1674 | {
|
---|
1675 | Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
|
---|
1676 | ASMAtomicOrU32(&pThis->u32PortsInterrupted, 1 << i);
|
---|
1677 | fClear = false;
|
---|
1678 | break;
|
---|
1679 | }
|
---|
1680 | }
|
---|
1681 | u32Value >>= 1;
|
---|
1682 | i++;
|
---|
1683 | }
|
---|
1684 | }
|
---|
1685 | else
|
---|
1686 | fClear = false;
|
---|
1687 |
|
---|
1688 | if (fClear)
|
---|
1689 | ahciHbaClearInterrupt(pDevIns);
|
---|
1690 | else
|
---|
1691 | {
|
---|
1692 | Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, pThis->u32PortsInterrupted));
|
---|
1693 | /*
|
---|
1694 | * We need to set the interrupt again because the I/O APIC does not set it again even if the
|
---|
1695 | * line is still high.
|
---|
1696 | * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
|
---|
1697 | */
|
---|
1698 | PDMDevHlpPCISetIrq(pDevIns, 0, 0);
|
---|
1699 | PDMDevHlpPCISetIrq(pDevIns, 0, 1);
|
---|
1700 | }
|
---|
1701 |
|
---|
1702 | PDMDevHlpCritSectLeave(pDevIns, &pThis->lock);
|
---|
1703 | return VINF_SUCCESS;
|
---|
1704 | }
|
---|
1705 |
|
---|
1706 | /**
|
---|
1707 | * Read from the global interrupt status register.
|
---|
1708 | */
|
---|
1709 | static VBOXSTRICTRC HbaInterruptStatus_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1710 | {
|
---|
1711 | RT_NOREF(iReg);
|
---|
1712 |
|
---|
1713 | int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->lock, VINF_IOM_R3_MMIO_READ);
|
---|
1714 | if (rc != VINF_SUCCESS)
|
---|
1715 | return rc;
|
---|
1716 |
|
---|
1717 | uint32_t u32PortsInterrupted = ASMAtomicXchgU32(&pThis->u32PortsInterrupted, 0);
|
---|
1718 |
|
---|
1719 | PDMDevHlpCritSectLeave(pDevIns, &pThis->lock);
|
---|
1720 | Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, pThis->regHbaIs, u32PortsInterrupted));
|
---|
1721 |
|
---|
1722 | pThis->regHbaIs |= u32PortsInterrupted;
|
---|
1723 |
|
---|
1724 | #ifdef LOG_ENABLED
|
---|
1725 | Log(("%s:", __FUNCTION__));
|
---|
1726 | uint32_t const cPortsImpl = RT_MIN(pThis->cPortsImpl, RT_ELEMENTS(pThis->aPorts));
|
---|
1727 | for (unsigned i = 0; i < cPortsImpl; i++)
|
---|
1728 | {
|
---|
1729 | if ((pThis->regHbaIs >> i) & 0x01)
|
---|
1730 | Log((" P%d", i));
|
---|
1731 | }
|
---|
1732 | Log(("\n"));
|
---|
1733 | #endif
|
---|
1734 |
|
---|
1735 | *pu32Value = pThis->regHbaIs;
|
---|
1736 |
|
---|
1737 | return VINF_SUCCESS;
|
---|
1738 | }
|
---|
1739 |
|
---|
1740 | /**
|
---|
1741 | * Write to the global control register.
|
---|
1742 | */
|
---|
1743 | static VBOXSTRICTRC HbaControl_w(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t u32Value)
|
---|
1744 | {
|
---|
1745 | Log(("%s: write u32Value=%#010x\n"
|
---|
1746 | "%s: AE=%d IE=%d HR=%d\n",
|
---|
1747 | __FUNCTION__, u32Value,
|
---|
1748 | __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
|
---|
1749 | (u32Value & AHCI_HBA_CTRL_HR)));
|
---|
1750 | RT_NOREF(iReg);
|
---|
1751 |
|
---|
1752 | #ifndef IN_RING3
|
---|
1753 | RT_NOREF(pDevIns, pThis, u32Value);
|
---|
1754 | return VINF_IOM_R3_MMIO_WRITE;
|
---|
1755 | #else
|
---|
1756 | /*
|
---|
1757 | * Increase the active thread counter because we might set the host controller
|
---|
1758 | * reset bit.
|
---|
1759 | */
|
---|
1760 | ASMAtomicIncU32(&pThis->cThreadsActive);
|
---|
1761 | ASMAtomicWriteU32(&pThis->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE);
|
---|
1762 |
|
---|
1763 | /*
|
---|
1764 | * Do the HBA reset if requested and there is no other active thread at the moment,
|
---|
1765 | * the work is deferred to the last active thread otherwise.
|
---|
1766 | */
|
---|
1767 | uint32_t cThreadsActive = ASMAtomicDecU32(&pThis->cThreadsActive);
|
---|
1768 | if ( (u32Value & AHCI_HBA_CTRL_HR)
|
---|
1769 | && !cThreadsActive)
|
---|
1770 | ahciR3HBAReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PAHCICC));
|
---|
1771 |
|
---|
1772 | return VINF_SUCCESS;
|
---|
1773 | #endif
|
---|
1774 | }
|
---|
1775 |
|
---|
1776 | /**
|
---|
1777 | * Read the global control register.
|
---|
1778 | */
|
---|
1779 | static VBOXSTRICTRC HbaControl_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1780 | {
|
---|
1781 | RT_NOREF(pDevIns, iReg);
|
---|
1782 | Log(("%s: read regHbaCtrl=%#010x\n"
|
---|
1783 | "%s: AE=%d IE=%d HR=%d\n",
|
---|
1784 | __FUNCTION__, pThis->regHbaCtrl,
|
---|
1785 | __FUNCTION__, (pThis->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (pThis->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
|
---|
1786 | (pThis->regHbaCtrl & AHCI_HBA_CTRL_HR)));
|
---|
1787 | *pu32Value = pThis->regHbaCtrl;
|
---|
1788 | return VINF_SUCCESS;
|
---|
1789 | }
|
---|
1790 |
|
---|
1791 | /**
|
---|
1792 | * Read the global capabilities register.
|
---|
1793 | */
|
---|
1794 | static VBOXSTRICTRC HbaCapabilities_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1795 | {
|
---|
1796 | RT_NOREF(pDevIns, iReg);
|
---|
1797 | Log(("%s: read regHbaCap=%#010x\n"
|
---|
1798 | "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
|
---|
1799 | __FUNCTION__, pThis->regHbaCap,
|
---|
1800 | __FUNCTION__, (pThis->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (pThis->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
|
---|
1801 | (pThis->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (pThis->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
|
---|
1802 | (pThis->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (pThis->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
|
---|
1803 | (pThis->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (pThis->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
|
---|
1804 | (pThis->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (pThis->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
|
---|
1805 | (pThis->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (pThis->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
|
---|
1806 | (pThis->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (pThis->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
|
---|
1807 | (pThis->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (pThis->regHbaCap & AHCI_HBA_CAP_NP)));
|
---|
1808 | *pu32Value = pThis->regHbaCap;
|
---|
1809 | return VINF_SUCCESS;
|
---|
1810 | }
|
---|
1811 |
|
---|
1812 | /**
|
---|
1813 | * Write to the global command completion coalescing control register.
|
---|
1814 | */
|
---|
1815 | static VBOXSTRICTRC HbaCccCtl_w(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t u32Value)
|
---|
1816 | {
|
---|
1817 | RT_NOREF(iReg);
|
---|
1818 | Log(("%s: write u32Value=%#010x\n"
|
---|
1819 | "%s: TV=%d CC=%d INT=%d EN=%d\n",
|
---|
1820 | __FUNCTION__, u32Value,
|
---|
1821 | __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
|
---|
1822 | AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
|
---|
1823 |
|
---|
1824 | pThis->regHbaCccCtl = u32Value;
|
---|
1825 | pThis->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
|
---|
1826 | pThis->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
|
---|
1827 | pThis->uCccNr = AHCI_HBA_CCC_CTL_CC_GET(u32Value);
|
---|
1828 |
|
---|
1829 | if (u32Value & AHCI_HBA_CCC_CTL_EN)
|
---|
1830 | PDMDevHlpTimerSetMillies(pDevIns, pThis->hHbaCccTimer, pThis->uCccTimeout); /* Arm the timer */
|
---|
1831 | else
|
---|
1832 | PDMDevHlpTimerStop(pDevIns, pThis->hHbaCccTimer);
|
---|
1833 |
|
---|
1834 | return VINF_SUCCESS;
|
---|
1835 | }
|
---|
1836 |
|
---|
1837 | /**
|
---|
1838 | * Read the global command completion coalescing control register.
|
---|
1839 | */
|
---|
1840 | static VBOXSTRICTRC HbaCccCtl_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1841 | {
|
---|
1842 | RT_NOREF(pDevIns, iReg);
|
---|
1843 | Log(("%s: read regHbaCccCtl=%#010x\n"
|
---|
1844 | "%s: TV=%d CC=%d INT=%d EN=%d\n",
|
---|
1845 | __FUNCTION__, pThis->regHbaCccCtl,
|
---|
1846 | __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(pThis->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(pThis->regHbaCccCtl),
|
---|
1847 | AHCI_HBA_CCC_CTL_INT_GET(pThis->regHbaCccCtl), (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
|
---|
1848 | *pu32Value = pThis->regHbaCccCtl;
|
---|
1849 | return VINF_SUCCESS;
|
---|
1850 | }
|
---|
1851 |
|
---|
1852 | /**
|
---|
1853 | * Write to the global command completion coalescing ports register.
|
---|
1854 | */
|
---|
1855 | static VBOXSTRICTRC HbaCccPorts_w(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t u32Value)
|
---|
1856 | {
|
---|
1857 | RT_NOREF(pDevIns, iReg);
|
---|
1858 | Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
|
---|
1859 |
|
---|
1860 | pThis->regHbaCccPorts = u32Value;
|
---|
1861 |
|
---|
1862 | return VINF_SUCCESS;
|
---|
1863 | }
|
---|
1864 |
|
---|
1865 | /**
|
---|
1866 | * Read the global command completion coalescing ports register.
|
---|
1867 | */
|
---|
1868 | static VBOXSTRICTRC HbaCccPorts_r(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t *pu32Value)
|
---|
1869 | {
|
---|
1870 | RT_NOREF(pDevIns, iReg);
|
---|
1871 | Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, pThis->regHbaCccPorts));
|
---|
1872 |
|
---|
1873 | #ifdef LOG_ENABLED
|
---|
1874 | Log(("%s:", __FUNCTION__));
|
---|
1875 | uint32_t const cPortsImpl = RT_MIN(pThis->cPortsImpl, RT_ELEMENTS(pThis->aPorts));
|
---|
1876 | for (unsigned i = 0; i < cPortsImpl; i++)
|
---|
1877 | {
|
---|
1878 | if ((pThis->regHbaCccPorts >> i) & 0x01)
|
---|
1879 | Log((" P%d", i));
|
---|
1880 | }
|
---|
1881 | Log(("\n"));
|
---|
1882 | #endif
|
---|
1883 |
|
---|
1884 | *pu32Value = pThis->regHbaCccPorts;
|
---|
1885 | return VINF_SUCCESS;
|
---|
1886 | }
|
---|
1887 |
|
---|
1888 | /**
|
---|
1889 | * Invalid write to global register
|
---|
1890 | */
|
---|
1891 | static VBOXSTRICTRC HbaInvalid_w(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t iReg, uint32_t u32Value)
|
---|
1892 | {
|
---|
1893 | RT_NOREF(pDevIns, pThis, iReg, u32Value);
|
---|
1894 | Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
|
---|
1895 | return VINF_SUCCESS;
|
---|
1896 | }
|
---|
1897 |
|
---|
1898 | /**
|
---|
1899 | * Invalid Port write.
|
---|
1900 | */
|
---|
1901 | static VBOXSTRICTRC PortInvalid_w(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t u32Value)
|
---|
1902 | {
|
---|
1903 | RT_NOREF(pDevIns, pThis, pAhciPort, iReg, u32Value);
|
---|
1904 | ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
|
---|
1905 | return VINF_SUCCESS;
|
---|
1906 | }
|
---|
1907 |
|
---|
1908 | /**
|
---|
1909 | * Invalid Port read.
|
---|
1910 | */
|
---|
1911 | static VBOXSTRICTRC PortInvalid_r(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t iReg, uint32_t *pu32Value)
|
---|
1912 | {
|
---|
1913 | RT_NOREF(pDevIns, pThis, pAhciPort, iReg, pu32Value);
|
---|
1914 | ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
|
---|
1915 | return VINF_IOM_MMIO_UNUSED_00;
|
---|
1916 | }
|
---|
1917 |
|
---|
1918 | /**
|
---|
1919 | * Register descriptor table for global HBA registers
|
---|
1920 | */
|
---|
1921 | static const AHCIOPREG g_aOpRegs[] =
|
---|
1922 | {
|
---|
1923 | {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
|
---|
1924 | {"HbaControl" , HbaControl_r, HbaControl_w},
|
---|
1925 | {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
|
---|
1926 | {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
|
---|
1927 | {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
|
---|
1928 | {"HbaCccCtl", HbaCccCtl_r, HbaCccCtl_w},
|
---|
1929 | {"HbaCccPorts", HbaCccPorts_r, HbaCccPorts_w},
|
---|
1930 | };
|
---|
1931 |
|
---|
1932 | /**
|
---|
1933 | * Register descriptor table for port registers
|
---|
1934 | */
|
---|
1935 | static const AHCIPORTOPREG g_aPortOpRegs[] =
|
---|
1936 | {
|
---|
1937 | {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
|
---|
1938 | {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
|
---|
1939 | {"PortFisAddr", PortFisAddr_r, PortFisAddr_w},
|
---|
1940 | {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
|
---|
1941 | {"PortIntrSts", PortIntrSts_r, PortIntrSts_w},
|
---|
1942 | {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
|
---|
1943 | {"PortCmd", PortCmd_r, PortCmd_w},
|
---|
1944 | {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
|
---|
1945 | {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
|
---|
1946 | {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
|
---|
1947 | {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
|
---|
1948 | {"PortSControl", PortSControl_r, PortSControl_w},
|
---|
1949 | {"PortSError", PortSError_r, PortSError_w},
|
---|
1950 | {"PortSActive", PortSActive_r, PortSActive_w},
|
---|
1951 | {"PortCmdIssue", PortCmdIssue_r, PortCmdIssue_w},
|
---|
1952 | {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
|
---|
1953 | };
|
---|
1954 |
|
---|
1955 | #ifdef IN_RING3
|
---|
1956 |
|
---|
1957 | /**
|
---|
1958 | * Reset initiated by system software for one port.
|
---|
1959 | *
|
---|
1960 | * @param pAhciPort The port to reset, shared bits.
|
---|
1961 | * @param pAhciPortR3 The port to reset, ring-3 bits.
|
---|
1962 | */
|
---|
1963 | static void ahciR3PortSwReset(PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3)
|
---|
1964 | {
|
---|
1965 | bool fAllTasksCanceled;
|
---|
1966 |
|
---|
1967 | /* Cancel all tasks first. */
|
---|
1968 | fAllTasksCanceled = ahciR3CancelActiveTasks(pAhciPortR3);
|
---|
1969 | Assert(fAllTasksCanceled);
|
---|
1970 |
|
---|
1971 | Assert(pAhciPort->cTasksActive == 0);
|
---|
1972 |
|
---|
1973 | pAhciPort->regIS = 0;
|
---|
1974 | pAhciPort->regIE = 0;
|
---|
1975 | pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
|
---|
1976 | AHCI_PORT_CMD_SUD | /* Device has spun up. */
|
---|
1977 | AHCI_PORT_CMD_POD; /* Port is powered on. */
|
---|
1978 |
|
---|
1979 | /* Hotplugging supported?. */
|
---|
1980 | if (pAhciPort->fHotpluggable)
|
---|
1981 | pAhciPort->regCMD |= AHCI_PORT_CMD_HPCP;
|
---|
1982 |
|
---|
1983 | pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
|
---|
1984 | pAhciPort->regSIG = UINT32_MAX;
|
---|
1985 | pAhciPort->regSSTS = 0;
|
---|
1986 | pAhciPort->regSCTL = 0;
|
---|
1987 | pAhciPort->regSERR = 0;
|
---|
1988 | pAhciPort->regSACT = 0;
|
---|
1989 | pAhciPort->regCI = 0;
|
---|
1990 |
|
---|
1991 | pAhciPort->fResetDevice = false;
|
---|
1992 | pAhciPort->fPoweredOn = true;
|
---|
1993 | pAhciPort->fSpunUp = true;
|
---|
1994 | pAhciPort->cMultSectors = ATA_MAX_MULT_SECTORS;
|
---|
1995 | pAhciPort->uATATransferMode = ATA_MODE_UDMA | 6;
|
---|
1996 |
|
---|
1997 | pAhciPort->u32TasksNew = 0;
|
---|
1998 | pAhciPort->u32TasksRedo = 0;
|
---|
1999 | pAhciPort->u32TasksFinished = 0;
|
---|
2000 | pAhciPort->u32QueuedTasksFinished = 0;
|
---|
2001 | pAhciPort->u32CurrentCommandSlot = 0;
|
---|
2002 |
|
---|
2003 | if (pAhciPort->fPresent)
|
---|
2004 | {
|
---|
2005 | pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
|
---|
2006 |
|
---|
2007 | if (pAhciPort->fPoweredOn)
|
---|
2008 | {
|
---|
2009 | /*
|
---|
2010 | * Set states in the Port Signature and SStatus registers.
|
---|
2011 | */
|
---|
2012 | if (pAhciPort->fATAPI)
|
---|
2013 | pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
|
---|
2014 | else
|
---|
2015 | pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
|
---|
2016 | pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
|
---|
2017 | (0x02 << 4) | /* Generation 2 (3.0GBps) speed. */
|
---|
2018 | (0x03 << 0); /* Device detected and communication established. */
|
---|
2019 | }
|
---|
2020 | }
|
---|
2021 | }
|
---|
2022 |
|
---|
2023 | /**
|
---|
2024 | * Hardware reset used for machine power on and reset.
|
---|
2025 | *
|
---|
2026 | * @param pAhciPort The port to reset, shared bits.
|
---|
2027 | */
|
---|
2028 | static void ahciPortHwReset(PAHCIPORT pAhciPort)
|
---|
2029 | {
|
---|
2030 | /* Reset the address registers. */
|
---|
2031 | pAhciPort->regCLB = 0;
|
---|
2032 | pAhciPort->regCLBU = 0;
|
---|
2033 | pAhciPort->regFB = 0;
|
---|
2034 | pAhciPort->regFBU = 0;
|
---|
2035 |
|
---|
2036 | /* Reset calculated addresses. */
|
---|
2037 | pAhciPort->GCPhysAddrClb = 0;
|
---|
2038 | pAhciPort->GCPhysAddrFb = 0;
|
---|
2039 | }
|
---|
2040 |
|
---|
2041 | /**
|
---|
2042 | * Create implemented ports bitmap.
|
---|
2043 | *
|
---|
2044 | * @returns 32bit bitmask with a bit set for every implemented port.
|
---|
2045 | * @param cPorts Number of ports.
|
---|
2046 | */
|
---|
2047 | static uint32_t ahciGetPortsImplemented(unsigned cPorts)
|
---|
2048 | {
|
---|
2049 | uint32_t uPortsImplemented = 0;
|
---|
2050 |
|
---|
2051 | for (unsigned i = 0; i < cPorts; i++)
|
---|
2052 | uPortsImplemented |= (1 << i);
|
---|
2053 |
|
---|
2054 | return uPortsImplemented;
|
---|
2055 | }
|
---|
2056 |
|
---|
2057 | /**
|
---|
2058 | * Reset the entire HBA.
|
---|
2059 | *
|
---|
2060 | * @param pDevIns The device instance.
|
---|
2061 | * @param pThis The shared AHCI state.
|
---|
2062 | * @param pThisCC The ring-3 AHCI state.
|
---|
2063 | */
|
---|
2064 | static void ahciR3HBAReset(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIR3 pThisCC)
|
---|
2065 | {
|
---|
2066 | unsigned i;
|
---|
2067 | int rc = VINF_SUCCESS;
|
---|
2068 |
|
---|
2069 | LogRel(("AHCI#%u: Reset the HBA\n", pDevIns->iInstance));
|
---|
2070 |
|
---|
2071 | /* Stop the CCC timer. */
|
---|
2072 | if (pThis->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)
|
---|
2073 | {
|
---|
2074 | rc = PDMDevHlpTimerStop(pDevIns, pThis->hHbaCccTimer);
|
---|
2075 | if (RT_FAILURE(rc))
|
---|
2076 | AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
|
---|
2077 | }
|
---|
2078 |
|
---|
2079 | /* Reset every port */
|
---|
2080 | uint32_t const cPortsImpl = RT_MIN(pThis->cPortsImpl, RT_ELEMENTS(pThisCC->aPorts));
|
---|
2081 | for (i = 0; i < cPortsImpl; i++)
|
---|
2082 | {
|
---|
2083 | PAHCIPORT pAhciPort = &pThis->aPorts[i];
|
---|
2084 | PAHCIPORTR3 pAhciPortR3 = &pThisCC->aPorts[i];
|
---|
2085 |
|
---|
2086 | pAhciPort->iLUN = i;
|
---|
2087 | pAhciPortR3->iLUN = i;
|
---|
2088 | ahciR3PortSwReset(pAhciPort, pAhciPortR3);
|
---|
2089 | }
|
---|
2090 |
|
---|
2091 | /* Init Global registers */
|
---|
2092 | pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2)
|
---|
2093 | | AHCI_HBA_CAP_S64A /* 64bit addressing supported */
|
---|
2094 | | AHCI_HBA_CAP_SAM /* AHCI mode only */
|
---|
2095 | | AHCI_HBA_CAP_SNCQ /* Support native command queuing */
|
---|
2096 | | AHCI_HBA_CAP_SSS /* Staggered spin up */
|
---|
2097 | | AHCI_HBA_CAP_CCCS /* Support command completion coalescing */
|
---|
2098 | | AHCI_HBA_CAP_NCS_SET(pThis->cCmdSlotsAvail) /* Number of command slots we support */
|
---|
2099 | | AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
|
---|
2100 | pThis->regHbaCtrl = AHCI_HBA_CTRL_AE;
|
---|
2101 | pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
|
---|
2102 | pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
|
---|
2103 | pThis->regHbaCccCtl = 0;
|
---|
2104 | pThis->regHbaCccPorts = 0;
|
---|
2105 | pThis->uCccTimeout = 0;
|
---|
2106 | pThis->uCccPortNr = 0;
|
---|
2107 | pThis->uCccNr = 0;
|
---|
2108 |
|
---|
2109 | /* Clear pending interrupts. */
|
---|
2110 | pThis->regHbaIs = 0;
|
---|
2111 | pThis->u32PortsInterrupted = 0;
|
---|
2112 | ahciHbaClearInterrupt(pDevIns);
|
---|
2113 |
|
---|
2114 | pThis->f64BitAddr = false;
|
---|
2115 | pThis->u32PortsInterrupted = 0;
|
---|
2116 | pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
|
---|
2117 | /* Clear the HBA Reset bit */
|
---|
2118 | pThis->regHbaCtrl &= ~AHCI_HBA_CTRL_HR;
|
---|
2119 | }
|
---|
2120 |
|
---|
2121 | #endif /* IN_RING3 */
|
---|
2122 |
|
---|
2123 | /**
|
---|
2124 | * Reads from a AHCI controller register.
|
---|
2125 | *
|
---|
2126 | * @returns Strict VBox status code.
|
---|
2127 | *
|
---|
2128 | * @param pDevIns The device instance.
|
---|
2129 | * @param pThis The shared AHCI state.
|
---|
2130 | * @param uReg The register to write.
|
---|
2131 | * @param pv Where to store the result.
|
---|
2132 | * @param cb Number of bytes read.
|
---|
2133 | */
|
---|
2134 | static VBOXSTRICTRC ahciRegisterRead(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t uReg, void *pv, unsigned cb)
|
---|
2135 | {
|
---|
2136 | VBOXSTRICTRC rc;
|
---|
2137 | uint32_t iReg;
|
---|
2138 |
|
---|
2139 | /*
|
---|
2140 | * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
|
---|
2141 | * Otherwise it accesses the registers of a port.
|
---|
2142 | */
|
---|
2143 | if (uReg < AHCI_HBA_GLOBAL_SIZE)
|
---|
2144 | {
|
---|
2145 | iReg = uReg >> 2;
|
---|
2146 | Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
|
---|
2147 | if (iReg < RT_ELEMENTS(g_aOpRegs))
|
---|
2148 | {
|
---|
2149 | const AHCIOPREG *pReg = &g_aOpRegs[iReg];
|
---|
2150 | rc = pReg->pfnRead(pDevIns, pThis, iReg, (uint32_t *)pv);
|
---|
2151 | }
|
---|
2152 | else
|
---|
2153 | {
|
---|
2154 | Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
|
---|
2155 | *(uint32_t *)pv = 0;
|
---|
2156 | rc = VINF_SUCCESS;
|
---|
2157 | }
|
---|
2158 | }
|
---|
2159 | else
|
---|
2160 | {
|
---|
2161 | uint32_t iRegOffset;
|
---|
2162 | uint32_t iPort;
|
---|
2163 |
|
---|
2164 | /* Calculate accessed port. */
|
---|
2165 | uReg -= AHCI_HBA_GLOBAL_SIZE;
|
---|
2166 | iPort = uReg / AHCI_PORT_REGISTER_SIZE;
|
---|
2167 | iRegOffset = (uReg % AHCI_PORT_REGISTER_SIZE);
|
---|
2168 | iReg = iRegOffset >> 2;
|
---|
2169 |
|
---|
2170 | Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
|
---|
2171 |
|
---|
2172 | if (RT_LIKELY( iPort < RT_MIN(pThis->cPortsImpl, RT_ELEMENTS(pThis->aPorts))
|
---|
2173 | && iReg < RT_ELEMENTS(g_aPortOpRegs)))
|
---|
2174 | {
|
---|
2175 | const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
|
---|
2176 | rc = pPortReg->pfnRead(pDevIns, pThis, &pThis->aPorts[iPort], iReg, (uint32_t *)pv);
|
---|
2177 | }
|
---|
2178 | else
|
---|
2179 | {
|
---|
2180 | Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
|
---|
2181 | rc = VINF_IOM_MMIO_UNUSED_00;
|
---|
2182 | }
|
---|
2183 |
|
---|
2184 | /*
|
---|
2185 | * Windows Vista tries to read one byte from some registers instead of four.
|
---|
2186 | * Correct the value according to the read size.
|
---|
2187 | */
|
---|
2188 | if (RT_SUCCESS(rc) && cb != sizeof(uint32_t))
|
---|
2189 | {
|
---|
2190 | switch (cb)
|
---|
2191 | {
|
---|
2192 | case 1:
|
---|
2193 | {
|
---|
2194 | uint8_t uNewValue;
|
---|
2195 | uint8_t *p = (uint8_t *)pv;
|
---|
2196 |
|
---|
2197 | iRegOffset &= 3;
|
---|
2198 | Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
|
---|
2199 | uNewValue = p[iRegOffset];
|
---|
2200 | /* Clear old value */
|
---|
2201 | *(uint32_t *)pv = 0;
|
---|
2202 | *(uint8_t *)pv = uNewValue;
|
---|
2203 | break;
|
---|
2204 | }
|
---|
2205 | default:
|
---|
2206 | ASSERT_GUEST_MSG_FAILED(("%s: unsupported access width cb=%d iPort=%x iRegOffset=%x iReg=%x!!!\n",
|
---|
2207 | __FUNCTION__, cb, iPort, iRegOffset, iReg));
|
---|
2208 | }
|
---|
2209 | }
|
---|
2210 | }
|
---|
2211 |
|
---|
2212 | return rc;
|
---|
2213 | }
|
---|
2214 |
|
---|
2215 | /**
|
---|
2216 | * Writes a value to one of the AHCI controller registers.
|
---|
2217 | *
|
---|
2218 | * @returns Strict VBox status code.
|
---|
2219 | *
|
---|
2220 | * @param pDevIns The device instance.
|
---|
2221 | * @param pThis The shared AHCI state.
|
---|
2222 | * @param offReg The offset of the register to write to.
|
---|
2223 | * @param u32Value The value to write.
|
---|
2224 | */
|
---|
2225 | static VBOXSTRICTRC ahciRegisterWrite(PPDMDEVINS pDevIns, PAHCI pThis, uint32_t offReg, uint32_t u32Value)
|
---|
2226 | {
|
---|
2227 | VBOXSTRICTRC rc;
|
---|
2228 | uint32_t iReg;
|
---|
2229 |
|
---|
2230 | /*
|
---|
2231 | * If the access offset is smaller than 100h the guest accesses the global registers.
|
---|
2232 | * Otherwise it accesses the registers of a port.
|
---|
2233 | */
|
---|
2234 | if (offReg < AHCI_HBA_GLOBAL_SIZE)
|
---|
2235 | {
|
---|
2236 | Log3(("Write global HBA register\n"));
|
---|
2237 | iReg = offReg >> 2;
|
---|
2238 | if (iReg < RT_ELEMENTS(g_aOpRegs))
|
---|
2239 | {
|
---|
2240 | const AHCIOPREG *pReg = &g_aOpRegs[iReg];
|
---|
2241 | rc = pReg->pfnWrite(pDevIns, pThis, iReg, u32Value);
|
---|
2242 | }
|
---|
2243 | else
|
---|
2244 | {
|
---|
2245 | Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
|
---|
2246 | rc = VINF_SUCCESS;
|
---|
2247 | }
|
---|
2248 | }
|
---|
2249 | else
|
---|
2250 | {
|
---|
2251 | uint32_t iPort;
|
---|
2252 | Log3(("Write Port register\n"));
|
---|
2253 | /* Calculate accessed port. */
|
---|
2254 | offReg -= AHCI_HBA_GLOBAL_SIZE;
|
---|
2255 | iPort = offReg / AHCI_PORT_REGISTER_SIZE;
|
---|
2256 | iReg = (offReg % AHCI_PORT_REGISTER_SIZE) >> 2;
|
---|
2257 | Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
|
---|
2258 | if (RT_LIKELY( iPort < RT_MIN(pThis->cPortsImpl, RT_ELEMENTS(pThis->aPorts))
|
---|
2259 | && iReg < RT_ELEMENTS(g_aPortOpRegs)))
|
---|
2260 | {
|
---|
2261 | const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
|
---|
2262 | rc = pPortReg->pfnWrite(pDevIns, pThis, &pThis->aPorts[iPort], iReg, u32Value);
|
---|
2263 | }
|
---|
2264 | else
|
---|
2265 | {
|
---|
2266 | Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
|
---|
2267 | rc = VINF_SUCCESS;
|
---|
2268 | }
|
---|
2269 | }
|
---|
2270 |
|
---|
2271 | return rc;
|
---|
2272 | }
|
---|
2273 |
|
---|
2274 |
|
---|
2275 | /**
|
---|
2276 | * @callback_method_impl{FNIOMMMIONEWWRITE}
|
---|
2277 | */
|
---|
2278 | static DECLCALLBACK(VBOXSTRICTRC) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
|
---|
2279 | {
|
---|
2280 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
2281 | Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d off=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, off));
|
---|
2282 | RT_NOREF(pvUser);
|
---|
2283 |
|
---|
2284 | VBOXSTRICTRC rc = ahciRegisterRead(pDevIns, pThis, off, pv, cb);
|
---|
2285 |
|
---|
2286 | Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d off=%RGp rc=%Rrc\n",
|
---|
2287 | pDevIns->iInstance, pv, cb, pv, cb, off, VBOXSTRICTRC_VAL(rc)));
|
---|
2288 | return rc;
|
---|
2289 | }
|
---|
2290 |
|
---|
2291 | /**
|
---|
2292 | * @callback_method_impl{FNIOMMMIONEWWRITE}
|
---|
2293 | */
|
---|
2294 | static DECLCALLBACK(VBOXSTRICTRC) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
|
---|
2295 | {
|
---|
2296 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
2297 |
|
---|
2298 | Assert(cb == 4 || cb == 8); /* Assert IOM flags & sanity */
|
---|
2299 | Assert(!(off & (cb - 1))); /* Ditto. */
|
---|
2300 |
|
---|
2301 | /* Break up 64 bits writes into two dword writes. */
|
---|
2302 | /** @todo Eliminate this code once the IOM/EM starts taking care of these
|
---|
2303 | * situations. */
|
---|
2304 | if (cb == 8)
|
---|
2305 | {
|
---|
2306 | /*
|
---|
2307 | * Only write the first 4 bytes if they weren't already.
|
---|
2308 | * It is possible that the last write to the register caused a world
|
---|
2309 | * switch and we entered this function again.
|
---|
2310 | * Writing the first 4 bytes again could cause indeterminate behavior
|
---|
2311 | * which can cause errors in the guest.
|
---|
2312 | */
|
---|
2313 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
2314 | if (!pThis->f8ByteMMIO4BytesWrittenSuccessfully)
|
---|
2315 | {
|
---|
2316 | rc = ahciMMIOWrite(pDevIns, pvUser, off, pv, 4);
|
---|
2317 | if (rc != VINF_SUCCESS)
|
---|
2318 | return rc;
|
---|
2319 |
|
---|
2320 | pThis->f8ByteMMIO4BytesWrittenSuccessfully = true;
|
---|
2321 | }
|
---|
2322 |
|
---|
2323 | rc = ahciMMIOWrite(pDevIns, pvUser, off + 4, (uint8_t *)pv + 4, 4);
|
---|
2324 | /*
|
---|
2325 | * Reset flag again so that the first 4 bytes are written again on the next
|
---|
2326 | * 8byte MMIO access.
|
---|
2327 | */
|
---|
2328 | if (rc == VINF_SUCCESS)
|
---|
2329 | pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
|
---|
2330 |
|
---|
2331 | return rc;
|
---|
2332 | }
|
---|
2333 |
|
---|
2334 | /* Do the access. */
|
---|
2335 | Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, off));
|
---|
2336 | return ahciRegisterWrite(pDevIns, pThis, off, *(uint32_t const *)pv);
|
---|
2337 | }
|
---|
2338 |
|
---|
2339 |
|
---|
2340 | /**
|
---|
2341 | * @callback_method_impl{FNIOMIOPORTNEWOUT,
|
---|
2342 | * Fake IDE port handler provided to make solaris happy.}
|
---|
2343 | */
|
---|
2344 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
2345 | ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
|
---|
2346 | {
|
---|
2347 | RT_NOREF(pDevIns, pvUser, offPort, u32, cb);
|
---|
2348 | ASSERT_GUEST_MSG_FAILED(("Should not happen\n"));
|
---|
2349 | return VINF_SUCCESS;
|
---|
2350 | }
|
---|
2351 |
|
---|
2352 | /**
|
---|
2353 | * @callback_method_impl{FNIOMIOPORTNEWIN,
|
---|
2354 | * Fake IDE port handler provided to make solaris happy.}
|
---|
2355 | */
|
---|
2356 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
2357 | ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
2358 | {
|
---|
2359 | *pu32 = 0;
|
---|
2360 | RT_NOREF(pDevIns, pvUser, offPort, cb);
|
---|
2361 | ASSERT_GUEST_MSG_FAILED(("Should not happen\n"));
|
---|
2362 | return VERR_IOM_IOPORT_UNUSED;
|
---|
2363 | }
|
---|
2364 |
|
---|
2365 |
|
---|
2366 | /**
|
---|
2367 | * @callback_method_impl{FNIOMIOPORTNEWOUT,
|
---|
2368 | * I/O port handler for writes to the index/data register pair.}
|
---|
2369 | */
|
---|
2370 | static DECLCALLBACK(VBOXSTRICTRC) ahciIdxDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
|
---|
2371 | {
|
---|
2372 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
2373 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
2374 | RT_NOREF(pvUser, cb);
|
---|
2375 |
|
---|
2376 | if (offPort >= 8)
|
---|
2377 | {
|
---|
2378 | ASSERT_GUEST(cb == 4);
|
---|
2379 |
|
---|
2380 | uint32_t const iReg = (offPort - 8) / 4;
|
---|
2381 | if (iReg == 0)
|
---|
2382 | {
|
---|
2383 | /* Write the index register. */
|
---|
2384 | pThis->regIdx = u32;
|
---|
2385 | }
|
---|
2386 | else
|
---|
2387 | {
|
---|
2388 | /** @todo range check? */
|
---|
2389 | ASSERT_GUEST(iReg == 1);
|
---|
2390 | rc = ahciRegisterWrite(pDevIns, pThis, pThis->regIdx, u32);
|
---|
2391 | if (rc == VINF_IOM_R3_MMIO_WRITE)
|
---|
2392 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
2393 | }
|
---|
2394 | }
|
---|
2395 | /* else: ignore */
|
---|
2396 |
|
---|
2397 | Log2(("#%d ahciIdxDataWrite: pu32=%p:{%.*Rhxs} cb=%d offPort=%#x rc=%Rrc\n",
|
---|
2398 | pDevIns->iInstance, &u32, cb, &u32, cb, offPort, VBOXSTRICTRC_VAL(rc)));
|
---|
2399 | return rc;
|
---|
2400 | }
|
---|
2401 |
|
---|
2402 | /**
|
---|
2403 | * @callback_method_impl{FNIOMIOPORTNEWOUT,
|
---|
2404 | * I/O port handler for reads from the index/data register pair.}
|
---|
2405 | */
|
---|
2406 | static DECLCALLBACK(VBOXSTRICTRC) ahciIdxDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
2407 | {
|
---|
2408 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
2409 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
2410 | RT_NOREF(pvUser);
|
---|
2411 |
|
---|
2412 | if (offPort >= 8)
|
---|
2413 | {
|
---|
2414 | ASSERT_GUEST(cb == 4);
|
---|
2415 |
|
---|
2416 | uint32_t const iReg = (offPort - 8) / 4;
|
---|
2417 | if (iReg == 0)
|
---|
2418 | {
|
---|
2419 | /* Read the index register. */
|
---|
2420 | *pu32 = pThis->regIdx;
|
---|
2421 | }
|
---|
2422 | else
|
---|
2423 | {
|
---|
2424 | /** @todo range check? */
|
---|
2425 | ASSERT_GUEST(iReg == 1);
|
---|
2426 | rc = ahciRegisterRead(pDevIns, pThis, pThis->regIdx, pu32, cb);
|
---|
2427 | if (rc == VINF_IOM_R3_MMIO_READ)
|
---|
2428 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
2429 | else if (rc == VINF_IOM_MMIO_UNUSED_00)
|
---|
2430 | rc = VERR_IOM_IOPORT_UNUSED;
|
---|
2431 | }
|
---|
2432 | }
|
---|
2433 | else
|
---|
2434 | *pu32 = UINT32_MAX;
|
---|
2435 |
|
---|
2436 | Log2(("#%d ahciIdxDataRead: pu32=%p:{%.*Rhxs} cb=%d offPort=%#x rc=%Rrc\n",
|
---|
2437 | pDevIns->iInstance, pu32, cb, pu32, cb, offPort, VBOXSTRICTRC_VAL(rc)));
|
---|
2438 | return rc;
|
---|
2439 | }
|
---|
2440 |
|
---|
2441 | #ifdef IN_RING3
|
---|
2442 |
|
---|
2443 | /* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
|
---|
2444 |
|
---|
2445 | /**
|
---|
2446 | * Gets the pointer to the status LED of a unit.
|
---|
2447 | *
|
---|
2448 | * @returns VBox status code.
|
---|
2449 | * @param pInterface Pointer to the interface structure containing the called function pointer.
|
---|
2450 | * @param iLUN The unit which status LED we desire.
|
---|
2451 | * @param ppLed Where to store the LED pointer.
|
---|
2452 | */
|
---|
2453 | static DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
|
---|
2454 | {
|
---|
2455 | PAHCICC pThisCC = RT_FROM_MEMBER(pInterface, AHCICC, ILeds);
|
---|
2456 | if (iLUN < AHCI_MAX_NR_PORTS_IMPL)
|
---|
2457 | {
|
---|
2458 | PAHCI pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PAHCI);
|
---|
2459 | *ppLed = &pThis->aPorts[iLUN].Led;
|
---|
2460 | Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
|
---|
2461 | return VINF_SUCCESS;
|
---|
2462 | }
|
---|
2463 | return VERR_PDM_LUN_NOT_FOUND;
|
---|
2464 | }
|
---|
2465 |
|
---|
2466 | /**
|
---|
2467 | * @interface_method_impl{PDMIBASE,pfnQueryInterface}
|
---|
2468 | */
|
---|
2469 | static DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
|
---|
2470 | {
|
---|
2471 | PAHCICC pThisCC = RT_FROM_MEMBER(pInterface, AHCICC, IBase);
|
---|
2472 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
|
---|
2473 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
|
---|
2474 | return NULL;
|
---|
2475 | }
|
---|
2476 |
|
---|
2477 | /**
|
---|
2478 | * @interface_method_impl{PDMIBASE,pfnQueryInterface}
|
---|
2479 | */
|
---|
2480 | static DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
|
---|
2481 | {
|
---|
2482 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IBase);
|
---|
2483 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPortR3->IBase);
|
---|
2484 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAPORT, &pAhciPortR3->IPort);
|
---|
2485 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMEDIAEXPORT, &pAhciPortR3->IMediaExPort);
|
---|
2486 | return NULL;
|
---|
2487 | }
|
---|
2488 |
|
---|
2489 | /**
|
---|
2490 | * @interface_method_impl{PDMIMEDIAPORT,pfnQueryDeviceLocation}
|
---|
2491 | */
|
---|
2492 | static DECLCALLBACK(int) ahciR3PortQueryDeviceLocation(PPDMIMEDIAPORT pInterface, const char **ppcszController,
|
---|
2493 | uint32_t *piInstance, uint32_t *piLUN)
|
---|
2494 | {
|
---|
2495 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IPort);
|
---|
2496 | PPDMDEVINS pDevIns = pAhciPortR3->pDevIns;
|
---|
2497 |
|
---|
2498 | AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
|
---|
2499 | AssertPtrReturn(piInstance, VERR_INVALID_POINTER);
|
---|
2500 | AssertPtrReturn(piLUN, VERR_INVALID_POINTER);
|
---|
2501 |
|
---|
2502 | *ppcszController = pDevIns->pReg->szName;
|
---|
2503 | *piInstance = pDevIns->iInstance;
|
---|
2504 | *piLUN = pAhciPortR3->iLUN;
|
---|
2505 |
|
---|
2506 | return VINF_SUCCESS;
|
---|
2507 | }
|
---|
2508 |
|
---|
2509 | /**
|
---|
2510 | * @interface_method_impl{PDMIMEDIAPORT,pfnQueryScsiInqStrings}
|
---|
2511 | */
|
---|
2512 | static DECLCALLBACK(int) ahciR3PortQueryScsiInqStrings(PPDMIMEDIAPORT pInterface, const char **ppszVendorId,
|
---|
2513 | const char **ppszProductId, const char **ppszRevision)
|
---|
2514 | {
|
---|
2515 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IPort);
|
---|
2516 | PAHCI pThis = PDMDEVINS_2_DATA(pAhciPortR3->pDevIns, PAHCI);
|
---|
2517 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
2518 |
|
---|
2519 | if (ppszVendorId)
|
---|
2520 | *ppszVendorId = &pAhciPort->szInquiryVendorId[0];
|
---|
2521 | if (ppszProductId)
|
---|
2522 | *ppszProductId = &pAhciPort->szInquiryProductId[0];
|
---|
2523 | if (ppszRevision)
|
---|
2524 | *ppszRevision = &pAhciPort->szInquiryRevision[0];
|
---|
2525 | return VINF_SUCCESS;
|
---|
2526 | }
|
---|
2527 |
|
---|
2528 | #ifdef LOG_ENABLED
|
---|
2529 |
|
---|
2530 | /**
|
---|
2531 | * Dump info about the FIS
|
---|
2532 | *
|
---|
2533 | * @param pAhciPort The port the command FIS was read from (shared bits).
|
---|
2534 | * @param cmdFis The FIS to print info from.
|
---|
2535 | */
|
---|
2536 | static void ahciDumpFisInfo(PAHCIPORT pAhciPort, uint8_t *cmdFis)
|
---|
2537 | {
|
---|
2538 | ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
|
---|
2539 | /* Print FIS type. */
|
---|
2540 | switch (cmdFis[AHCI_CMDFIS_TYPE])
|
---|
2541 | {
|
---|
2542 | case AHCI_CMDFIS_TYPE_H2D:
|
---|
2543 | {
|
---|
2544 | ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
|
---|
2545 | ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
|
---|
2546 | if (cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
|
---|
2547 | ahciLog(("%s: Command register update\n", __FUNCTION__));
|
---|
2548 | else
|
---|
2549 | ahciLog(("%s: Control register update\n", __FUNCTION__));
|
---|
2550 | ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
|
---|
2551 | ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
|
---|
2552 | ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
|
---|
2553 | ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
|
---|
2554 | ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
|
---|
2555 | ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
|
---|
2556 |
|
---|
2557 | ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
|
---|
2558 | ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
|
---|
2559 | ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
|
---|
2560 | ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
|
---|
2561 |
|
---|
2562 | ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
|
---|
2563 | ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
|
---|
2564 | ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
|
---|
2565 | if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
|
---|
2566 | ahciLog(("%s: Reset bit is set\n", __FUNCTION__));
|
---|
2567 | break;
|
---|
2568 | }
|
---|
2569 | case AHCI_CMDFIS_TYPE_D2H:
|
---|
2570 | {
|
---|
2571 | ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
|
---|
2572 | ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
|
---|
2573 | break;
|
---|
2574 | }
|
---|
2575 | case AHCI_CMDFIS_TYPE_SETDEVBITS:
|
---|
2576 | {
|
---|
2577 | ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
|
---|
2578 | ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
|
---|
2579 | break;
|
---|
2580 | }
|
---|
2581 | case AHCI_CMDFIS_TYPE_DMAACTD2H:
|
---|
2582 | {
|
---|
2583 | ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
|
---|
2584 | ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
|
---|
2585 | break;
|
---|
2586 | }
|
---|
2587 | case AHCI_CMDFIS_TYPE_DMASETUP:
|
---|
2588 | {
|
---|
2589 | ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
|
---|
2590 | ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
|
---|
2591 | break;
|
---|
2592 | }
|
---|
2593 | case AHCI_CMDFIS_TYPE_PIOSETUP:
|
---|
2594 | {
|
---|
2595 | ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
|
---|
2596 | ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
|
---|
2597 | break;
|
---|
2598 | }
|
---|
2599 | case AHCI_CMDFIS_TYPE_DATA:
|
---|
2600 | {
|
---|
2601 | ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
|
---|
2602 | break;
|
---|
2603 | }
|
---|
2604 | default:
|
---|
2605 | ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
|
---|
2606 | break;
|
---|
2607 | }
|
---|
2608 | ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
|
---|
2609 | }
|
---|
2610 |
|
---|
2611 | /**
|
---|
2612 | * Dump info about the command header
|
---|
2613 | *
|
---|
2614 | * @param pAhciPort Pointer to the port the command header was read from
|
---|
2615 | * (shared bits).
|
---|
2616 | * @param pCmdHdr The command header to print info from.
|
---|
2617 | */
|
---|
2618 | static void ahciDumpCmdHdrInfo(PAHCIPORT pAhciPort, CmdHdr *pCmdHdr)
|
---|
2619 | {
|
---|
2620 | ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
|
---|
2621 | ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
|
---|
2622 | if (pCmdHdr->u32DescInf & AHCI_CMDHDR_C)
|
---|
2623 | ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
|
---|
2624 | if (pCmdHdr->u32DescInf & AHCI_CMDHDR_B)
|
---|
2625 | ahciLog(("%s: BIST Fis\n", __FUNCTION__));
|
---|
2626 | if (pCmdHdr->u32DescInf & AHCI_CMDHDR_R)
|
---|
2627 | ahciLog(("%s: Device Reset Fis\n", __FUNCTION__));
|
---|
2628 | if (pCmdHdr->u32DescInf & AHCI_CMDHDR_P)
|
---|
2629 | ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
|
---|
2630 | if (pCmdHdr->u32DescInf & AHCI_CMDHDR_W)
|
---|
2631 | ahciLog(("%s: Device write\n", __FUNCTION__));
|
---|
2632 | else
|
---|
2633 | ahciLog(("%s: Device read\n", __FUNCTION__));
|
---|
2634 | if (pCmdHdr->u32DescInf & AHCI_CMDHDR_A)
|
---|
2635 | ahciLog(("%s: ATAPI command\n", __FUNCTION__));
|
---|
2636 | else
|
---|
2637 | ahciLog(("%s: ATA command\n", __FUNCTION__));
|
---|
2638 |
|
---|
2639 | ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
|
---|
2640 | ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
|
---|
2641 | }
|
---|
2642 |
|
---|
2643 | #endif /* LOG_ENABLED */
|
---|
2644 |
|
---|
2645 | /**
|
---|
2646 | * Post the first D2H FIS from the device into guest memory.
|
---|
2647 | *
|
---|
2648 | * @param pDevIns The device instance.
|
---|
2649 | * @param pAhciPort Pointer to the port which "receives" the FIS (shared bits).
|
---|
2650 | */
|
---|
2651 | static void ahciPostFirstD2HFisIntoMemory(PPDMDEVINS pDevIns, PAHCIPORT pAhciPort)
|
---|
2652 | {
|
---|
2653 | uint8_t d2hFis[AHCI_CMDFIS_TYPE_D2H_SIZE];
|
---|
2654 |
|
---|
2655 | pAhciPort->fFirstD2HFisSent = true;
|
---|
2656 |
|
---|
2657 | ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
|
---|
2658 | memset(&d2hFis[0], 0, sizeof(d2hFis));
|
---|
2659 | d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
|
---|
2660 | d2hFis[AHCI_CMDFIS_ERR] = 0x01;
|
---|
2661 |
|
---|
2662 | d2hFis[AHCI_CMDFIS_STS] = 0x00;
|
---|
2663 |
|
---|
2664 | /* Set the signature based on the device type. */
|
---|
2665 | if (pAhciPort->fATAPI)
|
---|
2666 | {
|
---|
2667 | d2hFis[AHCI_CMDFIS_CYLL] = 0x14;
|
---|
2668 | d2hFis[AHCI_CMDFIS_CYLH] = 0xeb;
|
---|
2669 | }
|
---|
2670 | else
|
---|
2671 | {
|
---|
2672 | d2hFis[AHCI_CMDFIS_CYLL] = 0x00;
|
---|
2673 | d2hFis[AHCI_CMDFIS_CYLH] = 0x00;
|
---|
2674 | }
|
---|
2675 |
|
---|
2676 | d2hFis[AHCI_CMDFIS_HEAD] = 0x00;
|
---|
2677 | d2hFis[AHCI_CMDFIS_SECTN] = 0x01;
|
---|
2678 | d2hFis[AHCI_CMDFIS_SECTC] = 0x01;
|
---|
2679 |
|
---|
2680 | pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
|
---|
2681 | if (!pAhciPort->fATAPI)
|
---|
2682 | pAhciPort->regTFD |= ATA_STAT_READY;
|
---|
2683 |
|
---|
2684 | ahciPostFisIntoMemory(pDevIns, pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
|
---|
2685 | }
|
---|
2686 |
|
---|
2687 | /**
|
---|
2688 | * Post the FIS in the memory area allocated by the guest and set interrupt if necessary.
|
---|
2689 | *
|
---|
2690 | * @returns VBox status code
|
---|
2691 | * @param pDevIns The device instance.
|
---|
2692 | * @param pAhciPort The port which "receives" the FIS(shared bits).
|
---|
2693 | * @param uFisType The type of the FIS.
|
---|
2694 | * @param pCmdFis Pointer to the FIS which is to be posted into memory.
|
---|
2695 | */
|
---|
2696 | static int ahciPostFisIntoMemory(PPDMDEVINS pDevIns, PAHCIPORT pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
|
---|
2697 | {
|
---|
2698 | int rc = VINF_SUCCESS;
|
---|
2699 | RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
|
---|
2700 | unsigned cbFis = 0;
|
---|
2701 |
|
---|
2702 | ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
|
---|
2703 |
|
---|
2704 | if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
|
---|
2705 | {
|
---|
2706 | AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
|
---|
2707 |
|
---|
2708 | /* Determine the offset and size of the FIS based on uFisType. */
|
---|
2709 | switch (uFisType)
|
---|
2710 | {
|
---|
2711 | case AHCI_CMDFIS_TYPE_D2H:
|
---|
2712 | {
|
---|
2713 | GCPhysAddrRecFis += AHCI_RECFIS_RFIS_OFFSET;
|
---|
2714 | cbFis = AHCI_CMDFIS_TYPE_D2H_SIZE;
|
---|
2715 | break;
|
---|
2716 | }
|
---|
2717 | case AHCI_CMDFIS_TYPE_SETDEVBITS:
|
---|
2718 | {
|
---|
2719 | GCPhysAddrRecFis += AHCI_RECFIS_SDBFIS_OFFSET;
|
---|
2720 | cbFis = AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE;
|
---|
2721 | break;
|
---|
2722 | }
|
---|
2723 | case AHCI_CMDFIS_TYPE_DMASETUP:
|
---|
2724 | {
|
---|
2725 | GCPhysAddrRecFis += AHCI_RECFIS_DSFIS_OFFSET;
|
---|
2726 | cbFis = AHCI_CMDFIS_TYPE_DMASETUP_SIZE;
|
---|
2727 | break;
|
---|
2728 | }
|
---|
2729 | case AHCI_CMDFIS_TYPE_PIOSETUP:
|
---|
2730 | {
|
---|
2731 | GCPhysAddrRecFis += AHCI_RECFIS_PSFIS_OFFSET;
|
---|
2732 | cbFis = AHCI_CMDFIS_TYPE_PIOSETUP_SIZE;
|
---|
2733 | break;
|
---|
2734 | }
|
---|
2735 | default:
|
---|
2736 | /*
|
---|
2737 | * We should post the unknown FIS into memory too but this never happens because
|
---|
2738 | * we know which FIS types we generate. ;)
|
---|
2739 | */
|
---|
2740 | AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
|
---|
2741 | }
|
---|
2742 |
|
---|
2743 | /* Post the FIS into memory. */
|
---|
2744 | ahciLog(("%s: PDMDevHlpPCIPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
|
---|
2745 | PDMDevHlpPCIPhysWriteMeta(pDevIns, GCPhysAddrRecFis, pCmdFis, cbFis);
|
---|
2746 | }
|
---|
2747 |
|
---|
2748 | return rc;
|
---|
2749 | }
|
---|
2750 |
|
---|
2751 | DECLINLINE(void) ahciReqSetStatus(PAHCIREQ pAhciReq, uint8_t u8Error, uint8_t u8Status)
|
---|
2752 | {
|
---|
2753 | pAhciReq->cmdFis[AHCI_CMDFIS_ERR] = u8Error;
|
---|
2754 | pAhciReq->cmdFis[AHCI_CMDFIS_STS] = u8Status;
|
---|
2755 | }
|
---|
2756 |
|
---|
2757 | static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
|
---|
2758 | {
|
---|
2759 | for (uint32_t i = 0; i < cbSize; i++)
|
---|
2760 | {
|
---|
2761 | if (*pbSrc)
|
---|
2762 | pbDst[i ^ 1] = *pbSrc++;
|
---|
2763 | else
|
---|
2764 | pbDst[i ^ 1] = ' ';
|
---|
2765 | }
|
---|
2766 | }
|
---|
2767 |
|
---|
2768 | static uint32_t ataChecksum(void* ptr, size_t count)
|
---|
2769 | {
|
---|
2770 | uint8_t u8Sum = 0xa5, *p = (uint8_t*)ptr;
|
---|
2771 | size_t i;
|
---|
2772 |
|
---|
2773 | for (i = 0; i < count; i++)
|
---|
2774 | {
|
---|
2775 | u8Sum += *p++;
|
---|
2776 | }
|
---|
2777 |
|
---|
2778 | return (uint8_t)-(int32_t)u8Sum;
|
---|
2779 | }
|
---|
2780 |
|
---|
2781 | static int ahciIdentifySS(PAHCI pThis, PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3, void *pvBuf)
|
---|
2782 | {
|
---|
2783 | uint16_t *p = (uint16_t *)pvBuf;
|
---|
2784 | memset(p, 0, 512);
|
---|
2785 | p[0] = RT_H2LE_U16(0x0040);
|
---|
2786 | p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
|
---|
2787 | p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
|
---|
2788 | /* Block size; obsolete, but required for the BIOS. */
|
---|
2789 | p[5] = RT_H2LE_U16(512);
|
---|
2790 | p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
|
---|
2791 | ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
|
---|
2792 | p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
|
---|
2793 | p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
|
---|
2794 | p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
|
---|
2795 | ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
|
---|
2796 | ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
|
---|
2797 | #if ATA_MAX_MULT_SECTORS > 1
|
---|
2798 | p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
|
---|
2799 | #endif
|
---|
2800 | p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
|
---|
2801 | p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
|
---|
2802 | p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
|
---|
2803 | p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
|
---|
2804 | p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
|
---|
2805 | p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
|
---|
2806 | p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
|
---|
2807 | p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
|
---|
2808 | p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
|
---|
2809 | p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
|
---|
2810 | p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
|
---|
2811 | if (pAhciPort->cMultSectors)
|
---|
2812 | p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
|
---|
2813 | if (pAhciPort->cTotalSectors <= (1 << 28) - 1)
|
---|
2814 | {
|
---|
2815 | p[60] = RT_H2LE_U16(pAhciPort->cTotalSectors);
|
---|
2816 | p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
|
---|
2817 | }
|
---|
2818 | else
|
---|
2819 | {
|
---|
2820 | /* Report maximum number of sectors possible with LBA28 */
|
---|
2821 | p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
|
---|
2822 | p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
|
---|
2823 | }
|
---|
2824 | p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
|
---|
2825 | p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
|
---|
2826 | p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
|
---|
2827 | p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
|
---|
2828 | p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
|
---|
2829 | p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
|
---|
2830 | if ( pAhciPort->fTrimEnabled
|
---|
2831 | || pAhciPort->cbSector != 512
|
---|
2832 | || pAhciPortR3->pDrvMedia->pfnIsNonRotational(pAhciPortR3->pDrvMedia))
|
---|
2833 | {
|
---|
2834 | p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
|
---|
2835 | p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
|
---|
2836 | }
|
---|
2837 | else
|
---|
2838 | {
|
---|
2839 | p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
|
---|
2840 | p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
|
---|
2841 | }
|
---|
2842 | p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
|
---|
2843 | p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
|
---|
2844 | p[84] = RT_H2LE_U16(1 << 14);
|
---|
2845 | p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
|
---|
2846 | p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
|
---|
2847 | p[87] = RT_H2LE_U16(1 << 14);
|
---|
2848 | p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
|
---|
2849 | p[93] = RT_H2LE_U16(0x00);
|
---|
2850 | p[100] = RT_H2LE_U16(pAhciPort->cTotalSectors);
|
---|
2851 | p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
|
---|
2852 | p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
|
---|
2853 | p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
|
---|
2854 |
|
---|
2855 | /* valid information, more than one logical sector per physical sector, 2^cLogSectorsPerPhysicalExp logical sectors per physical sector */
|
---|
2856 | if (pAhciPort->cLogSectorsPerPhysicalExp)
|
---|
2857 | p[106] = RT_H2LE_U16(RT_BIT(14) | RT_BIT(13) | pAhciPort->cLogSectorsPerPhysicalExp);
|
---|
2858 |
|
---|
2859 | if (pAhciPort->cbSector != 512)
|
---|
2860 | {
|
---|
2861 | uint32_t cSectorSizeInWords = pAhciPort->cbSector / sizeof(uint16_t);
|
---|
2862 | /* Enable reporting of logical sector size. */
|
---|
2863 | p[106] |= RT_H2LE_U16(RT_BIT(12) | RT_BIT(14));
|
---|
2864 | p[117] = RT_H2LE_U16(cSectorSizeInWords);
|
---|
2865 | p[118] = RT_H2LE_U16(cSectorSizeInWords >> 16);
|
---|
2866 | }
|
---|
2867 |
|
---|
2868 | if (pAhciPortR3->pDrvMedia->pfnIsNonRotational(pAhciPortR3->pDrvMedia))
|
---|
2869 | p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
|
---|
2870 |
|
---|
2871 | if (pAhciPort->fTrimEnabled) /** @todo Set bit 14 in word 69 too? (Deterministic read after TRIM). */
|
---|
2872 | p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
|
---|
2873 |
|
---|
2874 | /* The following are SATA specific */
|
---|
2875 | p[75] = RT_H2LE_U16(pThis->cCmdSlotsAvail - 1); /* Number of commands we support, 0's based */
|
---|
2876 | p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
|
---|
2877 |
|
---|
2878 | uint32_t uCsum = ataChecksum(p, 510);
|
---|
2879 | p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
|
---|
2880 |
|
---|
2881 | return VINF_SUCCESS;
|
---|
2882 | }
|
---|
2883 |
|
---|
2884 | static int ahciR3AtapiIdentify(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq, PAHCIPORT pAhciPort, size_t cbData, size_t *pcbData)
|
---|
2885 | {
|
---|
2886 | uint16_t p[256];
|
---|
2887 |
|
---|
2888 | memset(p, 0, 512);
|
---|
2889 | /* Removable CDROM, 50us response, 12 byte packets */
|
---|
2890 | p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
|
---|
2891 | ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
|
---|
2892 | p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
|
---|
2893 | p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
|
---|
2894 | ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
|
---|
2895 | ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
|
---|
2896 | p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
|
---|
2897 | p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
|
---|
2898 | p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
|
---|
2899 | p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
|
---|
2900 | p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
|
---|
2901 | p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
|
---|
2902 | p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
|
---|
2903 | p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
|
---|
2904 | p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
|
---|
2905 | p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
|
---|
2906 | p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
|
---|
2907 | p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
|
---|
2908 | p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
|
---|
2909 | p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
|
---|
2910 | p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
|
---|
2911 | p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
|
---|
2912 | p[83] = RT_H2LE_U16(1 << 14);
|
---|
2913 | p[84] = RT_H2LE_U16(1 << 14);
|
---|
2914 | p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
|
---|
2915 | p[86] = RT_H2LE_U16(0);
|
---|
2916 | p[87] = RT_H2LE_U16(1 << 14);
|
---|
2917 | p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
|
---|
2918 | p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
|
---|
2919 |
|
---|
2920 | /* The following are SATA specific */
|
---|
2921 | p[75] = RT_H2LE_U16(31); /* We support 32 commands */
|
---|
2922 | p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
|
---|
2923 |
|
---|
2924 | /* Copy the buffer in to the scatter gather list. */
|
---|
2925 | *pcbData = ahciR3CopyBufferToPrdtl(pDevIns, pAhciReq, (void *)&p[0], RT_MIN(cbData, sizeof(p)), 0 /* cbSkip */);
|
---|
2926 | return VINF_SUCCESS;
|
---|
2927 | }
|
---|
2928 |
|
---|
2929 | /**
|
---|
2930 | * Reset all values after a reset of the attached storage device.
|
---|
2931 | *
|
---|
2932 | * @param pDevIns The device instance.
|
---|
2933 | * @param pThis The shared AHCI state.
|
---|
2934 | * @param pAhciPort The port the device is attached to, shared bits(shared
|
---|
2935 | * bits).
|
---|
2936 | * @param pAhciReq The state to get the tag number from.
|
---|
2937 | */
|
---|
2938 | static void ahciFinishStorageDeviceReset(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIREQ pAhciReq)
|
---|
2939 | {
|
---|
2940 | int rc;
|
---|
2941 |
|
---|
2942 | /* Send a status good D2H FIS. */
|
---|
2943 | pAhciPort->fResetDevice = false;
|
---|
2944 | if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
|
---|
2945 | ahciPostFirstD2HFisIntoMemory(pDevIns, pAhciPort);
|
---|
2946 |
|
---|
2947 | /* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
|
---|
2948 | if (pAhciPort->fATAPI)
|
---|
2949 | pAhciPort->regSIG = AHCI_PORT_SIG_ATAPI;
|
---|
2950 | else
|
---|
2951 | pAhciPort->regSIG = AHCI_PORT_SIG_DISK;
|
---|
2952 | ASMAtomicOrU32(&pAhciPort->u32TasksFinished, (1 << pAhciReq->uTag));
|
---|
2953 |
|
---|
2954 | rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
2955 | AssertRC(rc);
|
---|
2956 | }
|
---|
2957 |
|
---|
2958 | /**
|
---|
2959 | * Initiates a device reset caused by ATA_DEVICE_RESET (ATAPI only).
|
---|
2960 | *
|
---|
2961 | * @param pDevIns The device instance.
|
---|
2962 | * @param pThis The shared AHCI state.
|
---|
2963 | * @param pAhciPort The device to reset(shared bits).
|
---|
2964 | * @param pAhciReq The task state.
|
---|
2965 | */
|
---|
2966 | static void ahciDeviceReset(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIREQ pAhciReq)
|
---|
2967 | {
|
---|
2968 | ASMAtomicWriteBool(&pAhciPort->fResetDevice, true);
|
---|
2969 |
|
---|
2970 | /*
|
---|
2971 | * Because this ATAPI only and ATAPI can't have
|
---|
2972 | * more than one command active at a time the task counter should be 0
|
---|
2973 | * and it is possible to finish the reset now.
|
---|
2974 | */
|
---|
2975 | Assert(ASMAtomicReadU32(&pAhciPort->cTasksActive) == 0);
|
---|
2976 | ahciFinishStorageDeviceReset(pDevIns, pThis, pAhciPort, pAhciReq);
|
---|
2977 | }
|
---|
2978 |
|
---|
2979 | /**
|
---|
2980 | * Create a PIO setup FIS and post it into the memory area of the guest.
|
---|
2981 | *
|
---|
2982 | * @param pDevIns The device instance.
|
---|
2983 | * @param pThis The shared AHCI state.
|
---|
2984 | * @param pAhciPort The port of the SATA controller (shared bits).
|
---|
2985 | * @param cbTransfer Transfer size of the request.
|
---|
2986 | * @param pCmdFis Pointer to the command FIS from the guest.
|
---|
2987 | * @param fRead Flag whether this is a read request.
|
---|
2988 | * @param fInterrupt If an interrupt should be send to the guest.
|
---|
2989 | */
|
---|
2990 | static void ahciSendPioSetupFis(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort,
|
---|
2991 | size_t cbTransfer, uint8_t *pCmdFis, bool fRead, bool fInterrupt)
|
---|
2992 | {
|
---|
2993 | uint8_t abPioSetupFis[20];
|
---|
2994 | bool fAssertIntr = false;
|
---|
2995 |
|
---|
2996 | ahciLog(("%s: building PIO setup Fis\n", __FUNCTION__));
|
---|
2997 |
|
---|
2998 | AssertMsg( cbTransfer > 0
|
---|
2999 | && cbTransfer <= 65534,
|
---|
3000 | ("Can't send PIO setup FIS for requests with 0 bytes to transfer or greater than 65534\n"));
|
---|
3001 |
|
---|
3002 | if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
|
---|
3003 | {
|
---|
3004 | memset(&abPioSetupFis[0], 0, sizeof(abPioSetupFis));
|
---|
3005 | abPioSetupFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_PIOSETUP;
|
---|
3006 | abPioSetupFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
|
---|
3007 | if (fRead)
|
---|
3008 | abPioSetupFis[AHCI_CMDFIS_BITS] |= AHCI_CMDFIS_D;
|
---|
3009 | abPioSetupFis[AHCI_CMDFIS_STS] = pCmdFis[AHCI_CMDFIS_STS];
|
---|
3010 | abPioSetupFis[AHCI_CMDFIS_ERR] = pCmdFis[AHCI_CMDFIS_ERR];
|
---|
3011 | abPioSetupFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
|
---|
3012 | abPioSetupFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
|
---|
3013 | abPioSetupFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
|
---|
3014 | abPioSetupFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
|
---|
3015 | abPioSetupFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
|
---|
3016 | abPioSetupFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
|
---|
3017 | abPioSetupFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
|
---|
3018 | abPioSetupFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
|
---|
3019 | abPioSetupFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
|
---|
3020 |
|
---|
3021 | /* Set transfer count. */
|
---|
3022 | abPioSetupFis[16] = (cbTransfer >> 8) & 0xff;
|
---|
3023 | abPioSetupFis[17] = cbTransfer & 0xff;
|
---|
3024 |
|
---|
3025 | /* Update registers. */
|
---|
3026 | pAhciPort->regTFD = (pCmdFis[AHCI_CMDFIS_ERR] << 8) | pCmdFis[AHCI_CMDFIS_STS];
|
---|
3027 |
|
---|
3028 | ahciPostFisIntoMemory(pDevIns, pAhciPort, AHCI_CMDFIS_TYPE_PIOSETUP, abPioSetupFis);
|
---|
3029 |
|
---|
3030 | if (fInterrupt)
|
---|
3031 | {
|
---|
3032 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PSS);
|
---|
3033 | /* Check if we should assert an interrupt */
|
---|
3034 | if (pAhciPort->regIE & AHCI_PORT_IE_PSE)
|
---|
3035 | fAssertIntr = true;
|
---|
3036 | }
|
---|
3037 |
|
---|
3038 | if (fAssertIntr)
|
---|
3039 | {
|
---|
3040 | int rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
3041 | AssertRC(rc);
|
---|
3042 | }
|
---|
3043 | }
|
---|
3044 | }
|
---|
3045 |
|
---|
3046 | /**
|
---|
3047 | * Build a D2H FIS and post into the memory area of the guest.
|
---|
3048 | *
|
---|
3049 | * @param pDevIns The device instance.
|
---|
3050 | * @param pThis The shared AHCI state.
|
---|
3051 | * @param pAhciPort The port of the SATA controller (shared bits).
|
---|
3052 | * @param uTag The tag of the request.
|
---|
3053 | * @param pCmdFis Pointer to the command FIS from the guest.
|
---|
3054 | * @param fInterrupt If an interrupt should be send to the guest.
|
---|
3055 | */
|
---|
3056 | static void ahciSendD2HFis(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, uint32_t uTag, uint8_t *pCmdFis, bool fInterrupt)
|
---|
3057 | {
|
---|
3058 | uint8_t d2hFis[20];
|
---|
3059 | bool fAssertIntr = false;
|
---|
3060 |
|
---|
3061 | ahciLog(("%s: building D2H Fis\n", __FUNCTION__));
|
---|
3062 |
|
---|
3063 | if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
|
---|
3064 | {
|
---|
3065 | memset(&d2hFis[0], 0, sizeof(d2hFis));
|
---|
3066 | d2hFis[AHCI_CMDFIS_TYPE] = AHCI_CMDFIS_TYPE_D2H;
|
---|
3067 | d2hFis[AHCI_CMDFIS_BITS] = (fInterrupt ? AHCI_CMDFIS_I : 0);
|
---|
3068 | d2hFis[AHCI_CMDFIS_STS] = pCmdFis[AHCI_CMDFIS_STS];
|
---|
3069 | d2hFis[AHCI_CMDFIS_ERR] = pCmdFis[AHCI_CMDFIS_ERR];
|
---|
3070 | d2hFis[AHCI_CMDFIS_SECTN] = pCmdFis[AHCI_CMDFIS_SECTN];
|
---|
3071 | d2hFis[AHCI_CMDFIS_CYLL] = pCmdFis[AHCI_CMDFIS_CYLL];
|
---|
3072 | d2hFis[AHCI_CMDFIS_CYLH] = pCmdFis[AHCI_CMDFIS_CYLH];
|
---|
3073 | d2hFis[AHCI_CMDFIS_HEAD] = pCmdFis[AHCI_CMDFIS_HEAD];
|
---|
3074 | d2hFis[AHCI_CMDFIS_SECTNEXP] = pCmdFis[AHCI_CMDFIS_SECTNEXP];
|
---|
3075 | d2hFis[AHCI_CMDFIS_CYLLEXP] = pCmdFis[AHCI_CMDFIS_CYLLEXP];
|
---|
3076 | d2hFis[AHCI_CMDFIS_CYLHEXP] = pCmdFis[AHCI_CMDFIS_CYLHEXP];
|
---|
3077 | d2hFis[AHCI_CMDFIS_SECTC] = pCmdFis[AHCI_CMDFIS_SECTC];
|
---|
3078 | d2hFis[AHCI_CMDFIS_SECTCEXP] = pCmdFis[AHCI_CMDFIS_SECTCEXP];
|
---|
3079 |
|
---|
3080 | /* Update registers. */
|
---|
3081 | pAhciPort->regTFD = (pCmdFis[AHCI_CMDFIS_ERR] << 8) | pCmdFis[AHCI_CMDFIS_STS];
|
---|
3082 |
|
---|
3083 | ahciPostFisIntoMemory(pDevIns, pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
|
---|
3084 |
|
---|
3085 | if (pCmdFis[AHCI_CMDFIS_STS] & ATA_STAT_ERR)
|
---|
3086 | {
|
---|
3087 | /* Error bit is set. */
|
---|
3088 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
|
---|
3089 | if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
|
---|
3090 | fAssertIntr = true;
|
---|
3091 | /*
|
---|
3092 | * Don't mark the command slot as completed because the guest
|
---|
3093 | * needs it to identify the failed command.
|
---|
3094 | */
|
---|
3095 | }
|
---|
3096 | else if (fInterrupt)
|
---|
3097 | {
|
---|
3098 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
|
---|
3099 | /* Check if we should assert an interrupt */
|
---|
3100 | if (pAhciPort->regIE & AHCI_PORT_IE_DHRE)
|
---|
3101 | fAssertIntr = true;
|
---|
3102 |
|
---|
3103 | /* Mark command as completed. */
|
---|
3104 | ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(uTag));
|
---|
3105 | }
|
---|
3106 |
|
---|
3107 | if (fAssertIntr)
|
---|
3108 | {
|
---|
3109 | int rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
3110 | AssertRC(rc);
|
---|
3111 | }
|
---|
3112 | }
|
---|
3113 | }
|
---|
3114 |
|
---|
3115 | /**
|
---|
3116 | * Build a SDB Fis and post it into the memory area of the guest.
|
---|
3117 | *
|
---|
3118 | * @param pDevIns The device instance.
|
---|
3119 | * @param pThis The shared AHCI state.
|
---|
3120 | * @param pAhciPort The port for which the SDB Fis is send, shared bits.
|
---|
3121 | * @param pAhciPortR3 The port for which the SDB Fis is send, ring-3 bits.
|
---|
3122 | * @param uFinishedTasks Bitmask of finished tasks.
|
---|
3123 | * @param fInterrupt If an interrupt should be asserted.
|
---|
3124 | */
|
---|
3125 | static void ahciSendSDBFis(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3,
|
---|
3126 | uint32_t uFinishedTasks, bool fInterrupt)
|
---|
3127 | {
|
---|
3128 | uint32_t sdbFis[2];
|
---|
3129 | bool fAssertIntr = false;
|
---|
3130 | PAHCIREQ pTaskErr = ASMAtomicReadPtrT(&pAhciPortR3->pTaskErr, PAHCIREQ);
|
---|
3131 |
|
---|
3132 | ahciLog(("%s: Building SDB FIS\n", __FUNCTION__));
|
---|
3133 |
|
---|
3134 | if (pAhciPort->regCMD & AHCI_PORT_CMD_FRE)
|
---|
3135 | {
|
---|
3136 | memset(&sdbFis[0], 0, sizeof(sdbFis));
|
---|
3137 | sdbFis[0] = AHCI_CMDFIS_TYPE_SETDEVBITS;
|
---|
3138 | sdbFis[0] |= (fInterrupt ? (1 << 14) : 0);
|
---|
3139 | if (RT_UNLIKELY(pTaskErr))
|
---|
3140 | {
|
---|
3141 | sdbFis[0] = pTaskErr->cmdFis[AHCI_CMDFIS_ERR];
|
---|
3142 | sdbFis[0] |= (pTaskErr->cmdFis[AHCI_CMDFIS_STS] & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
|
---|
3143 |
|
---|
3144 | /* Update registers. */
|
---|
3145 | pAhciPort->regTFD = (pTaskErr->cmdFis[AHCI_CMDFIS_ERR] << 8) | pTaskErr->cmdFis[AHCI_CMDFIS_STS];
|
---|
3146 | }
|
---|
3147 | else
|
---|
3148 | {
|
---|
3149 | sdbFis[0] = 0;
|
---|
3150 | sdbFis[0] |= (ATA_STAT_READY | ATA_STAT_SEEK) << 16;
|
---|
3151 | pAhciPort->regTFD = ATA_STAT_READY | ATA_STAT_SEEK;
|
---|
3152 | }
|
---|
3153 |
|
---|
3154 | sdbFis[1] = pAhciPort->u32QueuedTasksFinished | uFinishedTasks;
|
---|
3155 |
|
---|
3156 | ahciPostFisIntoMemory(pDevIns, pAhciPort, AHCI_CMDFIS_TYPE_SETDEVBITS, (uint8_t *)sdbFis);
|
---|
3157 |
|
---|
3158 | if (RT_UNLIKELY(pTaskErr))
|
---|
3159 | {
|
---|
3160 | /* Error bit is set. */
|
---|
3161 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_TFES);
|
---|
3162 | if (pAhciPort->regIE & AHCI_PORT_IE_TFEE)
|
---|
3163 | fAssertIntr = true;
|
---|
3164 | }
|
---|
3165 |
|
---|
3166 | if (fInterrupt)
|
---|
3167 | {
|
---|
3168 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_SDBS);
|
---|
3169 | /* Check if we should assert an interrupt */
|
---|
3170 | if (pAhciPort->regIE & AHCI_PORT_IE_SDBE)
|
---|
3171 | fAssertIntr = true;
|
---|
3172 | }
|
---|
3173 |
|
---|
3174 | ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, uFinishedTasks);
|
---|
3175 |
|
---|
3176 | if (fAssertIntr)
|
---|
3177 | {
|
---|
3178 | int rc = ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
3179 | AssertRC(rc);
|
---|
3180 | }
|
---|
3181 | }
|
---|
3182 | }
|
---|
3183 |
|
---|
3184 | static uint32_t ahciGetNSectors(uint8_t *pCmdFis, bool fLBA48)
|
---|
3185 | {
|
---|
3186 | /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
|
---|
3187 | if (fLBA48)
|
---|
3188 | {
|
---|
3189 | if (!pCmdFis[AHCI_CMDFIS_SECTC] && !pCmdFis[AHCI_CMDFIS_SECTCEXP])
|
---|
3190 | return 65536;
|
---|
3191 | else
|
---|
3192 | return pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8 | pCmdFis[AHCI_CMDFIS_SECTC];
|
---|
3193 | }
|
---|
3194 | else
|
---|
3195 | {
|
---|
3196 | if (!pCmdFis[AHCI_CMDFIS_SECTC])
|
---|
3197 | return 256;
|
---|
3198 | else
|
---|
3199 | return pCmdFis[AHCI_CMDFIS_SECTC];
|
---|
3200 | }
|
---|
3201 | }
|
---|
3202 |
|
---|
3203 | static uint64_t ahciGetSector(PAHCIPORT pAhciPort, uint8_t *pCmdFis, bool fLBA48)
|
---|
3204 | {
|
---|
3205 | uint64_t iLBA;
|
---|
3206 | if (pCmdFis[AHCI_CMDFIS_HEAD] & 0x40)
|
---|
3207 | {
|
---|
3208 | /* any LBA variant */
|
---|
3209 | if (fLBA48)
|
---|
3210 | {
|
---|
3211 | /* LBA48 */
|
---|
3212 | iLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
|
---|
3213 | ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
|
---|
3214 | ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
|
---|
3215 | ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
|
---|
3216 | ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
|
---|
3217 | pCmdFis[AHCI_CMDFIS_SECTN];
|
---|
3218 | }
|
---|
3219 | else
|
---|
3220 | {
|
---|
3221 | /* LBA */
|
---|
3222 | iLBA = ((pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) << 24) | (pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
|
---|
3223 | (pCmdFis[AHCI_CMDFIS_CYLL] << 8) | pCmdFis[AHCI_CMDFIS_SECTN];
|
---|
3224 | }
|
---|
3225 | }
|
---|
3226 | else
|
---|
3227 | {
|
---|
3228 | /* CHS */
|
---|
3229 | iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
|
---|
3230 | (pCmdFis[AHCI_CMDFIS_HEAD] & 0x0f) * pAhciPort->PCHSGeometry.cSectors +
|
---|
3231 | (pCmdFis[AHCI_CMDFIS_SECTN] - 1);
|
---|
3232 | }
|
---|
3233 | return iLBA;
|
---|
3234 | }
|
---|
3235 |
|
---|
3236 | static uint64_t ahciGetSectorQueued(uint8_t *pCmdFis)
|
---|
3237 | {
|
---|
3238 | uint64_t uLBA;
|
---|
3239 |
|
---|
3240 | uLBA = ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLHEXP] << 40) |
|
---|
3241 | ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLLEXP] << 32) |
|
---|
3242 | ((uint64_t)pCmdFis[AHCI_CMDFIS_SECTNEXP] << 24) |
|
---|
3243 | ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLH] << 16) |
|
---|
3244 | ((uint64_t)pCmdFis[AHCI_CMDFIS_CYLL] << 8) |
|
---|
3245 | pCmdFis[AHCI_CMDFIS_SECTN];
|
---|
3246 |
|
---|
3247 | return uLBA;
|
---|
3248 | }
|
---|
3249 |
|
---|
3250 | DECLINLINE(uint32_t) ahciGetNSectorsQueued(uint8_t *pCmdFis)
|
---|
3251 | {
|
---|
3252 | if (!pCmdFis[AHCI_CMDFIS_FETEXP] && !pCmdFis[AHCI_CMDFIS_FET])
|
---|
3253 | return 65536;
|
---|
3254 | else
|
---|
3255 | return pCmdFis[AHCI_CMDFIS_FETEXP] << 8 | pCmdFis[AHCI_CMDFIS_FET];
|
---|
3256 | }
|
---|
3257 |
|
---|
3258 | /**
|
---|
3259 | * Copy from guest to host memory worker.
|
---|
3260 | *
|
---|
3261 | * @copydoc FNAHCIR3MEMCOPYCALLBACK
|
---|
3262 | */
|
---|
3263 | static DECLCALLBACK(void) ahciR3CopyBufferFromGuestWorker(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
|
---|
3264 | size_t cbCopy, size_t *pcbSkip)
|
---|
3265 | {
|
---|
3266 | size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
|
---|
3267 | cbCopy -= cbSkipped;
|
---|
3268 | GCPhys += cbSkipped;
|
---|
3269 | *pcbSkip -= cbSkipped;
|
---|
3270 |
|
---|
3271 | while (cbCopy)
|
---|
3272 | {
|
---|
3273 | size_t cbSeg = cbCopy;
|
---|
3274 | void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
|
---|
3275 |
|
---|
3276 | AssertPtr(pvSeg);
|
---|
3277 | Log5Func(("%RGp LB %#zx\n", GCPhys, cbSeg));
|
---|
3278 | PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvSeg, cbSeg);
|
---|
3279 | Log7Func(("%.*Rhxd\n", cbSeg, pvSeg));
|
---|
3280 | GCPhys += cbSeg;
|
---|
3281 | cbCopy -= cbSeg;
|
---|
3282 | }
|
---|
3283 | }
|
---|
3284 |
|
---|
3285 | /**
|
---|
3286 | * Copy from host to guest memory worker.
|
---|
3287 | *
|
---|
3288 | * @copydoc FNAHCIR3MEMCOPYCALLBACK
|
---|
3289 | */
|
---|
3290 | static DECLCALLBACK(void) ahciR3CopyBufferToGuestWorker(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, PRTSGBUF pSgBuf,
|
---|
3291 | size_t cbCopy, size_t *pcbSkip)
|
---|
3292 | {
|
---|
3293 | size_t cbSkipped = RT_MIN(cbCopy, *pcbSkip);
|
---|
3294 | cbCopy -= cbSkipped;
|
---|
3295 | GCPhys += cbSkipped;
|
---|
3296 | *pcbSkip -= cbSkipped;
|
---|
3297 |
|
---|
3298 | while (cbCopy)
|
---|
3299 | {
|
---|
3300 | size_t cbSeg = cbCopy;
|
---|
3301 | void *pvSeg = RTSgBufGetNextSegment(pSgBuf, &cbSeg);
|
---|
3302 |
|
---|
3303 | AssertPtr(pvSeg);
|
---|
3304 | Log5Func(("%RGp LB %#zx\n", GCPhys, cbSeg));
|
---|
3305 | Log6Func(("%.*Rhxd\n", cbSeg, pvSeg));
|
---|
3306 | PDMDevHlpPCIPhysWriteUser(pDevIns, GCPhys, pvSeg, cbSeg);
|
---|
3307 | GCPhys += cbSeg;
|
---|
3308 | cbCopy -= cbSeg;
|
---|
3309 | }
|
---|
3310 | }
|
---|
3311 |
|
---|
3312 | /**
|
---|
3313 | * Walks the PRDTL list copying data between the guest and host memory buffers.
|
---|
3314 | *
|
---|
3315 | * @returns Amount of bytes copied.
|
---|
3316 | * @param pDevIns The device instance.
|
---|
3317 | * @param pAhciReq AHCI request structure.
|
---|
3318 | * @param pfnCopyWorker The copy method to apply for each guest buffer.
|
---|
3319 | * @param pSgBuf The host S/G buffer.
|
---|
3320 | * @param cbSkip How many bytes to skip in advance before starting to copy.
|
---|
3321 | * @param cbCopy How many bytes to copy.
|
---|
3322 | */
|
---|
3323 | static size_t ahciR3PrdtlWalk(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
|
---|
3324 | PFNAHCIR3MEMCOPYCALLBACK pfnCopyWorker,
|
---|
3325 | PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
|
---|
3326 | {
|
---|
3327 | RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
|
---|
3328 | unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
|
---|
3329 | size_t cbCopied = 0;
|
---|
3330 |
|
---|
3331 | /*
|
---|
3332 | * Add the amount to skip to the host buffer size to avoid a
|
---|
3333 | * few conditionals later on.
|
---|
3334 | */
|
---|
3335 | cbCopy += cbSkip;
|
---|
3336 |
|
---|
3337 | AssertMsgReturn(cPrdtlEntries > 0, ("Copying 0 bytes is not possible\n"), 0);
|
---|
3338 |
|
---|
3339 | do
|
---|
3340 | {
|
---|
3341 | SGLEntry aPrdtlEntries[32];
|
---|
3342 | uint32_t cPrdtlEntriesRead = cPrdtlEntries < RT_ELEMENTS(aPrdtlEntries)
|
---|
3343 | ? cPrdtlEntries
|
---|
3344 | : RT_ELEMENTS(aPrdtlEntries);
|
---|
3345 |
|
---|
3346 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0],
|
---|
3347 | cPrdtlEntriesRead * sizeof(SGLEntry));
|
---|
3348 |
|
---|
3349 | for (uint32_t i = 0; (i < cPrdtlEntriesRead) && cbCopy; i++)
|
---|
3350 | {
|
---|
3351 | RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
|
---|
3352 | uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
|
---|
3353 |
|
---|
3354 | cbThisCopy = (uint32_t)RT_MIN(cbThisCopy, cbCopy);
|
---|
3355 |
|
---|
3356 | /* Copy into SG entry. */
|
---|
3357 | pfnCopyWorker(pDevIns, GCPhysAddrDataBase, pSgBuf, cbThisCopy, &cbSkip);
|
---|
3358 |
|
---|
3359 | cbCopy -= cbThisCopy;
|
---|
3360 | cbCopied += cbThisCopy;
|
---|
3361 | }
|
---|
3362 |
|
---|
3363 | GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
|
---|
3364 | cPrdtlEntries -= cPrdtlEntriesRead;
|
---|
3365 | } while (cPrdtlEntries && cbCopy);
|
---|
3366 |
|
---|
3367 | if (cbCopied < cbCopy)
|
---|
3368 | pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
|
---|
3369 |
|
---|
3370 | return cbCopied;
|
---|
3371 | }
|
---|
3372 |
|
---|
3373 | /**
|
---|
3374 | * Copies a data buffer into the S/G buffer set up by the guest.
|
---|
3375 | *
|
---|
3376 | * @returns Amount of bytes copied to the PRDTL.
|
---|
3377 | * @param pDevIns The device instance.
|
---|
3378 | * @param pAhciReq AHCI request structure.
|
---|
3379 | * @param pSgBuf The S/G buffer to copy from.
|
---|
3380 | * @param cbSkip How many bytes to skip in advance before starting to copy.
|
---|
3381 | * @param cbCopy How many bytes to copy.
|
---|
3382 | */
|
---|
3383 | static size_t ahciR3CopySgBufToPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq, PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
|
---|
3384 | {
|
---|
3385 | return ahciR3PrdtlWalk(pDevIns, pAhciReq, ahciR3CopyBufferToGuestWorker, pSgBuf, cbSkip, cbCopy);
|
---|
3386 | }
|
---|
3387 |
|
---|
3388 | /**
|
---|
3389 | * Copies the S/G buffer into a data buffer.
|
---|
3390 | *
|
---|
3391 | * @returns Amount of bytes copied from the PRDTL.
|
---|
3392 | * @param pDevIns The device instance.
|
---|
3393 | * @param pAhciReq AHCI request structure.
|
---|
3394 | * @param pSgBuf The S/G buffer to copy into.
|
---|
3395 | * @param cbSkip How many bytes to skip in advance before starting to copy.
|
---|
3396 | * @param cbCopy How many bytes to copy.
|
---|
3397 | */
|
---|
3398 | static size_t ahciR3CopySgBufFromPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq, PRTSGBUF pSgBuf, size_t cbSkip, size_t cbCopy)
|
---|
3399 | {
|
---|
3400 | return ahciR3PrdtlWalk(pDevIns, pAhciReq, ahciR3CopyBufferFromGuestWorker, pSgBuf, cbSkip, cbCopy);
|
---|
3401 | }
|
---|
3402 |
|
---|
3403 | /**
|
---|
3404 | * Copy a simple memory buffer to the guest memory buffer.
|
---|
3405 | *
|
---|
3406 | * @returns Amount of bytes copied from the PRDTL.
|
---|
3407 | * @param pDevIns The device instance.
|
---|
3408 | * @param pAhciReq AHCI request structure.
|
---|
3409 | * @param pvSrc The buffer to copy from.
|
---|
3410 | * @param cbSrc How many bytes to copy.
|
---|
3411 | * @param cbSkip How many bytes to skip initially.
|
---|
3412 | */
|
---|
3413 | static size_t ahciR3CopyBufferToPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq, const void *pvSrc, size_t cbSrc, size_t cbSkip)
|
---|
3414 | {
|
---|
3415 | RTSGSEG Seg;
|
---|
3416 | RTSGBUF SgBuf;
|
---|
3417 | Seg.pvSeg = (void *)pvSrc;
|
---|
3418 | Seg.cbSeg = cbSrc;
|
---|
3419 | RTSgBufInit(&SgBuf, &Seg, 1);
|
---|
3420 | return ahciR3CopySgBufToPrdtl(pDevIns, pAhciReq, &SgBuf, cbSkip, cbSrc);
|
---|
3421 | }
|
---|
3422 |
|
---|
3423 | /**
|
---|
3424 | * Calculates the size of the guest buffer described by the PRDT.
|
---|
3425 | *
|
---|
3426 | * @returns VBox status code.
|
---|
3427 | * @param pDevIns The device instance.
|
---|
3428 | * @param pAhciReq AHCI request structure.
|
---|
3429 | * @param pcbPrdt Where to store the size of the guest buffer.
|
---|
3430 | */
|
---|
3431 | static int ahciR3PrdtQuerySize(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq, size_t *pcbPrdt)
|
---|
3432 | {
|
---|
3433 | RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
|
---|
3434 | unsigned cPrdtlEntries = pAhciReq->cPrdtlEntries;
|
---|
3435 | size_t cbPrdt = 0;
|
---|
3436 |
|
---|
3437 | do
|
---|
3438 | {
|
---|
3439 | SGLEntry aPrdtlEntries[32];
|
---|
3440 | uint32_t const cPrdtlEntriesRead = RT_MIN(cPrdtlEntries, RT_ELEMENTS(aPrdtlEntries));
|
---|
3441 |
|
---|
3442 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
|
---|
3443 |
|
---|
3444 | for (uint32_t i = 0; i < cPrdtlEntriesRead; i++)
|
---|
3445 | cbPrdt += (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
|
---|
3446 |
|
---|
3447 | GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
|
---|
3448 | cPrdtlEntries -= cPrdtlEntriesRead;
|
---|
3449 | } while (cPrdtlEntries);
|
---|
3450 |
|
---|
3451 | *pcbPrdt = cbPrdt;
|
---|
3452 | return VINF_SUCCESS;
|
---|
3453 | }
|
---|
3454 |
|
---|
3455 | /**
|
---|
3456 | * Cancels all active tasks on the port.
|
---|
3457 | *
|
---|
3458 | * @returns Whether all active tasks were canceled.
|
---|
3459 | * @param pAhciPortR3 The AHCI port, ring-3 bits.
|
---|
3460 | */
|
---|
3461 | static bool ahciR3CancelActiveTasks(PAHCIPORTR3 pAhciPortR3)
|
---|
3462 | {
|
---|
3463 | if (pAhciPortR3->pDrvMediaEx)
|
---|
3464 | {
|
---|
3465 | int rc = pAhciPortR3->pDrvMediaEx->pfnIoReqCancelAll(pAhciPortR3->pDrvMediaEx);
|
---|
3466 | AssertRC(rc);
|
---|
3467 | }
|
---|
3468 | return true; /* always true for now because tasks don't use guest memory as the buffer which makes canceling a task impossible. */
|
---|
3469 | }
|
---|
3470 |
|
---|
3471 | /**
|
---|
3472 | * Creates the array of ranges to trim.
|
---|
3473 | *
|
---|
3474 | * @returns VBox status code.
|
---|
3475 | * @param pDevIns The device instance.
|
---|
3476 | * @param pAhciPort AHCI port state, shared bits.
|
---|
3477 | * @param pAhciReq The request handling the TRIM request.
|
---|
3478 | * @param idxRangeStart Index of the first range to start copying.
|
---|
3479 | * @param paRanges Where to store the ranges.
|
---|
3480 | * @param cRanges Number of ranges fitting into the array.
|
---|
3481 | * @param pcRanges Where to store the amount of ranges actually copied on success.
|
---|
3482 | */
|
---|
3483 | static int ahciTrimRangesCreate(PPDMDEVINS pDevIns, PAHCIPORT pAhciPort, PAHCIREQ pAhciReq, uint32_t idxRangeStart,
|
---|
3484 | PRTRANGE paRanges, uint32_t cRanges, uint32_t *pcRanges)
|
---|
3485 | {
|
---|
3486 | SGLEntry aPrdtlEntries[32];
|
---|
3487 | uint64_t aRanges[64];
|
---|
3488 | uint32_t cPrdtlEntries = pAhciReq->cPrdtlEntries;
|
---|
3489 | RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
|
---|
3490 | int rc = VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
|
---|
3491 | uint32_t idxRange = 0;
|
---|
3492 |
|
---|
3493 | LogFlowFunc(("pAhciPort=%#p pAhciReq=%#p\n", pAhciPort, pAhciReq));
|
---|
3494 |
|
---|
3495 | AssertMsgReturn(pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD, ("This is not a trim request\n"), VERR_INVALID_PARAMETER);
|
---|
3496 |
|
---|
3497 | if (!cPrdtlEntries)
|
---|
3498 | pAhciReq->fFlags |= AHCI_REQ_OVERFLOW;
|
---|
3499 |
|
---|
3500 | /* Convert the ranges from ATA to our format. */
|
---|
3501 | while ( cPrdtlEntries
|
---|
3502 | && idxRange < cRanges)
|
---|
3503 | {
|
---|
3504 | uint32_t cPrdtlEntriesRead = RT_MIN(cPrdtlEntries, RT_ELEMENTS(aPrdtlEntries));
|
---|
3505 |
|
---|
3506 | rc = VINF_SUCCESS;
|
---|
3507 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysPrdtl, &aPrdtlEntries[0], cPrdtlEntriesRead * sizeof(SGLEntry));
|
---|
3508 |
|
---|
3509 | for (uint32_t i = 0; i < cPrdtlEntriesRead && idxRange < cRanges; i++)
|
---|
3510 | {
|
---|
3511 | RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
|
---|
3512 | uint32_t cbThisCopy = (aPrdtlEntries[i].u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
|
---|
3513 |
|
---|
3514 | cbThisCopy = RT_MIN(cbThisCopy, sizeof(aRanges));
|
---|
3515 |
|
---|
3516 | /* Copy into buffer. */
|
---|
3517 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysAddrDataBase, aRanges, cbThisCopy);
|
---|
3518 |
|
---|
3519 | for (unsigned idxRangeSrc = 0; idxRangeSrc < RT_ELEMENTS(aRanges) && idxRange < cRanges; idxRangeSrc++)
|
---|
3520 | {
|
---|
3521 | /* Skip range if told to do so. */
|
---|
3522 | if (!idxRangeStart)
|
---|
3523 | {
|
---|
3524 | aRanges[idxRangeSrc] = RT_H2LE_U64(aRanges[idxRangeSrc]);
|
---|
3525 | if (AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) != 0)
|
---|
3526 | {
|
---|
3527 | paRanges[idxRange].offStart = (aRanges[idxRangeSrc] & AHCI_RANGE_LBA_MASK) * pAhciPort->cbSector;
|
---|
3528 | paRanges[idxRange].cbRange = AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) * pAhciPort->cbSector;
|
---|
3529 | idxRange++;
|
---|
3530 | }
|
---|
3531 | else
|
---|
3532 | break;
|
---|
3533 | }
|
---|
3534 | else
|
---|
3535 | idxRangeStart--;
|
---|
3536 | }
|
---|
3537 | }
|
---|
3538 |
|
---|
3539 | GCPhysPrdtl += cPrdtlEntriesRead * sizeof(SGLEntry);
|
---|
3540 | cPrdtlEntries -= cPrdtlEntriesRead;
|
---|
3541 | }
|
---|
3542 |
|
---|
3543 | *pcRanges = idxRange;
|
---|
3544 |
|
---|
3545 | LogFlowFunc(("returns rc=%Rrc\n", rc));
|
---|
3546 | return rc;
|
---|
3547 | }
|
---|
3548 |
|
---|
3549 | /**
|
---|
3550 | * Allocates a new AHCI request.
|
---|
3551 | *
|
---|
3552 | * @returns A new AHCI request structure or NULL if out of memory.
|
---|
3553 | * @param pAhciPortR3 The AHCI port, ring-3 bits.
|
---|
3554 | * @param uTag The tag to assign.
|
---|
3555 | */
|
---|
3556 | static PAHCIREQ ahciR3ReqAlloc(PAHCIPORTR3 pAhciPortR3, uint32_t uTag)
|
---|
3557 | {
|
---|
3558 | PAHCIREQ pAhciReq = NULL;
|
---|
3559 | PDMMEDIAEXIOREQ hIoReq = NULL;
|
---|
3560 |
|
---|
3561 | int rc = pAhciPortR3->pDrvMediaEx->pfnIoReqAlloc(pAhciPortR3->pDrvMediaEx, &hIoReq, (void **)&pAhciReq,
|
---|
3562 | uTag, PDMIMEDIAEX_F_SUSPEND_ON_RECOVERABLE_ERR);
|
---|
3563 | if (RT_SUCCESS(rc))
|
---|
3564 | {
|
---|
3565 | pAhciReq->hIoReq = hIoReq;
|
---|
3566 | pAhciReq->fMapped = false;
|
---|
3567 | }
|
---|
3568 | else
|
---|
3569 | pAhciReq = NULL;
|
---|
3570 | return pAhciReq;
|
---|
3571 | }
|
---|
3572 |
|
---|
3573 | /**
|
---|
3574 | * Frees a given AHCI request structure.
|
---|
3575 | *
|
---|
3576 | * @param pAhciPortR3 The AHCI port, ring-3 bits.
|
---|
3577 | * @param pAhciReq The request to free.
|
---|
3578 | */
|
---|
3579 | static void ahciR3ReqFree(PAHCIPORTR3 pAhciPortR3, PAHCIREQ pAhciReq)
|
---|
3580 | {
|
---|
3581 | if ( pAhciReq
|
---|
3582 | && !(pAhciReq->fFlags & AHCI_REQ_IS_ON_STACK))
|
---|
3583 | {
|
---|
3584 | int rc = pAhciPortR3->pDrvMediaEx->pfnIoReqFree(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq);
|
---|
3585 | AssertRC(rc);
|
---|
3586 | }
|
---|
3587 | }
|
---|
3588 |
|
---|
3589 | /**
|
---|
3590 | * Complete a data transfer task by freeing all occupied resources
|
---|
3591 | * and notifying the guest.
|
---|
3592 | *
|
---|
3593 | * @returns Flag whether the given request was canceled inbetween;
|
---|
3594 | *
|
---|
3595 | * @param pDevIns The device instance.
|
---|
3596 | * @param pThis The shared AHCI state.
|
---|
3597 | * @param pThisCC The ring-3 AHCI state.
|
---|
3598 | * @param pAhciPort Pointer to the port where to request completed, shared bits.
|
---|
3599 | * @param pAhciPortR3 Pointer to the port where to request completed, ring-3 bits.
|
---|
3600 | * @param pAhciReq Pointer to the task which finished.
|
---|
3601 | * @param rcReq IPRT status code of the completed request.
|
---|
3602 | */
|
---|
3603 | static bool ahciR3TransferComplete(PPDMDEVINS pDevIns, PAHCI pThis, PAHCICC pThisCC,
|
---|
3604 | PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3, PAHCIREQ pAhciReq, int rcReq)
|
---|
3605 | {
|
---|
3606 | bool fCanceled = false;
|
---|
3607 |
|
---|
3608 | LogFlowFunc(("pAhciPort=%p pAhciReq=%p rcReq=%d\n",
|
---|
3609 | pAhciPort, pAhciReq, rcReq));
|
---|
3610 |
|
---|
3611 | VBOXDD_AHCI_REQ_COMPLETED(pAhciReq, rcReq, pAhciReq->uOffset, pAhciReq->cbTransfer);
|
---|
3612 |
|
---|
3613 | if (pAhciReq->fMapped)
|
---|
3614 | PDMDevHlpPhysReleasePageMappingLock(pDevIns, &pAhciReq->PgLck);
|
---|
3615 |
|
---|
3616 | if (rcReq != VERR_PDM_MEDIAEX_IOREQ_CANCELED)
|
---|
3617 | {
|
---|
3618 | if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ)
|
---|
3619 | pAhciPort->Led.Actual.s.fReading = 0;
|
---|
3620 | else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_WRITE)
|
---|
3621 | pAhciPort->Led.Actual.s.fWriting = 0;
|
---|
3622 | else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
|
---|
3623 | pAhciPort->Led.Actual.s.fWriting = 0;
|
---|
3624 | else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
|
---|
3625 | {
|
---|
3626 | pAhciPort->Led.Actual.s.fWriting = 0;
|
---|
3627 | pAhciPort->Led.Actual.s.fReading = 0;
|
---|
3628 | }
|
---|
3629 |
|
---|
3630 | if (RT_FAILURE(rcReq))
|
---|
3631 | {
|
---|
3632 | /* Log the error. */
|
---|
3633 | if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
|
---|
3634 | {
|
---|
3635 | if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
|
---|
3636 | LogRel(("AHCI#%uP%u: Flush returned rc=%Rrc\n",
|
---|
3637 | pDevIns->iInstance, pAhciPort->iLUN, rcReq));
|
---|
3638 | else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
|
---|
3639 | LogRel(("AHCI#%uP%u: Trim returned rc=%Rrc\n",
|
---|
3640 | pDevIns->iInstance, pAhciPort->iLUN, rcReq));
|
---|
3641 | else
|
---|
3642 | LogRel(("AHCI#%uP%u: %s at offset %llu (%zu bytes left) returned rc=%Rrc\n",
|
---|
3643 | pDevIns->iInstance, pAhciPort->iLUN,
|
---|
3644 | pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ
|
---|
3645 | ? "Read"
|
---|
3646 | : "Write",
|
---|
3647 | pAhciReq->uOffset,
|
---|
3648 | pAhciReq->cbTransfer, rcReq));
|
---|
3649 | }
|
---|
3650 |
|
---|
3651 | ahciReqSetStatus(pAhciReq, ID_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
3652 | /*
|
---|
3653 | * We have to duplicate the request here as the underlying I/O
|
---|
3654 | * request will be freed later.
|
---|
3655 | */
|
---|
3656 | PAHCIREQ pReqDup = (PAHCIREQ)RTMemDup(pAhciReq, sizeof(AHCIREQ));
|
---|
3657 | if ( pReqDup
|
---|
3658 | && !ASMAtomicCmpXchgPtr(&pAhciPortR3->pTaskErr, pReqDup, NULL))
|
---|
3659 | RTMemFree(pReqDup);
|
---|
3660 | }
|
---|
3661 | else
|
---|
3662 | {
|
---|
3663 | /* Status will be set already for non I/O requests. */
|
---|
3664 | if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_SCSI)
|
---|
3665 | {
|
---|
3666 | if (pAhciReq->u8ScsiSts == SCSI_STATUS_OK)
|
---|
3667 | {
|
---|
3668 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
3669 | pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
|
---|
3670 | | ((pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST) ? ATAPI_INT_REASON_IO : 0)
|
---|
3671 | | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
|
---|
3672 | }
|
---|
3673 | else
|
---|
3674 | {
|
---|
3675 | ahciReqSetStatus(pAhciReq, pAhciPort->abATAPISense[2] << 4, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
3676 | pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
|
---|
3677 | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
|
---|
3678 | pAhciReq->cbTransfer = 0;
|
---|
3679 | LogFlowFunc(("SCSI request completed with %u status\n", pAhciReq->u8ScsiSts));
|
---|
3680 | }
|
---|
3681 | }
|
---|
3682 | else if (pAhciReq->enmType != PDMMEDIAEXIOREQTYPE_INVALID)
|
---|
3683 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
3684 |
|
---|
3685 | /* Write updated command header into memory of the guest. */
|
---|
3686 | uint32_t u32PRDBC = 0;
|
---|
3687 | if (pAhciReq->enmType != PDMMEDIAEXIOREQTYPE_INVALID)
|
---|
3688 | {
|
---|
3689 | size_t cbXfer = 0;
|
---|
3690 | int rc = pAhciPortR3->pDrvMediaEx->pfnIoReqQueryXferSize(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq, &cbXfer);
|
---|
3691 | AssertRC(rc);
|
---|
3692 | u32PRDBC = (uint32_t)RT_MIN(cbXfer, pAhciReq->cbTransfer);
|
---|
3693 | }
|
---|
3694 | else
|
---|
3695 | u32PRDBC = (uint32_t)pAhciReq->cbTransfer;
|
---|
3696 |
|
---|
3697 | PDMDevHlpPCIPhysWriteMeta(pDevIns, pAhciReq->GCPhysCmdHdrAddr + RT_UOFFSETOF(CmdHdr, u32PRDBC),
|
---|
3698 | &u32PRDBC, sizeof(u32PRDBC));
|
---|
3699 |
|
---|
3700 | if (pAhciReq->fFlags & AHCI_REQ_OVERFLOW)
|
---|
3701 | {
|
---|
3702 | /*
|
---|
3703 | * The guest tried to transfer more data than there is space in the buffer.
|
---|
3704 | * Terminate task and set the overflow bit.
|
---|
3705 | */
|
---|
3706 | /* Notify the guest. */
|
---|
3707 | ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_OFS);
|
---|
3708 | if (pAhciPort->regIE & AHCI_PORT_IE_OFE)
|
---|
3709 | ahciHbaSetInterrupt(pDevIns, pThis, pAhciPort->iLUN, VERR_IGNORED);
|
---|
3710 | }
|
---|
3711 | }
|
---|
3712 |
|
---|
3713 | /*
|
---|
3714 | * Make a copy of the required data now and free the request. Otherwise the guest
|
---|
3715 | * might issue a new request with the same tag and we run into a conflict when allocating
|
---|
3716 | * a new request with the same tag later on.
|
---|
3717 | */
|
---|
3718 | uint32_t fFlags = pAhciReq->fFlags;
|
---|
3719 | uint32_t uTag = pAhciReq->uTag;
|
---|
3720 | size_t cbTransfer = pAhciReq->cbTransfer;
|
---|
3721 | bool fRead = pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ;
|
---|
3722 | uint8_t cmdFis[AHCI_CMDFIS_TYPE_H2D_SIZE];
|
---|
3723 | memcpy(&cmdFis[0], &pAhciReq->cmdFis[0], sizeof(cmdFis));
|
---|
3724 |
|
---|
3725 | ahciR3ReqFree(pAhciPortR3, pAhciReq);
|
---|
3726 |
|
---|
3727 | /* Post a PIO setup FIS first if this is a PIO command which transfers data. */
|
---|
3728 | if (fFlags & AHCI_REQ_PIO_DATA)
|
---|
3729 | ahciSendPioSetupFis(pDevIns, pThis, pAhciPort, cbTransfer, &cmdFis[0], fRead, false /* fInterrupt */);
|
---|
3730 |
|
---|
3731 | if (fFlags & AHCI_REQ_CLEAR_SACT)
|
---|
3732 | {
|
---|
3733 | if (RT_SUCCESS(rcReq) && !ASMAtomicReadPtrT(&pAhciPortR3->pTaskErr, PAHCIREQ))
|
---|
3734 | ASMAtomicOrU32(&pAhciPort->u32QueuedTasksFinished, RT_BIT_32(uTag));
|
---|
3735 | }
|
---|
3736 |
|
---|
3737 | if (fFlags & AHCI_REQ_IS_QUEUED)
|
---|
3738 | {
|
---|
3739 | /*
|
---|
3740 | * Always raise an interrupt after task completion; delaying
|
---|
3741 | * this (interrupt coalescing) increases latency and has a significant
|
---|
3742 | * impact on performance (see @bugref{5071})
|
---|
3743 | */
|
---|
3744 | ahciSendSDBFis(pDevIns, pThis, pAhciPort, pAhciPortR3, 0, true);
|
---|
3745 | }
|
---|
3746 | else
|
---|
3747 | ahciSendD2HFis(pDevIns, pThis, pAhciPort, uTag, &cmdFis[0], true);
|
---|
3748 | }
|
---|
3749 | else
|
---|
3750 | {
|
---|
3751 | /*
|
---|
3752 | * Task was canceled, do the cleanup but DO NOT access the guest memory!
|
---|
3753 | * The guest might use it for other things now because it doesn't know about that task anymore.
|
---|
3754 | */
|
---|
3755 | fCanceled = true;
|
---|
3756 |
|
---|
3757 | /* Leave a log message about the canceled request. */
|
---|
3758 | if (pAhciPort->cErrors++ < MAX_LOG_REL_ERRORS)
|
---|
3759 | {
|
---|
3760 | if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
|
---|
3761 | LogRel(("AHCI#%uP%u: Canceled flush returned rc=%Rrc\n",
|
---|
3762 | pDevIns->iInstance, pAhciPort->iLUN, rcReq));
|
---|
3763 | else if (pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
|
---|
3764 | LogRel(("AHCI#%uP%u: Canceled trim returned rc=%Rrc\n",
|
---|
3765 | pDevIns->iInstance,pAhciPort->iLUN, rcReq));
|
---|
3766 | else
|
---|
3767 | LogRel(("AHCI#%uP%u: Canceled %s at offset %llu (%zu bytes left) returned rc=%Rrc\n",
|
---|
3768 | pDevIns->iInstance, pAhciPort->iLUN,
|
---|
3769 | pAhciReq->enmType == PDMMEDIAEXIOREQTYPE_READ
|
---|
3770 | ? "read"
|
---|
3771 | : "write",
|
---|
3772 | pAhciReq->uOffset,
|
---|
3773 | pAhciReq->cbTransfer, rcReq));
|
---|
3774 | }
|
---|
3775 |
|
---|
3776 | ahciR3ReqFree(pAhciPortR3, pAhciReq);
|
---|
3777 | }
|
---|
3778 |
|
---|
3779 | /*
|
---|
3780 | * Decrement the active task counter as the last step or we might run into a
|
---|
3781 | * hang during power off otherwise (see @bugref{7859}).
|
---|
3782 | * Before it could happen that we signal PDM that we are done while we still have to
|
---|
3783 | * copy the data to the guest but EMT might be busy destroying the driver chains
|
---|
3784 | * below us while we have to delegate copying data to EMT instead of doing it
|
---|
3785 | * on this thread.
|
---|
3786 | */
|
---|
3787 | ASMAtomicDecU32(&pAhciPort->cTasksActive);
|
---|
3788 |
|
---|
3789 | if (pAhciPort->cTasksActive == 0 && pThisCC->fSignalIdle)
|
---|
3790 | PDMDevHlpAsyncNotificationCompleted(pDevIns);
|
---|
3791 |
|
---|
3792 | return fCanceled;
|
---|
3793 | }
|
---|
3794 |
|
---|
3795 | /**
|
---|
3796 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyFromBuf}
|
---|
3797 | */
|
---|
3798 | static DECLCALLBACK(int) ahciR3IoReqCopyFromBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
|
---|
3799 | void *pvIoReqAlloc, uint32_t offDst, PRTSGBUF pSgBuf,
|
---|
3800 | size_t cbCopy)
|
---|
3801 | {
|
---|
3802 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3803 | int rc = VINF_SUCCESS;
|
---|
3804 | PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
|
---|
3805 | RT_NOREF(hIoReq);
|
---|
3806 |
|
---|
3807 | ahciR3CopySgBufToPrdtl(pAhciPortR3->pDevIns, pIoReq, pSgBuf, offDst, cbCopy);
|
---|
3808 |
|
---|
3809 | if (pIoReq->fFlags & AHCI_REQ_OVERFLOW)
|
---|
3810 | rc = VERR_PDM_MEDIAEX_IOBUF_OVERFLOW;
|
---|
3811 |
|
---|
3812 | return rc;
|
---|
3813 | }
|
---|
3814 |
|
---|
3815 | /**
|
---|
3816 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCopyToBuf}
|
---|
3817 | */
|
---|
3818 | static DECLCALLBACK(int) ahciR3IoReqCopyToBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
|
---|
3819 | void *pvIoReqAlloc, uint32_t offSrc, PRTSGBUF pSgBuf,
|
---|
3820 | size_t cbCopy)
|
---|
3821 | {
|
---|
3822 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3823 | int rc = VINF_SUCCESS;
|
---|
3824 | PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
|
---|
3825 | RT_NOREF(hIoReq);
|
---|
3826 |
|
---|
3827 | ahciR3CopySgBufFromPrdtl(pAhciPortR3->pDevIns, pIoReq, pSgBuf, offSrc, cbCopy);
|
---|
3828 | if (pIoReq->fFlags & AHCI_REQ_OVERFLOW)
|
---|
3829 | rc = VERR_PDM_MEDIAEX_IOBUF_UNDERRUN;
|
---|
3830 |
|
---|
3831 | return rc;
|
---|
3832 | }
|
---|
3833 |
|
---|
3834 | /**
|
---|
3835 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqQueryBuf}
|
---|
3836 | */
|
---|
3837 | static DECLCALLBACK(int) ahciR3IoReqQueryBuf(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
|
---|
3838 | void *pvIoReqAlloc, void **ppvBuf, size_t *pcbBuf)
|
---|
3839 | {
|
---|
3840 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3841 | PPDMDEVINS pDevIns = pAhciPortR3->pDevIns;
|
---|
3842 | PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
|
---|
3843 | int rc = VERR_NOT_SUPPORTED;
|
---|
3844 | RT_NOREF(hIoReq);
|
---|
3845 |
|
---|
3846 | /* Only allow single 4KB page aligned buffers at the moment. */
|
---|
3847 | if ( pIoReq->cPrdtlEntries == 1
|
---|
3848 | && pIoReq->cbTransfer == _4K)
|
---|
3849 | {
|
---|
3850 | RTGCPHYS GCPhysPrdt = pIoReq->GCPhysPrdtl;
|
---|
3851 | SGLEntry PrdtEntry;
|
---|
3852 |
|
---|
3853 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysPrdt, &PrdtEntry, sizeof(SGLEntry));
|
---|
3854 |
|
---|
3855 | RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(PrdtEntry.u32DBAUp, PrdtEntry.u32DBA);
|
---|
3856 | uint32_t cbData = (PrdtEntry.u32DescInf & SGLENTRY_DESCINF_DBC) + 1;
|
---|
3857 |
|
---|
3858 | if ( cbData >= _4K
|
---|
3859 | && !(GCPhysAddrDataBase & (_4K - 1)))
|
---|
3860 | {
|
---|
3861 | rc = PDMDevHlpPCIPhysGCPhys2CCPtr(pDevIns, NULL /* pPciDev */, GCPhysAddrDataBase, 0, ppvBuf, &pIoReq->PgLck);
|
---|
3862 | if (RT_SUCCESS(rc))
|
---|
3863 | {
|
---|
3864 | pIoReq->fMapped = true;
|
---|
3865 | *pcbBuf = cbData;
|
---|
3866 | }
|
---|
3867 | else
|
---|
3868 | rc = VERR_NOT_SUPPORTED;
|
---|
3869 | }
|
---|
3870 | }
|
---|
3871 |
|
---|
3872 | return rc;
|
---|
3873 | }
|
---|
3874 |
|
---|
3875 | /**
|
---|
3876 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqQueryDiscardRanges}
|
---|
3877 | */
|
---|
3878 | static DECLCALLBACK(int) ahciR3IoReqQueryDiscardRanges(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
|
---|
3879 | void *pvIoReqAlloc, uint32_t idxRangeStart,
|
---|
3880 | uint32_t cRanges, PRTRANGE paRanges,
|
---|
3881 | uint32_t *pcRanges)
|
---|
3882 | {
|
---|
3883 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3884 | PPDMDEVINS pDevIns = pAhciPortR3->pDevIns;
|
---|
3885 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
3886 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
3887 | PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
|
---|
3888 | RT_NOREF(hIoReq);
|
---|
3889 |
|
---|
3890 | return ahciTrimRangesCreate(pDevIns, pAhciPort, pIoReq, idxRangeStart, paRanges, cRanges, pcRanges);
|
---|
3891 | }
|
---|
3892 |
|
---|
3893 | /**
|
---|
3894 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqCompleteNotify}
|
---|
3895 | */
|
---|
3896 | static DECLCALLBACK(int) ahciR3IoReqCompleteNotify(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
|
---|
3897 | void *pvIoReqAlloc, int rcReq)
|
---|
3898 | {
|
---|
3899 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3900 | PPDMDEVINS pDevIns = pAhciPortR3->pDevIns;
|
---|
3901 | PAHCIR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAHCICC);
|
---|
3902 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
3903 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
3904 | PAHCIREQ pIoReq = (PAHCIREQ)pvIoReqAlloc;
|
---|
3905 | RT_NOREF(hIoReq);
|
---|
3906 |
|
---|
3907 | ahciR3TransferComplete(pDevIns, pThis, pThisCC, pAhciPort, pAhciPortR3, pIoReq, rcReq);
|
---|
3908 | return VINF_SUCCESS;
|
---|
3909 | }
|
---|
3910 |
|
---|
3911 | /**
|
---|
3912 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnIoReqStateChanged}
|
---|
3913 | */
|
---|
3914 | static DECLCALLBACK(void) ahciR3IoReqStateChanged(PPDMIMEDIAEXPORT pInterface, PDMMEDIAEXIOREQ hIoReq,
|
---|
3915 | void *pvIoReqAlloc, PDMMEDIAEXIOREQSTATE enmState)
|
---|
3916 | {
|
---|
3917 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3918 | PPDMDEVINS pDevIns = pAhciPortR3->pDevIns;
|
---|
3919 | PAHCIR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAHCICC);
|
---|
3920 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
3921 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
3922 | RT_NOREF(hIoReq, pvIoReqAlloc);
|
---|
3923 |
|
---|
3924 | switch (enmState)
|
---|
3925 | {
|
---|
3926 | case PDMMEDIAEXIOREQSTATE_SUSPENDED:
|
---|
3927 | {
|
---|
3928 | /* Make sure the request is not accounted for so the VM can suspend successfully. */
|
---|
3929 | uint32_t cTasksActive = ASMAtomicDecU32(&pAhciPort->cTasksActive);
|
---|
3930 | if (!cTasksActive && pThisCC->fSignalIdle)
|
---|
3931 | PDMDevHlpAsyncNotificationCompleted(pDevIns);
|
---|
3932 | break;
|
---|
3933 | }
|
---|
3934 | case PDMMEDIAEXIOREQSTATE_ACTIVE:
|
---|
3935 | /* Make sure the request is accounted for so the VM suspends only when the request is complete. */
|
---|
3936 | ASMAtomicIncU32(&pAhciPort->cTasksActive);
|
---|
3937 | break;
|
---|
3938 | default:
|
---|
3939 | AssertMsgFailed(("Invalid request state given %u\n", enmState));
|
---|
3940 | }
|
---|
3941 | }
|
---|
3942 |
|
---|
3943 | /**
|
---|
3944 | * @interface_method_impl{PDMIMEDIAEXPORT,pfnMediumEjected}
|
---|
3945 | */
|
---|
3946 | static DECLCALLBACK(void) ahciR3MediumEjected(PPDMIMEDIAEXPORT pInterface)
|
---|
3947 | {
|
---|
3948 | PAHCIPORTR3 pAhciPortR3 = RT_FROM_MEMBER(pInterface, AHCIPORTR3, IMediaExPort);
|
---|
3949 | PPDMDEVINS pDevIns = pAhciPortR3->pDevIns;
|
---|
3950 | PAHCIR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAHCICC);
|
---|
3951 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
3952 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
3953 |
|
---|
3954 | if (pThisCC->pMediaNotify)
|
---|
3955 | {
|
---|
3956 | int rc = PDMDevHlpVMReqCallNoWait(pDevIns, VMCPUID_ANY,
|
---|
3957 | (PFNRT)pThisCC->pMediaNotify->pfnEjected, 2,
|
---|
3958 | pThisCC->pMediaNotify, pAhciPort->iLUN);
|
---|
3959 | AssertRC(rc);
|
---|
3960 | }
|
---|
3961 | }
|
---|
3962 |
|
---|
3963 | /**
|
---|
3964 | * Process an non read/write ATA command.
|
---|
3965 | *
|
---|
3966 | * @returns The direction of the data transfer
|
---|
3967 | * @param pDevIns The device instance.
|
---|
3968 | * @param pThis The shared AHCI state.
|
---|
3969 | * @param pAhciPort The AHCI port of the request, shared bits.
|
---|
3970 | * @param pAhciPortR3 The AHCI port of the request, ring-3 bits.
|
---|
3971 | * @param pAhciReq The AHCI request state.
|
---|
3972 | * @param pCmdFis Pointer to the command FIS.
|
---|
3973 | */
|
---|
3974 | static PDMMEDIAEXIOREQTYPE ahciProcessCmd(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3,
|
---|
3975 | PAHCIREQ pAhciReq, uint8_t *pCmdFis)
|
---|
3976 | {
|
---|
3977 | PDMMEDIAEXIOREQTYPE enmType = PDMMEDIAEXIOREQTYPE_INVALID;
|
---|
3978 | bool fLBA48 = false;
|
---|
3979 |
|
---|
3980 | AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
|
---|
3981 |
|
---|
3982 | pAhciReq->cbTransfer = 0;
|
---|
3983 |
|
---|
3984 | switch (pCmdFis[AHCI_CMDFIS_CMD])
|
---|
3985 | {
|
---|
3986 | case ATA_IDENTIFY_DEVICE:
|
---|
3987 | {
|
---|
3988 | if (pAhciPortR3->pDrvMedia && !pAhciPort->fATAPI)
|
---|
3989 | {
|
---|
3990 | uint16_t u16Temp[256];
|
---|
3991 |
|
---|
3992 | /* Fill the buffer. */
|
---|
3993 | ahciIdentifySS(pThis, pAhciPort, pAhciPortR3, u16Temp);
|
---|
3994 |
|
---|
3995 | /* Copy the buffer. */
|
---|
3996 | size_t cbCopied = ahciR3CopyBufferToPrdtl(pDevIns, pAhciReq, &u16Temp[0], sizeof(u16Temp), 0 /* cbSkip */);
|
---|
3997 |
|
---|
3998 | pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
|
---|
3999 | pAhciReq->cbTransfer = cbCopied;
|
---|
4000 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
4001 | }
|
---|
4002 | else
|
---|
4003 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_SEEK | ATA_STAT_ERR);
|
---|
4004 | break;
|
---|
4005 | }
|
---|
4006 | case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
|
---|
4007 | case ATA_READ_NATIVE_MAX_ADDRESS:
|
---|
4008 | break;
|
---|
4009 | case ATA_SET_FEATURES:
|
---|
4010 | {
|
---|
4011 | switch (pCmdFis[AHCI_CMDFIS_FET])
|
---|
4012 | {
|
---|
4013 | case 0x02: /* write cache enable */
|
---|
4014 | case 0xaa: /* read look-ahead enable */
|
---|
4015 | case 0x55: /* read look-ahead disable */
|
---|
4016 | case 0xcc: /* reverting to power-on defaults enable */
|
---|
4017 | case 0x66: /* reverting to power-on defaults disable */
|
---|
4018 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
4019 | break;
|
---|
4020 | case 0x82: /* write cache disable */
|
---|
4021 | enmType = PDMMEDIAEXIOREQTYPE_FLUSH;
|
---|
4022 | break;
|
---|
4023 | case 0x03:
|
---|
4024 | {
|
---|
4025 | /* set transfer mode */
|
---|
4026 | Log2(("%s: transfer mode %#04x\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
|
---|
4027 | switch (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8)
|
---|
4028 | {
|
---|
4029 | case 0x00: /* PIO default */
|
---|
4030 | case 0x08: /* PIO mode */
|
---|
4031 | break;
|
---|
4032 | case ATA_MODE_MDMA: /* MDMA mode */
|
---|
4033 | pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
|
---|
4034 | break;
|
---|
4035 | case ATA_MODE_UDMA: /* UDMA mode */
|
---|
4036 | pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
|
---|
4037 | break;
|
---|
4038 | }
|
---|
4039 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
4040 | break;
|
---|
4041 | }
|
---|
4042 | default:
|
---|
4043 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4044 | }
|
---|
4045 | break;
|
---|
4046 | }
|
---|
4047 | case ATA_DEVICE_RESET:
|
---|
4048 | {
|
---|
4049 | if (!pAhciPort->fATAPI)
|
---|
4050 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4051 | else
|
---|
4052 | {
|
---|
4053 | /* Reset the device. */
|
---|
4054 | ahciDeviceReset(pDevIns, pThis, pAhciPort, pAhciReq);
|
---|
4055 | }
|
---|
4056 | break;
|
---|
4057 | }
|
---|
4058 | case ATA_FLUSH_CACHE_EXT:
|
---|
4059 | case ATA_FLUSH_CACHE:
|
---|
4060 | enmType = PDMMEDIAEXIOREQTYPE_FLUSH;
|
---|
4061 | break;
|
---|
4062 | case ATA_PACKET:
|
---|
4063 | if (!pAhciPort->fATAPI)
|
---|
4064 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4065 | else
|
---|
4066 | enmType = PDMMEDIAEXIOREQTYPE_SCSI;
|
---|
4067 | break;
|
---|
4068 | case ATA_IDENTIFY_PACKET_DEVICE:
|
---|
4069 | if (!pAhciPort->fATAPI)
|
---|
4070 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4071 | else
|
---|
4072 | {
|
---|
4073 | size_t cbData;
|
---|
4074 | ahciR3AtapiIdentify(pDevIns, pAhciReq, pAhciPort, 512, &cbData);
|
---|
4075 |
|
---|
4076 | pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
|
---|
4077 | pAhciReq->cbTransfer = cbData;
|
---|
4078 | pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
|
---|
4079 | | ((pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST) ? ATAPI_INT_REASON_IO : 0)
|
---|
4080 | | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
|
---|
4081 |
|
---|
4082 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
4083 | }
|
---|
4084 | break;
|
---|
4085 | case ATA_SET_MULTIPLE_MODE:
|
---|
4086 | if ( pCmdFis[AHCI_CMDFIS_SECTC] != 0
|
---|
4087 | && ( pCmdFis[AHCI_CMDFIS_SECTC] > ATA_MAX_MULT_SECTORS
|
---|
4088 | || (pCmdFis[AHCI_CMDFIS_SECTC] & (pCmdFis[AHCI_CMDFIS_SECTC] - 1)) != 0))
|
---|
4089 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4090 | else
|
---|
4091 | {
|
---|
4092 | Log2(("%s: set multi sector count to %d\n", __FUNCTION__, pCmdFis[AHCI_CMDFIS_SECTC]));
|
---|
4093 | pAhciPort->cMultSectors = pCmdFis[AHCI_CMDFIS_SECTC];
|
---|
4094 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
4095 | }
|
---|
4096 | break;
|
---|
4097 | case ATA_STANDBY_IMMEDIATE:
|
---|
4098 | break; /* Do nothing. */
|
---|
4099 | case ATA_CHECK_POWER_MODE:
|
---|
4100 | pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] = 0xff; /* drive active or idle */
|
---|
4101 | RT_FALL_THRU();
|
---|
4102 | case ATA_INITIALIZE_DEVICE_PARAMETERS:
|
---|
4103 | case ATA_IDLE_IMMEDIATE:
|
---|
4104 | case ATA_RECALIBRATE:
|
---|
4105 | case ATA_NOP:
|
---|
4106 | case ATA_READ_VERIFY_SECTORS_EXT:
|
---|
4107 | case ATA_READ_VERIFY_SECTORS:
|
---|
4108 | case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
|
---|
4109 | case ATA_SLEEP:
|
---|
4110 | ahciReqSetStatus(pAhciReq, 0, ATA_STAT_READY | ATA_STAT_SEEK);
|
---|
4111 | break;
|
---|
4112 | case ATA_READ_DMA_EXT:
|
---|
4113 | fLBA48 = true;
|
---|
4114 | RT_FALL_THRU();
|
---|
4115 | case ATA_READ_DMA:
|
---|
4116 | {
|
---|
4117 | pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
|
---|
4118 | pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
|
---|
4119 | enmType = PDMMEDIAEXIOREQTYPE_READ;
|
---|
4120 | break;
|
---|
4121 | }
|
---|
4122 | case ATA_WRITE_DMA_EXT:
|
---|
4123 | fLBA48 = true;
|
---|
4124 | RT_FALL_THRU();
|
---|
4125 | case ATA_WRITE_DMA:
|
---|
4126 | {
|
---|
4127 | pAhciReq->cbTransfer = ahciGetNSectors(pCmdFis, fLBA48) * pAhciPort->cbSector;
|
---|
4128 | pAhciReq->uOffset = ahciGetSector(pAhciPort, pCmdFis, fLBA48) * pAhciPort->cbSector;
|
---|
4129 | enmType = PDMMEDIAEXIOREQTYPE_WRITE;
|
---|
4130 | break;
|
---|
4131 | }
|
---|
4132 | case ATA_READ_FPDMA_QUEUED:
|
---|
4133 | {
|
---|
4134 | pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
|
---|
4135 | pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
|
---|
4136 | pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
|
---|
4137 | enmType = PDMMEDIAEXIOREQTYPE_READ;
|
---|
4138 | break;
|
---|
4139 | }
|
---|
4140 | case ATA_WRITE_FPDMA_QUEUED:
|
---|
4141 | {
|
---|
4142 | pAhciReq->cbTransfer = ahciGetNSectorsQueued(pCmdFis) * pAhciPort->cbSector;
|
---|
4143 | pAhciReq->uOffset = ahciGetSectorQueued(pCmdFis) * pAhciPort->cbSector;
|
---|
4144 | pAhciReq->fFlags |= AHCI_REQ_IS_QUEUED;
|
---|
4145 | enmType = PDMMEDIAEXIOREQTYPE_WRITE;
|
---|
4146 | break;
|
---|
4147 | }
|
---|
4148 | case ATA_READ_LOG_EXT:
|
---|
4149 | {
|
---|
4150 | size_t cbLogRead = ((pCmdFis[AHCI_CMDFIS_SECTCEXP] << 8) | pCmdFis[AHCI_CMDFIS_SECTC]) * 512;
|
---|
4151 | unsigned offLogRead = ((pCmdFis[AHCI_CMDFIS_CYLLEXP] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * 512;
|
---|
4152 | unsigned iPage = pCmdFis[AHCI_CMDFIS_SECTN];
|
---|
4153 |
|
---|
4154 | LogFlow(("Trying to read %zu bytes starting at offset %u from page %u\n", cbLogRead, offLogRead, iPage));
|
---|
4155 |
|
---|
4156 | uint8_t aBuf[512];
|
---|
4157 |
|
---|
4158 | memset(aBuf, 0, sizeof(aBuf));
|
---|
4159 |
|
---|
4160 | if (offLogRead + cbLogRead <= sizeof(aBuf))
|
---|
4161 | {
|
---|
4162 | switch (iPage)
|
---|
4163 | {
|
---|
4164 | case 0x10:
|
---|
4165 | {
|
---|
4166 | LogFlow(("Reading error page\n"));
|
---|
4167 | PAHCIREQ pTaskErr = ASMAtomicXchgPtrT(&pAhciPortR3->pTaskErr, NULL, PAHCIREQ);
|
---|
4168 | if (pTaskErr)
|
---|
4169 | {
|
---|
4170 | aBuf[0] = (pTaskErr->fFlags & AHCI_REQ_IS_QUEUED) ? pTaskErr->uTag : (1 << 7);
|
---|
4171 | aBuf[2] = pTaskErr->cmdFis[AHCI_CMDFIS_STS];
|
---|
4172 | aBuf[3] = pTaskErr->cmdFis[AHCI_CMDFIS_ERR];
|
---|
4173 | aBuf[4] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTN];
|
---|
4174 | aBuf[5] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLL];
|
---|
4175 | aBuf[6] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLH];
|
---|
4176 | aBuf[7] = pTaskErr->cmdFis[AHCI_CMDFIS_HEAD];
|
---|
4177 | aBuf[8] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTNEXP];
|
---|
4178 | aBuf[9] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLLEXP];
|
---|
4179 | aBuf[10] = pTaskErr->cmdFis[AHCI_CMDFIS_CYLHEXP];
|
---|
4180 | aBuf[12] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTC];
|
---|
4181 | aBuf[13] = pTaskErr->cmdFis[AHCI_CMDFIS_SECTCEXP];
|
---|
4182 |
|
---|
4183 | /* Calculate checksum */
|
---|
4184 | uint8_t uChkSum = 0;
|
---|
4185 | for (unsigned i = 0; i < RT_ELEMENTS(aBuf)-1; i++)
|
---|
4186 | uChkSum += aBuf[i];
|
---|
4187 |
|
---|
4188 | aBuf[511] = (uint8_t)-(int8_t)uChkSum;
|
---|
4189 |
|
---|
4190 | /* Finally free the error task state structure because it is completely unused now. */
|
---|
4191 | RTMemFree(pTaskErr);
|
---|
4192 | }
|
---|
4193 |
|
---|
4194 | /*
|
---|
4195 | * Reading this log page results in an abort of all outstanding commands
|
---|
4196 | * and clearing the SActive register and TaskFile register.
|
---|
4197 | *
|
---|
4198 | * See SATA2 1.2 spec chapter 4.2.3.4
|
---|
4199 | */
|
---|
4200 | bool fAbortedAll = ahciR3CancelActiveTasks(pAhciPortR3);
|
---|
4201 | Assert(fAbortedAll); NOREF(fAbortedAll);
|
---|
4202 | ahciSendSDBFis(pDevIns, pThis, pAhciPort, pAhciPortR3, UINT32_C(0xffffffff), true);
|
---|
4203 |
|
---|
4204 | break;
|
---|
4205 | }
|
---|
4206 | }
|
---|
4207 |
|
---|
4208 | /* Copy the buffer. */
|
---|
4209 | size_t cbCopied = ahciR3CopyBufferToPrdtl(pDevIns, pAhciReq, &aBuf[offLogRead], cbLogRead, 0 /* cbSkip */);
|
---|
4210 |
|
---|
4211 | pAhciReq->fFlags |= AHCI_REQ_PIO_DATA;
|
---|
4212 | pAhciReq->cbTransfer = cbCopied;
|
---|
4213 | }
|
---|
4214 |
|
---|
4215 | break;
|
---|
4216 | }
|
---|
4217 | case ATA_DATA_SET_MANAGEMENT:
|
---|
4218 | {
|
---|
4219 | if (pAhciPort->fTrimEnabled)
|
---|
4220 | {
|
---|
4221 | /* Check that the trim bit is set and all other bits are 0. */
|
---|
4222 | if ( !(pAhciReq->cmdFis[AHCI_CMDFIS_FET] & UINT16_C(0x01))
|
---|
4223 | || (pAhciReq->cmdFis[AHCI_CMDFIS_FET] & ~UINT16_C(0x1)))
|
---|
4224 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4225 | else
|
---|
4226 | enmType = PDMMEDIAEXIOREQTYPE_DISCARD;
|
---|
4227 | break;
|
---|
4228 | }
|
---|
4229 | /* else: fall through and report error to the guest. */
|
---|
4230 | }
|
---|
4231 | RT_FALL_THRU();
|
---|
4232 | /* All not implemented commands go below. */
|
---|
4233 | case ATA_SECURITY_FREEZE_LOCK:
|
---|
4234 | case ATA_SMART:
|
---|
4235 | case ATA_NV_CACHE:
|
---|
4236 | case ATA_IDLE:
|
---|
4237 | case ATA_TRUSTED_RECEIVE_DMA: /* Windows 8+ */
|
---|
4238 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4239 | break;
|
---|
4240 | default: /* For debugging purposes. */
|
---|
4241 | AssertMsgFailed(("Unknown command issued (%#x)\n", pCmdFis[AHCI_CMDFIS_CMD]));
|
---|
4242 | ahciReqSetStatus(pAhciReq, ABRT_ERR, ATA_STAT_READY | ATA_STAT_ERR);
|
---|
4243 | }
|
---|
4244 |
|
---|
4245 | return enmType;
|
---|
4246 | }
|
---|
4247 |
|
---|
4248 | /**
|
---|
4249 | * Retrieve a command FIS from guest memory.
|
---|
4250 | *
|
---|
4251 | * @returns whether the H2D FIS was successfully read from the guest memory.
|
---|
4252 | * @param pDevIns The device instance.
|
---|
4253 | * @param pThis The shared AHCI state.
|
---|
4254 | * @param pAhciPort The AHCI port of the request, shared bits.
|
---|
4255 | * @param pAhciReq The state of the actual task.
|
---|
4256 | */
|
---|
4257 | static bool ahciPortTaskGetCommandFis(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIREQ pAhciReq)
|
---|
4258 | {
|
---|
4259 | AssertMsgReturn(pAhciPort->GCPhysAddrClb && pAhciPort->GCPhysAddrFb,
|
---|
4260 | ("%s: GCPhysAddrClb and/or GCPhysAddrFb are 0\n", __FUNCTION__),
|
---|
4261 | false);
|
---|
4262 |
|
---|
4263 | /*
|
---|
4264 | * First we are reading the command header pointed to by regCLB.
|
---|
4265 | * From this we get the address of the command table which we are reading too.
|
---|
4266 | * We can process the Command FIS afterwards.
|
---|
4267 | */
|
---|
4268 | CmdHdr cmdHdr;
|
---|
4269 | pAhciReq->GCPhysCmdHdrAddr = pAhciPort->GCPhysAddrClb + pAhciReq->uTag * sizeof(CmdHdr);
|
---|
4270 | LogFlow(("%s: PDMDevHlpPCIPhysReadMeta GCPhysAddrCmdLst=%RGp cbCmdHdr=%u\n", __FUNCTION__,
|
---|
4271 | pAhciReq->GCPhysCmdHdrAddr, sizeof(CmdHdr)));
|
---|
4272 | PDMDevHlpPCIPhysReadMeta(pDevIns, pAhciReq->GCPhysCmdHdrAddr, &cmdHdr, sizeof(CmdHdr));
|
---|
4273 |
|
---|
4274 | #ifdef LOG_ENABLED
|
---|
4275 | /* Print some infos about the command header. */
|
---|
4276 | ahciDumpCmdHdrInfo(pAhciPort, &cmdHdr);
|
---|
4277 | #endif
|
---|
4278 |
|
---|
4279 | RTGCPHYS GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(cmdHdr.u32CmdTblAddrUp, cmdHdr.u32CmdTblAddr);
|
---|
4280 |
|
---|
4281 | AssertMsgReturn((cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
|
---|
4282 | ("This is not a command FIS!!\n"),
|
---|
4283 | false);
|
---|
4284 |
|
---|
4285 | /* Read the command Fis. */
|
---|
4286 | LogFlow(("%s: PDMDevHlpPCIPhysReadMeta GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
|
---|
4287 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysAddrCmdTbl, &pAhciReq->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
|
---|
4288 |
|
---|
4289 | AssertMsgReturn(pAhciReq->cmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D,
|
---|
4290 | ("This is not a command FIS\n"),
|
---|
4291 | false);
|
---|
4292 |
|
---|
4293 | /* Set transfer direction. */
|
---|
4294 | pAhciReq->fFlags |= (cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? 0 : AHCI_REQ_XFER_2_HOST;
|
---|
4295 |
|
---|
4296 | /* If this is an ATAPI command read the atapi command. */
|
---|
4297 | if (cmdHdr.u32DescInf & AHCI_CMDHDR_A)
|
---|
4298 | {
|
---|
4299 | GCPhysAddrCmdTbl += AHCI_CMDHDR_ACMD_OFFSET;
|
---|
4300 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysAddrCmdTbl, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE);
|
---|
4301 | }
|
---|
4302 |
|
---|
4303 | /* We "received" the FIS. Clear the BSY bit in regTFD. */
|
---|
4304 | if ((cmdHdr.u32DescInf & AHCI_CMDHDR_C) && (pAhciReq->fFlags & AHCI_REQ_CLEAR_SACT))
|
---|
4305 | {
|
---|
4306 | /*
|
---|
4307 | * We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
|
---|
4308 | * but this FIS does not assert an interrupt
|
---|
4309 | */
|
---|
4310 | ahciSendD2HFis(pDevIns, pThis, pAhciPort, pAhciReq->uTag, pAhciReq->cmdFis, false);
|
---|
4311 | pAhciPort->regTFD &= ~AHCI_PORT_TFD_BSY;
|
---|
4312 | }
|
---|
4313 |
|
---|
4314 | pAhciReq->GCPhysPrdtl = AHCI_RTGCPHYS_FROM_U32(cmdHdr.u32CmdTblAddrUp, cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
|
---|
4315 | pAhciReq->cPrdtlEntries = AHCI_CMDHDR_PRDTL_ENTRIES(cmdHdr.u32DescInf);
|
---|
4316 |
|
---|
4317 | #ifdef LOG_ENABLED
|
---|
4318 | /* Print some infos about the FIS. */
|
---|
4319 | ahciDumpFisInfo(pAhciPort, &pAhciReq->cmdFis[0]);
|
---|
4320 |
|
---|
4321 | /* Print the PRDT */
|
---|
4322 | ahciLog(("PRDT address %RGp number of entries %u\n", pAhciReq->GCPhysPrdtl, pAhciReq->cPrdtlEntries));
|
---|
4323 | RTGCPHYS GCPhysPrdtl = pAhciReq->GCPhysPrdtl;
|
---|
4324 |
|
---|
4325 | for (unsigned i = 0; i < pAhciReq->cPrdtlEntries; i++)
|
---|
4326 | {
|
---|
4327 | SGLEntry SGEntry;
|
---|
4328 |
|
---|
4329 | ahciLog(("Entry %u at address %RGp\n", i, GCPhysPrdtl));
|
---|
4330 | PDMDevHlpPCIPhysReadMeta(pDevIns, GCPhysPrdtl, &SGEntry, sizeof(SGLEntry));
|
---|
4331 |
|
---|
4332 | RTGCPHYS GCPhysDataAddr = AHCI_RTGCPHYS_FROM_U32(SGEntry.u32DBAUp, SGEntry.u32DBA);
|
---|
4333 | ahciLog(("GCPhysAddr=%RGp Size=%u\n", GCPhysDataAddr, SGEntry.u32DescInf & SGLENTRY_DESCINF_DBC));
|
---|
4334 |
|
---|
4335 | GCPhysPrdtl += sizeof(SGLEntry);
|
---|
4336 | }
|
---|
4337 | #endif
|
---|
4338 |
|
---|
4339 | return true;
|
---|
4340 | }
|
---|
4341 |
|
---|
4342 | /**
|
---|
4343 | * Submits a given request for execution.
|
---|
4344 | *
|
---|
4345 | * @returns Flag whether the request was canceled inbetween.
|
---|
4346 | * @param pDevIns The device instance.
|
---|
4347 | * @param pThis The shared AHCI state.
|
---|
4348 | * @param pThisCC The ring-3 AHCI state.
|
---|
4349 | * @param pAhciPort The port the request is for, shared bits.
|
---|
4350 | * @param pAhciPortR3 The port the request is for, ring-3 bits.
|
---|
4351 | * @param pAhciReq The request to submit.
|
---|
4352 | * @param enmType The request type.
|
---|
4353 | */
|
---|
4354 | static bool ahciR3ReqSubmit(PPDMDEVINS pDevIns, PAHCI pThis, PAHCICC pThisCC, PAHCIPORT pAhciPort, PAHCIPORTR3 pAhciPortR3,
|
---|
4355 | PAHCIREQ pAhciReq, PDMMEDIAEXIOREQTYPE enmType)
|
---|
4356 | {
|
---|
4357 | int rc = VINF_SUCCESS;
|
---|
4358 | bool fReqCanceled = false;
|
---|
4359 |
|
---|
4360 | VBOXDD_AHCI_REQ_SUBMIT(pAhciReq, pAhciReq->enmType, pAhciReq->uOffset, pAhciReq->cbTransfer);
|
---|
4361 |
|
---|
4362 | if (enmType == PDMMEDIAEXIOREQTYPE_FLUSH)
|
---|
4363 | rc = pAhciPortR3->pDrvMediaEx->pfnIoReqFlush(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq);
|
---|
4364 | else if (enmType == PDMMEDIAEXIOREQTYPE_DISCARD)
|
---|
4365 | {
|
---|
4366 | uint32_t cRangesMax;
|
---|
4367 |
|
---|
4368 | /* The data buffer contains LBA range entries. Each range is 8 bytes big. */
|
---|
4369 | if (!pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] && !pAhciReq->cmdFis[AHCI_CMDFIS_SECTCEXP])
|
---|
4370 | cRangesMax = 65536 * 512 / 8;
|
---|
4371 | else
|
---|
4372 | cRangesMax = pAhciReq->cmdFis[AHCI_CMDFIS_SECTC] * 512 / 8;
|
---|
4373 |
|
---|
4374 | pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
|
---|
4375 | rc = pAhciPortR3->pDrvMediaEx->pfnIoReqDiscard(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq,
|
---|
4376 | cRangesMax);
|
---|
4377 | }
|
---|
4378 | else if (enmType == PDMMEDIAEXIOREQTYPE_READ)
|
---|
4379 | {
|
---|
4380 | pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
|
---|
4381 | rc = pAhciPortR3->pDrvMediaEx->pfnIoReqRead(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq,
|
---|
4382 | pAhciReq->uOffset, pAhciReq->cbTransfer);
|
---|
4383 | }
|
---|
4384 | else if (enmType == PDMMEDIAEXIOREQTYPE_WRITE)
|
---|
4385 | {
|
---|
4386 | pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
|
---|
4387 | rc = pAhciPortR3->pDrvMediaEx->pfnIoReqWrite(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq,
|
---|
4388 | pAhciReq->uOffset, pAhciReq->cbTransfer);
|
---|
4389 | }
|
---|
4390 | else if (enmType == PDMMEDIAEXIOREQTYPE_SCSI)
|
---|
4391 | {
|
---|
4392 | size_t cbBuf = 0;
|
---|
4393 |
|
---|
4394 | if (pAhciReq->cPrdtlEntries)
|
---|
4395 | rc = ahciR3PrdtQuerySize(pDevIns, pAhciReq, &cbBuf);
|
---|
4396 | pAhciReq->cbTransfer = cbBuf;
|
---|
4397 | if (RT_SUCCESS(rc))
|
---|
4398 | {
|
---|
4399 | PDMMEDIAEXIOREQSCSITXDIR enmTxDir = PDMMEDIAEXIOREQSCSITXDIR_NONE;
|
---|
4400 | if (cbBuf && (pAhciReq->fFlags & AHCI_REQ_XFER_2_HOST))
|
---|
4401 | {
|
---|
4402 | pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
|
---|
4403 | enmTxDir = PDMMEDIAEXIOREQSCSITXDIR_FROM_DEVICE;
|
---|
4404 | }
|
---|
4405 | else if (cbBuf)
|
---|
4406 | {
|
---|
4407 | pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
|
---|
4408 | enmTxDir = PDMMEDIAEXIOREQSCSITXDIR_TO_DEVICE;
|
---|
4409 | }
|
---|
4410 | rc = pAhciPortR3->pDrvMediaEx->pfnIoReqSendScsiCmd(pAhciPortR3->pDrvMediaEx, pAhciReq->hIoReq,
|
---|
4411 | 0, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE,
|
---|
4412 | enmTxDir, NULL, cbBuf,
|
---|
4413 | &pAhciPort->abATAPISense[0], sizeof(pAhciPort->abATAPISense), NULL,
|
---|
4414 | &pAhciReq->u8ScsiSts, 30 * RT_MS_1SEC);
|
---|
4415 | }
|
---|
4416 | }
|
---|
4417 |
|
---|
4418 | if (rc == VINF_SUCCESS)
|
---|
4419 | fReqCanceled = ahciR3TransferComplete(pDevIns, pThis, pThisCC, pAhciPort, pAhciPortR3, pAhciReq, VINF_SUCCESS);
|
---|
4420 | else if (rc != VINF_PDM_MEDIAEX_IOREQ_IN_PROGRESS)
|
---|
4421 | fReqCanceled = ahciR3TransferComplete(pDevIns, pThis, pThisCC, pAhciPort, pAhciPortR3, pAhciReq, rc);
|
---|
4422 |
|
---|
4423 | return fReqCanceled;
|
---|
4424 | }
|
---|
4425 |
|
---|
4426 | /**
|
---|
4427 | * Prepares the command for execution coping it from guest memory and doing a few
|
---|
4428 | * validation checks on it.
|
---|
4429 | *
|
---|
4430 | * @returns Whether the command was successfully fetched from guest memory and
|
---|
4431 | * can be continued.
|
---|
4432 | * @param pDevIns The device instance.
|
---|
4433 | * @param pThis The shared AHCI state.
|
---|
4434 | * @param pAhciPort The AHCI port the request is for, shared bits.
|
---|
4435 | * @param pAhciReq Request structure to copy the command to.
|
---|
4436 | */
|
---|
4437 | static bool ahciR3CmdPrepare(PPDMDEVINS pDevIns, PAHCI pThis, PAHCIPORT pAhciPort, PAHCIREQ pAhciReq)
|
---|
4438 | {
|
---|
4439 | /* Set current command slot */
|
---|
4440 | ASMAtomicWriteU32(&pAhciPort->u32CurrentCommandSlot, pAhciReq->uTag);
|
---|
4441 |
|
---|
4442 | bool fContinue = ahciPortTaskGetCommandFis(pDevIns, pThis, pAhciPort, pAhciReq);
|
---|
4443 | if (fContinue)
|
---|
4444 | {
|
---|
4445 | /* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
|
---|
4446 | if (pAhciPort->regSACT & RT_BIT_32(pAhciReq->uTag))
|
---|
4447 | {
|
---|
4448 | pAhciReq->fFlags |= AHCI_REQ_CLEAR_SACT;
|
---|
4449 | ASMAtomicOrU32(&pAhciPort->u32TasksFinished, RT_BIT_32(pAhciReq->uTag));
|
---|
4450 | }
|
---|
4451 |
|
---|
4452 | if (pAhciReq->cmdFis[AHCI_CMDFIS_BITS] & AHCI_CMDFIS_C)
|
---|
4453 | {
|
---|
4454 | /*
|
---|
4455 | * It is possible that the request counter can get one higher than the maximum because
|
---|
4456 | * the request counter is decremented after the guest was notified about the completed
|
---|
4457 | * request (see @bugref{7859}). If the completing thread is preempted in between the
|
---|
4458 | * guest might already issue another request before the request counter is decremented
|
---|
4459 | * which would trigger the following assertion incorrectly in the past.
|
---|
4460 | */
|
---|
4461 | AssertLogRelMsg(ASMAtomicReadU32(&pAhciPort->cTasksActive) <= AHCI_NR_COMMAND_SLOTS,
|
---|
4462 | ("AHCI#%uP%u: There are more than %u (+1) requests active",
|
---|
4463 | pDevIns->iInstance, pAhciPort->iLUN,
|
---|
4464 | AHCI_NR_COMMAND_SLOTS));
|
---|
4465 | ASMAtomicIncU32(&pAhciPort->cTasksActive);
|
---|
4466 | }
|
---|
4467 | else
|
---|
4468 | {
|
---|
4469 | /* If the reset bit is set put the device into reset state. */
|
---|
4470 | if (pAhciReq->cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
|
---|
4471 | {
|
---|
4472 | ahciLog(("%s: Setting device into reset state\n", __FUNCTION__));
|
---|
4473 | pAhciPort->fResetDevice = true;
|
---|
4474 | ahciSendD2HFis(pDevIns, pThis, pAhciPort, pAhciReq->uTag, pAhciReq->cmdFis, true);
|
---|
4475 | }
|
---|
4476 | else if (pAhciPort->fResetDevice) /* The bit is not set and we are in a reset state. */
|
---|
4477 | ahciFinishStorageDeviceReset(pDevIns, pThis, pAhciPort, pAhciReq);
|
---|
4478 | else /* We are not in a reset state update the control registers. */
|
---|
4479 | AssertMsgFailed(("%s: Update the control register\n", __FUNCTION__));
|
---|
4480 |
|
---|
4481 | fContinue = false;
|
---|
4482 | }
|
---|
4483 | }
|
---|
4484 | else
|
---|
4485 | {
|
---|
4486 | /*
|
---|
4487 | * Couldn't find anything in either the AHCI or SATA spec which
|
---|
4488 | * indicates what should be done if the FIS is not read successfully.
|
---|
4489 | * The closest thing is in the state machine, stating that the device
|
---|
4490 | * should go into idle state again (SATA spec 1.0 chapter 8.7.1).
|
---|
4491 | * Do the same here and ignore any corrupt FIS types, after all
|
---|
4492 | * the guest messed up everything and this behavior is undefined.
|
---|
4493 | */
|
---|
4494 | fContinue = false;
|
---|
4495 | }
|
---|
4496 |
|
---|
4497 | return fContinue;
|
---|
4498 | }
|
---|
4499 |
|
---|
4500 | /**
|
---|
4501 | * @callback_method_impl{FNPDMTHREADDEV, The async IO thread for one port.}
|
---|
4502 | */
|
---|
4503 | static DECLCALLBACK(int) ahciAsyncIOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
|
---|
4504 | {
|
---|
4505 | PAHCIPORTR3 pAhciPortR3 = (PAHCIPORTR3)pThread->pvUser;
|
---|
4506 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4507 | PAHCIR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PAHCICC);
|
---|
4508 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
4509 | int rc = VINF_SUCCESS;
|
---|
4510 |
|
---|
4511 | ahciLog(("%s: Port %d entering async IO loop.\n", __FUNCTION__, pAhciPort->iLUN));
|
---|
4512 |
|
---|
4513 | if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
|
---|
4514 | return VINF_SUCCESS;
|
---|
4515 |
|
---|
4516 | while (pThread->enmState == PDMTHREADSTATE_RUNNING)
|
---|
4517 | {
|
---|
4518 | unsigned idx = 0;
|
---|
4519 | uint32_t u32Tasks = 0;
|
---|
4520 | uint32_t u32RegHbaCtrl = 0;
|
---|
4521 |
|
---|
4522 | ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, true);
|
---|
4523 | u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
|
---|
4524 | if (!u32Tasks)
|
---|
4525 | {
|
---|
4526 | Assert(ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping));
|
---|
4527 | rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pAhciPort->hEvtProcess, RT_INDEFINITE_WAIT);
|
---|
4528 | AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
|
---|
4529 | if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
|
---|
4530 | break;
|
---|
4531 | LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
|
---|
4532 | u32Tasks = ASMAtomicXchgU32(&pAhciPort->u32TasksNew, 0);
|
---|
4533 | }
|
---|
4534 |
|
---|
4535 | ASMAtomicWriteBool(&pAhciPort->fWrkThreadSleeping, false);
|
---|
4536 | ASMAtomicIncU32(&pThis->cThreadsActive);
|
---|
4537 |
|
---|
4538 | /* Check whether the thread should be suspended. */
|
---|
4539 | if (pThisCC->fSignalIdle)
|
---|
4540 | {
|
---|
4541 | if (!ASMAtomicDecU32(&pThis->cThreadsActive))
|
---|
4542 | PDMDevHlpAsyncNotificationCompleted(pDevIns);
|
---|
4543 | continue;
|
---|
4544 | }
|
---|
4545 |
|
---|
4546 | /*
|
---|
4547 | * Check whether the global host controller bit is set and go to sleep immediately again
|
---|
4548 | * if it is set.
|
---|
4549 | */
|
---|
4550 | u32RegHbaCtrl = ASMAtomicReadU32(&pThis->regHbaCtrl);
|
---|
4551 | if ( u32RegHbaCtrl & AHCI_HBA_CTRL_HR
|
---|
4552 | && !ASMAtomicDecU32(&pThis->cThreadsActive))
|
---|
4553 | {
|
---|
4554 | ahciR3HBAReset(pDevIns, pThis, pThisCC);
|
---|
4555 | if (pThisCC->fSignalIdle)
|
---|
4556 | PDMDevHlpAsyncNotificationCompleted(pDevIns);
|
---|
4557 | continue;
|
---|
4558 | }
|
---|
4559 |
|
---|
4560 | idx = ASMBitFirstSetU32(u32Tasks);
|
---|
4561 | while ( idx
|
---|
4562 | && !pAhciPort->fPortReset)
|
---|
4563 | {
|
---|
4564 | bool fReqCanceled = false;
|
---|
4565 |
|
---|
4566 | /* Decrement to get the slot number. */
|
---|
4567 | idx--;
|
---|
4568 | ahciLog(("%s: Processing command at slot %d\n", __FUNCTION__, idx));
|
---|
4569 |
|
---|
4570 | PAHCIREQ pAhciReq = ahciR3ReqAlloc(pAhciPortR3, idx);
|
---|
4571 | if (RT_LIKELY(pAhciReq))
|
---|
4572 | {
|
---|
4573 | pAhciReq->uTag = idx;
|
---|
4574 | pAhciReq->fFlags = 0;
|
---|
4575 |
|
---|
4576 | bool fContinue = ahciR3CmdPrepare(pDevIns, pThis, pAhciPort, pAhciReq);
|
---|
4577 | if (fContinue)
|
---|
4578 | {
|
---|
4579 | PDMMEDIAEXIOREQTYPE enmType = ahciProcessCmd(pDevIns, pThis, pAhciPort, pAhciPortR3,
|
---|
4580 | pAhciReq, pAhciReq->cmdFis);
|
---|
4581 | pAhciReq->enmType = enmType;
|
---|
4582 |
|
---|
4583 | if (enmType != PDMMEDIAEXIOREQTYPE_INVALID)
|
---|
4584 | fReqCanceled = ahciR3ReqSubmit(pDevIns, pThis, pThisCC, pAhciPort, pAhciPortR3, pAhciReq, enmType);
|
---|
4585 | else
|
---|
4586 | fReqCanceled = ahciR3TransferComplete(pDevIns, pThis, pThisCC, pAhciPort, pAhciPortR3,
|
---|
4587 | pAhciReq, VINF_SUCCESS);
|
---|
4588 | } /* Command */
|
---|
4589 | else
|
---|
4590 | ahciR3ReqFree(pAhciPortR3, pAhciReq);
|
---|
4591 | }
|
---|
4592 | else /* !Request allocated, use on stack variant to signal the error. */
|
---|
4593 | {
|
---|
4594 | AHCIREQ Req;
|
---|
4595 | Req.uTag = idx;
|
---|
4596 | Req.fFlags = AHCI_REQ_IS_ON_STACK;
|
---|
4597 | Req.fMapped = false;
|
---|
4598 | Req.cbTransfer = 0;
|
---|
4599 | Req.uOffset = 0;
|
---|
4600 | Req.enmType = PDMMEDIAEXIOREQTYPE_INVALID;
|
---|
4601 |
|
---|
4602 | bool fContinue = ahciR3CmdPrepare(pDevIns, pThis, pAhciPort, &Req);
|
---|
4603 | if (fContinue)
|
---|
4604 | fReqCanceled = ahciR3TransferComplete(pDevIns, pThis, pThisCC, pAhciPort, pAhciPortR3, &Req, VERR_NO_MEMORY);
|
---|
4605 | }
|
---|
4606 |
|
---|
4607 | /*
|
---|
4608 | * Don't process other requests if the last one was canceled,
|
---|
4609 | * the others are not valid anymore.
|
---|
4610 | */
|
---|
4611 | if (fReqCanceled)
|
---|
4612 | break;
|
---|
4613 |
|
---|
4614 | u32Tasks &= ~RT_BIT_32(idx); /* Clear task bit. */
|
---|
4615 | idx = ASMBitFirstSetU32(u32Tasks);
|
---|
4616 | } /* while tasks available */
|
---|
4617 |
|
---|
4618 | /* Check whether a port reset was active. */
|
---|
4619 | if ( ASMAtomicReadBool(&pAhciPort->fPortReset)
|
---|
4620 | && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT)
|
---|
4621 | ahciPortResetFinish(pDevIns, pThis, pAhciPort, pAhciPortR3);
|
---|
4622 |
|
---|
4623 | /*
|
---|
4624 | * Check whether a host controller reset is pending and execute the reset
|
---|
4625 | * if this is the last active thread.
|
---|
4626 | */
|
---|
4627 | u32RegHbaCtrl = ASMAtomicReadU32(&pThis->regHbaCtrl);
|
---|
4628 | uint32_t cThreadsActive = ASMAtomicDecU32(&pThis->cThreadsActive);
|
---|
4629 | if ( (u32RegHbaCtrl & AHCI_HBA_CTRL_HR)
|
---|
4630 | && !cThreadsActive)
|
---|
4631 | ahciR3HBAReset(pDevIns, pThis, pThisCC);
|
---|
4632 |
|
---|
4633 | if (!cThreadsActive && pThisCC->fSignalIdle)
|
---|
4634 | PDMDevHlpAsyncNotificationCompleted(pDevIns);
|
---|
4635 | } /* While running */
|
---|
4636 |
|
---|
4637 | ahciLog(("%s: Port %d async IO thread exiting\n", __FUNCTION__, pAhciPort->iLUN));
|
---|
4638 | return VINF_SUCCESS;
|
---|
4639 | }
|
---|
4640 |
|
---|
4641 | /**
|
---|
4642 | * @callback_method_impl{FNPDMTHREADWAKEUPDEV}
|
---|
4643 | */
|
---|
4644 | static DECLCALLBACK(int) ahciAsyncIOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
|
---|
4645 | {
|
---|
4646 | PAHCIPORTR3 pAhciPortR3 = (PAHCIPORTR3)pThread->pvUser;
|
---|
4647 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4648 | PAHCIPORT pAhciPort = &RT_SAFE_SUBSCRIPT(pThis->aPorts, pAhciPortR3->iLUN);
|
---|
4649 | return PDMDevHlpSUPSemEventSignal(pDevIns, pAhciPort->hEvtProcess);
|
---|
4650 | }
|
---|
4651 |
|
---|
4652 | /* -=-=-=-=- DBGF -=-=-=-=- */
|
---|
4653 |
|
---|
4654 | /**
|
---|
4655 | * AHCI status info callback.
|
---|
4656 | *
|
---|
4657 | * @param pDevIns The device instance.
|
---|
4658 | * @param pHlp The output helpers.
|
---|
4659 | * @param pszArgs The arguments.
|
---|
4660 | */
|
---|
4661 | static DECLCALLBACK(void) ahciR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
4662 | {
|
---|
4663 | RT_NOREF(pszArgs);
|
---|
4664 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4665 |
|
---|
4666 | /*
|
---|
4667 | * Show info.
|
---|
4668 | */
|
---|
4669 | pHlp->pfnPrintf(pHlp,
|
---|
4670 | "%s#%d: mmio=%RGp ports=%u GC=%RTbool R0=%RTbool\n",
|
---|
4671 | pDevIns->pReg->szName,
|
---|
4672 | pDevIns->iInstance,
|
---|
4673 | PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio),
|
---|
4674 | pThis->cPortsImpl,
|
---|
4675 | pDevIns->fRCEnabled,
|
---|
4676 | pDevIns->fR0Enabled);
|
---|
4677 |
|
---|
4678 | /*
|
---|
4679 | * Show global registers.
|
---|
4680 | */
|
---|
4681 | pHlp->pfnPrintf(pHlp, "HbaCap=%#x\n", pThis->regHbaCap);
|
---|
4682 | pHlp->pfnPrintf(pHlp, "HbaCtrl=%#x\n", pThis->regHbaCtrl);
|
---|
4683 | pHlp->pfnPrintf(pHlp, "HbaIs=%#x\n", pThis->regHbaIs);
|
---|
4684 | pHlp->pfnPrintf(pHlp, "HbaPi=%#x\n", pThis->regHbaPi);
|
---|
4685 | pHlp->pfnPrintf(pHlp, "HbaVs=%#x\n", pThis->regHbaVs);
|
---|
4686 | pHlp->pfnPrintf(pHlp, "HbaCccCtl=%#x\n", pThis->regHbaCccCtl);
|
---|
4687 | pHlp->pfnPrintf(pHlp, "HbaCccPorts=%#x\n", pThis->regHbaCccPorts);
|
---|
4688 | pHlp->pfnPrintf(pHlp, "PortsInterrupted=%#x\n", pThis->u32PortsInterrupted);
|
---|
4689 |
|
---|
4690 | /*
|
---|
4691 | * Per port data.
|
---|
4692 | */
|
---|
4693 | uint32_t const cPortsImpl = RT_MIN(pThis->cPortsImpl, RT_ELEMENTS(pThis->aPorts));
|
---|
4694 | for (unsigned i = 0; i < cPortsImpl; i++)
|
---|
4695 | {
|
---|
4696 | PAHCIPORT pThisPort = &pThis->aPorts[i];
|
---|
4697 |
|
---|
4698 | pHlp->pfnPrintf(pHlp, "Port %d: device-attached=%RTbool\n", pThisPort->iLUN, pThisPort->fPresent);
|
---|
4699 | pHlp->pfnPrintf(pHlp, "PortClb=%#x\n", pThisPort->regCLB);
|
---|
4700 | pHlp->pfnPrintf(pHlp, "PortClbU=%#x\n", pThisPort->regCLBU);
|
---|
4701 | pHlp->pfnPrintf(pHlp, "PortFb=%#x\n", pThisPort->regFB);
|
---|
4702 | pHlp->pfnPrintf(pHlp, "PortFbU=%#x\n", pThisPort->regFBU);
|
---|
4703 | pHlp->pfnPrintf(pHlp, "PortIs=%#x\n", pThisPort->regIS);
|
---|
4704 | pHlp->pfnPrintf(pHlp, "PortIe=%#x\n", pThisPort->regIE);
|
---|
4705 | pHlp->pfnPrintf(pHlp, "PortCmd=%#x\n", pThisPort->regCMD);
|
---|
4706 | pHlp->pfnPrintf(pHlp, "PortTfd=%#x\n", pThisPort->regTFD);
|
---|
4707 | pHlp->pfnPrintf(pHlp, "PortSig=%#x\n", pThisPort->regSIG);
|
---|
4708 | pHlp->pfnPrintf(pHlp, "PortSSts=%#x\n", pThisPort->regSSTS);
|
---|
4709 | pHlp->pfnPrintf(pHlp, "PortSCtl=%#x\n", pThisPort->regSCTL);
|
---|
4710 | pHlp->pfnPrintf(pHlp, "PortSErr=%#x\n", pThisPort->regSERR);
|
---|
4711 | pHlp->pfnPrintf(pHlp, "PortSAct=%#x\n", pThisPort->regSACT);
|
---|
4712 | pHlp->pfnPrintf(pHlp, "PortCi=%#x\n", pThisPort->regCI);
|
---|
4713 | pHlp->pfnPrintf(pHlp, "PortPhysClb=%RGp\n", pThisPort->GCPhysAddrClb);
|
---|
4714 | pHlp->pfnPrintf(pHlp, "PortPhysFb=%RGp\n", pThisPort->GCPhysAddrFb);
|
---|
4715 | pHlp->pfnPrintf(pHlp, "PortActTasksActive=%u\n", pThisPort->cTasksActive);
|
---|
4716 | pHlp->pfnPrintf(pHlp, "PortPoweredOn=%RTbool\n", pThisPort->fPoweredOn);
|
---|
4717 | pHlp->pfnPrintf(pHlp, "PortSpunUp=%RTbool\n", pThisPort->fSpunUp);
|
---|
4718 | pHlp->pfnPrintf(pHlp, "PortFirstD2HFisSent=%RTbool\n", pThisPort->fFirstD2HFisSent);
|
---|
4719 | pHlp->pfnPrintf(pHlp, "PortATAPI=%RTbool\n", pThisPort->fATAPI);
|
---|
4720 | pHlp->pfnPrintf(pHlp, "PortTasksFinished=%#x\n", pThisPort->u32TasksFinished);
|
---|
4721 | pHlp->pfnPrintf(pHlp, "PortQueuedTasksFinished=%#x\n", pThisPort->u32QueuedTasksFinished);
|
---|
4722 | pHlp->pfnPrintf(pHlp, "PortTasksNew=%#x\n", pThisPort->u32TasksNew);
|
---|
4723 | pHlp->pfnPrintf(pHlp, "\n");
|
---|
4724 | }
|
---|
4725 | }
|
---|
4726 |
|
---|
4727 | /* -=-=-=-=- Helper -=-=-=-=- */
|
---|
4728 |
|
---|
4729 | /**
|
---|
4730 | * Checks if all asynchronous I/O is finished, both AHCI and IDE.
|
---|
4731 | *
|
---|
4732 | * Used by ahciR3Reset, ahciR3Suspend and ahciR3PowerOff. ahciR3SavePrep makes
|
---|
4733 | * use of it in strict builds (which is why it's up here).
|
---|
4734 | *
|
---|
4735 | * @returns true if quiesced, false if busy.
|
---|
4736 | * @param pDevIns The device instance.
|
---|
4737 | */
|
---|
4738 | static bool ahciR3AllAsyncIOIsFinished(PPDMDEVINS pDevIns)
|
---|
4739 | {
|
---|
4740 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4741 |
|
---|
4742 | if (pThis->cThreadsActive)
|
---|
4743 | return false;
|
---|
4744 |
|
---|
4745 | for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aPorts); i++)
|
---|
4746 | {
|
---|
4747 | PAHCIPORT pThisPort = &pThis->aPorts[i];
|
---|
4748 | if (pThisPort->fPresent)
|
---|
4749 | {
|
---|
4750 | if ( (pThisPort->cTasksActive != 0)
|
---|
4751 | || (pThisPort->u32TasksNew != 0))
|
---|
4752 | return false;
|
---|
4753 | }
|
---|
4754 | }
|
---|
4755 | return true;
|
---|
4756 | }
|
---|
4757 |
|
---|
4758 | /* -=-=-=-=- Saved State -=-=-=-=- */
|
---|
4759 |
|
---|
4760 | /**
|
---|
4761 | * @callback_method_impl{FNSSMDEVSAVEPREP}
|
---|
4762 | */
|
---|
4763 | static DECLCALLBACK(int) ahciR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
4764 | {
|
---|
4765 | RT_NOREF(pDevIns, pSSM);
|
---|
4766 | Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
|
---|
4767 | return VINF_SUCCESS;
|
---|
4768 | }
|
---|
4769 |
|
---|
4770 | /**
|
---|
4771 | * @callback_method_impl{FNSSMDEVLOADPREP}
|
---|
4772 | */
|
---|
4773 | static DECLCALLBACK(int) ahciR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
4774 | {
|
---|
4775 | RT_NOREF(pDevIns, pSSM);
|
---|
4776 | Assert(ahciR3AllAsyncIOIsFinished(pDevIns));
|
---|
4777 | return VINF_SUCCESS;
|
---|
4778 | }
|
---|
4779 |
|
---|
4780 | /**
|
---|
4781 | * @callback_method_impl{FNSSMDEVLIVEEXEC}
|
---|
4782 | */
|
---|
4783 | static DECLCALLBACK(int) ahciR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
|
---|
4784 | {
|
---|
4785 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4786 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
4787 | RT_NOREF(uPass);
|
---|
4788 |
|
---|
4789 | /* config. */
|
---|
4790 | pHlp->pfnSSMPutU32(pSSM, pThis->cPortsImpl);
|
---|
4791 | for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
|
---|
4792 | {
|
---|
4793 | pHlp->pfnSSMPutBool(pSSM, pThis->aPorts[i].fPresent);
|
---|
4794 | pHlp->pfnSSMPutBool(pSSM, pThis->aPorts[i].fHotpluggable);
|
---|
4795 | pHlp->pfnSSMPutStrZ(pSSM, pThis->aPorts[i].szSerialNumber);
|
---|
4796 | pHlp->pfnSSMPutStrZ(pSSM, pThis->aPorts[i].szFirmwareRevision);
|
---|
4797 | pHlp->pfnSSMPutStrZ(pSSM, pThis->aPorts[i].szModelNumber);
|
---|
4798 | }
|
---|
4799 |
|
---|
4800 | static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
|
---|
4801 | for (uint32_t i = 0; i < RT_ELEMENTS(s_apszIdeEmuPortNames); i++)
|
---|
4802 | {
|
---|
4803 | uint32_t iPort;
|
---|
4804 | int rc = pHlp->pfnCFGMQueryU32Def(pDevIns->pCfg, s_apszIdeEmuPortNames[i], &iPort, i);
|
---|
4805 | AssertRCReturn(rc, rc);
|
---|
4806 | pHlp->pfnSSMPutU32(pSSM, iPort);
|
---|
4807 | }
|
---|
4808 |
|
---|
4809 | return VINF_SSM_DONT_CALL_AGAIN;
|
---|
4810 | }
|
---|
4811 |
|
---|
4812 | /**
|
---|
4813 | * @callback_method_impl{FNSSMDEVSAVEEXEC}
|
---|
4814 | */
|
---|
4815 | static DECLCALLBACK(int) ahciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
4816 | {
|
---|
4817 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4818 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
4819 | uint32_t i;
|
---|
4820 | int rc;
|
---|
4821 |
|
---|
4822 | Assert(!pThis->f8ByteMMIO4BytesWrittenSuccessfully);
|
---|
4823 |
|
---|
4824 | /* The config */
|
---|
4825 | rc = ahciR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
|
---|
4826 | AssertRCReturn(rc, rc);
|
---|
4827 |
|
---|
4828 | /* The main device structure. */
|
---|
4829 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaCap);
|
---|
4830 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaCtrl);
|
---|
4831 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaIs);
|
---|
4832 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaPi);
|
---|
4833 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaVs);
|
---|
4834 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaCccCtl);
|
---|
4835 | pHlp->pfnSSMPutU32(pSSM, pThis->regHbaCccPorts);
|
---|
4836 | pHlp->pfnSSMPutU8(pSSM, pThis->uCccPortNr);
|
---|
4837 | pHlp->pfnSSMPutU64(pSSM, pThis->uCccTimeout);
|
---|
4838 | pHlp->pfnSSMPutU32(pSSM, pThis->uCccNr);
|
---|
4839 | pHlp->pfnSSMPutU32(pSSM, pThis->uCccCurrentNr);
|
---|
4840 | pHlp->pfnSSMPutU32(pSSM, pThis->u32PortsInterrupted);
|
---|
4841 | pHlp->pfnSSMPutBool(pSSM, pThis->fReset);
|
---|
4842 | pHlp->pfnSSMPutBool(pSSM, pThis->f64BitAddr);
|
---|
4843 | pHlp->pfnSSMPutBool(pSSM, pDevIns->fR0Enabled);
|
---|
4844 | pHlp->pfnSSMPutBool(pSSM, pDevIns->fRCEnabled);
|
---|
4845 | pHlp->pfnSSMPutBool(pSSM, pThis->fLegacyPortResetMethod);
|
---|
4846 |
|
---|
4847 | /* Now every port. */
|
---|
4848 | for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
|
---|
4849 | {
|
---|
4850 | Assert(pThis->aPorts[i].cTasksActive == 0);
|
---|
4851 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regCLB);
|
---|
4852 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regCLBU);
|
---|
4853 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regFB);
|
---|
4854 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regFBU);
|
---|
4855 | pHlp->pfnSSMPutGCPhys(pSSM, pThis->aPorts[i].GCPhysAddrClb);
|
---|
4856 | pHlp->pfnSSMPutGCPhys(pSSM, pThis->aPorts[i].GCPhysAddrFb);
|
---|
4857 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regIS);
|
---|
4858 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regIE);
|
---|
4859 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regCMD);
|
---|
4860 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regTFD);
|
---|
4861 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regSIG);
|
---|
4862 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regSSTS);
|
---|
4863 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regSCTL);
|
---|
4864 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regSERR);
|
---|
4865 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regSACT);
|
---|
4866 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].regCI);
|
---|
4867 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].PCHSGeometry.cCylinders);
|
---|
4868 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].PCHSGeometry.cHeads);
|
---|
4869 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].PCHSGeometry.cSectors);
|
---|
4870 | pHlp->pfnSSMPutU64(pSSM, pThis->aPorts[i].cTotalSectors);
|
---|
4871 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].cMultSectors);
|
---|
4872 | pHlp->pfnSSMPutU8(pSSM, pThis->aPorts[i].uATATransferMode);
|
---|
4873 | pHlp->pfnSSMPutBool(pSSM, pThis->aPorts[i].fResetDevice);
|
---|
4874 | pHlp->pfnSSMPutBool(pSSM, pThis->aPorts[i].fPoweredOn);
|
---|
4875 | pHlp->pfnSSMPutBool(pSSM, pThis->aPorts[i].fSpunUp);
|
---|
4876 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].u32TasksFinished);
|
---|
4877 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].u32QueuedTasksFinished);
|
---|
4878 | pHlp->pfnSSMPutU32(pSSM, pThis->aPorts[i].u32CurrentCommandSlot);
|
---|
4879 |
|
---|
4880 | /* ATAPI saved state. */
|
---|
4881 | pHlp->pfnSSMPutBool(pSSM, pThis->aPorts[i].fATAPI);
|
---|
4882 | pHlp->pfnSSMPutMem(pSSM, &pThis->aPorts[i].abATAPISense[0], sizeof(pThis->aPorts[i].abATAPISense));
|
---|
4883 | }
|
---|
4884 |
|
---|
4885 | return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* sanity/terminator */
|
---|
4886 | }
|
---|
4887 |
|
---|
4888 | /**
|
---|
4889 | * Loads a saved legacy ATA emulated device state.
|
---|
4890 | *
|
---|
4891 | * @returns VBox status code.
|
---|
4892 | * @param pHlp The device helper call table.
|
---|
4893 | * @param pSSM The handle to the saved state.
|
---|
4894 | */
|
---|
4895 | static int ahciR3LoadLegacyEmulationState(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
|
---|
4896 | {
|
---|
4897 | int rc;
|
---|
4898 | uint32_t u32Version;
|
---|
4899 | uint32_t u32;
|
---|
4900 | uint32_t u32IOBuffer;
|
---|
4901 |
|
---|
4902 | /* Test for correct version. */
|
---|
4903 | rc = pHlp->pfnSSMGetU32(pSSM, &u32Version);
|
---|
4904 | AssertRCReturn(rc, rc);
|
---|
4905 | LogFlow(("LoadOldSavedStates u32Version = %d\n", u32Version));
|
---|
4906 |
|
---|
4907 | if ( u32Version != ATA_CTL_SAVED_STATE_VERSION
|
---|
4908 | && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
|
---|
4909 | && u32Version != ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
|
---|
4910 | {
|
---|
4911 | AssertMsgFailed(("u32Version=%d\n", u32Version));
|
---|
4912 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
4913 | }
|
---|
4914 |
|
---|
4915 | pHlp->pfnSSMSkip(pSSM, 19 + 5 * sizeof(bool) + 8 /* sizeof(BMDMAState) */);
|
---|
4916 |
|
---|
4917 | for (uint32_t j = 0; j < 2; j++)
|
---|
4918 | {
|
---|
4919 | pHlp->pfnSSMSkip(pSSM, 88 + 5 * sizeof(bool) );
|
---|
4920 |
|
---|
4921 | if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
|
---|
4922 | pHlp->pfnSSMSkip(pSSM, 64);
|
---|
4923 | else
|
---|
4924 | pHlp->pfnSSMSkip(pSSM, 2);
|
---|
4925 | /** @todo triple-check this hack after passthrough is working */
|
---|
4926 | pHlp->pfnSSMSkip(pSSM, 1);
|
---|
4927 |
|
---|
4928 | if (u32Version > ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
|
---|
4929 | pHlp->pfnSSMSkip(pSSM, 4);
|
---|
4930 |
|
---|
4931 | pHlp->pfnSSMSkip(pSSM, sizeof(PDMLED));
|
---|
4932 | pHlp->pfnSSMGetU32(pSSM, &u32IOBuffer);
|
---|
4933 | if (u32IOBuffer)
|
---|
4934 | pHlp->pfnSSMSkip(pSSM, u32IOBuffer);
|
---|
4935 | }
|
---|
4936 |
|
---|
4937 | rc = pHlp->pfnSSMGetU32(pSSM, &u32);
|
---|
4938 | if (RT_FAILURE(rc))
|
---|
4939 | return rc;
|
---|
4940 | if (u32 != ~0U)
|
---|
4941 | {
|
---|
4942 | AssertMsgFailed(("u32=%#x expected ~0\n", u32));
|
---|
4943 | rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
|
---|
4944 | return rc;
|
---|
4945 | }
|
---|
4946 |
|
---|
4947 | return VINF_SUCCESS;
|
---|
4948 | }
|
---|
4949 |
|
---|
4950 | /**
|
---|
4951 | * @callback_method_impl{FNSSMDEVLOADEXEC}
|
---|
4952 | */
|
---|
4953 | static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
4954 | {
|
---|
4955 | PAHCI pThis = PDMDEVINS_2_DATA(pDevIns, PAHCI);
|
---|
4956 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
4957 | uint32_t u32;
|
---|
4958 | int rc;
|
---|
4959 |
|
---|
4960 | if ( uVersion > AHCI_SAVED_STATE_VERSION
|
---|
4961 | || uVersion < AHCI_SAVED_STATE_VERSION_VBOX_30)
|
---|
4962 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
4963 |
|
---|
4964 | /* Deal with the priod after removing the saved IDE bits where the saved
|
---|
4965 | state version remained unchanged. */
|
---|
4966 | if ( uVersion == AHCI_SAVED_STATE_VERSION_IDE_EMULATION
|
---|
4967 | && pHlp->pfnSSMHandleRevision(pSSM) >= 79045
|
---|
4968 | && pHlp->pfnSSMHandleRevision(pSSM) < 79201)
|
---|
4969 | uVersion++;
|
---|
4970 |
|
---|
4971 | /*
|
---|
4972 | * Check whether we have to resort to the legacy port reset method to
|
---|
4973 | * prevent older BIOS versions from failing after a reset.
|
---|
4974 | */
|
---|
4975 | if (uVersion <= AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES)
|
---|
4976 | pThis->fLegacyPortResetMethod = true;
|
---|
4977 |
|
---|
4978 | /* Verify config. */
|
---|
4979 | if (uVersion > AHCI_SAVED_STATE_VERSION_VBOX_30)
|
---|
4980 | {
|
---|
4981 | rc = pHlp->pfnSSMGetU32(pSSM, &u32);
|
---|
4982 | AssertRCReturn(rc, rc);
|
---|
4983 | if (u32 != pThis->cPortsImpl)
|
---|
4984 | {
|
---|
4985 | LogRel(("AHCI: Config mismatch: cPortsImpl - saved=%u config=%u\n", u32, pThis->cPortsImpl));
|
---|
4986 | if ( u32 < pThis->cPortsImpl
|
---|
4987 | || u32 > AHCI_MAX_NR_PORTS_IMPL)
|
---|
4988 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cPortsImpl - saved=%u config=%u"),
|
---|
4989 | u32, pThis->cPortsImpl);
|
---|
4990 | }
|
---|
4991 |
|
---|
4992 | for (uint32_t i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
|
---|
4993 | {
|
---|
4994 | bool fInUse;
|
---|
4995 | rc = pHlp->pfnSSMGetBool(pSSM, &fInUse);
|
---|
4996 | AssertRCReturn(rc, rc);
|
---|
4997 | if (fInUse != pThis->aPorts[i].fPresent)
|
---|
4998 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
|
---|
4999 | N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
|
---|
5000 | fInUse ? "target" : "source", i);
|
---|
5001 |
|
---|
5002 | if (uVersion > AHCI_SAVED_STATE_VERSION_PRE_HOTPLUG_FLAG)
|
---|
5003 | {
|
---|
5004 | bool fHotpluggable;
|
---|
5005 | rc = pHlp->pfnSSMGetBool(pSSM, &fHotpluggable);
|
---|
5006 | AssertRCReturn(rc, rc);
|
---|
5007 | if (fHotpluggable != pThis->aPorts[i].fHotpluggable)
|
---|
5008 | return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
|
---|
5009 | N_("AHCI: Port %u config mismatch: Hotplug flag - saved=%RTbool config=%RTbool\n"),
|
---|
5010 | i, fHotpluggable, pThis->aPorts[i].fHotpluggable);
|
---|
5011 | }
|
---|
5012 | else
|
---|
5013 | Assert(pThis->aPorts[i].fHotpluggable);
|
---|
5014 |
|
---|
5015 | char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1];
|
---|
5016 | rc = pHlp->pfnSSMGetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
|
---|
5017 | AssertRCReturn(rc, rc);
|
---|
5018 | if (strcmp(szSerialNumber, pThis->aPorts[i].szSerialNumber))
|
---|
5019 | LogRel(("AHCI: Port %u config mismatch: Serial number - saved='%s' config='%s'\n",
|
---|
5020 | i, szSerialNumber, pThis->aPorts[i].szSerialNumber));
|
---|
5021 |
|
---|
5022 | char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1];
|
---|
5023 | rc = pHlp->pfnSSMGetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
|
---|
5024 | AssertRCReturn(rc, rc);
|
---|
5025 | if (strcmp(szFirmwareRevision, pThis->aPorts[i].szFirmwareRevision))
|
---|
5026 | LogRel(("AHCI: Port %u config mismatch: Firmware revision - saved='%s' config='%s'\n",
|
---|
5027 |
---|