VirtualBox

source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 74942

Last change on this file since 74942 was 74919, checked in by vboxsync, 6 years ago

Serial: Make sure the data is periodically removed from the TX queue even if there is no driver connected to the device
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1/* $Id: UartCore.cpp 74919 2018-10-18 13:12:30Z vboxsync $ */
2/** @file
3 * UartCore - UART (16550A up to 16950) emulation.
4 *
5 * The documentation for this device was taken from the PC16550D spec from TI.
6 */
7
8/*
9 * Copyright (C) 2018 Oracle Corporation
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20
21/*********************************************************************************************************************************
22* Header Files *
23*********************************************************************************************************************************/
24#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25#include <VBox/vmm/tm.h>
26#include <iprt/log.h>
27#include <iprt/uuid.h>
28#include <iprt/assert.h>
29
30#include "VBoxDD.h"
31#include "UartCore.h"
32
33
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37
38/** The RBR/DLL register index (from the base of the port range). */
39#define UART_REG_RBR_DLL_INDEX 0
40
41/** The THR/DLL register index (from the base of the port range). */
42#define UART_REG_THR_DLL_INDEX 0
43
44/** The IER/DLM register index (from the base of the port range). */
45#define UART_REG_IER_DLM_INDEX 1
46/** Enable received data available interrupt */
47# define UART_REG_IER_ERBFI RT_BIT(0)
48/** Enable transmitter holding register empty interrupt */
49# define UART_REG_IER_ETBEI RT_BIT(1)
50/** Enable receiver line status interrupt */
51# define UART_REG_IER_ELSI RT_BIT(2)
52/** Enable modem status interrupt. */
53# define UART_REG_IER_EDSSI RT_BIT(3)
54/** Sleep mode enable. */
55# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56/** Low power mode enable. */
57# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58/** Mask of writeable bits. */
59# define UART_REG_IER_MASK_WR 0x0f
60/** Mask of writeable bits for 16750+. */
61# define UART_REG_IER_MASK_WR_16750 0x3f
62
63/** The IIR register index (from the base of the port range). */
64#define UART_REG_IIR_INDEX 2
65/** Interrupt Pending - high means no interrupt pending. */
66# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67/** Interrupt identification mask. */
68# define UART_REG_IIR_ID_MASK 0x0e
69/** Sets the interrupt identification to the given value. */
70# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71/** Gets the interrupt identification from the given IIR register value. */
72# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
73/** Receiver Line Status interrupt. */
74# define UART_REG_IIR_ID_RCL 0x3
75/** Received Data Available interrupt. */
76# define UART_REG_IIR_ID_RDA 0x2
77/** Character Timeou Indicator interrupt. */
78# define UART_REG_IIR_ID_CTI 0x6
79/** Transmitter Holding Register Empty interrupt. */
80# define UART_REG_IIR_ID_THRE 0x1
81/** Modem Status interrupt. */
82# define UART_REG_IIR_ID_MS 0x0
83/** 64 byte FIFOs enabled (15750+ only). */
84# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85/** FIFOs enabled. */
86# define UART_REG_IIR_FIFOS_EN 0xc0
87/** Bits relevant for checking whether the interrupt status has changed. */
88# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90/** The FCR register index (from the base of the port range). */
91#define UART_REG_FCR_INDEX 2
92/** Enable the TX/RX FIFOs. */
93# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94/** Reset the receive FIFO. */
95# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96/** Reset the transmit FIFO. */
97# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98/** DMA Mode Select. */
99# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100/** 64 Byte FIFO enable (15750+ only). */
101# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102/** Receiver level interrupt trigger. */
103# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104/** Returns the receive level trigger value from the given FCR register. */
105# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106/** RCV Interrupt trigger level - 1 byte. */
107# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108/** RCV Interrupt trigger level - 4 bytes. */
109# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110/** RCV Interrupt trigger level - 8 bytes. */
111# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112/** RCV Interrupt trigger level - 14 bytes. */
113# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114/** Mask of writeable bits. */
115# define UART_REG_FCR_MASK_WR 0xcf
116/** Mask of sticky bits. */
117# define UART_REG_FCR_MASK_STICKY 0xe9
118
119/** The LCR register index (from the base of the port range). */
120#define UART_REG_LCR_INDEX 3
121/** Word Length Select Mask. */
122# define UART_REG_LCR_WLS_MASK 0x3
123/** Returns the WLS value form the given LCR register value. */
124# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125/** Number of stop bits. */
126# define UART_REG_LCR_STB RT_BIT(2)
127/** Parity Enable. */
128# define UART_REG_LCR_PEN RT_BIT(3)
129/** Even Parity. */
130# define UART_REG_LCR_EPS RT_BIT(4)
131/** Stick parity. */
132# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133/** Set Break. */
134# define UART_REG_LCR_BRK_SET RT_BIT(6)
135/** Divisor Latch Access Bit. */
136# define UART_REG_LCR_DLAB RT_BIT(7)
137
138/** The MCR register index (from the base of the port range). */
139#define UART_REG_MCR_INDEX 4
140/** Data Terminal Ready. */
141# define UART_REG_MCR_DTR RT_BIT(0)
142/** Request To Send. */
143# define UART_REG_MCR_RTS RT_BIT(1)
144/** Out1. */
145# define UART_REG_MCR_OUT1 RT_BIT(2)
146/** Out2. */
147# define UART_REG_MCR_OUT2 RT_BIT(3)
148/** Loopback connection. */
149# define UART_REG_MCR_LOOP RT_BIT(4)
150/** Flow Control Enable (15750+ only). */
151# define UART_REG_MCR_AFE RT_BIT(5)
152/** Mask of writeable bits (15450 and 15550A). */
153# define UART_REG_MCR_MASK_WR 0x1f
154/** Mask of writeable bits (15750+). */
155# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157/** The LSR register index (from the base of the port range). */
158#define UART_REG_LSR_INDEX 5
159/** Data Ready. */
160# define UART_REG_LSR_DR RT_BIT(0)
161/** Overrun Error. */
162# define UART_REG_LSR_OE RT_BIT(1)
163/** Parity Error. */
164# define UART_REG_LSR_PE RT_BIT(2)
165/** Framing Error. */
166# define UART_REG_LSR_FE RT_BIT(3)
167/** Break Interrupt. */
168# define UART_REG_LSR_BI RT_BIT(4)
169/** Transmitter Holding Register. */
170# define UART_REG_LSR_THRE RT_BIT(5)
171/** Transmitter Empty. */
172# define UART_REG_LSR_TEMT RT_BIT(6)
173/** Error in receiver FIFO. */
174# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175/** The bits to check in this register when checking for the RCL interrupt. */
176# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178/** The MSR register index (from the base of the port range). */
179#define UART_REG_MSR_INDEX 6
180/** Delta Clear to Send. */
181# define UART_REG_MSR_DCTS RT_BIT(0)
182/** Delta Data Set Ready. */
183# define UART_REG_MSR_DDSR RT_BIT(1)
184/** Trailing Edge Ring Indicator. */
185# define UART_REG_MSR_TERI RT_BIT(2)
186/** Delta Data Carrier Detect. */
187# define UART_REG_MSR_DDCD RT_BIT(3)
188/** Clear to Send. */
189# define UART_REG_MSR_CTS RT_BIT(4)
190/** Data Set Ready. */
191# define UART_REG_MSR_DSR RT_BIT(5)
192/** Ring Indicator. */
193# define UART_REG_MSR_RI RT_BIT(6)
194/** Data Carrier Detect. */
195# define UART_REG_MSR_DCD RT_BIT(7)
196/** The bits to check in this register when checking for the MS interrupt. */
197# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199/** The SCR register index (from the base of the port range). */
200#define UART_REG_SCR_INDEX 7
201
202/** Set the specified bits in the given register. */
203#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) |= (a_Set))
204/** Clear the specified bits in the given register. */
205#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208/*********************************************************************************************************************************
209* Structures and Typedefs *
210*********************************************************************************************************************************/
211
212#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215/*********************************************************************************************************************************
216* Global Variables *
217*********************************************************************************************************************************/
218
219#ifdef IN_RING3
220/**
221 * FIFO ITL levels.
222 */
223static struct
224{
225 /** ITL level for a 16byte FIFO. */
226 uint8_t cbItl16;
227 /** ITL level for a 64byte FIFO. */
228 uint8_t cbItl64;
229} s_aFifoItl[] =
230{
231 /* cbItl16 cbItl64 */
232 { 1, 1 },
233 { 4, 16 },
234 { 8, 32 },
235 { 14, 56 }
236};
237
238
239/**
240 * String versions of the parity enum.
241 */
242static const char *s_aszParity[] =
243{
244 "INVALID",
245 "NONE",
246 "EVEN",
247 "ODD",
248 "MARK",
249 "SPACE",
250 "INVALID"
251};
252
253
254/**
255 * String versions of the stop bits enum.
256 */
257static const char *s_aszStopBits[] =
258{
259 "INVALID",
260 "1",
261 "1.5",
262 "2",
263 "INVALID"
264};
265#endif
266
267
268/*********************************************************************************************************************************
269* Internal Functions *
270*********************************************************************************************************************************/
271
272
273/**
274 * Updates the IRQ state based on the current device state.
275 *
276 * @returns nothing.
277 * @param pThis The UART core instance.
278 */
279static void uartIrqUpdate(PUARTCORE pThis)
280{
281 LogFlowFunc(("pThis=%#p\n", pThis));
282
283 /*
284 * The interrupt uses a priority scheme, only the interrupt with the
285 * highest priority is indicated in the interrupt identification register.
286 *
287 * The priorities are as follows (high to low):
288 * * Receiver line status
289 * * Received data available
290 * * Character timeout indication (only in FIFO mode).
291 * * Transmitter holding register empty
292 * * Modem status change.
293 */
294 uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
295 if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
296 && (pThis->uRegIer & UART_REG_IER_ELSI))
297 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
298 else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
299 && pThis->fIrqCtiPending)
300 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
301 else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
302 && (pThis->uRegIer & UART_REG_IER_ERBFI)
303 && ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
304 || pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
305 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
306 else if ( (pThis->uRegLsr & UART_REG_LSR_THRE)
307 && pThis->fThreEmptyPending)
308 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
309 else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
310 && (pThis->uRegIer & UART_REG_IER_EDSSI))
311 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
312
313 LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
314
315 /* Change interrupt only if the interrupt status really changed from the previous value. */
316 if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
317 {
318 LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
319 pThis->uRegIir, uRegIirNew,
320 pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
321 uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
322 if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
323 pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
324 else
325 pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
326 }
327 else
328 LogFlow((" No change in interrupt source\n"));
329
330 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
331 uRegIirNew |= UART_REG_IIR_FIFOS_EN;
332 if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
333 uRegIirNew |= UART_REG_IIR_64BYTE_FIFOS_EN;
334
335 pThis->uRegIir = uRegIirNew;
336}
337
338
339/**
340 * Returns the amount of bytes stored in the given FIFO.
341 *
342 * @returns Amount of bytes stored in the FIFO.
343 * @param pFifo The FIFO.
344 */
345DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
346{
347 return pFifo->cbUsed;
348}
349
350
351/**
352 * Puts a new character into the given FIFO.
353 *
354 * @returns Flag whether the FIFO overflowed.
355 * @param pFifo The FIFO to put the data into.
356 * @param fOvrWr Flag whether to overwrite data if the FIFO is full.
357 * @param bData The data to add.
358 */
359DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
360{
361 if (fOvrWr || pFifo->cbUsed < pFifo->cbMax)
362 {
363 pFifo->abBuf[pFifo->offWrite] = bData;
364 pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
365 }
366
367 bool fOverFlow = false;
368 if (pFifo->cbUsed < pFifo->cbMax)
369 pFifo->cbUsed++;
370 else
371 {
372 fOverFlow = true;
373 if (fOvrWr) /* Advance the read position to account for the lost character. */
374 pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
375 }
376
377 return fOverFlow;
378}
379
380
381/**
382 * Returns the next character in the FIFO.
383 *
384 * @return Next byte in the FIFO.
385 * @param pFifo The FIFO to get data from.
386 */
387DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
388{
389 uint8_t bRet = 0;
390
391 if (pFifo->cbUsed)
392 {
393 bRet = pFifo->abBuf[pFifo->offRead];
394 pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
395 pFifo->cbUsed--;
396 }
397
398 return bRet;
399}
400
401
402#ifdef IN_RING3
403/**
404 * Clears the given FIFO.
405 *
406 * @returns nothing.
407 * @param pFifo The FIFO to clear.
408 */
409DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
410{
411 memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
412 pFifo->cbUsed = 0;
413 pFifo->offWrite = 0;
414 pFifo->offRead = 0;
415}
416
417
418/**
419 * Returns the amount of free bytes in the given FIFO.
420 *
421 * @returns The amount of bytes free in the given FIFO.
422 * @param pFifo The FIFO.
423 */
424DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
425{
426 return pFifo->cbMax - pFifo->cbUsed;
427}
428
429
430/**
431 * Tries to copy the requested amount of data from the given FIFO into the provided buffer.
432 *
433 * @returns Amount of bytes actually copied.
434 * @param pFifo The FIFO to copy data from.
435 * @param pvDst Where to copy the data to.
436 * @param cbCopy How much to copy.
437 */
438DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
439{
440 size_t cbCopied = 0;
441 uint8_t *pbDst = (uint8_t *)pvDst;
442
443 cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
444 while (cbCopy)
445 {
446 uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
447 memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
448
449 pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
450 pFifo->cbUsed -= cbThisCopy;
451 pbDst += cbThisCopy;
452 cbCopied += cbThisCopy;
453 cbCopy -= cbThisCopy;
454 }
455
456 return cbCopied;
457}
458
459
460#if 0 /* unused */
461/**
462 * Tries to copy the requested amount of data from the provided buffer into the given FIFO.
463 *
464 * @returns Amount of bytes actually copied.
465 * @param pFifo The FIFO to copy data to.
466 * @param pvSrc Where to copy the data from.
467 * @param cbCopy How much to copy.
468 */
469DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
470{
471 size_t cbCopied = 0;
472 uint8_t *pbSrc = (uint8_t *)pvSrc;
473
474 cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
475 while (cbCopy)
476 {
477 uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
478 memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
479
480 pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
481 pFifo->cbUsed += cbThisCopy;
482 pbSrc += cbThisCopy;
483 cbCopied += cbThisCopy;
484 cbCopy -= cbThisCopy;
485 }
486
487 return cbCopied;
488}
489#endif
490
491
492/**
493 * Updates the delta bits for the given MSR register value which has the status line
494 * bits set.
495 *
496 * @returns nothing.
497 * @param pThis The serial port instance.
498 * @param uMsrSts MSR value with the appropriate status bits set.
499 */
500static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
501{
502 /* Compare current and new states and set remaining bits accordingly. */
503 if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
504 uMsrSts |= UART_REG_MSR_DCTS;
505 if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
506 uMsrSts |= UART_REG_MSR_DDSR;
507 if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
508 uMsrSts |= UART_REG_MSR_TERI;
509 if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
510 uMsrSts |= UART_REG_MSR_DDCD;
511
512 pThis->uRegMsr = uMsrSts;
513
514 uartIrqUpdate(pThis);
515}
516
517
518/**
519 * Updates the serial port parameters of the attached driver with the current configuration.
520 *
521 * @returns nothing.
522 * @param pThis The serial port instance.
523 */
524static void uartR3ParamsUpdate(PUARTCORE pThis)
525{
526 if ( pThis->uRegDivisor != 0
527 && pThis->pDrvSerial)
528 {
529 uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
530 unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
531 uint32_t cFrameBits = cDataBits;
532 PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
533 PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
534
535 if (pThis->uRegLcr & UART_REG_LCR_STB)
536 {
537 enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
538 cFrameBits += 2;
539 }
540 else
541 cFrameBits++;
542
543 if (pThis->uRegLcr & UART_REG_LCR_PEN)
544 {
545 /* Select the correct parity mode based on the even and stick parity bits. */
546 switch (pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK))
547 {
548 case 0:
549 enmParity = PDMSERIALPARITY_ODD;
550 break;
551 case UART_REG_LCR_EPS:
552 enmParity = PDMSERIALPARITY_EVEN;
553 break;
554 case UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK:
555 enmParity = PDMSERIALPARITY_SPACE;
556 break;
557 case UART_REG_LCR_PAR_STICK:
558 enmParity = PDMSERIALPARITY_MARK;
559 break;
560 default:
561 /* We should never get here as all cases where caught earlier. */
562 AssertMsgFailed(("This shouldn't happen at all: %#x\n",
563 pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK)));
564 }
565
566 cFrameBits++;
567 }
568
569 uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
570 pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
571
572 LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
573 uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
574
575 int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
576 if (RT_FAILURE(rc))
577 LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
578 pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
579
580 /* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
581 pThis->pDrvSerial->pfnQueuesFlush(pThis->pDrvSerial, true /*fQueueRecv*/, false /*fQueueXmit*/);
582 ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
583 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
584 }
585}
586
587
588/**
589 * Updates the internal device state with the given PDM status line states.
590 *
591 * @returns nothing.
592 * @param pThis The serial port instance.
593 * @param fStsLines The PDM status line states.
594 */
595static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
596{
597 uint8_t uRegMsrNew = 0; /* The new MSR value. */
598
599 if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
600 uRegMsrNew |= UART_REG_MSR_DCD;
601 if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
602 uRegMsrNew |= UART_REG_MSR_RI;
603 if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
604 uRegMsrNew |= UART_REG_MSR_DSR;
605 if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
606 uRegMsrNew |= UART_REG_MSR_CTS;
607
608 uartR3MsrUpdate(pThis, uRegMsrNew);
609}
610
611
612/**
613 * Fills up the receive FIFO with as much data as possible.
614 *
615 * @returns nothing.
616 * @param pThis The serial port instance.
617 */
618static void uartR3RecvFifoFill(PUARTCORE pThis)
619{
620 LogFlowFunc(("pThis=%#p\n", pThis));
621
622 PUARTFIFO pFifo = &pThis->FifoRecv;
623 size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
624 ASMAtomicReadU32(&pThis->cbAvailRdr));
625 size_t cbFilled = 0;
626
627 while (cbFilled < cbFill)
628 {
629 size_t cbThisRead = cbFill - cbFilled;
630
631 if (pFifo->offRead <= pFifo->offWrite)
632 cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
633 else
634 cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
635
636 size_t cbRead = 0;
637 int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
638 AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
639
640 pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
641 pFifo->cbUsed += (uint8_t)cbRead;
642 cbFilled += cbRead;
643
644 if (cbRead < cbThisRead)
645 break;
646 }
647
648 if (cbFilled)
649 {
650 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
651 if (pFifo->cbUsed < pFifo->cbItl)
652 {
653 pThis->fIrqCtiPending = false;
654 TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
655 }
656 uartIrqUpdate(pThis);
657 }
658
659 Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
660 ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
661}
662
663
664/**
665 * Fetches a single byte and writes it to RBR.
666 *
667 * @returns nothing.
668 * @param pThis The serial port instance.
669 */
670static void uartR3ByteFetch(PUARTCORE pThis)
671{
672 if (ASMAtomicReadU32(&pThis->cbAvailRdr))
673 {
674 AssertPtr(pThis->pDrvSerial);
675 size_t cbRead = 0;
676 int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
677 AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
678 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
679 uartIrqUpdate(pThis);
680 }
681}
682
683
684/**
685 * Fetches a ready data based on the FIFO setting.
686 *
687 * @returns nothing.
688 * @param pThis The serial port instance.
689 */
690static void uartR3DataFetch(PUARTCORE pThis)
691{
692 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
693 uartR3RecvFifoFill(pThis);
694 else
695 uartR3ByteFetch(pThis);
696}
697
698
699/**
700 * Reset the transmit/receive related bits to the standard values
701 * (after a detach/attach/reset event).
702 *
703 * @returns nothing.
704 * @param pThis The serial port instance.
705 */
706static void uartR3XferReset(PUARTCORE pThis)
707{
708 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
709 pThis->fThreEmptyPending = false;
710
711 uartFifoClear(&pThis->FifoXmit);
712 uartFifoClear(&pThis->FifoRecv);
713 uartR3ParamsUpdate(pThis);
714 uartIrqUpdate(pThis);
715
716 if (pThis->pDrvSerial)
717 {
718 /* Set the modem lines to reflect the current state. */
719 int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /*fRts*/, false /*fDtr*/);
720 if (RT_FAILURE(rc))
721 LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
722 pThis->pDevInsR3->iInstance, rc));
723
724 uint32_t fStsLines = 0;
725 rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
726 if (RT_SUCCESS(rc))
727 uartR3StsLinesUpdate(pThis, fStsLines);
728 else
729 LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
730 pThis->pDevInsR3->iInstance, rc));
731 }
732
733}
734
735
736/**
737 * Tries to copy the specified amount of data from the active TX queue (register or FIFO).
738 *
739 * @returns nothing.
740 * @param pThis The serial port instance.
741 * @param pvBuf Where to store the data.
742 * @param cbRead How much to read from the TX queue.
743 * @param pcbRead Where to store the amount of data read.
744 */
745static void uartR3TxQueueCopyFrom(PUARTCORE pThis, void *pvBuf, size_t cbRead, size_t *pcbRead)
746{
747 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
748 {
749 *pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
750 if (!pThis->FifoXmit.cbUsed)
751 {
752 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
753 pThis->fThreEmptyPending = true;
754 }
755 if (*pcbRead)
756 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
757 uartIrqUpdate(pThis);
758 }
759 else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
760 {
761 *(uint8_t *)pvBuf = pThis->uRegThr;
762 *pcbRead = 1;
763 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
764 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
765 pThis->fThreEmptyPending = true;
766 uartIrqUpdate(pThis);
767 }
768 else
769 {
770 /*
771 * This can happen if there was data in the FIFO when the connection was closed,
772 * indicate this condition to the lower driver by returning 0 bytes.
773 */
774 *pcbRead = 0;
775 }
776}
777#endif
778
779
780/**
781 * Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
782 *
783 * @returns VBox status code.
784 * @param pThis The serial port instance.
785 * @param uVal The value to write.
786 */
787DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
788{
789 int rc = VINF_SUCCESS;
790
791 /* A set DLAB causes a write to the lower 8bits of the divisor latch. */
792 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
793 {
794 if (uVal != (pThis->uRegDivisor & 0xff))
795 {
796#ifndef IN_RING3
797 rc = VINF_IOM_R3_IOPORT_WRITE;
798#else
799 pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) | uVal;
800 uartR3ParamsUpdate(pThis);
801#endif
802 }
803 }
804 else
805 {
806 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
807 {
808#ifndef IN_RING3
809 if (!uartFifoUsedGet(&pThis->FifoXmit))
810 rc = VINF_IOM_R3_IOPORT_WRITE;
811 else
812 {
813 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, uVal);
814 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
815 }
816#else
817 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, uVal);
818 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
819 pThis->fThreEmptyPending = false;
820 uartIrqUpdate(pThis);
821 if ( pThis->pDrvSerial
822 && uartFifoUsedGet(&pThis->FifoXmit) == 1)
823 {
824 int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
825 if (RT_FAILURE(rc2))
826 LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
827 }
828#endif
829 }
830 else
831 {
832 /* Notify the lower driver about available data only if the register was empty before. */
833 if (pThis->uRegLsr & UART_REG_LSR_THRE)
834 {
835#ifndef IN_RING3
836 rc = VINF_IOM_R3_IOPORT_WRITE;
837#else
838 pThis->uRegThr = uVal;
839 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
840 pThis->fThreEmptyPending = false;
841 uartIrqUpdate(pThis);
842 if (pThis->pDrvSerial)
843 {
844 int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial);
845 if (RT_FAILURE(rc2))
846 LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
847 }
848 else
849 TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
850#endif
851 }
852 else
853 pThis->uRegThr = uVal;
854 }
855 }
856
857 return rc;
858}
859
860
861/**
862 * Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
863 *
864 * @returns VBox status code.
865 * @param pThis The serial port instance.
866 * @param uVal The value to write.
867 */
868DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
869{
870 int rc = VINF_SUCCESS;
871
872 /* A set DLAB causes a write to the higher 8bits of the divisor latch. */
873 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
874 {
875 if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
876 {
877#ifndef IN_RING3
878 rc = VINF_IOM_R3_IOPORT_WRITE;
879#else
880 pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) | (uVal << 8);
881 uartR3ParamsUpdate(pThis);
882#endif
883 }
884 }
885 else
886 {
887 if (pThis->enmType < UARTTYPE_16750)
888 pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
889 else
890 pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
891
892 if (pThis->uRegLsr & UART_REG_LSR_THRE)
893 pThis->fThreEmptyPending = true;
894
895 uartIrqUpdate(pThis);
896 }
897
898 return rc;
899}
900
901
902/**
903 * Write handler for the FCR register.
904 *
905 * @returns VBox status code.
906 * @param pThis The serial port instance.
907 * @param uVal The value to write.
908 */
909DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
910{
911#ifndef IN_RING3
912 RT_NOREF(pThis, uVal);
913 return VINF_IOM_R3_IOPORT_WRITE;
914#else
915 int rc = VINF_SUCCESS;
916 if ( pThis->enmType >= UARTTYPE_16550A
917 && uVal != pThis->uRegFcr)
918 {
919 /* A change in the FIFO enable bit clears both FIFOs automatically. */
920 if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
921 {
922 uartFifoClear(&pThis->FifoXmit);
923 uartFifoClear(&pThis->FifoRecv);
924
925 /*
926 * If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
927 * byte in the RBR register which will be lost so we have to adjust the available bytes.
928 */
929 if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
930 && (uVal & UART_REG_FCR_FIFO_EN))
931 ASMAtomicDecU32(&pThis->cbAvailRdr);
932
933 /* Clear the DR bit too. */
934 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
935 }
936
937 if (rc == VINF_SUCCESS)
938 {
939 if (uVal & UART_REG_FCR_RCV_FIFO_RST)
940 {
941 TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
942 pThis->fIrqCtiPending = false;
943 uartFifoClear(&pThis->FifoRecv);
944 }
945 if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
946 uartFifoClear(&pThis->FifoXmit);
947
948 /*
949 * The 64byte FIFO enable bit is only changeable for 16750
950 * and if the DLAB bit in LCR is set.
951 */
952 if ( pThis->enmType < UARTTYPE_16750
953 || !(pThis->uRegLcr & UART_REG_LCR_DLAB))
954 uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
955 else /* Use previous value. */
956 uVal |= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
957
958 if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
959 {
960 pThis->FifoRecv.cbMax = 64;
961 pThis->FifoXmit.cbMax = 64;
962 }
963 else
964 {
965 pThis->FifoRecv.cbMax = 16;
966 pThis->FifoXmit.cbMax = 16;
967 }
968
969 if (uVal & UART_REG_FCR_FIFO_EN)
970 {
971 uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
972 if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
973 pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
974 else
975 pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
976 }
977
978 /* The FIFO reset bits are self clearing. */
979 pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
980 uartIrqUpdate(pThis);
981 }
982
983 /* Fill in the next data. */
984 if (ASMAtomicReadU32(&pThis->cbAvailRdr))
985 uartR3DataFetch(pThis);
986 }
987
988 return rc;
989#endif
990}
991
992
993/**
994 * Write handler for the LCR register.
995 *
996 * @returns VBox status code.
997 * @param pThis The serial port instance.
998 * @param uVal The value to write.
999 */
1000DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
1001{
1002 int rc = VINF_SUCCESS;
1003
1004 /* Any change except the DLAB bit causes a switch to R3. */
1005 if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
1006 {
1007#ifndef IN_RING3
1008 rc = VINF_IOM_R3_IOPORT_WRITE;
1009#else
1010 /* Check whether the BREAK bit changed before updating the LCR value. */
1011 bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
1012 bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
1013 pThis->uRegLcr = uVal;
1014 uartR3ParamsUpdate(pThis);
1015
1016 if ( fBrkChg
1017 && pThis->pDrvSerial)
1018 pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
1019#endif
1020 }
1021 else
1022 pThis->uRegLcr = uVal;
1023
1024 return rc;
1025}
1026
1027
1028/**
1029 * Write handler for the MCR register.
1030 *
1031 * @returns VBox status code.
1032 * @param pThis The serial port instance.
1033 * @param uVal The value to write.
1034 */
1035DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
1036{
1037 int rc = VINF_SUCCESS;
1038
1039 if (pThis->enmType < UARTTYPE_16750)
1040 uVal &= UART_REG_MCR_MASK_WR;
1041 else
1042 uVal &= UART_REG_MCR_MASK_WR_15750;
1043 if (pThis->uRegMcr != uVal)
1044 {
1045#ifndef IN_RING3
1046 rc = VINF_IOM_R3_IOPORT_WRITE;
1047#else
1048 /*
1049 * When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
1050 * disconnected and looped back to MSR.
1051 */
1052 if ( (uVal & UART_REG_MCR_LOOP)
1053 && !(pThis->uRegMcr & UART_REG_MCR_LOOP)
1054 && pThis->pDrvSerial)
1055 pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /*fRts*/, false /*fDtr*/);
1056
1057 pThis->uRegMcr = uVal;
1058 if (uVal & UART_REG_MCR_LOOP)
1059 {
1060 uint8_t uRegMsrSts = 0;
1061
1062 if (uVal & UART_REG_MCR_RTS)
1063 uRegMsrSts |= UART_REG_MSR_CTS;
1064 if (uVal & UART_REG_MCR_DTR)
1065 uRegMsrSts |= UART_REG_MSR_DSR;
1066 if (uVal & UART_REG_MCR_OUT1)
1067 uRegMsrSts |= UART_REG_MSR_RI;
1068 if (uVal & UART_REG_MCR_OUT2)
1069 uRegMsrSts |= UART_REG_MSR_DCD;
1070 uartR3MsrUpdate(pThis, uRegMsrSts);
1071 }
1072 else if (pThis->pDrvSerial)
1073 pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1074 RT_BOOL(uVal & UART_REG_MCR_RTS),
1075 RT_BOOL(uVal & UART_REG_MCR_DTR));
1076#endif
1077 }
1078
1079 return rc;
1080}
1081
1082
1083/**
1084 * Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1085 *
1086 * @returns VBox status code.
1087 * @param pThis The serial port instance.
1088 * @param puVal Where to store the read value on success.
1089 */
1090DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
1091{
1092 int rc = VINF_SUCCESS;
1093
1094 /* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1095 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1096 *puVal = pThis->uRegDivisor & 0xff;
1097 else
1098 {
1099 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1100 {
1101 /*
1102 * Only go back to R3 if there is new data available for the FIFO
1103 * and we would clear the interrupt to fill it up again.
1104 */
1105 if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1106 && ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1107 {
1108#ifndef IN_RING3
1109 rc = VINF_IOM_R3_IOPORT_READ;
1110#else
1111 uartR3RecvFifoFill(pThis);
1112#endif
1113 }
1114
1115 if (rc == VINF_SUCCESS)
1116 {
1117 *puVal = uartFifoGet(&pThis->FifoRecv);
1118 pThis->fIrqCtiPending = false;
1119 if (!pThis->FifoRecv.cbUsed)
1120 {
1121 TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
1122 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1123 }
1124 else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1125 TMTimerSetRelative(pThis->CTX_SUFF(pTimerRcvFifoTimeout), pThis->cSymbolXferTicks * 4, NULL);
1126 uartIrqUpdate(pThis);
1127 }
1128 }
1129 else
1130 {
1131 *puVal = pThis->uRegRbr;
1132
1133 if (pThis->uRegLsr & UART_REG_LSR_DR)
1134 {
1135 Assert(pThis->cbAvailRdr);
1136 uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1137 if (!cbAvail)
1138 {
1139 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1140 uartIrqUpdate(pThis);
1141 }
1142 else
1143 {
1144#ifndef IN_RING3
1145 /* Restore state and go back to R3. */
1146 ASMAtomicIncU32(&pThis->cbAvailRdr);
1147 rc = VINF_IOM_R3_IOPORT_READ;
1148#else
1149 /* Fetch new data and keep the DR bit set. */
1150 uartR3DataFetch(pThis);
1151#endif
1152 }
1153 }
1154 }
1155 }
1156
1157 return rc;
1158}
1159
1160
1161/**
1162 * Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1163 *
1164 * @returns VBox status code.
1165 * @param pThis The serial port instance.
1166 * @param puVal Where to store the read value on success.
1167 */
1168DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1169{
1170 int rc = VINF_SUCCESS;
1171
1172 /* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1173 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1174 *puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1175 else
1176 *puVal = pThis->uRegIer;
1177
1178 return rc;
1179}
1180
1181
1182/**
1183 * Read handler for the IIR register.
1184 *
1185 * @returns VBox status code.
1186 * @param pThis The serial port instance.
1187 * @param puVal Where to store the read value on success.
1188 */
1189DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1190{
1191 *puVal = pThis->uRegIir;
1192 /* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1193 if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1194 {
1195 pThis->fThreEmptyPending = false;
1196 uartIrqUpdate(pThis);
1197 }
1198 return VINF_SUCCESS;
1199}
1200
1201
1202/**
1203 * Read handler for the LSR register.
1204 *
1205 * @returns VBox status code.
1206 * @param pThis The serial port instance.
1207 * @param puVal Where to store the read value on success.
1208 */
1209DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1210{
1211 int rc = VINF_SUCCESS;
1212
1213 /* Yield if configured and there is no data available. */
1214 if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1215 && (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1216 {
1217#ifndef IN_RING3
1218 return VINF_IOM_R3_IOPORT_READ;
1219#else
1220 RTThreadYield();
1221#endif
1222 }
1223
1224 *puVal = pThis->uRegLsr;
1225 /*
1226 * Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1227 * as well as the Break Interrupt (BI).
1228 */
1229 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1230 uartIrqUpdate(pThis);
1231
1232 return rc;
1233}
1234
1235
1236/**
1237 * Read handler for the MSR register.
1238 *
1239 * @returns VBox status code.
1240 * @param pThis The serial port instance.
1241 * @param puVal Where to store the read value on success.
1242 */
1243DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1244{
1245 *puVal = pThis->uRegMsr;
1246
1247 /* Clear any of the delta bits. */
1248 UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1249 uartIrqUpdate(pThis);
1250 return VINF_SUCCESS;
1251}
1252
1253
1254#ifdef LOG_ENABLED
1255/**
1256 * Converts the register index into a sensible memnonic.
1257 *
1258 * @returns Register memnonic.
1259 * @param pThis The serial port instance.
1260 * @param idxReg Register index.
1261 * @param fWrite Flag whether the register gets written.
1262 */
1263DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1264{
1265 const char *psz = "INV";
1266
1267 switch (idxReg)
1268 {
1269 /*case UART_REG_THR_DLL_INDEX:*/
1270 case UART_REG_RBR_DLL_INDEX:
1271 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1272 psz = "DLL";
1273 else if (fWrite)
1274 psz = "THR";
1275 else
1276 psz = "RBR";
1277 break;
1278 case UART_REG_IER_DLM_INDEX:
1279 if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1280 psz = "DLM";
1281 else
1282 psz = "IER";
1283 break;
1284 /*case UART_REG_IIR_INDEX:*/
1285 case UART_REG_FCR_INDEX:
1286 if (fWrite)
1287 psz = "FCR";
1288 else
1289 psz = "IIR";
1290 break;
1291 case UART_REG_LCR_INDEX:
1292 psz = "LCR";
1293 break;
1294 case UART_REG_MCR_INDEX:
1295 psz = "MCR";
1296 break;
1297 case UART_REG_LSR_INDEX:
1298 psz = "LSR";
1299 break;
1300 case UART_REG_MSR_INDEX:
1301 psz = "MSR";
1302 break;
1303 case UART_REG_SCR_INDEX:
1304 psz = "SCR";
1305 break;
1306 }
1307
1308 return psz;
1309}
1310#endif
1311
1312
1313DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1314{
1315 AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1316
1317 int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1318 if (rc != VINF_SUCCESS)
1319 return rc;
1320
1321 uint8_t idxReg = uReg & 0x7;
1322 LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1323 pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /*fWrite*/), u32, cb));
1324
1325 uint8_t uVal = (uint8_t)u32;
1326 switch (idxReg)
1327 {
1328 case UART_REG_THR_DLL_INDEX:
1329 rc = uartRegThrDllWrite(pThis, uVal);
1330 break;
1331 case UART_REG_IER_DLM_INDEX:
1332 rc = uartRegIerDlmWrite(pThis, uVal);
1333 break;
1334 case UART_REG_FCR_INDEX:
1335 rc = uartRegFcrWrite(pThis, uVal);
1336 break;
1337 case UART_REG_LCR_INDEX:
1338 rc = uartRegLcrWrite(pThis, uVal);
1339 break;
1340 case UART_REG_MCR_INDEX:
1341 rc = uartRegMcrWrite(pThis, uVal);
1342 break;
1343 case UART_REG_SCR_INDEX:
1344 pThis->uRegScr = u32;
1345 break;
1346 default:
1347 break;
1348 }
1349
1350 PDMCritSectLeave(&pThis->CritSect);
1351 LogFlowFunc(("-> %Rrc\n", rc));
1352 return rc;
1353}
1354
1355
1356DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1357{
1358 if (cb != 1)
1359 return VERR_IOM_IOPORT_UNUSED;
1360
1361 int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1362 if (rc != VINF_SUCCESS)
1363 return rc;
1364
1365 uint8_t idxReg = uReg & 0x7;
1366 switch (idxReg)
1367 {
1368 case UART_REG_RBR_DLL_INDEX:
1369 rc = uartRegRbrDllRead(pThis, pu32);
1370 break;
1371 case UART_REG_IER_DLM_INDEX:
1372 rc = uartRegIerDlmRead(pThis, pu32);
1373 break;
1374 case UART_REG_IIR_INDEX:
1375 rc = uartRegIirRead(pThis, pu32);
1376 break;
1377 case UART_REG_LCR_INDEX:
1378 *pu32 = pThis->uRegLcr;
1379 break;
1380 case UART_REG_MCR_INDEX:
1381 *pu32 = pThis->uRegMcr;
1382 break;
1383 case UART_REG_LSR_INDEX:
1384 rc = uartRegLsrRead(pThis, pu32);
1385 break;
1386 case UART_REG_MSR_INDEX:
1387 rc = uartRegMsrRead(pThis, pu32);
1388 break;
1389 case UART_REG_SCR_INDEX:
1390 *pu32 = pThis->uRegScr;
1391 break;
1392 default:
1393 rc = VERR_IOM_IOPORT_UNUSED;
1394 }
1395
1396 PDMCritSectLeave(&pThis->CritSect);
1397 LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1398 pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /*fWrite*/), *pu32, cb, rc));
1399 return rc;
1400}
1401
1402
1403#ifdef IN_RING3
1404
1405/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1406
1407/**
1408 * @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1409 */
1410static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1411{
1412 LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1413 RT_NOREF(pDevIns, pTimer);
1414 PUARTCORE pThis = (PUARTCORE)pvUser;
1415 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1416 if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
1417 {
1418 pThis->fIrqCtiPending = true;
1419 uartIrqUpdate(pThis);
1420 }
1421 PDMCritSectLeave(&pThis->CritSect);
1422}
1423
1424/**
1425 * @callback_method_impl{FNTMTIMERDEV, TX timer function when there is no driver connected for draining the THR/FIFO.}
1426 */
1427static DECLCALLBACK(void) uartR3TxUnconnectedTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1428{
1429 LogFlowFunc(("pDevIns=%#p pTimer=%#p pvUser=%#p\n", pDevIns, pTimer, pvUser));
1430 RT_NOREF(pDevIns, pTimer);
1431 PUARTCORE pThis = (PUARTCORE)pvUser;
1432 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1433 uint8_t bIgnore = 0;
1434 size_t cbRead = 0;
1435 uartR3TxQueueCopyFrom(pThis, &bIgnore, sizeof(uint8_t), &cbRead);
1436 if (cbRead == 1)
1437 TMTimerSetRelative(pThis->CTX_SUFF(pTimerTxUnconnected), pThis->cSymbolXferTicks, NULL);
1438 PDMCritSectLeave(&pThis->CritSect);
1439}
1440
1441
1442/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1443
1444
1445/**
1446 * @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1447 */
1448static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1449{
1450 LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1451 PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1452
1453 AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1454
1455 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1456 uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1457 LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1458 if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1459 uartR3RecvFifoFill(pThis);
1460 else if (!cbAvailOld)
1461 {
1462 size_t cbRead = 0;
1463 int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1464 AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1465 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1466 uartIrqUpdate(pThis);
1467 }
1468 PDMCritSectLeave(&pThis->CritSect);
1469
1470 return VINF_SUCCESS;
1471}
1472
1473
1474/**
1475 * @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1476 */
1477static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1478{
1479 LogFlowFunc(("pInterface=%#p\n", pInterface));
1480 PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1481
1482 /* Set the transmitter empty bit because everything was sent. */
1483 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1484 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1485 uartIrqUpdate(pThis);
1486 PDMCritSectLeave(&pThis->CritSect);
1487 return VINF_SUCCESS;
1488}
1489
1490
1491/**
1492 * @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1493 */
1494static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void *pvBuf, size_t cbRead, size_t *pcbRead)
1495{
1496 LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1497 PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1498
1499 AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1500
1501 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1502 uartR3TxQueueCopyFrom(pThis, pvBuf, cbRead, pcbRead);
1503 PDMCritSectLeave(&pThis->CritSect);
1504
1505 LogFlowFunc(("-> VINF_SUCCESS{*pcbRead=%zu}\n", *pcbRead));
1506 return VINF_SUCCESS;
1507}
1508
1509
1510/**
1511 * @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1512 */
1513static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1514{
1515 LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1516 PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1517
1518 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1519 uartR3StsLinesUpdate(pThis, fNewStatusLines);
1520 PDMCritSectLeave(&pThis->CritSect);
1521 return VINF_SUCCESS;
1522}
1523
1524
1525/**
1526 * @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1527 */
1528static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1529{
1530 LogFlowFunc(("pInterface=%#p\n", pInterface));
1531 PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1532
1533 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1534 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1535 uartIrqUpdate(pThis);
1536 PDMCritSectLeave(&pThis->CritSect);
1537 return VINF_SUCCESS;
1538}
1539
1540
1541/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1542
1543/**
1544 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1545 */
1546static DECLCALLBACK(void *) uartR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1547{
1548 PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1549 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1550 PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1551 return NULL;
1552}
1553
1554
1555DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1556{
1557 SSMR3PutU16(pSSM, pThis->uRegDivisor);
1558 SSMR3PutU8(pSSM, pThis->uRegRbr);
1559 SSMR3PutU8(pSSM, pThis->uRegThr);
1560 SSMR3PutU8(pSSM, pThis->uRegIer);
1561 SSMR3PutU8(pSSM, pThis->uRegIir);
1562 SSMR3PutU8(pSSM, pThis->uRegFcr);
1563 SSMR3PutU8(pSSM, pThis->uRegLcr);
1564 SSMR3PutU8(pSSM, pThis->uRegMcr);
1565 SSMR3PutU8(pSSM, pThis->uRegLsr);
1566 SSMR3PutU8(pSSM, pThis->uRegMsr);
1567 SSMR3PutU8(pSSM, pThis->uRegScr);
1568 SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1569 SSMR3PutBool(pSSM, pThis->fThreEmptyPending);
1570 SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1571 SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1572 SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1573 SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1574
1575 int rc = TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1576 if (RT_SUCCESS(rc))
1577 rc = TMR3TimerSave(pThis->pTimerTxUnconnectedR3, pSSM);
1578
1579 return rc;
1580}
1581
1582
1583DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1584 uint8_t *puIrq, RTIOPORT *pPortBase)
1585{
1586 RT_NOREF(uPass);
1587 int rc = VINF_SUCCESS;
1588
1589 if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1590 {
1591 SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1592 SSMR3GetU8(pSSM, &pThis->uRegRbr);
1593 SSMR3GetU8(pSSM, &pThis->uRegThr);
1594 SSMR3GetU8(pSSM, &pThis->uRegIer);
1595 SSMR3GetU8(pSSM, &pThis->uRegIir);
1596 SSMR3GetU8(pSSM, &pThis->uRegFcr);
1597 SSMR3GetU8(pSSM, &pThis->uRegLcr);
1598 SSMR3GetU8(pSSM, &pThis->uRegMcr);
1599 SSMR3GetU8(pSSM, &pThis->uRegLsr);
1600 SSMR3GetU8(pSSM, &pThis->uRegMsr);
1601 SSMR3GetU8(pSSM, &pThis->uRegScr);
1602 SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1603 SSMR3GetBool(pSSM, &pThis->fThreEmptyPending);
1604 SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1605 SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1606 SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1607 SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1608
1609 TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1610 if (uVersion > UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER)
1611 TMR3TimerLoad(pThis->pTimerTxUnconnectedR3, pSSM);
1612 }
1613 else
1614 {
1615 if (uVersion == UART_SAVED_STATE_VERSION_16450)
1616 {
1617 pThis->enmType = UARTTYPE_16450;
1618 LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1619 }
1620
1621 int uIrq;
1622 int32_t iTmp;
1623 uint32_t PortBase;
1624
1625 SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1626 SSMR3GetU8(pSSM, &pThis->uRegRbr);
1627 SSMR3GetU8(pSSM, &pThis->uRegIer);
1628 SSMR3GetU8(pSSM, &pThis->uRegLcr);
1629 SSMR3GetU8(pSSM, &pThis->uRegMcr);
1630 SSMR3GetU8(pSSM, &pThis->uRegLsr);
1631 SSMR3GetU8(pSSM, &pThis->uRegMsr);
1632 SSMR3GetU8(pSSM, &pThis->uRegScr);
1633 if (uVersion > UART_SAVED_STATE_VERSION_16450)
1634 SSMR3GetU8(pSSM, &pThis->uRegFcr);
1635 SSMR3GetS32(pSSM, &iTmp);
1636 pThis->fThreEmptyPending = RT_BOOL(iTmp);
1637 SSMR3GetS32(pSSM, &uIrq);
1638 SSMR3Skip(pSSM, sizeof(int32_t));
1639 SSMR3GetU32(pSSM, &PortBase);
1640 rc = SSMR3Skip(pSSM, sizeof(int32_t));
1641
1642 if ( RT_SUCCESS(rc)
1643 && uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1644 {
1645 SSMR3GetU8(pSSM, &pThis->uRegThr);
1646 SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1647 SSMR3GetU8(pSSM, &pThis->uRegIir);
1648
1649 int iTimeoutPending = 0;
1650 SSMR3GetS32(pSSM, &iTimeoutPending);
1651 pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1652
1653 TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1654 TMR3TimerSkip(pSSM, NULL);
1655 SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1656 rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1657 }
1658
1659 if (RT_SUCCESS(rc))
1660 {
1661 AssertPtr(puIrq);
1662 AssertPtr(pPortBase);
1663 *puIrq = (uint8_t)uIrq;
1664 *pPortBase = (RTIOPORT)PortBase;
1665 }
1666 }
1667
1668 return rc;
1669}
1670
1671
1672DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1673{
1674 RT_NOREF(pSSM);
1675
1676 uartR3ParamsUpdate(pThis);
1677 uartIrqUpdate(pThis);
1678
1679 if (pThis->pDrvSerial)
1680 {
1681 /* Set the modem lines to reflect the current state. */
1682 int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1683 RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1684 RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1685 if (RT_FAILURE(rc))
1686 LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1687 pThis->pDevInsR3->iInstance, rc));
1688
1689 uint32_t fStsLines = 0;
1690 rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1691 if (RT_SUCCESS(rc))
1692 uartR3StsLinesUpdate(pThis, fStsLines);
1693 else
1694 LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1695 pThis->pDevInsR3->iInstance, rc));
1696 }
1697
1698 return VINF_SUCCESS;
1699}
1700
1701
1702DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1703{
1704 RT_NOREF(offDelta);
1705 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1706 pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1707 pThis->pTimerTxUnconnectedRC = TMTimerRCPtr(pThis->pTimerTxUnconnectedR3);
1708}
1709
1710
1711DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1712{
1713 pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1714 pThis->uRegRbr = 0;
1715 pThis->uRegThr = 0;
1716 pThis->uRegIer = 0;
1717 pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1718 pThis->uRegFcr = 0;
1719 pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1720 pThis->uRegMcr = 0;
1721 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
1722 pThis->uRegMsr = 0; /* Updated below. */
1723 pThis->uRegScr = 0;
1724 pThis->fIrqCtiPending = false;
1725 pThis->fThreEmptyPending = true;
1726
1727 /* Standard FIFO size for 15550A. */
1728 pThis->FifoXmit.cbMax = 16;
1729 pThis->FifoRecv.cbMax = 16;
1730 pThis->FifoRecv.cbItl = 1;
1731
1732 uartR3XferReset(pThis);
1733}
1734
1735
1736DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1737{
1738 int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1739 if (RT_SUCCESS(rc))
1740 {
1741 pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1742 if (!pThis->pDrvSerial)
1743 {
1744 AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1745 return VERR_PDM_MISSING_INTERFACE;
1746 }
1747 uartR3XferReset(pThis);
1748 }
1749 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1750 {
1751 pThis->pDrvBase = NULL;
1752 pThis->pDrvSerial = NULL;
1753 rc = VINF_SUCCESS;
1754 uartR3XferReset(pThis);
1755 LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1756 }
1757 else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1758 LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1759
1760 return rc;
1761}
1762
1763
1764DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1765{
1766 /* Zero out important members. */
1767 pThis->pDrvBase = NULL;
1768 pThis->pDrvSerial = NULL;
1769 uartR3XferReset(pThis);
1770}
1771
1772
1773DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1774{
1775 PDMR3CritSectDelete(&pThis->CritSect);
1776}
1777
1778
1779DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1780 R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1781 RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1782{
1783 int rc = VINF_SUCCESS;
1784
1785 /*
1786 * Initialize the instance data.
1787 * (Do this early or the destructor might choke on something!)
1788 */
1789 pThis->pDevInsR3 = pDevInsR3;
1790 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1791 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1792 pThis->iLUN = iLUN;
1793 pThis->enmType = enmType;
1794 pThis->fFlags = fFlags;
1795 pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1796 pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1797 pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1798
1799 /* IBase */
1800 pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1801
1802 /* ISerialPort */
1803 pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1804 pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1805 pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1806 pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1807 pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1808
1809 rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1810 pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1811 AssertRCReturn(rc, rc);
1812
1813 /*
1814 * Attach the char driver and get the interfaces.
1815 */
1816 rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1817 if (RT_SUCCESS(rc))
1818 {
1819 pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1820 if (!pThis->pDrvSerial)
1821 {
1822 AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1823 return VERR_PDM_MISSING_INTERFACE;
1824 }
1825 }
1826 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1827 {
1828 pThis->pDrvBase = NULL;
1829 pThis->pDrvSerial = NULL;
1830 LogRel(("Serial#%d: no unit\n", iLUN));
1831 }
1832 else
1833 {
1834 AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1835 /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1836 return rc;
1837 }
1838
1839 /*
1840 * Create the receive FIFO character timeout indicator timer.
1841 */
1842 rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1843 TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1844 &pThis->pTimerRcvFifoTimeoutR3);
1845 AssertRCReturn(rc, rc);
1846
1847 rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1848 AssertRCReturn(rc, rc);
1849
1850 pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1851 pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1852
1853 /*
1854 * Create the transmit timer when no device is connected.
1855 */
1856 rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3TxUnconnectedTimer, pThis,
1857 TMTIMER_FLAGS_NO_CRIT_SECT, "UART TX uncon. Timer",
1858 &pThis->pTimerTxUnconnectedR3);
1859 AssertRCReturn(rc, rc);
1860
1861 rc = TMR3TimerSetCritSect(pThis->pTimerTxUnconnectedR3, &pThis->CritSect);
1862 AssertRCReturn(rc, rc);
1863
1864 pThis->pTimerTxUnconnectedR0 = TMTimerR0Ptr(pThis->pTimerTxUnconnectedR3);
1865 pThis->pTimerTxUnconnectedRC = TMTimerRCPtr(pThis->pTimerTxUnconnectedR3);
1866
1867 uartR3Reset(pThis);
1868 return VINF_SUCCESS;
1869}
1870
1871#endif /* IN_RING3 */
1872
1873#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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