UartCore.cpp@ 73636

Last change on this file since 73636 was 73636, checked in by vboxsync, 7 years ago
Devices/Serial: Fix Widows guests, the THRE empty interrupt status is only returned once to the guest every time it occurs
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1	/* $Id: UartCore.cpp 73636 2018-08-13 13:07:26Z vboxsync $ */
2	/** @file
3	* UartCore - UART (16550A up to 16950) emulation.
4	*
5	* The documentation for this device was taken from the PC16550D spec from TI.
6	*/
7
8	/*
9	* Copyright (C) 2018 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25	#include <VBox/vmm/tm.h>
26	#include <iprt/log.h>
27	#include <iprt/uuid.h>
28	#include <iprt/assert.h>
29
30	#include "VBoxDD.h"
31	#include "UartCore.h"
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37
38	/** The RBR/DLL register index (from the base of the port range). */
39	#define UART_REG_RBR_DLL_INDEX 0
40
41	/** The THR/DLL register index (from the base of the port range). */
42	#define UART_REG_THR_DLL_INDEX 0
43
44	/** The IER/DLM register index (from the base of the port range). */
45	#define UART_REG_IER_DLM_INDEX 1
46	/** Enable received data available interrupt */
47	# define UART_REG_IER_ERBFI RT_BIT(0)
48	/** Enable transmitter holding register empty interrupt */
49	# define UART_REG_IER_ETBEI RT_BIT(1)
50	/** Enable receiver line status interrupt */
51	# define UART_REG_IER_ELSI RT_BIT(2)
52	/** Enable modem status interrupt. */
53	# define UART_REG_IER_EDSSI RT_BIT(3)
54	/** Sleep mode enable. */
55	# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56	/** Low power mode enable. */
57	# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58	/** Mask of writeable bits. */
59	# define UART_REG_IER_MASK_WR 0x0f
60	/** Mask of writeable bits for 16750+. */
61	# define UART_REG_IER_MASK_WR_16750 0x3f
62
63	/** The IIR register index (from the base of the port range). */
64	#define UART_REG_IIR_INDEX 2
65	/** Interrupt Pending - high means no interrupt pending. */
66	# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67	/** Interrupt identification mask. */
68	# define UART_REG_IIR_ID_MASK 0x0e
69	/** Sets the interrupt identification to the given value. */
70	# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71	/** Gets the interrupt identification from the given IIR register value. */
72	# define UART_REG_IIR_ID_GET(a_Val) (((a_Val) >> 1) & UART_REG_IIR_ID_MASK)
73	/** Receiver Line Status interrupt. */
74	# define UART_REG_IIR_ID_RCL 0x3
75	/** Received Data Available interrupt. */
76	# define UART_REG_IIR_ID_RDA 0x2
77	/** Character Timeou Indicator interrupt. */
78	# define UART_REG_IIR_ID_CTI 0x6
79	/** Transmitter Holding Register Empty interrupt. */
80	# define UART_REG_IIR_ID_THRE 0x1
81	/** Modem Status interrupt. */
82	# define UART_REG_IIR_ID_MS 0x0
83	/** 64 byte FIFOs enabled (15750+ only). */
84	# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
85	/** FIFOs enabled. */
86	# define UART_REG_IIR_FIFOS_EN 0xc0
87	/** Bits relevant for checking whether the interrupt status has changed. */
88	# define UART_REG_IIR_CHANGED_MASK 0x0f
89
90	/** The FCR register index (from the base of the port range). */
91	#define UART_REG_FCR_INDEX 2
92	/** Enable the TX/RX FIFOs. */
93	# define UART_REG_FCR_FIFO_EN RT_BIT(0)
94	/** Reset the receive FIFO. */
95	# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
96	/** Reset the transmit FIFO. */
97	# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
98	/** DMA Mode Select. */
99	# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
100	/** 64 Byte FIFO enable (15750+ only). */
101	# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
102	/** Receiver level interrupt trigger. */
103	# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
104	/** Returns the receive level trigger value from the given FCR register. */
105	# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
106	/** RCV Interrupt trigger level - 1 byte. */
107	# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
108	/** RCV Interrupt trigger level - 4 bytes. */
109	# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
110	/** RCV Interrupt trigger level - 8 bytes. */
111	# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
112	/** RCV Interrupt trigger level - 14 bytes. */
113	# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
114	/** Mask of writeable bits. */
115	# define UART_REG_FCR_MASK_WR 0xcf
116	/** Mask of sticky bits. */
117	# define UART_REG_FCR_MASK_STICKY 0xe9
118
119	/** The LCR register index (from the base of the port range). */
120	#define UART_REG_LCR_INDEX 3
121	/** Word Length Select Mask. */
122	# define UART_REG_LCR_WLS_MASK 0x3
123	/** Returns the WLS value form the given LCR register value. */
124	# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
125	/** Number of stop bits. */
126	# define UART_REG_LCR_STB RT_BIT(2)
127	/** Parity Enable. */
128	# define UART_REG_LCR_PEN RT_BIT(3)
129	/** Even Parity. */
130	# define UART_REG_LCR_EPS RT_BIT(4)
131	/** Stick parity. */
132	# define UART_REG_LCR_PAR_STICK RT_BIT(5)
133	/** Set Break. */
134	# define UART_REG_LCR_BRK_SET RT_BIT(6)
135	/** Divisor Latch Access Bit. */
136	# define UART_REG_LCR_DLAB RT_BIT(7)
137
138	/** The MCR register index (from the base of the port range). */
139	#define UART_REG_MCR_INDEX 4
140	/** Data Terminal Ready. */
141	# define UART_REG_MCR_DTR RT_BIT(0)
142	/** Request To Send. */
143	# define UART_REG_MCR_RTS RT_BIT(1)
144	/** Out1. */
145	# define UART_REG_MCR_OUT1 RT_BIT(2)
146	/** Out2. */
147	# define UART_REG_MCR_OUT2 RT_BIT(3)
148	/** Loopback connection. */
149	# define UART_REG_MCR_LOOP RT_BIT(4)
150	/** Flow Control Enable (15750+ only). */
151	# define UART_REG_MCR_AFE RT_BIT(5)
152	/** Mask of writeable bits (15450 and 15550A). */
153	# define UART_REG_MCR_MASK_WR 0x1f
154	/** Mask of writeable bits (15750+). */
155	# define UART_REG_MCR_MASK_WR_15750 0x3f
156
157	/** The LSR register index (from the base of the port range). */
158	#define UART_REG_LSR_INDEX 5
159	/** Data Ready. */
160	# define UART_REG_LSR_DR RT_BIT(0)
161	/** Overrun Error. */
162	# define UART_REG_LSR_OE RT_BIT(1)
163	/** Parity Error. */
164	# define UART_REG_LSR_PE RT_BIT(2)
165	/** Framing Error. */
166	# define UART_REG_LSR_FE RT_BIT(3)
167	/** Break Interrupt. */
168	# define UART_REG_LSR_BI RT_BIT(4)
169	/** Transmitter Holding Register. */
170	# define UART_REG_LSR_THRE RT_BIT(5)
171	/** Transmitter Empty. */
172	# define UART_REG_LSR_TEMT RT_BIT(6)
173	/** Error in receiver FIFO. */
174	# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
175	/** The bits to check in this register when checking for the RCL interrupt. */
176	# define UART_REG_LSR_BITS_IIR_RCL 0x1e
177
178	/** The MSR register index (from the base of the port range). */
179	#define UART_REG_MSR_INDEX 6
180	/** Delta Clear to Send. */
181	# define UART_REG_MSR_DCTS RT_BIT(0)
182	/** Delta Data Set Ready. */
183	# define UART_REG_MSR_DDSR RT_BIT(1)
184	/** Trailing Edge Ring Indicator. */
185	# define UART_REG_MSR_TERI RT_BIT(2)
186	/** Delta Data Carrier Detect. */
187	# define UART_REG_MSR_DDCD RT_BIT(3)
188	/** Clear to Send. */
189	# define UART_REG_MSR_CTS RT_BIT(4)
190	/** Data Set Ready. */
191	# define UART_REG_MSR_DSR RT_BIT(5)
192	/** Ring Indicator. */
193	# define UART_REG_MSR_RI RT_BIT(6)
194	/** Data Carrier Detect. */
195	# define UART_REG_MSR_DCD RT_BIT(7)
196	/** The bits to check in this register when checking for the MS interrupt. */
197	# define UART_REG_MSR_BITS_IIR_MS 0x0f
198
199	/** The SCR register index (from the base of the port range). */
200	#define UART_REG_SCR_INDEX 7
201
202	/** Set the specified bits in the given register. */
203	#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) \|= (a_Set))
204	/** Clear the specified bits in the given register. */
205	#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
206
207
208	/*********************************************************************************************************************************
209	* Structures and Typedefs *
210	*********************************************************************************************************************************/
211
212	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
213
214
215	/*********************************************************************************************************************************
216	* Global Variables *
217	*********************************************************************************************************************************/
218
219	#ifdef IN_RING3
220	/**
221	* FIFO ITL levels.
222	*/
223	static struct
224	{
225	/** ITL level for a 16byte FIFO. */
226	uint8_t cbItl16;
227	/** ITL level for a 64byte FIFO. */
228	uint8_t cbItl64;
229	} s_aFifoItl[] =
230	{
231	/* cbItl16 cbItl64 */
232	{ 1, 1 },
233	{ 4, 16 },
234	{ 8, 32 },
235	{ 14, 56 }
236	};
237
238
239	/**
240	* String versions of the parity enum.
241	*/
242	static const char *s_aszParity[] =
243	{
244	"INVALID",
245	"NONE",
246	"EVEN",
247	"ODD",
248	"MARK",
249	"SPACE",
250	"INVALID"
251	};
252
253
254	/**
255	* String versions of the stop bits enum.
256	*/
257	static const char *s_aszStopBits[] =
258	{
259	"INVALID",
260	"1",
261	"1.5",
262	"2",
263	"INVALID"
264	};
265	#endif
266
267
268	/*********************************************************************************************************************************
269	* Internal Functions *
270	*********************************************************************************************************************************/
271
272
273	/**
274	* Updates the IRQ state based on the current device state.
275	*
276	* @returns nothing.
277	* @param pThis The UART core instance.
278	*/
279	static void uartIrqUpdate(PUARTCORE pThis)
280	{
281	LogFlowFunc(("pThis=%#p\n", pThis));
282
283	/*
284	* The interrupt uses a priority scheme, only the interrupt with the
285	* highest priority is indicated in the interrupt identification register.
286	*
287	* The priorities are as follows (high to low):
288	* * Receiver line status
289	* * Received data available
290	* * Character timeout indication (only in FIFO mode).
291	* * Transmitter holding register empty
292	* * Modem status change.
293	*/
294	uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
295	if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
296	&& (pThis->uRegIer & UART_REG_IER_ELSI))
297	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
298	else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
299	&& pThis->fIrqCtiPending)
300	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
301	else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
302	&& (pThis->uRegIer & UART_REG_IER_ERBFI)
303	&& ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
304	\|\| pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
305	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
306	else if ( (pThis->uRegLsr & UART_REG_LSR_THRE)
307	&& pThis->fThreEmptyPending)
308	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
309	else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
310	&& (pThis->uRegIer & UART_REG_IER_EDSSI))
311	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
312
313	LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
314
315	/* Change interrupt only if the interrupt status really changed from the previous value. */
316	if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
317	{
318	LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
319	pThis->uRegIir, uRegIirNew,
320	pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
321	uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
322	if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
323	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
324	else
325	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
326	}
327	else
328	LogFlow((" No change in interrupt source\n"));
329
330	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
331	uRegIirNew \|= UART_REG_IIR_FIFOS_EN;
332	if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
333	uRegIirNew \|= UART_REG_IIR_64BYTE_FIFOS_EN;
334
335	pThis->uRegIir = uRegIirNew;
336	}
337
338
339	#ifdef IN_RING3
340	/**
341	* Clears the given FIFO.
342	*
343	* @returns nothing.
344	* @param pFifo The FIFO to clear.
345	*/
346	DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
347	{
348	memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
349	pFifo->cbUsed = 0;
350	pFifo->offWrite = 0;
351	pFifo->offRead = 0;
352	}
353
354
355	/**
356	* Returns the amount of free bytes in the given FIFO.
357	*
358	* @returns The amount of bytes free in the given FIFO.
359	* @param pFifo The FIFO.
360	*/
361	DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
362	{
363	return pFifo->cbMax - pFifo->cbUsed;
364	}
365
366
367	/**
368	* Puts a new character into the given FIFO.
369	*
370	* @returns Flag whether the FIFO overflowed.
371	* @param pFifo The FIFO to put the data into.
372	* @param fOvrWr Flag whether to overwrite data if the FIFO is full.
373	* @param bData The data to add.
374	*/
375	DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
376	{
377	if (fOvrWr \|\| pFifo->cbUsed < pFifo->cbMax)
378	{
379	pFifo->abBuf[pFifo->offWrite] = bData;
380	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
381	}
382
383	bool fOverFlow = false;
384	if (pFifo->cbUsed < pFifo->cbMax)
385	pFifo->cbUsed++;
386	else
387	{
388	fOverFlow = true;
389	if (fOvrWr) /* Advance the read position to account for the lost character. */
390	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
391	}
392
393	return fOverFlow;
394	}
395	#endif
396
397
398	/**
399	* Returns the next character in the FIFO.
400	*
401	* @return Next byte in the FIFO.
402	* @param pFifo The FIFO to get data from.
403	*/
404	DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
405	{
406	uint8_t bRet = 0;
407
408	if (pFifo->cbUsed)
409	{
410	bRet = pFifo->abBuf[pFifo->offRead];
411	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
412	pFifo->cbUsed--;
413	}
414
415	return bRet;
416	}
417
418
419	#ifdef IN_RING3
420	/**
421	* Tries to copy the requested amount of data from the given FIFO into the provided buffer.
422	*
423	* @returns Amount of bytes actually copied.
424	* @param pFifo The FIFO to copy data from.
425	* @param pvDst Where to copy the data to.
426	* @param cbCopy How much to copy.
427	*/
428	DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
429	{
430	size_t cbCopied = 0;
431	uint8_t pbDst = (uint8_t )pvDst;
432
433	cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
434	while (cbCopy)
435	{
436	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
437	memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
438
439	pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
440	pFifo->cbUsed -= cbThisCopy;
441	pbDst += cbThisCopy;
442	cbCopied += cbThisCopy;
443	cbCopy -= cbThisCopy;
444	}
445
446	return cbCopied;
447	}
448
449
450	#if 0 /* unused */
451	/**
452	* Tries to copy the requested amount of data from the provided buffer into the given FIFO.
453	*
454	* @returns Amount of bytes actually copied.
455	* @param pFifo The FIFO to copy data to.
456	* @param pvSrc Where to copy the data from.
457	* @param cbCopy How much to copy.
458	*/
459	DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
460	{
461	size_t cbCopied = 0;
462	uint8_t pbSrc = (uint8_t )pvSrc;
463
464	cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
465	while (cbCopy)
466	{
467	uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
468	memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
469
470	pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
471	pFifo->cbUsed += cbThisCopy;
472	pbSrc += cbThisCopy;
473	cbCopied += cbThisCopy;
474	cbCopy -= cbThisCopy;
475	}
476
477	return cbCopied;
478	}
479	#endif
480
481
482	/**
483	* Updates the delta bits for the given MSR register value which has the status line
484	* bits set.
485	*
486	* @returns nothing.
487	* @param pThis The serial port instance.
488	* @param uMsrSts MSR value with the appropriate status bits set.
489	*/
490	static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
491	{
492	/* Compare current and new states and set remaining bits accordingly. */
493	if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
494	uMsrSts \|= UART_REG_MSR_DCTS;
495	if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
496	uMsrSts \|= UART_REG_MSR_DDSR;
497	if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
498	uMsrSts \|= UART_REG_MSR_TERI;
499	if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
500	uMsrSts \|= UART_REG_MSR_DDCD;
501
502	pThis->uRegMsr = uMsrSts;
503
504	uartIrqUpdate(pThis);
505	}
506
507
508	/**
509	* Updates the serial port parameters of the attached driver with the current configuration.
510	*
511	* @returns nothing.
512	* @param pThis The serial port instance.
513	*/
514	static void uartR3ParamsUpdate(PUARTCORE pThis)
515	{
516	if ( pThis->uRegDivisor != 0
517	&& pThis->pDrvSerial)
518	{
519	uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
520	unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
521	uint32_t cFrameBits = cDataBits;
522	PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
523	PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
524
525	if (pThis->uRegLcr & UART_REG_LCR_STB)
526	{
527	enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
528	cFrameBits += 2;
529	}
530	else
531	cFrameBits++;
532
533	if (pThis->uRegLcr & UART_REG_LCR_PEN)
534	{
535	/* Select the correct parity mode based on the even and stick parity bits. */
536	switch (pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK))
537	{
538	case 0:
539	enmParity = PDMSERIALPARITY_ODD;
540	break;
541	case UART_REG_LCR_EPS:
542	enmParity = PDMSERIALPARITY_EVEN;
543	break;
544	case UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK:
545	enmParity = PDMSERIALPARITY_SPACE;
546	break;
547	case UART_REG_LCR_PAR_STICK:
548	enmParity = PDMSERIALPARITY_MARK;
549	break;
550	default:
551	/* We should never get here as all cases where caught earlier. */
552	AssertMsgFailed(("This shouldn't happen at all: %#x\n",
553	pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK)));
554	}
555
556	cFrameBits++;
557	}
558
559	uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
560	pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
561
562	LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
563	uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
564
565	int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
566	if (RT_FAILURE(rc))
567	LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
568	pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
569
570	/* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
571	ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
572	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
573	}
574	}
575
576
577	/**
578	* Updates the internal device state with the given PDM status line states.
579	*
580	* @returns nothing.
581	* @param pThis The serial port instance.
582	* @param fStsLines The PDM status line states.
583	*/
584	static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
585	{
586	uint8_t uRegMsrNew = 0; /* The new MSR value. */
587
588	if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
589	uRegMsrNew \|= UART_REG_MSR_DCD;
590	if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
591	uRegMsrNew \|= UART_REG_MSR_RI;
592	if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
593	uRegMsrNew \|= UART_REG_MSR_DSR;
594	if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
595	uRegMsrNew \|= UART_REG_MSR_CTS;
596
597	uartR3MsrUpdate(pThis, uRegMsrNew);
598	}
599
600
601	/**
602	* Fills up the receive FIFO with as much data as possible.
603	*
604	* @returns nothing.
605	* @param pThis The serial port instance.
606	*/
607	static void uartR3RecvFifoFill(PUARTCORE pThis)
608	{
609	LogFlowFunc(("pThis=%#p\n", pThis));
610
611	PUARTFIFO pFifo = &pThis->FifoRecv;
612	size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
613	ASMAtomicReadU32(&pThis->cbAvailRdr));
614	size_t cbFilled = 0;
615
616	while (cbFilled < cbFill)
617	{
618	size_t cbThisRead = cbFill - cbFilled;
619
620	if (pFifo->offRead <= pFifo->offWrite)
621	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
622	else
623	cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
624
625	size_t cbRead = 0;
626	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
627	AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
628
629	pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
630	pFifo->cbUsed += (uint8_t)cbRead;
631	cbFilled += cbRead;
632
633	if (cbRead < cbThisRead)
634	break;
635	}
636
637	if (cbFilled)
638	{
639	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
640	uartIrqUpdate(pThis);
641	}
642
643	Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
644	ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
645	}
646
647
648	/**
649	* Fetches a single byte and writes it to RBR.
650	*
651	* @returns nothing.
652	* @param pThis The serial port instance.
653	*/
654	static void uartR3ByteFetch(PUARTCORE pThis)
655	{
656	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
657	{
658	AssertPtr(pThis->pDrvSerial);
659	size_t cbRead = 0;
660	int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
661	AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
662	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
663	uartIrqUpdate(pThis);
664	}
665	}
666
667
668	/**
669	* Fetches a ready data based on the FIFO setting.
670	*
671	* @returns nothing.
672	* @param pThis The serial port instance.
673	*/
674	static void uartR3DataFetch(PUARTCORE pThis)
675	{
676	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
677	uartR3RecvFifoFill(pThis);
678	else
679	uartR3ByteFetch(pThis);
680	}
681
682
683	/**
684	* Reset the transmit/receive related bits to the standard values
685	* (after a detach/attach/reset event).
686	*
687	* @returns nothing.
688	* @param pThis The serial port instance.
689	*/
690	static void uartR3XferReset(PUARTCORE pThis)
691	{
692	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
693	pThis->fThreEmptyPending = false;
694
695	uartFifoClear(&pThis->FifoXmit);
696	uartFifoClear(&pThis->FifoRecv);
697	uartR3ParamsUpdate(pThis);
698	uartIrqUpdate(pThis);
699
700	if (pThis->pDrvSerial)
701	{
702	/* Set the modem lines to reflect the current state. */
703	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
704	if (RT_FAILURE(rc))
705	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
706	pThis->pDevInsR3->iInstance, rc));
707
708	uint32_t fStsLines = 0;
709	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
710	if (RT_SUCCESS(rc))
711	uartR3StsLinesUpdate(pThis, fStsLines);
712	else
713	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
714	pThis->pDevInsR3->iInstance, rc));
715	}
716
717	}
718	#endif
719
720
721	/**
722	* Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
723	*
724	* @returns VBox status code.
725	* @param pThis The serial port instance.
726	* @param uVal The value to write.
727	*/
728	DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
729	{
730	int rc = VINF_SUCCESS;
731
732	/* A set DLAB causes a write to the lower 8bits of the divisor latch. */
733	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
734	{
735	if (uVal != (pThis->uRegDivisor & 0xff))
736	{
737	#ifndef IN_RING3
738	rc = VINF_IOM_R3_IOPORT_WRITE;
739	#else
740	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) \| uVal;
741	uartR3ParamsUpdate(pThis);
742	#endif
743	}
744	}
745	else
746	{
747	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
748	{
749	#ifndef IN_RING3
750	rc = VINF_IOM_R3_IOPORT_WRITE;
751	#else
752	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, uVal);
753	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
754	pThis->fThreEmptyPending = false;
755	uartIrqUpdate(pThis);
756	if (pThis->pDrvSerial)
757	{
758	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial, 1);
759	if (RT_FAILURE(rc2))
760	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
761	}
762	#endif
763	}
764	else
765	{
766	/* Notify the lower driver about available data only if the register was empty before. */
767	if (pThis->uRegLsr & UART_REG_LSR_THRE)
768	{
769	#ifndef IN_RING3
770	rc = VINF_IOM_R3_IOPORT_WRITE;
771	#else
772	pThis->uRegThr = uVal;
773	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
774	pThis->fThreEmptyPending = false;
775	uartIrqUpdate(pThis);
776	if (pThis->pDrvSerial)
777	{
778	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial, 1);
779	if (RT_FAILURE(rc2))
780	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pThis->pDevInsR3->iInstance, rc2));
781	}
782	#endif
783	}
784	else
785	pThis->uRegThr = uVal;
786	}
787	}
788
789	return rc;
790	}
791
792
793	/**
794	* Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
795	*
796	* @returns VBox status code.
797	* @param pThis The serial port instance.
798	* @param uVal The value to write.
799	*/
800	DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
801	{
802	int rc = VINF_SUCCESS;
803
804	/* A set DLAB causes a write to the higher 8bits of the divisor latch. */
805	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
806	{
807	if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
808	{
809	#ifndef IN_RING3
810	rc = VINF_IOM_R3_IOPORT_WRITE;
811	#else
812	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) \| (uVal << 8);
813	uartR3ParamsUpdate(pThis);
814	#endif
815	}
816	}
817	else
818	{
819	if (pThis->enmType < UARTTYPE_16750)
820	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
821	else
822	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
823	uartIrqUpdate(pThis);
824	}
825
826	return rc;
827	}
828
829
830	/**
831	* Write handler for the FCR register.
832	*
833	* @returns VBox status code.
834	* @param pThis The serial port instance.
835	* @param uVal The value to write.
836	*/
837	DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
838	{
839	#ifndef IN_RING3
840	RT_NOREF(pThis, uVal);
841	return VINF_IOM_R3_IOPORT_WRITE;
842	#else
843	int rc = VINF_SUCCESS;
844	if ( pThis->enmType >= UARTTYPE_16550A
845	&& uVal != pThis->uRegFcr)
846	{
847	/* A change in the FIFO enable bit clears both FIFOs automatically. */
848	if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
849	{
850	uartFifoClear(&pThis->FifoXmit);
851	uartFifoClear(&pThis->FifoRecv);
852
853	/*
854	* If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
855	* byte in the RBR register which will be lost so we have to adjust the available bytes.
856	*/
857	if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
858	&& (uVal & UART_REG_FCR_FIFO_EN))
859	ASMAtomicDecU32(&pThis->cbAvailRdr);
860
861	/* Clear the DR bit too. */
862	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
863	}
864
865	if (rc == VINF_SUCCESS)
866	{
867	if (uVal & UART_REG_FCR_RCV_FIFO_RST)
868	{
869	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
870	pThis->fIrqCtiPending = false;
871	uartFifoClear(&pThis->FifoRecv);
872	}
873	if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
874	uartFifoClear(&pThis->FifoXmit);
875
876	/*
877	* The 64byte FIFO enable bit is only changeable for 16750
878	* and if the DLAB bit in LCR is set.
879	*/
880	if ( pThis->enmType < UARTTYPE_16750
881	\|\| !(pThis->uRegLcr & UART_REG_LCR_DLAB))
882	uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
883	else /* Use previous value. */
884	uVal \|= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
885
886	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
887	{
888	pThis->FifoRecv.cbMax = 64;
889	pThis->FifoXmit.cbMax = 64;
890	}
891	else
892	{
893	pThis->FifoRecv.cbMax = 16;
894	pThis->FifoXmit.cbMax = 16;
895	}
896
897	if (uVal & UART_REG_FCR_FIFO_EN)
898	{
899	uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
900	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
901	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
902	else
903	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
904	}
905
906	/* The FIFO reset bits are self clearing. */
907	pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
908	uartIrqUpdate(pThis);
909	}
910
911	/* Fill in the next data. */
912	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
913	uartR3DataFetch(pThis);
914	}
915
916	return rc;
917	#endif
918	}
919
920
921	/**
922	* Write handler for the LCR register.
923	*
924	* @returns VBox status code.
925	* @param pThis The serial port instance.
926	* @param uVal The value to write.
927	*/
928	DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
929	{
930	int rc = VINF_SUCCESS;
931
932	/* Any change except the DLAB bit causes a switch to R3. */
933	if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
934	{
935	#ifndef IN_RING3
936	rc = VINF_IOM_R3_IOPORT_WRITE;
937	#else
938	/* Check whether the BREAK bit changed before updating the LCR value. */
939	bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
940	bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
941	pThis->uRegLcr = uVal;
942	uartR3ParamsUpdate(pThis);
943
944	if ( fBrkChg
945	&& pThis->pDrvSerial)
946	pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
947	#endif
948	}
949	else
950	pThis->uRegLcr = uVal;
951
952	return rc;
953	}
954
955
956	/**
957	* Write handler for the MCR register.
958	*
959	* @returns VBox status code.
960	* @param pThis The serial port instance.
961	* @param uVal The value to write.
962	*/
963	DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
964	{
965	int rc = VINF_SUCCESS;
966
967	if (pThis->enmType < UARTTYPE_16750)
968	uVal &= UART_REG_MCR_MASK_WR;
969	else
970	uVal &= UART_REG_MCR_MASK_WR_15750;
971	if (pThis->uRegMcr != uVal)
972	{
973	#ifndef IN_RING3
974	rc = VINF_IOM_R3_IOPORT_WRITE;
975	#else
976	/*
977	* When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
978	* disconnected and looped back to MSR.
979	*/
980	if ( (uVal & UART_REG_MCR_LOOP)
981	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP)
982	&& pThis->pDrvSerial)
983	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
984
985	pThis->uRegMcr = uVal;
986	if (uVal & UART_REG_MCR_LOOP)
987	{
988	uint8_t uRegMsrSts = 0;
989
990	if (uVal & UART_REG_MCR_RTS)
991	uRegMsrSts \|= UART_REG_MSR_CTS;
992	if (uVal & UART_REG_MCR_DTR)
993	uRegMsrSts \|= UART_REG_MSR_DSR;
994	if (uVal & UART_REG_MCR_OUT1)
995	uRegMsrSts \|= UART_REG_MSR_RI;
996	if (uVal & UART_REG_MCR_OUT2)
997	uRegMsrSts \|= UART_REG_MSR_DCD;
998	uartR3MsrUpdate(pThis, uRegMsrSts);
999	}
1000	else if (pThis->pDrvSerial)
1001	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1002	RT_BOOL(uVal & UART_REG_MCR_RTS),
1003	RT_BOOL(uVal & UART_REG_MCR_DTR));
1004	#endif
1005	}
1006
1007	return rc;
1008	}
1009
1010
1011	/**
1012	* Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
1013	*
1014	* @returns VBox status code.
1015	* @param pThis The serial port instance.
1016	* @param puVal Where to store the read value on success.
1017	*/
1018	DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
1019	{
1020	int rc = VINF_SUCCESS;
1021
1022	/* A set DLAB causes a read from the lower 8bits of the divisor latch. */
1023	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1024	*puVal = pThis->uRegDivisor & 0xff;
1025	else
1026	{
1027	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1028	{
1029	/*
1030	* Only go back to R3 if there is new data available for the FIFO
1031	* and we would clear the interrupt to fill it up again.
1032	*/
1033	if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
1034	&& ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
1035	{
1036	#ifndef IN_RING3
1037	rc = VINF_IOM_R3_IOPORT_READ;
1038	#else
1039	uartR3RecvFifoFill(pThis);
1040	#endif
1041	}
1042
1043	if (rc == VINF_SUCCESS)
1044	{
1045	*puVal = uartFifoGet(&pThis->FifoRecv);
1046	pThis->fIrqCtiPending = false;
1047	if (!pThis->FifoRecv.cbUsed)
1048	{
1049	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
1050	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1051	}
1052	else
1053	{
1054	uint64_t tsCtiFire = TMTimerGet(pThis->CTX_SUFF(pTimerRcvFifoTimeout)) + pThis->cSymbolXferTicks * 4;
1055	TMTimerSet(pThis->CTX_SUFF(pTimerRcvFifoTimeout), tsCtiFire);
1056	}
1057	uartIrqUpdate(pThis);
1058	}
1059	}
1060	else
1061	{
1062	*puVal = pThis->uRegRbr;
1063
1064	if (pThis->uRegLsr & UART_REG_LSR_DR)
1065	{
1066	Assert(pThis->cbAvailRdr);
1067	uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1068	if (!cbAvail)
1069	{
1070	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1071	uartIrqUpdate(pThis);
1072	}
1073	else
1074	{
1075	#ifndef IN_RING3
1076	/* Restore state and go back to R3. */
1077	ASMAtomicIncU32(&pThis->cbAvailRdr);
1078	rc = VINF_IOM_R3_IOPORT_READ;
1079	#else
1080	/* Fetch new data and keep the DR bit set. */
1081	uartR3DataFetch(pThis);
1082	#endif
1083	}
1084	}
1085	}
1086	}
1087
1088	return rc;
1089	}
1090
1091
1092	/**
1093	* Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1094	*
1095	* @returns VBox status code.
1096	* @param pThis The serial port instance.
1097	* @param puVal Where to store the read value on success.
1098	*/
1099	DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1100	{
1101	int rc = VINF_SUCCESS;
1102
1103	/* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1104	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1105	*puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1106	else
1107	*puVal = pThis->uRegIer;
1108
1109	return rc;
1110	}
1111
1112
1113	/**
1114	* Read handler for the IIR register.
1115	*
1116	* @returns VBox status code.
1117	* @param pThis The serial port instance.
1118	* @param puVal Where to store the read value on success.
1119	*/
1120	DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1121	{
1122	*puVal = pThis->uRegIir;
1123	/* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
1124	if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
1125	{
1126	pThis->fThreEmptyPending = false;
1127	uartIrqUpdate(pThis);
1128	}
1129	return VINF_SUCCESS;
1130	}
1131
1132
1133	/**
1134	* Read handler for the LSR register.
1135	*
1136	* @returns VBox status code.
1137	* @param pThis The serial port instance.
1138	* @param puVal Where to store the read value on success.
1139	*/
1140	DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1141	{
1142	int rc = VINF_SUCCESS;
1143
1144	/* Yield if configured and there is no data available. */
1145	if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1146	&& (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1147	{
1148	#ifndef IN_RING3
1149	return VINF_IOM_R3_IOPORT_READ;
1150	#else
1151	RTThreadYield();
1152	#endif
1153	}
1154
1155	*puVal = pThis->uRegLsr;
1156	/*
1157	* Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1158	* as well as the Break Interrupt (BI).
1159	*/
1160	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1161	uartIrqUpdate(pThis);
1162
1163	return rc;
1164	}
1165
1166
1167	/**
1168	* Read handler for the MSR register.
1169	*
1170	* @returns VBox status code.
1171	* @param pThis The serial port instance.
1172	* @param puVal Where to store the read value on success.
1173	*/
1174	DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1175	{
1176	*puVal = pThis->uRegMsr;
1177
1178	/* Clear any of the delta bits. */
1179	UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1180	uartIrqUpdate(pThis);
1181	return VINF_SUCCESS;
1182	}
1183
1184
1185	#ifdef LOG_ENABLED
1186	/**
1187	* Converts the register index into a sensible memnonic.
1188	*
1189	* @returns Register memnonic.
1190	* @param pThis The serial port instance.
1191	* @param idxReg Register index.
1192	* @param fWrite Flag whether the register gets written.
1193	*/
1194	DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1195	{
1196	const char *psz = "INV";
1197
1198	switch (idxReg)
1199	{
1200	/case UART_REG_THR_DLL_INDEX:/
1201	case UART_REG_RBR_DLL_INDEX:
1202	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1203	psz = "DLL";
1204	else if (fWrite)
1205	psz = "THR";
1206	else
1207	psz = "RBR";
1208	break;
1209	case UART_REG_IER_DLM_INDEX:
1210	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1211	psz = "DLM";
1212	else
1213	psz = "IER";
1214	break;
1215	/case UART_REG_IIR_INDEX:/
1216	case UART_REG_FCR_INDEX:
1217	if (fWrite)
1218	psz = "FCR";
1219	else
1220	psz = "IIR";
1221	break;
1222	case UART_REG_LCR_INDEX:
1223	psz = "LCR";
1224	break;
1225	case UART_REG_MCR_INDEX:
1226	psz = "MCR";
1227	break;
1228	case UART_REG_LSR_INDEX:
1229	psz = "LSR";
1230	break;
1231	case UART_REG_MSR_INDEX:
1232	psz = "MSR";
1233	break;
1234	case UART_REG_SCR_INDEX:
1235	psz = "SCR";
1236	break;
1237	}
1238
1239	return psz;
1240	}
1241	#endif
1242
1243
1244	DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1245	{
1246	AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1247
1248	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1249	if (rc != VINF_SUCCESS)
1250	return rc;
1251
1252	uint8_t idxReg = uReg & 0x7;
1253	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1254	pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /fWrite/), u32, cb));
1255
1256	uint8_t uVal = (uint8_t)u32;
1257	switch (idxReg)
1258	{
1259	case UART_REG_THR_DLL_INDEX:
1260	rc = uartRegThrDllWrite(pThis, uVal);
1261	break;
1262	case UART_REG_IER_DLM_INDEX:
1263	rc = uartRegIerDlmWrite(pThis, uVal);
1264	break;
1265	case UART_REG_FCR_INDEX:
1266	rc = uartRegFcrWrite(pThis, uVal);
1267	break;
1268	case UART_REG_LCR_INDEX:
1269	rc = uartRegLcrWrite(pThis, uVal);
1270	break;
1271	case UART_REG_MCR_INDEX:
1272	rc = uartRegMcrWrite(pThis, uVal);
1273	break;
1274	case UART_REG_SCR_INDEX:
1275	pThis->uRegScr = u32;
1276	break;
1277	default:
1278	break;
1279	}
1280
1281	PDMCritSectLeave(&pThis->CritSect);
1282	LogFlowFunc(("-> %Rrc\n", rc));
1283	return rc;
1284	}
1285
1286
1287	DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1288	{
1289	if (cb != 1)
1290	return VERR_IOM_IOPORT_UNUSED;
1291
1292	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1293	if (rc != VINF_SUCCESS)
1294	return rc;
1295
1296	uint8_t idxReg = uReg & 0x7;
1297	switch (idxReg)
1298	{
1299	case UART_REG_RBR_DLL_INDEX:
1300	rc = uartRegRbrDllRead(pThis, pu32);
1301	break;
1302	case UART_REG_IER_DLM_INDEX:
1303	rc = uartRegIerDlmRead(pThis, pu32);
1304	break;
1305	case UART_REG_IIR_INDEX:
1306	rc = uartRegIirRead(pThis, pu32);
1307	break;
1308	case UART_REG_LCR_INDEX:
1309	*pu32 = pThis->uRegLcr;
1310	break;
1311	case UART_REG_MCR_INDEX:
1312	*pu32 = pThis->uRegMcr;
1313	break;
1314	case UART_REG_LSR_INDEX:
1315	rc = uartRegLsrRead(pThis, pu32);
1316	break;
1317	case UART_REG_MSR_INDEX:
1318	rc = uartRegMsrRead(pThis, pu32);
1319	break;
1320	case UART_REG_SCR_INDEX:
1321	*pu32 = pThis->uRegScr;
1322	break;
1323	default:
1324	rc = VERR_IOM_IOPORT_UNUSED;
1325	}
1326
1327	PDMCritSectLeave(&pThis->CritSect);
1328	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1329	pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /fWrite/), *pu32, cb, rc));
1330	return rc;
1331	}
1332
1333
1334	#ifdef IN_RING3
1335
1336	/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1337
1338	/**
1339	* @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1340	*/
1341	static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1342	{
1343	RT_NOREF(pDevIns, pTimer);
1344	PUARTCORE pThis = (PUARTCORE)pvUser;
1345	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1346	if (pThis->FifoRecv.cbUsed)
1347	{
1348	pThis->fIrqCtiPending = true;
1349	uartIrqUpdate(pThis);
1350	}
1351	PDMCritSectLeave(&pThis->CritSect);
1352	}
1353
1354
1355	/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1356
1357
1358	/**
1359	* @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1360	*/
1361	static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1362	{
1363	LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1364	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1365
1366	AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1367
1368	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1369	LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
1370	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1371	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1372	uartR3RecvFifoFill(pThis);
1373	else if (!cbAvailOld)
1374	{
1375	size_t cbRead = 0;
1376	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1377	AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1378	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1379	uartIrqUpdate(pThis);
1380	}
1381	PDMCritSectLeave(&pThis->CritSect);
1382
1383	return VINF_SUCCESS;
1384	}
1385
1386
1387	/**
1388	* @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1389	*/
1390	static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1391	{
1392	LogFlowFunc(("pInterface=%#p\n", pInterface));
1393	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1394
1395	/* Set the transmitter empty bit because everything was sent. */
1396	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1397	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1398	uartIrqUpdate(pThis);
1399	PDMCritSectLeave(&pThis->CritSect);
1400	return VINF_SUCCESS;
1401	}
1402
1403
1404	/**
1405	* @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1406	*/
1407	static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void pvBuf, size_t cbRead, size_t pcbRead)
1408	{
1409	LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1410	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1411
1412	AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1413
1414	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1415	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1416	{
1417	*pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
1418	if (!pThis->FifoXmit.cbUsed)
1419	{
1420	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1421	pThis->fThreEmptyPending = true;
1422	}
1423	if (*pcbRead)
1424	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1425	uartIrqUpdate(pThis);
1426	}
1427	else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
1428	{
1429	(uint8_t )pvBuf = pThis->uRegThr;
1430	*pcbRead = 1;
1431	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1432	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1433	pThis->fThreEmptyPending = true;
1434	uartIrqUpdate(pThis);
1435	}
1436	else
1437	{
1438	/*
1439	* This can happen if there was data in the FIFO when the connection was closed,
1440	* idicate this condition to the lower driver by returning 0 bytes.
1441	*/
1442	*pcbRead = 0;
1443	}
1444	PDMCritSectLeave(&pThis->CritSect);
1445
1446	LogFlowFunc(("-> VINF_SUCCESS{pcbRead=%zu}\n", pcbRead));
1447	return VINF_SUCCESS;
1448	}
1449
1450
1451	/**
1452	* @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1453	*/
1454	static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1455	{
1456	LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1457	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1458
1459	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1460	uartR3StsLinesUpdate(pThis, fNewStatusLines);
1461	PDMCritSectLeave(&pThis->CritSect);
1462	return VINF_SUCCESS;
1463	}
1464
1465
1466	/**
1467	* @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1468	*/
1469	static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1470	{
1471	LogFlowFunc(("pInterface=%#p\n", pInterface));
1472	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1473
1474	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1475	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1476	uartIrqUpdate(pThis);
1477	PDMCritSectLeave(&pThis->CritSect);
1478	return VINF_SUCCESS;
1479	}
1480
1481
1482	/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1483
1484	/**
1485	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1486	*/
1487	static DECLCALLBACK(void ) uartR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1488	{
1489	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1490	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1491	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1492	return NULL;
1493	}
1494
1495
1496	DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1497	{
1498	SSMR3PutU16(pSSM, pThis->uRegDivisor);
1499	SSMR3PutU8(pSSM, pThis->uRegRbr);
1500	SSMR3PutU8(pSSM, pThis->uRegThr);
1501	SSMR3PutU8(pSSM, pThis->uRegIer);
1502	SSMR3PutU8(pSSM, pThis->uRegIir);
1503	SSMR3PutU8(pSSM, pThis->uRegFcr);
1504	SSMR3PutU8(pSSM, pThis->uRegLcr);
1505	SSMR3PutU8(pSSM, pThis->uRegMcr);
1506	SSMR3PutU8(pSSM, pThis->uRegLsr);
1507	SSMR3PutU8(pSSM, pThis->uRegMsr);
1508	SSMR3PutU8(pSSM, pThis->uRegScr);
1509	SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1510	SSMR3PutBool(pSSM, pThis->fThreEmptyPending);
1511	SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1512	SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1513	SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1514	SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1515
1516	return TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1517	}
1518
1519
1520	DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1521	uint8_t puIrq, RTIOPORT pPortBase)
1522	{
1523	RT_NOREF(uPass);
1524	int rc = VINF_SUCCESS;
1525
1526	if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1527	{
1528	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1529	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1530	SSMR3GetU8(pSSM, &pThis->uRegThr);
1531	SSMR3GetU8(pSSM, &pThis->uRegIer);
1532	SSMR3GetU8(pSSM, &pThis->uRegIir);
1533	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1534	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1535	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1536	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1537	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1538	SSMR3GetU8(pSSM, &pThis->uRegScr);
1539	SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1540	SSMR3GetBool(pSSM, &pThis->fThreEmptyPending);
1541	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1542	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1543	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1544	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1545
1546	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1547	}
1548	else
1549	{
1550	if (uVersion == UART_SAVED_STATE_VERSION_16450)
1551	{
1552	pThis->enmType = UARTTYPE_16450;
1553	LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1554	}
1555
1556	int uIrq;
1557	int32_t iTmp;
1558	uint32_t PortBase;
1559
1560	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1561	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1562	SSMR3GetU8(pSSM, &pThis->uRegIer);
1563	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1564	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1565	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1566	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1567	SSMR3GetU8(pSSM, &pThis->uRegScr);
1568	if (uVersion > UART_SAVED_STATE_VERSION_16450)
1569	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1570	SSMR3GetS32(pSSM, &iTmp);
1571	pThis->fThreEmptyPending = RT_BOOL(iTmp);
1572	SSMR3GetS32(pSSM, &uIrq);
1573	SSMR3Skip(pSSM, sizeof(int32_t));
1574	SSMR3GetU32(pSSM, &PortBase);
1575	rc = SSMR3Skip(pSSM, sizeof(int32_t));
1576
1577	if ( RT_SUCCESS(rc)
1578	&& uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1579	{
1580	SSMR3GetU8(pSSM, &pThis->uRegThr);
1581	SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1582	SSMR3GetU8(pSSM, &pThis->uRegIir);
1583
1584	int iTimeoutPending = 0;
1585	SSMR3GetS32(pSSM, &iTimeoutPending);
1586	pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1587
1588	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1589	TMR3TimerSkip(pSSM, NULL);
1590	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1591	rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1592	}
1593
1594	if (RT_SUCCESS(rc))
1595	{
1596	AssertPtr(puIrq);
1597	AssertPtr(pPortBase);
1598	*puIrq = (uint8_t)uIrq;
1599	*pPortBase = (RTIOPORT)PortBase;
1600	}
1601	}
1602
1603	return rc;
1604	}
1605
1606
1607	DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1608	{
1609	RT_NOREF(pSSM);
1610
1611	uartR3ParamsUpdate(pThis);
1612	uartIrqUpdate(pThis);
1613
1614	if (pThis->pDrvSerial)
1615	{
1616	/* Set the modem lines to reflect the current state. */
1617	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1618	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1619	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1620	if (RT_FAILURE(rc))
1621	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1622	pThis->pDevInsR3->iInstance, rc));
1623
1624	uint32_t fStsLines = 0;
1625	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1626	if (RT_SUCCESS(rc))
1627	uartR3StsLinesUpdate(pThis, fStsLines);
1628	else
1629	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1630	pThis->pDevInsR3->iInstance, rc));
1631	}
1632
1633	return VINF_SUCCESS;
1634	}
1635
1636
1637	DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1638	{
1639	RT_NOREF(offDelta);
1640	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1641	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1642	}
1643
1644
1645	DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1646	{
1647	pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1648	pThis->uRegRbr = 0;
1649	pThis->uRegThr = 0;
1650	pThis->uRegIer = 0;
1651	pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1652	pThis->uRegFcr = 0;
1653	pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1654	pThis->uRegMcr = 0;
1655	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
1656	pThis->uRegMsr = 0; /* Updated below. */
1657	pThis->uRegScr = 0;
1658	pThis->fIrqCtiPending = false;
1659	pThis->fThreEmptyPending = false;
1660
1661	/* Standard FIFO size for 15550A. */
1662	pThis->FifoXmit.cbMax = 16;
1663	pThis->FifoRecv.cbMax = 16;
1664	pThis->FifoRecv.cbItl = 1;
1665
1666	uartR3XferReset(pThis);
1667	}
1668
1669
1670	DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1671	{
1672	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1673	if (RT_SUCCESS(rc))
1674	{
1675	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1676	if (!pThis->pDrvSerial)
1677	{
1678	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1679	return VERR_PDM_MISSING_INTERFACE;
1680	}
1681	uartR3XferReset(pThis);
1682	}
1683	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1684	{
1685	pThis->pDrvBase = NULL;
1686	pThis->pDrvSerial = NULL;
1687	rc = VINF_SUCCESS;
1688	uartR3XferReset(pThis);
1689	LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1690	}
1691	else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1692	LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1693
1694	return rc;
1695	}
1696
1697
1698	DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1699	{
1700	/* Zero out important members. */
1701	pThis->pDrvBase = NULL;
1702	pThis->pDrvSerial = NULL;
1703	uartR3XferReset(pThis);
1704	}
1705
1706
1707	DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1708	{
1709	PDMR3CritSectDelete(&pThis->CritSect);
1710	}
1711
1712
1713	DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1714	R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1715	RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1716	{
1717	int rc = VINF_SUCCESS;
1718
1719	/*
1720	* Initialize the instance data.
1721	* (Do this early or the destructor might choke on something!)
1722	*/
1723	pThis->pDevInsR3 = pDevInsR3;
1724	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1725	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1726	pThis->iLUN = iLUN;
1727	pThis->enmType = enmType;
1728	pThis->fFlags = fFlags;
1729	pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1730	pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1731	pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1732
1733	/* IBase */
1734	pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1735
1736	/* ISerialPort */
1737	pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1738	pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1739	pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1740	pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1741	pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1742
1743	rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1744	pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1745	AssertRCReturn(rc, rc);
1746
1747	/*
1748	* Attach the char driver and get the interfaces.
1749	*/
1750	rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1751	if (RT_SUCCESS(rc))
1752	{
1753	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1754	if (!pThis->pDrvSerial)
1755	{
1756	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1757	return VERR_PDM_MISSING_INTERFACE;
1758	}
1759	}
1760	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1761	{
1762	pThis->pDrvBase = NULL;
1763	pThis->pDrvSerial = NULL;
1764	LogRel(("Serial#%d: no unit\n", iLUN));
1765	}
1766	else
1767	{
1768	AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1769	/* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1770	return rc;
1771	}
1772
1773	/*
1774	* Create the receive FIFO character timeout indicator timer.
1775	*/
1776	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1777	TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1778	&pThis->pTimerRcvFifoTimeoutR3);
1779	AssertRCReturn(rc, rc);
1780
1781	rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1782	AssertRCReturn(rc, rc);
1783
1784	pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1785	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1786
1787	uartR3Reset(pThis);
1788	return VINF_SUCCESS;
1789	}
1790
1791	#endif /* IN_RING3 */
1792
1793	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 73636

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