1 | /* $Id: UartCore.cpp 103425 2024-02-19 11:12:14Z vboxsync $ */
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2 | /** @file
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3 | * UartCore - UART (16550A up to 16950) emulation.
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4 | *
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5 | * The documentation for this device was taken from the PC16550D spec from TI.
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6 | */
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7 |
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8 | /*
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9 | * Copyright (C) 2018-2023 Oracle and/or its affiliates.
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10 | *
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11 | * This file is part of VirtualBox base platform packages, as
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12 | * available from https://www.virtualbox.org.
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13 | *
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14 | * This program is free software; you can redistribute it and/or
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15 | * modify it under the terms of the GNU General Public License
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16 | * as published by the Free Software Foundation, in version 3 of the
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17 | * License.
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18 | *
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19 | * This program is distributed in the hope that it will be useful, but
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20 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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22 | * General Public License for more details.
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23 | *
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24 | * You should have received a copy of the GNU General Public License
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25 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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26 | *
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27 | * SPDX-License-Identifier: GPL-3.0-only
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28 | */
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29 |
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30 |
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31 | /*********************************************************************************************************************************
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32 | * Header Files *
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33 | *********************************************************************************************************************************/
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34 | #define LOG_GROUP LOG_GROUP_DEV_SERIAL
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35 | #include <VBox/vmm/tm.h>
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36 | #include <iprt/log.h>
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37 | #include <iprt/uuid.h>
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38 | #include <iprt/assert.h>
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39 |
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40 | #include "VBoxDD.h"
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41 | #include "UartCore.h"
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42 |
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43 |
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44 | /*********************************************************************************************************************************
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45 | * Defined Constants And Macros *
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46 | *********************************************************************************************************************************/
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47 |
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48 | /** The RBR/DLL register index (from the base of the port range). */
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49 | #define UART_REG_RBR_DLL_INDEX 0
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50 |
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51 | /** The THR/DLL register index (from the base of the port range). */
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52 | #define UART_REG_THR_DLL_INDEX 0
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53 |
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54 | /** The IER/DLM register index (from the base of the port range). */
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55 | #define UART_REG_IER_DLM_INDEX 1
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56 | /** Enable received data available interrupt */
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57 | # define UART_REG_IER_ERBFI RT_BIT(0)
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58 | /** Enable transmitter holding register empty interrupt */
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59 | # define UART_REG_IER_ETBEI RT_BIT(1)
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60 | /** Enable receiver line status interrupt */
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61 | # define UART_REG_IER_ELSI RT_BIT(2)
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62 | /** Enable modem status interrupt. */
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63 | # define UART_REG_IER_EDSSI RT_BIT(3)
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64 | /** Sleep mode enable. */
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65 | # define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
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66 | /** Low power mode enable. */
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67 | # define UART_REG_IER_LP_MODE_EN RT_BIT(5)
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68 | /** Mask of writeable bits. */
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69 | # define UART_REG_IER_MASK_WR 0x0f
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70 | /** Mask of writeable bits for 16750+. */
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71 | # define UART_REG_IER_MASK_WR_16750 0x3f
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72 |
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73 | /** The IIR register index (from the base of the port range). */
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74 | #define UART_REG_IIR_INDEX 2
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75 | /** Interrupt Pending - high means no interrupt pending. */
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76 | # define UART_REG_IIR_IP_NO_INT RT_BIT(0)
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77 | /** Interrupt identification mask. */
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78 | # define UART_REG_IIR_ID_MASK 0x0e
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79 | /** Sets the interrupt identification to the given value. */
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80 | # define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
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81 | /** Gets the interrupt identification from the given IIR register value. */
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82 | # define UART_REG_IIR_ID_GET(a_Val) (((a_Val) & UART_REG_IIR_ID_MASK) >> 1)
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83 | /** Receiver Line Status interrupt. */
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84 | # define UART_REG_IIR_ID_RCL 0x3
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85 | /** Received Data Available interrupt. */
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86 | # define UART_REG_IIR_ID_RDA 0x2
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87 | /** Character Timeou Indicator interrupt. */
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88 | # define UART_REG_IIR_ID_CTI 0x6
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89 | /** Transmitter Holding Register Empty interrupt. */
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90 | # define UART_REG_IIR_ID_THRE 0x1
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91 | /** Modem Status interrupt. */
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92 | # define UART_REG_IIR_ID_MS 0x0
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93 | /** 64 byte FIFOs enabled (15750+ only). */
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94 | # define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
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95 | /** FIFOs enabled. */
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96 | # define UART_REG_IIR_FIFOS_EN 0xc0
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97 | /** Bits relevant for checking whether the interrupt status has changed. */
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98 | # define UART_REG_IIR_CHANGED_MASK 0x0f
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99 |
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100 | /** The FCR register index (from the base of the port range). */
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101 | #define UART_REG_FCR_INDEX 2
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102 | /** Enable the TX/RX FIFOs. */
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103 | # define UART_REG_FCR_FIFO_EN RT_BIT(0)
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104 | /** Reset the receive FIFO. */
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105 | # define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
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106 | /** Reset the transmit FIFO. */
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107 | # define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
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108 | /** DMA Mode Select. */
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109 | # define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
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110 | /** 64 Byte FIFO enable (15750+ only). */
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111 | # define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
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112 | /** Receiver level interrupt trigger. */
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113 | # define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
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114 | /** Returns the receive level trigger value from the given FCR register. */
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115 | # define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
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116 | /** RCV Interrupt trigger level - 1 byte. */
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117 | # define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
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118 | /** RCV Interrupt trigger level - 4 bytes. */
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119 | # define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
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120 | /** RCV Interrupt trigger level - 8 bytes. */
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121 | # define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
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122 | /** RCV Interrupt trigger level - 14 bytes. */
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123 | # define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
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124 | /** Mask of writeable bits. */
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125 | # define UART_REG_FCR_MASK_WR 0xcf
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126 | /** Mask of sticky bits. */
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127 | # define UART_REG_FCR_MASK_STICKY 0xe9
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128 |
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129 | /** The LCR register index (from the base of the port range). */
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130 | #define UART_REG_LCR_INDEX 3
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131 | /** Word Length Select Mask. */
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132 | # define UART_REG_LCR_WLS_MASK 0x3
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133 | /** Returns the WLS value form the given LCR register value. */
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134 | # define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
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135 | /** Number of stop bits. */
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136 | # define UART_REG_LCR_STB RT_BIT(2)
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137 | /** Parity Enable. */
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138 | # define UART_REG_LCR_PEN RT_BIT(3)
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139 | /** Even Parity. */
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140 | # define UART_REG_LCR_EPS RT_BIT(4)
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141 | /** Stick parity. */
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142 | # define UART_REG_LCR_PAR_STICK RT_BIT(5)
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143 | /** Set Break. */
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144 | # define UART_REG_LCR_BRK_SET RT_BIT(6)
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145 | /** Divisor Latch Access Bit. */
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146 | # define UART_REG_LCR_DLAB RT_BIT(7)
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147 |
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148 | /** The MCR register index (from the base of the port range). */
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149 | #define UART_REG_MCR_INDEX 4
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150 | /** Data Terminal Ready. */
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151 | # define UART_REG_MCR_DTR RT_BIT(0)
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152 | /** Request To Send. */
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153 | # define UART_REG_MCR_RTS RT_BIT(1)
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154 | /** Out1. */
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155 | # define UART_REG_MCR_OUT1 RT_BIT(2)
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156 | /** Out2. */
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157 | # define UART_REG_MCR_OUT2 RT_BIT(3)
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158 | /** Loopback connection. */
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159 | # define UART_REG_MCR_LOOP RT_BIT(4)
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160 | /** Flow Control Enable (15750+ only). */
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161 | # define UART_REG_MCR_AFE RT_BIT(5)
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162 | /** Mask of writeable bits (15450 and 15550A). */
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163 | # define UART_REG_MCR_MASK_WR 0x1f
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164 | /** Mask of writeable bits (15750+). */
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165 | # define UART_REG_MCR_MASK_WR_15750 0x3f
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166 |
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167 | /** The LSR register index (from the base of the port range). */
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168 | #define UART_REG_LSR_INDEX 5
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169 | /** Data Ready. */
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170 | # define UART_REG_LSR_DR RT_BIT(0)
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171 | /** Overrun Error. */
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172 | # define UART_REG_LSR_OE RT_BIT(1)
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173 | /** Parity Error. */
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174 | # define UART_REG_LSR_PE RT_BIT(2)
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175 | /** Framing Error. */
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176 | # define UART_REG_LSR_FE RT_BIT(3)
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177 | /** Break Interrupt. */
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178 | # define UART_REG_LSR_BI RT_BIT(4)
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179 | /** Transmitter Holding Register. */
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180 | # define UART_REG_LSR_THRE RT_BIT(5)
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181 | /** Transmitter Empty. */
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182 | # define UART_REG_LSR_TEMT RT_BIT(6)
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183 | /** Error in receiver FIFO. */
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184 | # define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
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185 | /** The bits to check in this register when checking for the RCL interrupt. */
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186 | # define UART_REG_LSR_BITS_IIR_RCL 0x1e
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187 |
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188 | /** The MSR register index (from the base of the port range). */
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189 | #define UART_REG_MSR_INDEX 6
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190 | /** Delta Clear to Send. */
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191 | # define UART_REG_MSR_DCTS RT_BIT(0)
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192 | /** Delta Data Set Ready. */
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193 | # define UART_REG_MSR_DDSR RT_BIT(1)
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194 | /** Trailing Edge Ring Indicator. */
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195 | # define UART_REG_MSR_TERI RT_BIT(2)
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196 | /** Delta Data Carrier Detect. */
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197 | # define UART_REG_MSR_DDCD RT_BIT(3)
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198 | /** Clear to Send. */
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199 | # define UART_REG_MSR_CTS RT_BIT(4)
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200 | /** Data Set Ready. */
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201 | # define UART_REG_MSR_DSR RT_BIT(5)
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202 | /** Ring Indicator. */
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203 | # define UART_REG_MSR_RI RT_BIT(6)
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204 | /** Data Carrier Detect. */
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205 | # define UART_REG_MSR_DCD RT_BIT(7)
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206 | /** The bits to check in this register when checking for the MS interrupt. */
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207 | # define UART_REG_MSR_BITS_IIR_MS 0x0f
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208 |
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209 | /** The SCR register index (from the base of the port range). */
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210 | #define UART_REG_SCR_INDEX 7
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211 |
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212 | /** Set the specified bits in the given register. */
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213 | #define UART_REG_SET(a_Reg, a_Set) ((a_Reg) |= (a_Set))
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214 | /** Clear the specified bits in the given register. */
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215 | #define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
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216 |
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217 |
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218 | /*********************************************************************************************************************************
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219 | * Structures and Typedefs *
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220 | *********************************************************************************************************************************/
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221 |
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222 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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223 |
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224 |
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225 | /*********************************************************************************************************************************
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226 | * Global Variables *
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227 | *********************************************************************************************************************************/
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228 |
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229 | #ifdef IN_RING3
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230 | /**
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231 | * FIFO ITL levels.
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232 | */
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233 | static struct
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234 | {
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235 | /** ITL level for a 16byte FIFO. */
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236 | uint8_t cbItl16;
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237 | /** ITL level for a 64byte FIFO. */
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238 | uint8_t cbItl64;
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239 | } s_aFifoItl[] =
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240 | {
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241 | /* cbItl16 cbItl64 */
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242 | { 1, 1 },
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243 | { 4, 16 },
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244 | { 8, 32 },
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245 | { 14, 56 }
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246 | };
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247 |
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248 |
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249 | /**
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250 | * String versions of the parity enum.
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251 | */
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252 | static const char *s_aszParity[] =
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253 | {
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254 | "INVALID",
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255 | "NONE",
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256 | "EVEN",
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257 | "ODD",
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258 | "MARK",
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259 | "SPACE",
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260 | "INVALID"
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261 | };
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262 |
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263 |
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264 | /**
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265 | * String versions of the stop bits enum.
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266 | */
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267 | static const char *s_aszStopBits[] =
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268 | {
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269 | "INVALID",
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270 | "1",
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271 | "1.5",
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272 | "2",
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273 | "INVALID"
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274 | };
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275 | #endif
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276 |
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277 |
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278 | /*********************************************************************************************************************************
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279 | * Internal Functions *
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280 | *********************************************************************************************************************************/
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281 |
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282 |
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283 | /**
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284 | * Updates the IRQ state based on the current device state.
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285 | *
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286 | * @param pDevIns The device instance.
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287 | * @param pThis The shared serial port instance data.
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288 | * @param pThisCC The serial port instance data for the current context.
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289 | */
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290 | static void uartIrqUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
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291 | {
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292 | LogFlowFunc(("pThis=%#p\n", pThis));
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293 |
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294 | /*
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295 | * The interrupt uses a priority scheme, only the interrupt with the
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296 | * highest priority is indicated in the interrupt identification register.
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297 | *
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298 | * The priorities are as follows (high to low):
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299 | * * Receiver line status
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300 | * * Received data available
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301 | * * Character timeout indication (only in FIFO mode).
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302 | * * Transmitter holding register empty
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303 | * * Modem status change.
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304 | */
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305 | uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
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306 | if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
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307 | && (pThis->uRegIer & UART_REG_IER_ELSI))
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308 | uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
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309 | else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
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310 | && pThis->fIrqCtiPending)
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311 | uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
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312 | else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
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313 | && (pThis->uRegIer & UART_REG_IER_ERBFI)
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314 | && ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
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315 | || pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
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316 | uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
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317 | else if ( (pThis->uRegIer & UART_REG_IER_ETBEI)
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318 | && pThis->fThreEmptyPending)
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319 | uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
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320 | else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
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321 | && (pThis->uRegIer & UART_REG_IER_EDSSI))
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322 | uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
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323 |
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324 | LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
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325 |
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326 | if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
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327 | LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
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328 | pThis->uRegIir, uRegIirNew,
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329 | pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
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330 | uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
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331 | else
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332 | LogFlow((" No change in interrupt source\n"));
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333 |
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334 | /*
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335 | * Set interrupt value accordingly. As this is an ISA device most guests
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336 | * configure the IRQ as edge triggered instead of level triggered.
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337 | * So this needs to be done everytime, even if the internal interrupt state
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338 | * doesn't change in order to avoid the guest losing interrupts (reading one byte at
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339 | * a time from the FIFO for instance which doesn't change the interrupt source).
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340 | */
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341 | if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
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342 | pThisCC->pfnUartIrqReq(pDevIns, pThis, pThis->iLUN, 0);
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343 | else
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344 | pThisCC->pfnUartIrqReq(pDevIns, pThis, pThis->iLUN, 1);
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345 |
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346 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
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347 | uRegIirNew |= UART_REG_IIR_FIFOS_EN;
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348 | if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
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349 | uRegIirNew |= UART_REG_IIR_64BYTE_FIFOS_EN;
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350 |
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351 | pThis->uRegIir = uRegIirNew;
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352 | }
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353 |
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354 |
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355 | /**
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356 | * Returns the amount of bytes stored in the given FIFO.
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357 | *
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358 | * @returns Amount of bytes stored in the FIFO.
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359 | * @param pFifo The FIFO.
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360 | */
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361 | DECLINLINE(size_t) uartFifoUsedGet(PUARTFIFO pFifo)
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362 | {
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363 | return pFifo->cbUsed;
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364 | }
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365 |
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366 |
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367 | /**
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368 | * Puts a new character into the given FIFO.
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369 | *
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370 | * @returns Flag whether the FIFO overflowed.
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371 | * @param pFifo The FIFO to put the data into.
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372 | * @param fOvrWr Flag whether to overwrite data if the FIFO is full.
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373 | * @param bData The data to add.
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374 | */
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375 | DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
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376 | {
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377 | if (fOvrWr || pFifo->cbUsed < pFifo->cbMax)
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378 | {
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379 | pFifo->abBuf[pFifo->offWrite] = bData;
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380 | pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
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381 | }
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382 |
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383 | bool fOverFlow = false;
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384 | if (pFifo->cbUsed < pFifo->cbMax)
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385 | pFifo->cbUsed++;
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386 | else
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387 | {
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388 | fOverFlow = true;
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389 | if (fOvrWr) /* Advance the read position to account for the lost character. */
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390 | pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
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391 | }
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---|
392 |
|
---|
393 | return fOverFlow;
|
---|
394 | }
|
---|
395 |
|
---|
396 |
|
---|
397 | /**
|
---|
398 | * Returns the next character in the FIFO.
|
---|
399 | *
|
---|
400 | * @return Next byte in the FIFO.
|
---|
401 | * @param pFifo The FIFO to get data from.
|
---|
402 | */
|
---|
403 | DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
|
---|
404 | {
|
---|
405 | uint8_t bRet = 0;
|
---|
406 |
|
---|
407 | if (pFifo->cbUsed)
|
---|
408 | {
|
---|
409 | bRet = pFifo->abBuf[pFifo->offRead];
|
---|
410 | pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
|
---|
411 | pFifo->cbUsed--;
|
---|
412 | }
|
---|
413 |
|
---|
414 | return bRet;
|
---|
415 | }
|
---|
416 |
|
---|
417 | #ifdef IN_RING3
|
---|
418 |
|
---|
419 | /**
|
---|
420 | * Clears the given FIFO.
|
---|
421 | *
|
---|
422 | * @param pFifo The FIFO to clear.
|
---|
423 | */
|
---|
424 | DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
|
---|
425 | {
|
---|
426 | memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
|
---|
427 | pFifo->cbUsed = 0;
|
---|
428 | pFifo->offWrite = 0;
|
---|
429 | pFifo->offRead = 0;
|
---|
430 | }
|
---|
431 |
|
---|
432 |
|
---|
433 | /**
|
---|
434 | * Returns the amount of free bytes in the given FIFO.
|
---|
435 | *
|
---|
436 | * @returns The amount of bytes free in the given FIFO.
|
---|
437 | * @param pFifo The FIFO.
|
---|
438 | */
|
---|
439 | DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
|
---|
440 | {
|
---|
441 | return pFifo->cbMax - pFifo->cbUsed;
|
---|
442 | }
|
---|
443 |
|
---|
444 |
|
---|
445 | /**
|
---|
446 | * Tries to copy the requested amount of data from the given FIFO into the provided buffer.
|
---|
447 | *
|
---|
448 | * @returns Amount of bytes actually copied.
|
---|
449 | * @param pFifo The FIFO to copy data from.
|
---|
450 | * @param pvDst Where to copy the data to.
|
---|
451 | * @param cbCopy How much to copy.
|
---|
452 | */
|
---|
453 | DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
|
---|
454 | {
|
---|
455 | size_t cbCopied = 0;
|
---|
456 | uint8_t *pbDst = (uint8_t *)pvDst;
|
---|
457 |
|
---|
458 | cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
|
---|
459 | while (cbCopy)
|
---|
460 | {
|
---|
461 | uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
|
---|
462 | memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
|
---|
463 |
|
---|
464 | pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
|
---|
465 | pFifo->cbUsed -= cbThisCopy;
|
---|
466 | pbDst += cbThisCopy;
|
---|
467 | cbCopied += cbThisCopy;
|
---|
468 | cbCopy -= cbThisCopy;
|
---|
469 | }
|
---|
470 |
|
---|
471 | return cbCopied;
|
---|
472 | }
|
---|
473 |
|
---|
474 |
|
---|
475 | #if 0 /* unused */
|
---|
476 | /**
|
---|
477 | * Tries to copy the requested amount of data from the provided buffer into the given FIFO.
|
---|
478 | *
|
---|
479 | * @returns Amount of bytes actually copied.
|
---|
480 | * @param pFifo The FIFO to copy data to.
|
---|
481 | * @param pvSrc Where to copy the data from.
|
---|
482 | * @param cbCopy How much to copy.
|
---|
483 | */
|
---|
484 | DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
|
---|
485 | {
|
---|
486 | size_t cbCopied = 0;
|
---|
487 | uint8_t *pbSrc = (uint8_t *)pvSrc;
|
---|
488 |
|
---|
489 | cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
|
---|
490 | while (cbCopy)
|
---|
491 | {
|
---|
492 | uint8_t cbThisCopy = (uint8_t)RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
|
---|
493 | memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
|
---|
494 |
|
---|
495 | pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
|
---|
496 | pFifo->cbUsed += cbThisCopy;
|
---|
497 | pbSrc += cbThisCopy;
|
---|
498 | cbCopied += cbThisCopy;
|
---|
499 | cbCopy -= cbThisCopy;
|
---|
500 | }
|
---|
501 |
|
---|
502 | return cbCopied;
|
---|
503 | }
|
---|
504 | #endif
|
---|
505 |
|
---|
506 |
|
---|
507 | /**
|
---|
508 | * Updates the delta bits for the given MSR register value which has the status line
|
---|
509 | * bits set.
|
---|
510 | *
|
---|
511 | * @param pDevIns The device instance.
|
---|
512 | * @param pThis The shared serial port instance data.
|
---|
513 | * @param pThisCC The serial port instance data for the current context.
|
---|
514 | * @param uMsrSts MSR value with the appropriate status bits set.
|
---|
515 | */
|
---|
516 | static void uartR3MsrUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uMsrSts)
|
---|
517 | {
|
---|
518 | /* Compare current and new states and set remaining bits accordingly. */
|
---|
519 | if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
|
---|
520 | uMsrSts |= UART_REG_MSR_DCTS;
|
---|
521 | if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
|
---|
522 | uMsrSts |= UART_REG_MSR_DDSR;
|
---|
523 | if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
|
---|
524 | uMsrSts |= UART_REG_MSR_TERI;
|
---|
525 | if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
|
---|
526 | uMsrSts |= UART_REG_MSR_DDCD;
|
---|
527 |
|
---|
528 | pThis->uRegMsr = uMsrSts;
|
---|
529 |
|
---|
530 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
531 | }
|
---|
532 |
|
---|
533 |
|
---|
534 | /**
|
---|
535 | * Updates the serial port parameters of the attached driver with the current configuration.
|
---|
536 | *
|
---|
537 | * @param pDevIns The device instance.
|
---|
538 | * @param pThis The shared serial port instance data.
|
---|
539 | * @param pThisCC The serial port instance data for the current context.
|
---|
540 | */
|
---|
541 | static void uartR3ParamsUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
542 | {
|
---|
543 | if ( pThis->uRegDivisor != 0
|
---|
544 | && pThisCC->pDrvSerial)
|
---|
545 | {
|
---|
546 | uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
|
---|
547 | unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
|
---|
548 | uint32_t cFrameBits = cDataBits;
|
---|
549 | PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
|
---|
550 | PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
|
---|
551 |
|
---|
552 | if (pThis->uRegLcr & UART_REG_LCR_STB)
|
---|
553 | {
|
---|
554 | enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
|
---|
555 | cFrameBits += 2;
|
---|
556 | }
|
---|
557 | else
|
---|
558 | cFrameBits++;
|
---|
559 |
|
---|
560 | if (pThis->uRegLcr & UART_REG_LCR_PEN)
|
---|
561 | {
|
---|
562 | /* Select the correct parity mode based on the even and stick parity bits. */
|
---|
563 | switch (pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK))
|
---|
564 | {
|
---|
565 | case 0:
|
---|
566 | enmParity = PDMSERIALPARITY_ODD;
|
---|
567 | break;
|
---|
568 | case UART_REG_LCR_EPS:
|
---|
569 | enmParity = PDMSERIALPARITY_EVEN;
|
---|
570 | break;
|
---|
571 | case UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK:
|
---|
572 | enmParity = PDMSERIALPARITY_SPACE;
|
---|
573 | break;
|
---|
574 | case UART_REG_LCR_PAR_STICK:
|
---|
575 | enmParity = PDMSERIALPARITY_MARK;
|
---|
576 | break;
|
---|
577 | default:
|
---|
578 | /* We should never get here as all cases where caught earlier. */
|
---|
579 | AssertMsgFailed(("This shouldn't happen at all: %#x\n",
|
---|
580 | pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK)));
|
---|
581 | }
|
---|
582 |
|
---|
583 | cFrameBits++;
|
---|
584 | }
|
---|
585 |
|
---|
586 | uint64_t uTimerFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->hTimerRcvFifoTimeout);
|
---|
587 | pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
|
---|
588 |
|
---|
589 | LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
|
---|
590 | uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
|
---|
591 |
|
---|
592 | int rc = pThisCC->pDrvSerial->pfnChgParams(pThisCC->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
|
---|
593 | if (RT_FAILURE(rc))
|
---|
594 | LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
|
---|
595 | pDevIns->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
|
---|
596 |
|
---|
597 | /* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
|
---|
598 | pThisCC->pDrvSerial->pfnQueuesFlush(pThisCC->pDrvSerial, true /*fQueueRecv*/, false /*fQueueXmit*/);
|
---|
599 | ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
|
---|
600 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
601 | }
|
---|
602 | }
|
---|
603 |
|
---|
604 |
|
---|
605 | /**
|
---|
606 | * Updates the internal device state with the given PDM status line states.
|
---|
607 | *
|
---|
608 | * @param pDevIns The device instance.
|
---|
609 | * @param pThis The shared serial port instance data.
|
---|
610 | * @param pThisCC The serial port instance data for the current context.
|
---|
611 | * @param fStsLines The PDM status line states.
|
---|
612 | */
|
---|
613 | static void uartR3StsLinesUpdate(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t fStsLines)
|
---|
614 | {
|
---|
615 | uint8_t uRegMsrNew = 0; /* The new MSR value. */
|
---|
616 |
|
---|
617 | if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
|
---|
618 | uRegMsrNew |= UART_REG_MSR_DCD;
|
---|
619 | if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
|
---|
620 | uRegMsrNew |= UART_REG_MSR_RI;
|
---|
621 | if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
|
---|
622 | uRegMsrNew |= UART_REG_MSR_DSR;
|
---|
623 | if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
|
---|
624 | uRegMsrNew |= UART_REG_MSR_CTS;
|
---|
625 |
|
---|
626 | uartR3MsrUpdate(pDevIns, pThis, pThisCC, uRegMsrNew);
|
---|
627 | }
|
---|
628 |
|
---|
629 |
|
---|
630 | /**
|
---|
631 | * Fills up the receive FIFO with as much data as possible.
|
---|
632 | *
|
---|
633 | * @param pDevIns The device instance.
|
---|
634 | * @param pThis The shared serial port instance data.
|
---|
635 | * @param pThisCC The serial port instance data for the current context.
|
---|
636 | */
|
---|
637 | static void uartR3RecvFifoFill(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
638 | {
|
---|
639 | LogFlowFunc(("pThis=%#p\n", pThis));
|
---|
640 |
|
---|
641 | PUARTFIFO pFifo = &pThis->FifoRecv;
|
---|
642 | size_t const cbFifoFree = uartFifoFreeGet(pFifo);
|
---|
643 | uint32_t const cbAvailRdr = ASMAtomicReadU32(&pThis->cbAvailRdr);
|
---|
644 | size_t const cbFill = RT_MIN(cbFifoFree, cbAvailRdr);
|
---|
645 | size_t cbFilled = 0;
|
---|
646 |
|
---|
647 | while (cbFilled < cbFill)
|
---|
648 | {
|
---|
649 | size_t cbThisRead = cbFill - cbFilled;
|
---|
650 |
|
---|
651 | if (pFifo->offRead <= pFifo->offWrite)
|
---|
652 | cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
|
---|
653 | else
|
---|
654 | cbThisRead = RT_MIN(cbThisRead, (uint8_t)(pFifo->offRead - pFifo->offWrite));
|
---|
655 |
|
---|
656 | size_t cbRead = 0;
|
---|
657 | int rc = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
|
---|
658 | AssertRC(rc); Assert(cbRead <= UINT8_MAX); RT_NOREF(rc);
|
---|
659 |
|
---|
660 | pFifo->offWrite = (pFifo->offWrite + (uint8_t)cbRead) % pFifo->cbMax;
|
---|
661 | pFifo->cbUsed += (uint8_t)cbRead;
|
---|
662 | cbFilled += cbRead;
|
---|
663 |
|
---|
664 | if (cbRead < cbThisRead)
|
---|
665 | break;
|
---|
666 | }
|
---|
667 |
|
---|
668 | if (cbFilled)
|
---|
669 | {
|
---|
670 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
671 | if (pFifo->cbUsed < pFifo->cbItl)
|
---|
672 | {
|
---|
673 | pThis->fIrqCtiPending = false;
|
---|
674 | PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout, pThis->cSymbolXferTicks * 4, NULL);
|
---|
675 | }
|
---|
676 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
677 | }
|
---|
678 |
|
---|
679 | Assert(cbFilled <= (size_t)pThis->cbAvailRdr);
|
---|
680 | ASMAtomicSubU32(&pThis->cbAvailRdr, (uint32_t)cbFilled);
|
---|
681 | }
|
---|
682 |
|
---|
683 |
|
---|
684 | /**
|
---|
685 | * Fetches a single byte and writes it to RBR.
|
---|
686 | *
|
---|
687 | * @param pDevIns The device instance.
|
---|
688 | * @param pThis The shared serial port instance data.
|
---|
689 | * @param pThisCC The serial port instance data for the current context.
|
---|
690 | */
|
---|
691 | static void uartR3ByteFetch(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
692 | {
|
---|
693 | if (ASMAtomicReadU32(&pThis->cbAvailRdr))
|
---|
694 | {
|
---|
695 | size_t cbRead = 0;
|
---|
696 | int rc2 = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
|
---|
697 | AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
|
---|
698 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
699 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
700 | }
|
---|
701 | }
|
---|
702 |
|
---|
703 |
|
---|
704 | /**
|
---|
705 | * Fetches a ready data based on the FIFO setting.
|
---|
706 | *
|
---|
707 | * @param pDevIns The device instance.
|
---|
708 | * @param pThis The shared serial port instance data.
|
---|
709 | * @param pThisCC The serial port instance data for the current context.
|
---|
710 | */
|
---|
711 | static void uartR3DataFetch(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
712 | {
|
---|
713 | AssertPtrReturnVoid(pThisCC->pDrvSerial);
|
---|
714 |
|
---|
715 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
|
---|
716 | uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
|
---|
717 | else
|
---|
718 | uartR3ByteFetch(pDevIns, pThis, pThisCC);
|
---|
719 | }
|
---|
720 |
|
---|
721 |
|
---|
722 | /**
|
---|
723 | * Reset the transmit/receive related bits to the standard values
|
---|
724 | * (after a detach/attach/reset event).
|
---|
725 | *
|
---|
726 | * @param pDevIns The device instance.
|
---|
727 | * @param pThis The shared serial port instance data.
|
---|
728 | * @param pThisCC The serial port instance data for the current context.
|
---|
729 | */
|
---|
730 | static void uartR3XferReset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
731 | {
|
---|
732 | PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
|
---|
733 | PDMDevHlpTimerStop(pDevIns, pThis->hTimerTxUnconnected);
|
---|
734 | pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
|
---|
735 | pThis->fThreEmptyPending = false;
|
---|
736 |
|
---|
737 | uartFifoClear(&pThis->FifoXmit);
|
---|
738 | uartFifoClear(&pThis->FifoRecv);
|
---|
739 | uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
|
---|
740 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
741 |
|
---|
742 | if (pThisCC->pDrvSerial)
|
---|
743 | {
|
---|
744 | /* Set the modem lines to reflect the current state. */
|
---|
745 | int rc = pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial, false /*fRts*/, false /*fDtr*/);
|
---|
746 | if (RT_FAILURE(rc))
|
---|
747 | LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
|
---|
748 | pDevIns->iInstance, rc));
|
---|
749 |
|
---|
750 | uint32_t fStsLines = 0;
|
---|
751 | rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
|
---|
752 | if (RT_SUCCESS(rc))
|
---|
753 | uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
|
---|
754 | else
|
---|
755 | LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
|
---|
756 | pDevIns->iInstance, rc));
|
---|
757 | }
|
---|
758 |
|
---|
759 | }
|
---|
760 |
|
---|
761 |
|
---|
762 | /**
|
---|
763 | * Tries to copy the specified amount of data from the active TX queue (register or FIFO).
|
---|
764 | *
|
---|
765 | * @param pDevIns The device instance.
|
---|
766 | * @param pThis The shared serial port instance data.
|
---|
767 | * @param pThisCC The serial port instance data for the current context.
|
---|
768 | * @param pvBuf Where to store the data.
|
---|
769 | * @param cbRead How much to read from the TX queue.
|
---|
770 | * @param pcbRead Where to store the amount of data read.
|
---|
771 | */
|
---|
772 | static void uartR3TxQueueCopyFrom(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
|
---|
773 | void *pvBuf, size_t cbRead, size_t *pcbRead)
|
---|
774 | {
|
---|
775 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
|
---|
776 | {
|
---|
777 | *pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
|
---|
778 | if (!pThis->FifoXmit.cbUsed)
|
---|
779 | {
|
---|
780 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
|
---|
781 | pThis->fThreEmptyPending = true;
|
---|
782 | }
|
---|
783 | if (*pcbRead)
|
---|
784 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
|
---|
785 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
786 | }
|
---|
787 | else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
|
---|
788 | {
|
---|
789 | *(uint8_t *)pvBuf = pThis->uRegThr;
|
---|
790 | *pcbRead = 1;
|
---|
791 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
|
---|
792 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
|
---|
793 | pThis->fThreEmptyPending = true;
|
---|
794 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
795 | }
|
---|
796 | else
|
---|
797 | {
|
---|
798 | /*
|
---|
799 | * This can happen if there was data in the FIFO when the connection was closed,
|
---|
800 | * indicate this condition to the lower driver by returning 0 bytes.
|
---|
801 | */
|
---|
802 | *pcbRead = 0;
|
---|
803 | }
|
---|
804 | }
|
---|
805 |
|
---|
806 | #endif /* IN_RING3 */
|
---|
807 |
|
---|
808 |
|
---|
809 | /**
|
---|
810 | * Transmits the given byte.
|
---|
811 | *
|
---|
812 | * @returns Strict VBox status code.
|
---|
813 | * @param pDevIns The device instance.
|
---|
814 | * @param pThis The shared serial port instance data.
|
---|
815 | * @param pThisCC The serial port instance data for the current context.
|
---|
816 | * @param bVal Byte to transmit.
|
---|
817 | */
|
---|
818 | static VBOXSTRICTRC uartXmit(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t bVal)
|
---|
819 | {
|
---|
820 | int rc = VINF_SUCCESS;
|
---|
821 | #ifdef IN_RING3
|
---|
822 | bool fNotifyDrv = false;
|
---|
823 | #endif
|
---|
824 |
|
---|
825 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
|
---|
826 | {
|
---|
827 | #ifndef IN_RING3
|
---|
828 | RT_NOREF(pDevIns, pThisCC);
|
---|
829 | if (!uartFifoUsedGet(&pThis->FifoXmit))
|
---|
830 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
831 | else
|
---|
832 | {
|
---|
833 | uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, bVal);
|
---|
834 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
|
---|
835 | }
|
---|
836 | #else
|
---|
837 | uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, bVal);
|
---|
838 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
|
---|
839 | pThis->fThreEmptyPending = false;
|
---|
840 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
841 | if (uartFifoUsedGet(&pThis->FifoXmit) == 1)
|
---|
842 | fNotifyDrv = true;
|
---|
843 | #endif
|
---|
844 | }
|
---|
845 | else
|
---|
846 | {
|
---|
847 | /* Notify the lower driver about available data only if the register was empty before. */
|
---|
848 | if (pThis->uRegLsr & UART_REG_LSR_THRE)
|
---|
849 | {
|
---|
850 | #ifndef IN_RING3
|
---|
851 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
852 | #else
|
---|
853 | pThis->uRegThr = bVal;
|
---|
854 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
|
---|
855 | pThis->fThreEmptyPending = false;
|
---|
856 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
857 | fNotifyDrv = true;
|
---|
858 | #endif
|
---|
859 | }
|
---|
860 | else
|
---|
861 | pThis->uRegThr = bVal;
|
---|
862 | }
|
---|
863 |
|
---|
864 | #ifdef IN_RING3
|
---|
865 | if (fNotifyDrv)
|
---|
866 | {
|
---|
867 | /* Leave the device critical section before calling into the lower driver. */
|
---|
868 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
869 |
|
---|
870 | if ( pThisCC->pDrvSerial
|
---|
871 | && !(pThis->uRegMcr & UART_REG_MCR_LOOP))
|
---|
872 | {
|
---|
873 | int rc2 = pThisCC->pDrvSerial->pfnDataAvailWrNotify(pThisCC->pDrvSerial);
|
---|
874 | if (RT_FAILURE(rc2))
|
---|
875 | LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", pDevIns->iInstance, rc2));
|
---|
876 | }
|
---|
877 | else
|
---|
878 | PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerTxUnconnected, pThis->cSymbolXferTicks, NULL);
|
---|
879 |
|
---|
880 | rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_SUCCESS);
|
---|
881 | }
|
---|
882 | #endif
|
---|
883 |
|
---|
884 | return rc;
|
---|
885 | }
|
---|
886 |
|
---|
887 |
|
---|
888 | /**
|
---|
889 | * Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
|
---|
890 | *
|
---|
891 | * @returns Strict VBox status code.
|
---|
892 | * @param pDevIns The device instance.
|
---|
893 | * @param pThis The shared serial port instance data.
|
---|
894 | * @param pThisCC The serial port instance data for the current context.
|
---|
895 | * @param uVal The value to write.
|
---|
896 | */
|
---|
897 | DECLINLINE(VBOXSTRICTRC) uartRegThrDllWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
|
---|
898 | {
|
---|
899 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
900 |
|
---|
901 | /* A set DLAB causes a write to the lower 8bits of the divisor latch. */
|
---|
902 | if (pThis->uRegLcr & UART_REG_LCR_DLAB)
|
---|
903 | {
|
---|
904 | if (uVal != (pThis->uRegDivisor & 0xff))
|
---|
905 | {
|
---|
906 | #ifndef IN_RING3
|
---|
907 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
908 | #else
|
---|
909 | pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) | uVal;
|
---|
910 | uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
|
---|
911 | #endif
|
---|
912 | }
|
---|
913 | }
|
---|
914 | else
|
---|
915 | rc = uartXmit(pDevIns, pThis, pThisCC, uVal);
|
---|
916 |
|
---|
917 | return rc;
|
---|
918 | }
|
---|
919 |
|
---|
920 |
|
---|
921 | /**
|
---|
922 | * Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
|
---|
923 | *
|
---|
924 | * @returns Strict VBox status code.
|
---|
925 | * @param pDevIns The device instance.
|
---|
926 | * @param pThis The shared serial port instance data.
|
---|
927 | * @param pThisCC The serial port instance data for the current context.
|
---|
928 | * @param uVal The value to write.
|
---|
929 | */
|
---|
930 | DECLINLINE(VBOXSTRICTRC) uartRegIerDlmWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
|
---|
931 | {
|
---|
932 | /* A set DLAB causes a write to the higher 8bits of the divisor latch. */
|
---|
933 | if (pThis->uRegLcr & UART_REG_LCR_DLAB)
|
---|
934 | {
|
---|
935 | if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
|
---|
936 | {
|
---|
937 | #ifndef IN_RING3
|
---|
938 | return VINF_IOM_R3_IOPORT_WRITE;
|
---|
939 | #else
|
---|
940 | pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) | (uVal << 8);
|
---|
941 | uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
|
---|
942 | #endif
|
---|
943 | }
|
---|
944 | }
|
---|
945 | else
|
---|
946 | {
|
---|
947 | if (pThis->enmType < UARTTYPE_16750)
|
---|
948 | pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
|
---|
949 | else
|
---|
950 | pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
|
---|
951 |
|
---|
952 | if (pThis->uRegLsr & UART_REG_LSR_THRE)
|
---|
953 | pThis->fThreEmptyPending = true;
|
---|
954 |
|
---|
955 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
956 | }
|
---|
957 | return VINF_SUCCESS;
|
---|
958 | }
|
---|
959 |
|
---|
960 |
|
---|
961 | /**
|
---|
962 | * Write handler for the FCR register.
|
---|
963 | *
|
---|
964 | * @returns Strict VBox status code.
|
---|
965 | * @param pDevIns The device instance.
|
---|
966 | * @param pThis The shared serial port instance data.
|
---|
967 | * @param pThisCC The serial port instance data for the current context.
|
---|
968 | * @param uVal The value to write.
|
---|
969 | */
|
---|
970 | DECLINLINE(VBOXSTRICTRC) uartRegFcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
|
---|
971 | {
|
---|
972 | #ifndef IN_RING3
|
---|
973 | RT_NOREF(pDevIns, pThis, pThisCC, uVal);
|
---|
974 | return VINF_IOM_R3_IOPORT_WRITE;
|
---|
975 | #else /* IN_RING3 */
|
---|
976 | if ( pThis->enmType >= UARTTYPE_16550A
|
---|
977 | && uVal != pThis->uRegFcr)
|
---|
978 | {
|
---|
979 | /* A change in the FIFO enable bit clears both FIFOs automatically. */
|
---|
980 | if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
|
---|
981 | {
|
---|
982 | uartFifoClear(&pThis->FifoXmit);
|
---|
983 | uartFifoClear(&pThis->FifoRecv);
|
---|
984 |
|
---|
985 | /*
|
---|
986 | * If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
|
---|
987 | * byte in the RBR register which will be lost so we have to adjust the available bytes.
|
---|
988 | */
|
---|
989 | if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
|
---|
990 | && (uVal & UART_REG_FCR_FIFO_EN))
|
---|
991 | ASMAtomicDecU32(&pThis->cbAvailRdr);
|
---|
992 |
|
---|
993 | /* Clear the DR bit too. */
|
---|
994 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
995 | }
|
---|
996 |
|
---|
997 | /** @todo r=bird: Why was this here: if (rc == VINF_SUCCESS) */
|
---|
998 | {
|
---|
999 | if (uVal & UART_REG_FCR_RCV_FIFO_RST)
|
---|
1000 | {
|
---|
1001 | PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
|
---|
1002 | pThis->fIrqCtiPending = false;
|
---|
1003 | uartFifoClear(&pThis->FifoRecv);
|
---|
1004 | }
|
---|
1005 | if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
|
---|
1006 | uartFifoClear(&pThis->FifoXmit);
|
---|
1007 |
|
---|
1008 | /*
|
---|
1009 | * The 64byte FIFO enable bit is only changeable for 16750
|
---|
1010 | * and if the DLAB bit in LCR is set.
|
---|
1011 | */
|
---|
1012 | if ( pThis->enmType < UARTTYPE_16750
|
---|
1013 | || !(pThis->uRegLcr & UART_REG_LCR_DLAB))
|
---|
1014 | uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
|
---|
1015 | else /* Use previous value. */
|
---|
1016 | uVal |= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
|
---|
1017 |
|
---|
1018 | if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
|
---|
1019 | {
|
---|
1020 | pThis->FifoRecv.cbMax = 64;
|
---|
1021 | pThis->FifoXmit.cbMax = 64;
|
---|
1022 | }
|
---|
1023 | else
|
---|
1024 | {
|
---|
1025 | pThis->FifoRecv.cbMax = 16;
|
---|
1026 | pThis->FifoXmit.cbMax = 16;
|
---|
1027 | }
|
---|
1028 |
|
---|
1029 | if (uVal & UART_REG_FCR_FIFO_EN)
|
---|
1030 | {
|
---|
1031 | uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
|
---|
1032 | if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
|
---|
1033 | pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
|
---|
1034 | else
|
---|
1035 | pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
|
---|
1036 | }
|
---|
1037 |
|
---|
1038 | /* The FIFO reset bits are self clearing. */
|
---|
1039 | pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
|
---|
1040 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1041 | }
|
---|
1042 |
|
---|
1043 | /* Fill in the next data. */
|
---|
1044 | if (ASMAtomicReadU32(&pThis->cbAvailRdr))
|
---|
1045 | uartR3DataFetch(pDevIns, pThis, pThisCC);
|
---|
1046 | }
|
---|
1047 |
|
---|
1048 | return VINF_SUCCESS;
|
---|
1049 | #endif /* IN_RING3 */
|
---|
1050 | }
|
---|
1051 |
|
---|
1052 |
|
---|
1053 | /**
|
---|
1054 | * Write handler for the LCR register.
|
---|
1055 | *
|
---|
1056 | * @returns Strict VBox status code.
|
---|
1057 | * @param pDevIns The device instance.
|
---|
1058 | * @param pThis The shared serial port instance data.
|
---|
1059 | * @param pThisCC The serial port instance data for the current context.
|
---|
1060 | * @param uVal The value to write.
|
---|
1061 | */
|
---|
1062 | DECLINLINE(VBOXSTRICTRC) uartRegLcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
|
---|
1063 | {
|
---|
1064 | /* Any change except the DLAB bit causes a switch to R3. */
|
---|
1065 | if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
|
---|
1066 | {
|
---|
1067 | #ifndef IN_RING3
|
---|
1068 | RT_NOREF(pThisCC, pDevIns);
|
---|
1069 | return VINF_IOM_R3_IOPORT_WRITE;
|
---|
1070 | #else
|
---|
1071 | /* Check whether the BREAK bit changed before updating the LCR value. */
|
---|
1072 | bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
|
---|
1073 | bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
|
---|
1074 | pThis->uRegLcr = uVal;
|
---|
1075 | uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
|
---|
1076 |
|
---|
1077 | if ( fBrkChg
|
---|
1078 | && pThisCC->pDrvSerial)
|
---|
1079 | pThisCC->pDrvSerial->pfnChgBrk(pThisCC->pDrvSerial, fBrkEn);
|
---|
1080 | #endif
|
---|
1081 | }
|
---|
1082 | else
|
---|
1083 | pThis->uRegLcr = uVal;
|
---|
1084 |
|
---|
1085 | return VINF_SUCCESS;
|
---|
1086 | }
|
---|
1087 |
|
---|
1088 |
|
---|
1089 | /**
|
---|
1090 | * Write handler for the MCR register.
|
---|
1091 | *
|
---|
1092 | * @returns Strict VBox status code.
|
---|
1093 | * @param pDevIns The device instance.
|
---|
1094 | * @param pThis The shared serial port instance data.
|
---|
1095 | * @param pThisCC The serial port instance data for the current context.
|
---|
1096 | * @param uVal The value to write.
|
---|
1097 | */
|
---|
1098 | DECLINLINE(VBOXSTRICTRC) uartRegMcrWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint8_t uVal)
|
---|
1099 | {
|
---|
1100 | if (pThis->enmType < UARTTYPE_16750)
|
---|
1101 | uVal &= UART_REG_MCR_MASK_WR;
|
---|
1102 | else
|
---|
1103 | uVal &= UART_REG_MCR_MASK_WR_15750;
|
---|
1104 | if (pThis->uRegMcr != uVal)
|
---|
1105 | {
|
---|
1106 | #ifndef IN_RING3
|
---|
1107 | RT_NOREF(pThisCC, pDevIns);
|
---|
1108 | return VINF_IOM_R3_IOPORT_WRITE;
|
---|
1109 | #else
|
---|
1110 | /*
|
---|
1111 | * When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
|
---|
1112 | * disconnected and looped back to MSR.
|
---|
1113 | */
|
---|
1114 | if ( (uVal & UART_REG_MCR_LOOP)
|
---|
1115 | && !(pThis->uRegMcr & UART_REG_MCR_LOOP)
|
---|
1116 | && pThisCC->pDrvSerial)
|
---|
1117 | pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial, false /*fRts*/, false /*fDtr*/);
|
---|
1118 |
|
---|
1119 | pThis->uRegMcr = uVal;
|
---|
1120 | if (uVal & UART_REG_MCR_LOOP)
|
---|
1121 | {
|
---|
1122 | uint8_t uRegMsrSts = 0;
|
---|
1123 |
|
---|
1124 | if (uVal & UART_REG_MCR_RTS)
|
---|
1125 | uRegMsrSts |= UART_REG_MSR_CTS;
|
---|
1126 | if (uVal & UART_REG_MCR_DTR)
|
---|
1127 | uRegMsrSts |= UART_REG_MSR_DSR;
|
---|
1128 | if (uVal & UART_REG_MCR_OUT1)
|
---|
1129 | uRegMsrSts |= UART_REG_MSR_RI;
|
---|
1130 | if (uVal & UART_REG_MCR_OUT2)
|
---|
1131 | uRegMsrSts |= UART_REG_MSR_DCD;
|
---|
1132 | uartR3MsrUpdate(pDevIns, pThis, pThisCC, uRegMsrSts);
|
---|
1133 | }
|
---|
1134 | else if (pThisCC->pDrvSerial)
|
---|
1135 | {
|
---|
1136 | pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial,
|
---|
1137 | RT_BOOL(uVal & UART_REG_MCR_RTS),
|
---|
1138 | RT_BOOL(uVal & UART_REG_MCR_DTR));
|
---|
1139 |
|
---|
1140 | uint32_t fStsLines = 0;
|
---|
1141 | int rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
|
---|
1142 | if (RT_SUCCESS(rc))
|
---|
1143 | uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
|
---|
1144 | else
|
---|
1145 | LogRelMax(10, ("Serial#%d: Failed to query status line status with %Rrc during reset\n",
|
---|
1146 | pDevIns->iInstance, rc));
|
---|
1147 | }
|
---|
1148 | else /* Loopback mode got disabled and no driver attached, fake presence. */
|
---|
1149 | uartR3MsrUpdate(pDevIns, pThis, pThisCC, UART_REG_MSR_DCD | UART_REG_MSR_CTS | UART_REG_MSR_DSR);
|
---|
1150 | #endif
|
---|
1151 | }
|
---|
1152 |
|
---|
1153 | return VINF_SUCCESS;
|
---|
1154 | }
|
---|
1155 |
|
---|
1156 |
|
---|
1157 | /**
|
---|
1158 | * Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
|
---|
1159 | *
|
---|
1160 | * @returns VBox status code.
|
---|
1161 | * @param pDevIns The device instance.
|
---|
1162 | * @param pThis The shared serial port instance data.
|
---|
1163 | * @param pThisCC The serial port instance data for the current context.
|
---|
1164 | * @param puVal Where to store the read value on success.
|
---|
1165 | */
|
---|
1166 | DECLINLINE(VBOXSTRICTRC) uartRegRbrDllRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
|
---|
1167 | {
|
---|
1168 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
1169 |
|
---|
1170 | /* A set DLAB causes a read from the lower 8bits of the divisor latch. */
|
---|
1171 | if (pThis->uRegLcr & UART_REG_LCR_DLAB)
|
---|
1172 | *puVal = pThis->uRegDivisor & 0xff;
|
---|
1173 | else
|
---|
1174 | {
|
---|
1175 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
|
---|
1176 | {
|
---|
1177 | /*
|
---|
1178 | * Only go back to R3 if there is new data available for the FIFO
|
---|
1179 | * and we would clear the interrupt to fill it up again.
|
---|
1180 | */
|
---|
1181 | if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
|
---|
1182 | && ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
|
---|
1183 | {
|
---|
1184 | #ifndef IN_RING3
|
---|
1185 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1186 | #else
|
---|
1187 | uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
|
---|
1188 | #endif
|
---|
1189 | }
|
---|
1190 |
|
---|
1191 | if (rc == VINF_SUCCESS)
|
---|
1192 | {
|
---|
1193 | *puVal = uartFifoGet(&pThis->FifoRecv);
|
---|
1194 | pThis->fIrqCtiPending = false;
|
---|
1195 | if (!pThis->FifoRecv.cbUsed)
|
---|
1196 | {
|
---|
1197 | PDMDevHlpTimerStop(pDevIns, pThis->hTimerRcvFifoTimeout);
|
---|
1198 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
1199 | }
|
---|
1200 | else if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
|
---|
1201 | PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout,
|
---|
1202 | pThis->cSymbolXferTicks * 4, NULL);
|
---|
1203 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1204 | }
|
---|
1205 | }
|
---|
1206 | else
|
---|
1207 | {
|
---|
1208 | *puVal = pThis->uRegRbr;
|
---|
1209 |
|
---|
1210 | if (pThis->uRegLsr & UART_REG_LSR_DR)
|
---|
1211 | {
|
---|
1212 | Assert(pThis->cbAvailRdr);
|
---|
1213 | uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
|
---|
1214 | if (!cbAvail)
|
---|
1215 | {
|
---|
1216 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
1217 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1218 | }
|
---|
1219 | else
|
---|
1220 | {
|
---|
1221 | #ifndef IN_RING3
|
---|
1222 | /* Restore state and go back to R3. */
|
---|
1223 | ASMAtomicIncU32(&pThis->cbAvailRdr);
|
---|
1224 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1225 | #else
|
---|
1226 | /* Fetch new data and keep the DR bit set. */
|
---|
1227 | uartR3DataFetch(pDevIns, pThis, pThisCC);
|
---|
1228 | #endif
|
---|
1229 | }
|
---|
1230 | }
|
---|
1231 | }
|
---|
1232 | }
|
---|
1233 |
|
---|
1234 | return rc;
|
---|
1235 | }
|
---|
1236 |
|
---|
1237 |
|
---|
1238 | /**
|
---|
1239 | * Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
|
---|
1240 | *
|
---|
1241 | * @param pThis The shared serial port instance data.
|
---|
1242 | * @param puVal Where to store the read value on success.
|
---|
1243 | */
|
---|
1244 | DECLINLINE(void) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
|
---|
1245 | {
|
---|
1246 | /* A set DLAB causes a read from the upper 8bits of the divisor latch. */
|
---|
1247 | if (pThis->uRegLcr & UART_REG_LCR_DLAB)
|
---|
1248 | *puVal = (pThis->uRegDivisor & 0xff00) >> 8;
|
---|
1249 | else
|
---|
1250 | *puVal = pThis->uRegIer;
|
---|
1251 | }
|
---|
1252 |
|
---|
1253 |
|
---|
1254 | /**
|
---|
1255 | * Read handler for the IIR register.
|
---|
1256 | *
|
---|
1257 | * @param pDevIns The device instance.
|
---|
1258 | * @param pThis The shared serial port instance data.
|
---|
1259 | * @param pThisCC The serial port instance data for the current context.
|
---|
1260 | * @param puVal Where to store the read value on success.
|
---|
1261 | */
|
---|
1262 | DECLINLINE(void) uartRegIirRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
|
---|
1263 | {
|
---|
1264 | *puVal = pThis->uRegIir;
|
---|
1265 | /* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
|
---|
1266 | if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
|
---|
1267 | {
|
---|
1268 | pThis->fThreEmptyPending = false;
|
---|
1269 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1270 | }
|
---|
1271 | }
|
---|
1272 |
|
---|
1273 |
|
---|
1274 | /**
|
---|
1275 | * Read handler for the LSR register.
|
---|
1276 | *
|
---|
1277 | * @returns Strict VBox status code.
|
---|
1278 | * @param pDevIns The device instance.
|
---|
1279 | * @param pThis The shared serial port instance data.
|
---|
1280 | * @param pThisCC The serial port instance data for the current context.
|
---|
1281 | * @param puVal Where to store the read value on success.
|
---|
1282 | */
|
---|
1283 | DECLINLINE(VBOXSTRICTRC) uartRegLsrRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
|
---|
1284 | {
|
---|
1285 | /* Yield if configured and there is no data available. */
|
---|
1286 | if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
|
---|
1287 | && (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
|
---|
1288 | {
|
---|
1289 | #ifndef IN_RING3
|
---|
1290 | return VINF_IOM_R3_IOPORT_READ;
|
---|
1291 | #else
|
---|
1292 | RTThreadYield();
|
---|
1293 | #endif
|
---|
1294 | }
|
---|
1295 |
|
---|
1296 | *puVal = pThis->uRegLsr;
|
---|
1297 | /*
|
---|
1298 | * Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
|
---|
1299 | * as well as the Break Interrupt (BI).
|
---|
1300 | */
|
---|
1301 | UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
|
---|
1302 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1303 |
|
---|
1304 | return VINF_SUCCESS;
|
---|
1305 | }
|
---|
1306 |
|
---|
1307 |
|
---|
1308 | /**
|
---|
1309 | * Read handler for the MSR register.
|
---|
1310 | *
|
---|
1311 | * @param pDevIns The device instance.
|
---|
1312 | * @param pThis The shared serial port instance data.
|
---|
1313 | * @param pThisCC The serial port instance data for the current context.
|
---|
1314 | * @param puVal Where to store the read value on success.
|
---|
1315 | */
|
---|
1316 | DECLINLINE(void) uartRegMsrRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, uint32_t *puVal)
|
---|
1317 | {
|
---|
1318 | *puVal = pThis->uRegMsr;
|
---|
1319 |
|
---|
1320 | /* Clear any of the delta bits. */
|
---|
1321 | UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
|
---|
1322 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1323 | }
|
---|
1324 |
|
---|
1325 |
|
---|
1326 | #ifdef LOG_ENABLED
|
---|
1327 | /**
|
---|
1328 | * Converts the register index into a sensible memnonic.
|
---|
1329 | *
|
---|
1330 | * @returns Register memnonic.
|
---|
1331 | * @param pThis The shared serial port instance data.
|
---|
1332 | * @param idxReg Register index.
|
---|
1333 | * @param fWrite Flag whether the register gets written.
|
---|
1334 | */
|
---|
1335 | DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
|
---|
1336 | {
|
---|
1337 | const char *psz = "INV";
|
---|
1338 |
|
---|
1339 | switch (idxReg)
|
---|
1340 | {
|
---|
1341 | /*case UART_REG_THR_DLL_INDEX:*/
|
---|
1342 | case UART_REG_RBR_DLL_INDEX:
|
---|
1343 | if (pThis->uRegLcr & UART_REG_LCR_DLAB)
|
---|
1344 | psz = "DLL";
|
---|
1345 | else if (fWrite)
|
---|
1346 | psz = "THR";
|
---|
1347 | else
|
---|
1348 | psz = "RBR";
|
---|
1349 | break;
|
---|
1350 | case UART_REG_IER_DLM_INDEX:
|
---|
1351 | if (pThis->uRegLcr & UART_REG_LCR_DLAB)
|
---|
1352 | psz = "DLM";
|
---|
1353 | else
|
---|
1354 | psz = "IER";
|
---|
1355 | break;
|
---|
1356 | /*case UART_REG_IIR_INDEX:*/
|
---|
1357 | case UART_REG_FCR_INDEX:
|
---|
1358 | if (fWrite)
|
---|
1359 | psz = "FCR";
|
---|
1360 | else
|
---|
1361 | psz = "IIR";
|
---|
1362 | break;
|
---|
1363 | case UART_REG_LCR_INDEX:
|
---|
1364 | psz = "LCR";
|
---|
1365 | break;
|
---|
1366 | case UART_REG_MCR_INDEX:
|
---|
1367 | psz = "MCR";
|
---|
1368 | break;
|
---|
1369 | case UART_REG_LSR_INDEX:
|
---|
1370 | psz = "LSR";
|
---|
1371 | break;
|
---|
1372 | case UART_REG_MSR_INDEX:
|
---|
1373 | psz = "MSR";
|
---|
1374 | break;
|
---|
1375 | case UART_REG_SCR_INDEX:
|
---|
1376 | psz = "SCR";
|
---|
1377 | break;
|
---|
1378 | }
|
---|
1379 |
|
---|
1380 | return psz;
|
---|
1381 | }
|
---|
1382 | #endif
|
---|
1383 |
|
---|
1384 |
|
---|
1385 | /**
|
---|
1386 | * Performs a register write to the given register offset.
|
---|
1387 | *
|
---|
1388 | * @returns Strict VBox status code.
|
---|
1389 | * @param pDevIns The device instance.
|
---|
1390 | * @param pThis The shared UART core instance data.
|
---|
1391 | * @param pThisCC The current context UART core instance data.
|
---|
1392 | * @param uReg The register offset (byte offset) to start writing to.
|
---|
1393 | * @param u32 The value to write.
|
---|
1394 | * @param cb Number of bytes to write.
|
---|
1395 | */
|
---|
1396 | DECLHIDDEN(VBOXSTRICTRC) uartRegWrite(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
|
---|
1397 | uint32_t uReg, uint32_t u32, size_t cb)
|
---|
1398 | {
|
---|
1399 | AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
|
---|
1400 |
|
---|
1401 | VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
|
---|
1402 | if (rc == VINF_SUCCESS)
|
---|
1403 | {
|
---|
1404 | uint8_t idxReg = uReg & 0x7;
|
---|
1405 | LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
|
---|
1406 | pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /*fWrite*/), u32, cb));
|
---|
1407 |
|
---|
1408 | uint8_t uVal = (uint8_t)u32;
|
---|
1409 | switch (idxReg)
|
---|
1410 | {
|
---|
1411 | case UART_REG_THR_DLL_INDEX:
|
---|
1412 | rc = uartRegThrDllWrite(pDevIns, pThis, pThisCC, uVal);
|
---|
1413 | break;
|
---|
1414 | case UART_REG_IER_DLM_INDEX:
|
---|
1415 | rc = uartRegIerDlmWrite(pDevIns, pThis, pThisCC, uVal);
|
---|
1416 | break;
|
---|
1417 | case UART_REG_FCR_INDEX:
|
---|
1418 | rc = uartRegFcrWrite(pDevIns, pThis, pThisCC, uVal);
|
---|
1419 | break;
|
---|
1420 | case UART_REG_LCR_INDEX:
|
---|
1421 | rc = uartRegLcrWrite(pDevIns, pThis, pThisCC, uVal);
|
---|
1422 | break;
|
---|
1423 | case UART_REG_MCR_INDEX:
|
---|
1424 | rc = uartRegMcrWrite(pDevIns, pThis, pThisCC, uVal);
|
---|
1425 | break;
|
---|
1426 | case UART_REG_SCR_INDEX:
|
---|
1427 | pThis->uRegScr = uVal;
|
---|
1428 | break;
|
---|
1429 | default:
|
---|
1430 | break;
|
---|
1431 | }
|
---|
1432 |
|
---|
1433 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1434 | }
|
---|
1435 | LogFlowFunc(("-> %Rrc\n", VBOXSTRICTRC_VAL(rc)));
|
---|
1436 | return rc;
|
---|
1437 | }
|
---|
1438 |
|
---|
1439 |
|
---|
1440 | /**
|
---|
1441 | * Performs a register read from the given register offset.
|
---|
1442 | *
|
---|
1443 | * @returns VBox status code.
|
---|
1444 | * @param pDevIns The device instance.
|
---|
1445 | * @param pThis The shared UART core instance data.
|
---|
1446 | * @param pThisCC The current context UART core instance data.
|
---|
1447 | * @param uReg The register offset (byte offset) to start reading from.
|
---|
1448 | * @param pu32 Where to store the read value.
|
---|
1449 | * @param cb Number of bytes to read.
|
---|
1450 | */
|
---|
1451 | DECLHIDDEN(VBOXSTRICTRC) uartRegRead(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
|
---|
1452 | uint32_t uReg, uint32_t *pu32, size_t cb)
|
---|
1453 | {
|
---|
1454 | if (cb != 1)
|
---|
1455 | return VERR_IOM_IOPORT_UNUSED;
|
---|
1456 |
|
---|
1457 | VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
|
---|
1458 | if (rc == VINF_SUCCESS)
|
---|
1459 | {
|
---|
1460 | uint8_t idxReg = uReg & 0x7;
|
---|
1461 | switch (idxReg)
|
---|
1462 | {
|
---|
1463 | case UART_REG_RBR_DLL_INDEX:
|
---|
1464 | rc = uartRegRbrDllRead(pDevIns, pThis, pThisCC, pu32);
|
---|
1465 | break;
|
---|
1466 | case UART_REG_IER_DLM_INDEX:
|
---|
1467 | uartRegIerDlmRead(pThis, pu32);
|
---|
1468 | break;
|
---|
1469 | case UART_REG_IIR_INDEX:
|
---|
1470 | uartRegIirRead(pDevIns, pThis, pThisCC, pu32);
|
---|
1471 | break;
|
---|
1472 | case UART_REG_LCR_INDEX:
|
---|
1473 | *pu32 = pThis->uRegLcr;
|
---|
1474 | break;
|
---|
1475 | case UART_REG_MCR_INDEX:
|
---|
1476 | *pu32 = pThis->uRegMcr;
|
---|
1477 | break;
|
---|
1478 | case UART_REG_LSR_INDEX:
|
---|
1479 | rc = uartRegLsrRead(pDevIns, pThis, pThisCC, pu32);
|
---|
1480 | break;
|
---|
1481 | case UART_REG_MSR_INDEX:
|
---|
1482 | uartRegMsrRead(pDevIns, pThis, pThisCC, pu32);
|
---|
1483 | break;
|
---|
1484 | case UART_REG_SCR_INDEX:
|
---|
1485 | *pu32 = pThis->uRegScr;
|
---|
1486 | break;
|
---|
1487 | default:
|
---|
1488 | rc = VERR_IOM_IOPORT_UNUSED;
|
---|
1489 | }
|
---|
1490 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1491 | LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
|
---|
1492 | pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /*fWrite*/), *pu32, cb, VBOXSTRICTRC_VAL(rc)));
|
---|
1493 | }
|
---|
1494 | else
|
---|
1495 | LogFlowFunc(("-> %Rrc\n", VBOXSTRICTRC_VAL(rc)));
|
---|
1496 | return rc;
|
---|
1497 | }
|
---|
1498 |
|
---|
1499 |
|
---|
1500 | #ifdef IN_RING3
|
---|
1501 |
|
---|
1502 | /* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
|
---|
1503 |
|
---|
1504 | /**
|
---|
1505 | * @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
|
---|
1506 | */
|
---|
1507 | static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
|
---|
1508 | {
|
---|
1509 | LogFlowFunc(("pDevIns=%#p hTimer=%#p pvUser=%#p\n", pDevIns, hTimer, pvUser));
|
---|
1510 | PUARTCORER3 pThisCC = (PUARTCORECC)pvUser;
|
---|
1511 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1512 | RT_NOREF(hTimer);
|
---|
1513 |
|
---|
1514 | if (pThis->FifoRecv.cbUsed < pThis->FifoRecv.cbItl)
|
---|
1515 | {
|
---|
1516 | pThis->fIrqCtiPending = true;
|
---|
1517 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1518 | }
|
---|
1519 | }
|
---|
1520 |
|
---|
1521 | /**
|
---|
1522 | * @callback_method_impl{FNTMTIMERDEV,
|
---|
1523 | * TX timer function when there is no driver connected for
|
---|
1524 | * draining the THR/FIFO.}
|
---|
1525 | */
|
---|
1526 | static DECLCALLBACK(void) uartR3TxUnconnectedTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
|
---|
1527 | {
|
---|
1528 | LogFlowFunc(("pDevIns=%#p hTimer=%#p pvUser=%#p\n", pDevIns, hTimer, pvUser));
|
---|
1529 | PUARTCORER3 pThisCC = (PUARTCORECC)pvUser;
|
---|
1530 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1531 | Assert(hTimer == pThis->hTimerTxUnconnected);
|
---|
1532 |
|
---|
1533 | VBOXSTRICTRC rc1 = PDMDevHlpTimerLockClock2(pDevIns, hTimer, &pThis->CritSect, VINF_SUCCESS /* must get it */);
|
---|
1534 | AssertRCReturnVoid(VBOXSTRICTRC_VAL(rc1));
|
---|
1535 |
|
---|
1536 | uint8_t bVal = 0;
|
---|
1537 | size_t cbRead = 0;
|
---|
1538 | uartR3TxQueueCopyFrom(pDevIns, pThis, pThisCC, &bVal, sizeof(bVal), &cbRead);
|
---|
1539 | if (pThis->uRegMcr & UART_REG_MCR_LOOP)
|
---|
1540 | {
|
---|
1541 | /* Loopback mode is active, feed in the data at the receiving end. */
|
---|
1542 | uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, 1);
|
---|
1543 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
|
---|
1544 | {
|
---|
1545 | PUARTFIFO pFifo = &pThis->FifoRecv;
|
---|
1546 | if (uartFifoFreeGet(pFifo) > 0)
|
---|
1547 | {
|
---|
1548 | pFifo->abBuf[pFifo->offWrite] = bVal;
|
---|
1549 | pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
|
---|
1550 | pFifo->cbUsed++;
|
---|
1551 |
|
---|
1552 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
1553 | if (pFifo->cbUsed < pFifo->cbItl)
|
---|
1554 | {
|
---|
1555 | pThis->fIrqCtiPending = false;
|
---|
1556 | PDMDevHlpTimerSetRelative(pDevIns, pThis->hTimerRcvFifoTimeout,
|
---|
1557 | pThis->cSymbolXferTicks * 4, NULL);
|
---|
1558 | }
|
---|
1559 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1560 | }
|
---|
1561 |
|
---|
1562 | ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
|
---|
1563 | }
|
---|
1564 | else if (!cbAvailOld)
|
---|
1565 | {
|
---|
1566 | pThis->uRegRbr = bVal;
|
---|
1567 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
1568 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1569 | }
|
---|
1570 | else
|
---|
1571 | ASMAtomicSubU32(&pThis->cbAvailRdr, 1);
|
---|
1572 | }
|
---|
1573 |
|
---|
1574 | if (cbRead == 1)
|
---|
1575 | PDMDevHlpTimerSetRelative(pDevIns, hTimer, pThis->cSymbolXferTicks, NULL);
|
---|
1576 | else
|
---|
1577 | {
|
---|
1578 | /* NO data left, set the transmitter holding register as empty. */
|
---|
1579 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
|
---|
1580 | }
|
---|
1581 |
|
---|
1582 | PDMDevHlpTimerUnlockClock2(pDevIns, hTimer, &pThis->CritSect);
|
---|
1583 | }
|
---|
1584 |
|
---|
1585 |
|
---|
1586 | /* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
|
---|
1587 |
|
---|
1588 |
|
---|
1589 | /**
|
---|
1590 | * @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
|
---|
1591 | */
|
---|
1592 | static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
|
---|
1593 | {
|
---|
1594 | LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
|
---|
1595 | PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
|
---|
1596 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1597 | PPDMDEVINS pDevIns = pThisCC->pDevIns;
|
---|
1598 |
|
---|
1599 | AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
|
---|
1600 |
|
---|
1601 | int rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1602 | AssertRCReturn(rcLock, rcLock);
|
---|
1603 |
|
---|
1604 | uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
|
---|
1605 | LogFlow((" cbAvailRdr=%u -> cbAvailRdr=%u\n", cbAvailOld, cbAvail + cbAvailOld));
|
---|
1606 | if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
|
---|
1607 | uartR3RecvFifoFill(pDevIns, pThis, pThisCC);
|
---|
1608 | else if (!cbAvailOld)
|
---|
1609 | {
|
---|
1610 | size_t cbRead = 0;
|
---|
1611 | int rc = pThisCC->pDrvSerial->pfnReadRdr(pThisCC->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
|
---|
1612 | AssertRC(rc);
|
---|
1613 |
|
---|
1614 | if (cbRead)
|
---|
1615 | {
|
---|
1616 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
|
---|
1617 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1618 | }
|
---|
1619 | }
|
---|
1620 |
|
---|
1621 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1622 | return VINF_SUCCESS;
|
---|
1623 | }
|
---|
1624 |
|
---|
1625 |
|
---|
1626 | /**
|
---|
1627 | * @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
|
---|
1628 | */
|
---|
1629 | static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
|
---|
1630 | {
|
---|
1631 | LogFlowFunc(("pInterface=%#p\n", pInterface));
|
---|
1632 | PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
|
---|
1633 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1634 | PPDMDEVINS pDevIns = pThisCC->pDevIns;
|
---|
1635 |
|
---|
1636 | /* Set the transmitter empty bit because everything was sent. */
|
---|
1637 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1638 | AssertRCReturn(rcLock, rcLock);
|
---|
1639 |
|
---|
1640 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
|
---|
1641 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1642 |
|
---|
1643 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1644 | return VINF_SUCCESS;
|
---|
1645 | }
|
---|
1646 |
|
---|
1647 |
|
---|
1648 | /**
|
---|
1649 | * @interface_method_impl{PDMISERIALPORT,pfnReadWr}
|
---|
1650 | */
|
---|
1651 | static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void *pvBuf, size_t cbRead, size_t *pcbRead)
|
---|
1652 | {
|
---|
1653 | LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
|
---|
1654 | PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
|
---|
1655 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1656 | PPDMDEVINS pDevIns = pThisCC->pDevIns;
|
---|
1657 |
|
---|
1658 | AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
|
---|
1659 |
|
---|
1660 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1661 | AssertRCReturn(rcLock, rcLock);
|
---|
1662 |
|
---|
1663 | uartR3TxQueueCopyFrom(pDevIns, pThis, pThisCC, pvBuf, cbRead, pcbRead);
|
---|
1664 |
|
---|
1665 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1666 | LogFlowFunc(("-> VINF_SUCCESS{*pcbRead=%zu}\n", *pcbRead));
|
---|
1667 | return VINF_SUCCESS;
|
---|
1668 | }
|
---|
1669 |
|
---|
1670 |
|
---|
1671 | /**
|
---|
1672 | * @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
|
---|
1673 | */
|
---|
1674 | static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
|
---|
1675 | {
|
---|
1676 | LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
|
---|
1677 | PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
|
---|
1678 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1679 | PPDMDEVINS pDevIns = pThisCC->pDevIns;
|
---|
1680 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1681 | AssertRCReturn(rcLock, rcLock);
|
---|
1682 |
|
---|
1683 | uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fNewStatusLines);
|
---|
1684 |
|
---|
1685 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1686 | return VINF_SUCCESS;
|
---|
1687 | }
|
---|
1688 |
|
---|
1689 |
|
---|
1690 | /**
|
---|
1691 | * @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
|
---|
1692 | */
|
---|
1693 | static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
|
---|
1694 | {
|
---|
1695 | LogFlowFunc(("pInterface=%#p\n", pInterface));
|
---|
1696 | PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, ISerialPort);
|
---|
1697 | PUARTCORE pThis = pThisCC->pShared;
|
---|
1698 | PPDMDEVINS pDevIns = pThisCC->pDevIns;
|
---|
1699 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1700 | AssertRCReturn(rcLock, rcLock);
|
---|
1701 |
|
---|
1702 | UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
|
---|
1703 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1704 |
|
---|
1705 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1706 | return VINF_SUCCESS;
|
---|
1707 | }
|
---|
1708 |
|
---|
1709 |
|
---|
1710 | /* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
|
---|
1711 |
|
---|
1712 | /**
|
---|
1713 | * @interface_method_impl{PDMIBASE,pfnQueryInterface}
|
---|
1714 | */
|
---|
1715 | static DECLCALLBACK(void *) uartR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
|
---|
1716 | {
|
---|
1717 | PUARTCORECC pThisCC = RT_FROM_MEMBER(pInterface, UARTCORECC, IBase);
|
---|
1718 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
|
---|
1719 | PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThisCC->ISerialPort);
|
---|
1720 | return NULL;
|
---|
1721 | }
|
---|
1722 |
|
---|
1723 |
|
---|
1724 | /**
|
---|
1725 | * Saves the UART state to the given SSM handle.
|
---|
1726 | *
|
---|
1727 | * @returns VBox status code.
|
---|
1728 | * @param pDevIns The device instance.
|
---|
1729 | * @param pThis The UART core instance.
|
---|
1730 | * @param pSSM The SSM handle to save to.
|
---|
1731 | */
|
---|
1732 | DECLHIDDEN(int) uartR3SaveExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM)
|
---|
1733 | {
|
---|
1734 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
1735 |
|
---|
1736 | pHlp->pfnSSMPutU16(pSSM, pThis->uRegDivisor);
|
---|
1737 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegRbr);
|
---|
1738 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegThr);
|
---|
1739 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegIer);
|
---|
1740 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegIir);
|
---|
1741 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegFcr);
|
---|
1742 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegLcr);
|
---|
1743 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegMcr);
|
---|
1744 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegLsr);
|
---|
1745 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegMsr);
|
---|
1746 | pHlp->pfnSSMPutU8(pSSM, pThis->uRegScr);
|
---|
1747 | pHlp->pfnSSMPutBool(pSSM, pThis->fIrqCtiPending);
|
---|
1748 | pHlp->pfnSSMPutBool(pSSM, pThis->fThreEmptyPending);
|
---|
1749 | pHlp->pfnSSMPutU8(pSSM, pThis->FifoXmit.cbMax);
|
---|
1750 | pHlp->pfnSSMPutU8(pSSM, pThis->FifoXmit.cbItl);
|
---|
1751 | pHlp->pfnSSMPutU8(pSSM, pThis->FifoRecv.cbMax);
|
---|
1752 | pHlp->pfnSSMPutU8(pSSM, pThis->FifoRecv.cbItl);
|
---|
1753 |
|
---|
1754 | int rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
|
---|
1755 | if (RT_SUCCESS(rc))
|
---|
1756 | rc = PDMDevHlpTimerSave(pDevIns, pThis->hTimerTxUnconnected, pSSM);
|
---|
1757 |
|
---|
1758 | return rc;
|
---|
1759 | }
|
---|
1760 |
|
---|
1761 |
|
---|
1762 | /**
|
---|
1763 | * Loads the UART state from the given SSM handle.
|
---|
1764 | *
|
---|
1765 | * @returns VBox status code.
|
---|
1766 | * @param pDevIns The device instance.
|
---|
1767 | * @param pThis The UART core instance.
|
---|
1768 | * @param pSSM The SSM handle to load from.
|
---|
1769 | * @param uVersion Saved state version.
|
---|
1770 | * @param uPass The SSM pass the call is done in.
|
---|
1771 | * @param pbIrq Where to store the IRQ value for legacy
|
---|
1772 | * saved states - optional.
|
---|
1773 | * @param pPortBase Where to store the I/O port base for legacy
|
---|
1774 | * saved states - optional.
|
---|
1775 | */
|
---|
1776 | DECLHIDDEN(int) uartR3LoadExec(PPDMDEVINS pDevIns, PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
|
---|
1777 | uint8_t *pbIrq, RTIOPORT *pPortBase)
|
---|
1778 | {
|
---|
1779 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
1780 | int rc;
|
---|
1781 | RT_NOREF(uPass);
|
---|
1782 |
|
---|
1783 | if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
|
---|
1784 | {
|
---|
1785 | pHlp->pfnSSMGetU16(pSSM, &pThis->uRegDivisor);
|
---|
1786 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegRbr);
|
---|
1787 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegThr);
|
---|
1788 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIer);
|
---|
1789 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIir);
|
---|
1790 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegFcr);
|
---|
1791 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLcr);
|
---|
1792 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMcr);
|
---|
1793 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLsr);
|
---|
1794 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMsr);
|
---|
1795 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegScr);
|
---|
1796 | pHlp->pfnSSMGetBool(pSSM, &pThis->fIrqCtiPending);
|
---|
1797 | pHlp->pfnSSMGetBool(pSSM, &pThis->fThreEmptyPending);
|
---|
1798 | pHlp->pfnSSMGetU8(pSSM, &pThis->FifoXmit.cbMax);
|
---|
1799 | pHlp->pfnSSMGetU8(pSSM, &pThis->FifoXmit.cbItl);
|
---|
1800 | pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbMax);
|
---|
1801 | pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
|
---|
1802 |
|
---|
1803 | rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
|
---|
1804 | if (uVersion > UART_SAVED_STATE_VERSION_PRE_UNCONNECTED_TX_TIMER)
|
---|
1805 | rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerTxUnconnected, pSSM);
|
---|
1806 | }
|
---|
1807 | else
|
---|
1808 | {
|
---|
1809 | AssertPtr(pbIrq);
|
---|
1810 | AssertPtr(pPortBase);
|
---|
1811 | if (uVersion == UART_SAVED_STATE_VERSION_16450)
|
---|
1812 | {
|
---|
1813 | pThis->enmType = UARTTYPE_16450;
|
---|
1814 | LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pDevIns->iInstance));
|
---|
1815 | }
|
---|
1816 |
|
---|
1817 | pHlp->pfnSSMGetU16(pSSM, &pThis->uRegDivisor);
|
---|
1818 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegRbr);
|
---|
1819 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIer);
|
---|
1820 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLcr);
|
---|
1821 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMcr);
|
---|
1822 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegLsr);
|
---|
1823 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegMsr);
|
---|
1824 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegScr);
|
---|
1825 | if (uVersion > UART_SAVED_STATE_VERSION_16450)
|
---|
1826 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegFcr);
|
---|
1827 |
|
---|
1828 | int32_t iTmp = 0;
|
---|
1829 | pHlp->pfnSSMGetS32(pSSM, &iTmp);
|
---|
1830 | pThis->fThreEmptyPending = RT_BOOL(iTmp);
|
---|
1831 |
|
---|
1832 | rc = pHlp->pfnSSMGetS32(pSSM, &iTmp);
|
---|
1833 | AssertRCReturn(rc, rc);
|
---|
1834 | *pbIrq = (uint8_t)iTmp;
|
---|
1835 |
|
---|
1836 | pHlp->pfnSSMSkip(pSSM, sizeof(int32_t)); /* was: last_break_enable */
|
---|
1837 |
|
---|
1838 | uint32_t uPortBaseTmp = 0;
|
---|
1839 | rc = pHlp->pfnSSMGetU32(pSSM, &uPortBaseTmp);
|
---|
1840 | AssertRCReturn(rc, rc);
|
---|
1841 | *pPortBase = (RTIOPORT)uPortBaseTmp;
|
---|
1842 |
|
---|
1843 | rc = pHlp->pfnSSMSkip(pSSM, sizeof(bool)); /* was: msr_changed */
|
---|
1844 | if ( RT_SUCCESS(rc)
|
---|
1845 | && uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
|
---|
1846 | {
|
---|
1847 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegThr);
|
---|
1848 | pHlp->pfnSSMSkip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
|
---|
1849 | pHlp->pfnSSMGetU8(pSSM, &pThis->uRegIir);
|
---|
1850 |
|
---|
1851 | int32_t iTimeoutPending = 0;
|
---|
1852 | pHlp->pfnSSMGetS32(pSSM, &iTimeoutPending);
|
---|
1853 | pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
|
---|
1854 |
|
---|
1855 | rc = PDMDevHlpTimerLoad(pDevIns, pThis->hTimerRcvFifoTimeout, pSSM);
|
---|
1856 | AssertRCReturn(rc, rc);
|
---|
1857 |
|
---|
1858 | bool fWasActiveIgn;
|
---|
1859 | rc = pHlp->pfnTimerSkipLoad(pSSM, &fWasActiveIgn); /* was: transmit_timerR3 */
|
---|
1860 | AssertRCReturn(rc, rc);
|
---|
1861 |
|
---|
1862 | pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
|
---|
1863 | rc = pHlp->pfnSSMGetU8(pSSM, &pThis->FifoRecv.cbItl);
|
---|
1864 | }
|
---|
1865 | }
|
---|
1866 |
|
---|
1867 | return rc;
|
---|
1868 | }
|
---|
1869 |
|
---|
1870 |
|
---|
1871 | /**
|
---|
1872 | * Called when loading the state completed, updates the parameters of any driver underneath.
|
---|
1873 | *
|
---|
1874 | * @returns VBox status code.
|
---|
1875 | * @param pDevIns The device instance.
|
---|
1876 | * @param pThis The shared serial port instance data.
|
---|
1877 | * @param pThisCC The serial port instance data for the current context.
|
---|
1878 | * @param pSSM The SSM handle.
|
---|
1879 | */
|
---|
1880 | DECLHIDDEN(int) uartR3LoadDone(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, PSSMHANDLE pSSM)
|
---|
1881 | {
|
---|
1882 | RT_NOREF(pSSM);
|
---|
1883 |
|
---|
1884 | uartR3ParamsUpdate(pDevIns, pThis, pThisCC);
|
---|
1885 | uartIrqUpdate(pDevIns, pThis, pThisCC);
|
---|
1886 |
|
---|
1887 | if (pThisCC->pDrvSerial)
|
---|
1888 | {
|
---|
1889 | /* Set the modem lines to reflect the current state. */
|
---|
1890 | int rc = pThisCC->pDrvSerial->pfnChgModemLines(pThisCC->pDrvSerial,
|
---|
1891 | RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
|
---|
1892 | RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
|
---|
1893 | if (RT_FAILURE(rc))
|
---|
1894 | LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
|
---|
1895 | pDevIns->iInstance, rc));
|
---|
1896 |
|
---|
1897 | uint32_t fStsLines = 0;
|
---|
1898 | rc = pThisCC->pDrvSerial->pfnQueryStsLines(pThisCC->pDrvSerial, &fStsLines);
|
---|
1899 | if (RT_SUCCESS(rc))
|
---|
1900 | uartR3StsLinesUpdate(pDevIns, pThis, pThisCC, fStsLines);
|
---|
1901 | else
|
---|
1902 | LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
|
---|
1903 | pDevIns->iInstance, rc));
|
---|
1904 | }
|
---|
1905 |
|
---|
1906 | return VINF_SUCCESS;
|
---|
1907 | }
|
---|
1908 |
|
---|
1909 |
|
---|
1910 | /**
|
---|
1911 | * Resets the given UART core instance.
|
---|
1912 | *
|
---|
1913 | * @param pDevIns The device instance.
|
---|
1914 | * @param pThis The shared serial port instance data.
|
---|
1915 | * @param pThisCC The serial port instance data for the current context.
|
---|
1916 | */
|
---|
1917 | DECLHIDDEN(void) uartR3Reset(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
1918 | {
|
---|
1919 | pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
|
---|
1920 | pThis->uRegRbr = 0;
|
---|
1921 | pThis->uRegThr = 0;
|
---|
1922 | pThis->uRegIer = 0;
|
---|
1923 | pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
|
---|
1924 | pThis->uRegFcr = 0;
|
---|
1925 | pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
|
---|
1926 | pThis->uRegMcr = 0;
|
---|
1927 | pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
|
---|
1928 | pThis->uRegMsr = UART_REG_MSR_DCD | UART_REG_MSR_CTS | UART_REG_MSR_DSR | UART_REG_MSR_DCTS | UART_REG_MSR_DDSR | UART_REG_MSR_DDCD;
|
---|
1929 | pThis->uRegScr = 0;
|
---|
1930 | pThis->fIrqCtiPending = false;
|
---|
1931 | pThis->fThreEmptyPending = true;
|
---|
1932 |
|
---|
1933 | /* Standard FIFO size for 15550A. */
|
---|
1934 | pThis->FifoXmit.cbMax = 16;
|
---|
1935 | pThis->FifoRecv.cbMax = 16;
|
---|
1936 | pThis->FifoRecv.cbItl = 1;
|
---|
1937 |
|
---|
1938 | uartR3XferReset(pDevIns, pThis, pThisCC);
|
---|
1939 | }
|
---|
1940 |
|
---|
1941 |
|
---|
1942 | /**
|
---|
1943 | * Attaches the given UART core instance to the drivers at the given LUN.
|
---|
1944 | *
|
---|
1945 | * @returns VBox status code.
|
---|
1946 | * @param pDevIns The device instance.
|
---|
1947 | * @param pThis The shared serial port instance data.
|
---|
1948 | * @param pThisCC The serial port instance data for the current context.
|
---|
1949 | * @param iLUN The LUN being attached.
|
---|
1950 | */
|
---|
1951 | DECLHIDDEN(int) uartR3Attach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC, unsigned iLUN)
|
---|
1952 | {
|
---|
1953 | int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "Serial Char");
|
---|
1954 | if (RT_SUCCESS(rc))
|
---|
1955 | {
|
---|
1956 | pThisCC->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMISERIALCONNECTOR);
|
---|
1957 | if (!pThisCC->pDrvSerial)
|
---|
1958 | {
|
---|
1959 | AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pDevIns->iInstance));
|
---|
1960 | return VERR_PDM_MISSING_INTERFACE;
|
---|
1961 | }
|
---|
1962 | rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1963 | if (RT_SUCCESS(rc))
|
---|
1964 | {
|
---|
1965 | uartR3XferReset(pDevIns, pThis, pThisCC);
|
---|
1966 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1967 | }
|
---|
1968 | }
|
---|
1969 | else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
|
---|
1970 | {
|
---|
1971 | pThisCC->pDrvBase = NULL;
|
---|
1972 | pThisCC->pDrvSerial = NULL;
|
---|
1973 | rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1974 | if (RT_SUCCESS(rc))
|
---|
1975 | {
|
---|
1976 | uartR3XferReset(pDevIns, pThis, pThisCC);
|
---|
1977 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
1978 | }
|
---|
1979 | LogRel(("Serial#%d: no unit\n", pDevIns->iInstance));
|
---|
1980 | }
|
---|
1981 | else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
|
---|
1982 | LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pDevIns->iInstance, rc));
|
---|
1983 |
|
---|
1984 | return rc;
|
---|
1985 | }
|
---|
1986 |
|
---|
1987 |
|
---|
1988 | /**
|
---|
1989 | * Detaches any attached driver from the given UART core instance.
|
---|
1990 | *
|
---|
1991 | * @param pDevIns The device instance.
|
---|
1992 | * @param pThis The shared serial port instance data.
|
---|
1993 | * @param pThisCC The serial port instance data for the current context.
|
---|
1994 | */
|
---|
1995 | DECLHIDDEN(void) uartR3Detach(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC)
|
---|
1996 | {
|
---|
1997 | /* Zero out important members. */
|
---|
1998 | pThisCC->pDrvBase = NULL;
|
---|
1999 | pThisCC->pDrvSerial = NULL;
|
---|
2000 | int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
2001 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->CritSect, rcLock);
|
---|
2002 |
|
---|
2003 | uartR3XferReset(pDevIns, pThis, pThisCC);
|
---|
2004 |
|
---|
2005 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
2006 | }
|
---|
2007 |
|
---|
2008 |
|
---|
2009 | /**
|
---|
2010 | * Destroys the given UART core instance freeing all allocated resources.
|
---|
2011 | *
|
---|
2012 | * @param pDevIns The device instance.
|
---|
2013 | * @param pThis The shared UART core instance data..
|
---|
2014 | */
|
---|
2015 | DECLHIDDEN(void) uartR3Destruct(PPDMDEVINS pDevIns, PUARTCORE pThis)
|
---|
2016 | {
|
---|
2017 | PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
|
---|
2018 | }
|
---|
2019 |
|
---|
2020 |
|
---|
2021 | /**
|
---|
2022 | * Initializes the given UART core instance using the provided configuration.
|
---|
2023 | *
|
---|
2024 | * @returns VBox status code.
|
---|
2025 | * @param pDevIns The device instance pointer.
|
---|
2026 | * @param pThis The shared UART core instance data to
|
---|
2027 | * initialize.
|
---|
2028 | * @param pThisCC The ring-3 UART core instance data to
|
---|
2029 | * initialize.
|
---|
2030 | * @param enmType The type of UART emulated.
|
---|
2031 | * @param iLUN The LUN the UART should look for attached drivers.
|
---|
2032 | * @param fFlags Additional flags controlling device behavior.
|
---|
2033 | * @param pfnUartIrqReq Pointer to the interrupt request callback.
|
---|
2034 | */
|
---|
2035 | DECLHIDDEN(int) uartR3Init(PPDMDEVINS pDevIns, PUARTCORE pThis, PUARTCORECC pThisCC,
|
---|
2036 | UARTTYPE enmType, unsigned iLUN, uint32_t fFlags, PFNUARTCOREIRQREQ pfnUartIrqReq)
|
---|
2037 | {
|
---|
2038 | /*
|
---|
2039 | * Initialize the instance data.
|
---|
2040 | * (Do this early or the destructor might choke on something!)
|
---|
2041 | */
|
---|
2042 | pThis->iLUN = iLUN;
|
---|
2043 | pThis->enmType = enmType;
|
---|
2044 | pThis->fFlags = fFlags;
|
---|
2045 |
|
---|
2046 | pThisCC->iLUN = iLUN;
|
---|
2047 | pThisCC->pDevIns = pDevIns;
|
---|
2048 | pThisCC->pShared = pThis;
|
---|
2049 | pThisCC->pfnUartIrqReq = pfnUartIrqReq;
|
---|
2050 |
|
---|
2051 | /* IBase */
|
---|
2052 | pThisCC->IBase.pfnQueryInterface = uartR3QueryInterface;
|
---|
2053 |
|
---|
2054 | /* ISerialPort */
|
---|
2055 | pThisCC->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
|
---|
2056 | pThisCC->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
|
---|
2057 | pThisCC->ISerialPort.pfnReadWr = uartR3ReadWr;
|
---|
2058 | pThisCC->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
|
---|
2059 | pThisCC->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
|
---|
2060 |
|
---|
2061 | int rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
|
---|
2062 | pDevIns->pReg->szName, pDevIns->iInstance, iLUN);
|
---|
2063 | AssertRCReturn(rc, rc);
|
---|
2064 |
|
---|
2065 | /*
|
---|
2066 | * Attach the char driver and get the interfaces.
|
---|
2067 | */
|
---|
2068 | rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "UART");
|
---|
2069 | if (RT_SUCCESS(rc))
|
---|
2070 | {
|
---|
2071 | pThisCC->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMISERIALCONNECTOR);
|
---|
2072 | if (!pThisCC->pDrvSerial)
|
---|
2073 | {
|
---|
2074 | AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
|
---|
2075 | return VERR_PDM_MISSING_INTERFACE;
|
---|
2076 | }
|
---|
2077 | }
|
---|
2078 | else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
|
---|
2079 | {
|
---|
2080 | pThisCC->pDrvBase = NULL;
|
---|
2081 | pThisCC->pDrvSerial = NULL;
|
---|
2082 | LogRel(("Serial#%d: no unit\n", iLUN));
|
---|
2083 | }
|
---|
2084 | else
|
---|
2085 | {
|
---|
2086 | AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
|
---|
2087 | /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
|
---|
2088 | return rc;
|
---|
2089 | }
|
---|
2090 |
|
---|
2091 | /*
|
---|
2092 | * Create the receive FIFO character timeout indicator timer.
|
---|
2093 | */
|
---|
2094 | rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThisCC,
|
---|
2095 | TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "UART Rcv FIFO",
|
---|
2096 | &pThis->hTimerRcvFifoTimeout);
|
---|
2097 | AssertRCReturn(rc, rc);
|
---|
2098 |
|
---|
2099 | rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTimerRcvFifoTimeout, &pThis->CritSect);
|
---|
2100 | AssertRCReturn(rc, rc);
|
---|
2101 |
|
---|
2102 | /*
|
---|
2103 | * Create the transmit timer when no device is connected.
|
---|
2104 | */
|
---|
2105 | rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, uartR3TxUnconnectedTimer, pThisCC,
|
---|
2106 | TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_NO_RING0, "UART TX unconnect",
|
---|
2107 | &pThis->hTimerTxUnconnected);
|
---|
2108 | AssertRCReturn(rc, rc);
|
---|
2109 |
|
---|
2110 | uartR3Reset(pDevIns, pThis, pThisCC);
|
---|
2111 | return VINF_SUCCESS;
|
---|
2112 | }
|
---|
2113 |
|
---|
2114 | #else /* !IN_RING3 */
|
---|
2115 |
|
---|
2116 | /**
|
---|
2117 | * Initializes the ring-0 / raw-mode instance data.
|
---|
2118 | *
|
---|
2119 | * @returns VBox status code.
|
---|
2120 | * @param pThisCC The serial port instance data for the current context.
|
---|
2121 | * @param pfnUartIrqReq Pointer to the interrupt request callback.
|
---|
2122 | */
|
---|
2123 | DECLHIDDEN(int) uartRZInit(PUARTCORECC pThisCC, PFNUARTCOREIRQREQ pfnUartIrqReq)
|
---|
2124 | {
|
---|
2125 | AssertPtrReturn(pfnUartIrqReq, VERR_INVALID_POINTER);
|
---|
2126 | AssertPtrReturn(pThisCC, VERR_INVALID_POINTER);
|
---|
2127 | pThisCC->pfnUartIrqReq = pfnUartIrqReq;
|
---|
2128 | return VINF_SUCCESS;
|
---|
2129 | }
|
---|
2130 |
|
---|
2131 | #endif /* !IN_RING3 */
|
---|
2132 |
|
---|
2133 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|