VirtualBox

source: vbox/trunk/src/VBox/Devices/Security/DevTpm.cpp@ 102991

Last change on this file since 102991 was 102991, checked in by vboxsync, 4 months ago

Devices/Security/DevTpm: Fix device identification, the UEFI update introduced a new sanity check in the TPM driver code making TCG2 fail and reporting to TPM
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1/* $Id: DevTpm.cpp 102991 2024-01-22 17:30:30Z vboxsync $ */
2/** @file
3 * DevTpm - Trusted Platform Module emulation.
4 *
5 * This emulation is based on the spec available under (as of 2021-08-02):
6 * https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2p0-v1p05p_r14_pub.pdf
7 */
8
9/*
10 * Copyright (C) 2021-2023 Oracle and/or its affiliates.
11 *
12 * This file is part of VirtualBox base platform packages, as
13 * available from https://www.virtualbox.org.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation, in version 3 of the
18 * License.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see <https://www.gnu.org/licenses>.
27 *
28 * SPDX-License-Identifier: GPL-3.0-only
29 */
30
31
32/*********************************************************************************************************************************
33* Header Files *
34*********************************************************************************************************************************/
35#define LOG_GROUP LOG_GROUP_DEV_TPM
36#include <VBox/vmm/pdmdev.h>
37#include <VBox/vmm/pdmtpmifs.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40#include <iprt/uuid.h>
41
42#include <iprt/formats/tpm.h>
43
44#include "VBoxDD.h"
45
46
47/*********************************************************************************************************************************
48* Defined Constants And Macros *
49*********************************************************************************************************************************/
50
51/** The TPM saved state version. */
52#define TPM_SAVED_STATE_VERSION 1
53
54/** Default vendor ID. */
55#define TPM_VID_DEFAULT 0x1014
56/** Default device ID. */
57#define TPM_DID_DEFAULT 0x0001
58/** Default revision ID. */
59#define TPM_RID_DEFAULT 0x01
60/** Maximum size of the data buffer in bytes. */
61#define TPM_DATA_BUFFER_SIZE_MAX 3968
62
63/** The TPM MMIO base default as defined in chapter 5.2. */
64#define TPM_MMIO_BASE_DEFAULT 0xfed40000
65/** The size of the TPM MMIO area. */
66#define TPM_MMIO_SIZE 0x5000
67
68/** Number of localities as mandated by the TPM spec. */
69#define TPM_LOCALITY_COUNT 5
70/** Size of each locality in the TPM MMIO area (chapter 6.5.2).*/
71#define TPM_LOCALITY_MMIO_SIZE 0x1000
72
73/** @name TPM locality register related defines for the FIFO interface.
74 * @{ */
75/** Ownership management for a particular locality. */
76#define TPM_FIFO_LOCALITY_REG_ACCESS 0x00
77/** Indicates whether a dynamic OS has been established on this platform before.. */
78# define TPM_FIFO_LOCALITY_REG_ACCESS_ESTABLISHMENT RT_BIT(0)
79/** On reads indicates whether the locality requests use of the TPM (1) or not or is already active locality (0),
80 * writing a 1 requests the locality to be granted getting the active locality.. */
81# define TPM_FIFO_LOCALITY_REG_ACCESS_REQUEST_USE RT_BIT(1)
82/** Indicates whether another locality is requesting usage of the TPM. */
83# define TPM_FIFO_LOCALITY_REG_ACCESS_PENDING_REQUEST RT_BIT(2)
84/** Writing a 1 forces the TPM to give control to the locality if it has a higher priority. */
85# define TPM_FIFO_LOCALITY_REG_ACCESS_SEIZE RT_BIT(3)
86/** On reads indicates whether this locality has been seized by a higher locality (1) or not (0), writing a 1 clears this bit. */
87# define TPM_FIFO_LOCALITY_REG_ACCESS_BEEN_SEIZED RT_BIT(4)
88/** On reads indicates whether this locality is active (1) or not (0), writing a 1 relinquishes control for this locality. */
89# define TPM_FIFO_LOCALITY_REG_ACCESS_ACTIVE RT_BIT(5)
90/** Set bit indicates whether all other bits in this register have valid data. */
91# define TPM_FIFO_LOCALITY_REG_ACCESS_VALID RT_BIT(7)
92/** Writable mask. */
93# define TPM_FIFO_LOCALITY_REG_ACCESS_WR_MASK 0x3a
94
95/** Interrupt enable register. */
96#define TPM_FIFO_LOCALITY_REG_INT_ENABLE 0x08
97/** Data available interrupt enable bit. */
98# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_DATA_AVAIL RT_BIT_32(0)
99/** Status valid interrupt enable bit. */
100# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_STS_VALID RT_BIT_32(1)
101/** Locality change interrupt enable bit. */
102# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_LOCALITY_CHANGE RT_BIT_32(2)
103/** Interrupt polarity configuration. */
104# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_MASK 0x18
105# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_SHIFT 3
106# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INT_POLARITY_SHIFT)
107# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_GET(a) (((a) & TPM_FIFO_LOCALITY_REG_INT_POLARITY_MASK) >> TPM_FIFO_LOCALITY_REG_INT_POLARITY_SHIFT)
108/** High level interrupt trigger. */
109# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_HIGH 0
110/** Low level interrupt trigger. */
111# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_LOW 1
112/** Rising edge interrupt trigger. */
113# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_RISING 2
114/** Falling edge interrupt trigger. */
115# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_POLARITY_FALLING 3
116/** Command ready enable bit. */
117# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_CMD_RDY RT_BIT_32(7)
118/** Global interrupt enable/disable bit. */
119# define TPM_FIFO_LOCALITY_REG_INT_ENABLE_GLOBAL RT_BIT_32(31)
120
121/** Configured interrupt vector register. */
122#define TPM_FIFO_LOCALITY_REG_INT_VEC 0x0c
123
124/** Interrupt status register. */
125#define TPM_FIFO_LOCALITY_REG_INT_STS 0x10
126/** Data available interrupt occured bit, writing a 1 clears the bit. */
127# define TPM_FIFO_LOCALITY_REG_INT_STS_DATA_AVAIL RT_BIT_32(0)
128/** Status valid interrupt occured bit, writing a 1 clears the bit. */
129# define TPM_FIFO_LOCALITY_REG_INT_STS_STS_VALID RT_BIT_32(1)
130/** Locality change interrupt occured bit, writing a 1 clears the bit. */
131# define TPM_FIFO_LOCALITY_REG_INT_STS_LOCALITY_CHANGE RT_BIT_32(2)
132/** Command ready occured bit, writing a 1 clears the bit. */
133# define TPM_FIFO_LOCALITY_REG_INT_STS_CMD_RDY RT_BIT_32(7)
134/** Writable mask. */
135# define TPM_FIFO_LOCALITY_REG_INT_STS_WR_MASK UINT32_C(0x87)
136
137/** Interfacce capabilities register. */
138#define TPM_FIFO_LOCALITY_REG_IF_CAP 0x14
139/** Flag whether the TPM supports the data avilable interrupt. */
140# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_DATA_AVAIL RT_BIT(0)
141/** Flag whether the TPM supports the status valid interrupt. */
142# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_STS_VALID RT_BIT(1)
143/** Flag whether the TPM supports the data avilable interrupt. */
144# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LOCALITY_CHANGE RT_BIT(2)
145/** Flag whether the TPM supports high level interrupts. */
146# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LVL_HIGH RT_BIT(3)
147/** Flag whether the TPM supports low level interrupts. */
148# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LVL_LOW RT_BIT(4)
149/** Flag whether the TPM supports rising edge interrupts. */
150# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_RISING_EDGE RT_BIT(5)
151/** Flag whether the TPM supports falling edge interrupts. */
152# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_FALLING_EDGE RT_BIT(6)
153/** Flag whether the TPM supports the command ready interrupt. */
154# define TPM_FIFO_LOCALITY_REG_IF_CAP_INT_CMD_RDY RT_BIT(7)
155/** Flag whether the busrt count field is static or dynamic. */
156# define TPM_FIFO_LOCALITY_REG_IF_CAP_BURST_CNT_STATIC RT_BIT(8)
157/** Maximum transfer size support. */
158# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_MASK 0x600
159# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SHIFT 9
160# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SHIFT)
161/** Only legacy transfers supported. */
162# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_LEGACY 0x0
163/** 8B maximum transfer size. */
164# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_8B 0x1
165/** 32B maximum transfer size. */
166# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_32B 0x2
167/** 64B maximum transfer size. */
168# define TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_64B 0x3
169/** Interface version. */
170# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_MASK UINT32_C(0x70000000)
171# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SHIFT 28
172# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SHIFT)
173/** Interface 1.21 or ealier. */
174# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_21 0
175/** Interface 1.3. */
176# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3 2
177/** Interface 1.3 for TPM 2.0. */
178# define TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3_TPM2 3
179
180/** TPM status register. */
181#define TPM_FIFO_LOCALITY_REG_STS 0x18
182/** Writing a 1 forces the TPM to re-send the response. */
183# define TPM_FIFO_LOCALITY_REG_STS_RESPONSE_RETRY RT_BIT_32(1)
184/** Indicating whether the TPM has finished a self test. */
185# define TPM_FIFO_LOCALITY_REG_STS_SELF_TEST_DONE RT_BIT_32(2)
186/** Flag indicating whether the TPM expects more data for the command. */
187# define TPM_FIFO_LOCALITY_REG_STS_EXPECT RT_BIT_32(3)
188/** Flag indicating whether the TPM has more response data available. */
189# define TPM_FIFO_LOCALITY_REG_STS_DATA_AVAIL RT_BIT_32(4)
190/** Written by software to cause the TPM to execute a previously transfered command. */
191# define TPM_FIFO_LOCALITY_REG_STS_TPM_GO RT_BIT_32(5)
192/** On reads indicates whether the TPM is ready to receive a new command (1) or not (0),
193 * a write of 1 causes the TPM to transition to this state. */
194# define TPM_FIFO_LOCALITY_REG_STS_CMD_RDY RT_BIT_32(6)
195/** Indicates whether the Expect and data available bits are valid. */
196# define TPM_FIFO_LOCALITY_REG_STS_VALID RT_BIT_32(7)
197/** Sets the burst count. */
198# define TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_MASK UINT32_C(0xffff00)
199# define TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SHIFT UINT32_C(8)
200# define TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SHIFT)
201/** Cancels the active command. */
202# define TPM_FIFO_LOCALITY_REG_STS_CMD_CANCEL RT_BIT_32(24)
203/** Reset establishment bit. */
204# define TPM_FIFO_LOCALITY_REG_STS_RST_ESTABLISHMENT RT_BIT_32(25)
205/** Sets the TPM family. */
206# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_MASK UINT32_C(0x0c000000)
207# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SHIFT UINT32_C(26)
208# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SHIFT)
209# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_1_2 UINT32_C(0)
210# define TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_2_0 UINT32_C(1)
211
212
213/** TPM end of HASH operation signal register for locality 4. */
214#define TPM_FIFO_LOCALITY_REG_HASH_END 0x20
215/** Data FIFO read/write register. */
216#define TPM_FIFO_LOCALITY_REG_DATA_FIFO 0x24
217/** TPM start of HASH operation signal register for locality 4. */
218#define TPM_FIFO_LOCALITY_REG_HASH_START 0x28
219
220/** Locality interface ID register. */
221#define TPM_FIFO_LOCALITY_REG_INTF_ID 0x30
222/** Interface type field. */
223# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_MASK UINT32_C(0xf)
224# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT 0
225# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT)
226/** FIFO interface as defined in PTP for TPM 2.0 is active. */
227# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_FIFO_TPM20 0x0
228/** CRB interface is active. */
229# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_CRB 0x1
230/** FIFO interface as defined in TIS 1.3 is active. */
231# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_TIS1_3 0xf
232/** Interface type field. */
233# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_MASK UINT32_C(0xf)
234# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT 4
235# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT)
236/** FIFO interface for TPM 2.0 */
237# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_FIFO 0
238/** CRB interface version 0. */
239# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_CRB 1
240/** Only locality 0 is supported when clear, set if 5 localities are supported. */
241# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_LOCALITY RT_BIT(8)
242/** Maximum transfer size support. */
243# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_MASK 0x1800
244# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT 11
245# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT)
246/** Only legacy transfers supported. */
247# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_LEGACY 0x0
248/** 8B maximum transfer size. */
249# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_8B 0x1
250/** 32B maximum transfer size. */
251# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_32B 0x2
252/** 64B maximum transfer size. */
253# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B 0x3
254/** FIFO interface is supported and may be selected. */
255# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_FIFO RT_BIT(13)
256/** CRB interface is supported and may be selected. */
257# define TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_CRB RT_BIT(14)
258/** Interrupt polarity configuration. */
259# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_MASK 0x60000
260# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT 17
261# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SET(a) ((a) << TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
262# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_GET(a) (((a) & TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_MASK) >> TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
263/** Selects the FIFO interface, takes effect on next _TPM_INIT. */
264# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_FIFO 0
265/** Selects the CRB interface, takes effect on next _TPM_INIT. */
266# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_CRB 1
267/** Locks the interface selector field and prevents further changes. */
268# define TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_LOCK RT_BIT(19)
269
270
271/** Extended data FIFO read/write register. */
272#define TPM_FIFO_LOCALITY_REG_XDATA_FIFO 0x80
273/** TPM device and vendor ID. */
274#define TPM_FIFO_LOCALITY_REG_DID_VID 0xf00
275/** TPM revision ID. */
276#define TPM_FIFO_LOCALITY_REG_RID 0xf04
277/** @} */
278
279
280/** @name TPM locality register related defines for the CRB interface.
281 * @{ */
282/** Locality state register. */
283#define TPM_CRB_LOCALITY_REG_STATE 0x00
284/** Indicates whether a dynamic OS has been established on this platform before.. */
285# define TPM_CRB_LOCALITY_REG_ESTABLISHMENT RT_BIT(0)
286/** Flag whether the host has a locality assigned (1) or not (0). */
287# define TPM_CRB_LOCALITY_REG_STATE_LOC_ASSIGNED RT_BIT(1)
288/** Indicates the currently active locality. */
289# define TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_MASK UINT32_C(0x1c)
290# define TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SHIFT 2
291# define TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SET(a) ((a) << TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SHIFT)
292/** Flag whether the register contains valid values. */
293# define TPM_CRB_LOCALITY_REG_STATE_VALID RT_BIT(7)
294
295/** Locality control register. */
296#define TPM_CRB_LOCALITY_REG_CTRL 0x08
297/** Request TPM access from this locality. */
298# define TPM_CRB_LOCALITY_REG_CTRL_REQ_ACCESS RT_BIT(0)
299/** Release TPM access from this locality. */
300# define TPM_CRB_LOCALITY_REG_CTRL_RELINQUISH RT_BIT(1)
301/** Seize TPM access in favor of this locality if it has a higher priority. */
302# define TPM_CRB_LOCALITY_REG_CTRL_SEIZE RT_BIT(2)
303/** Resets the established bit if written from locality 3 or 4. */
304# define TPM_CRB_LOCALITY_REG_CTRL_RST_ESTABLISHMENT RT_BIT(3)
305
306/** Locality status register. */
307#define TPM_CRB_LOCALITY_REG_STS 0x0c
308/** Locality has been granted access to the TPM. */
309# define TPM_CRB_LOCALITY_REG_STS_GRANTED RT_BIT(0)
310/** A higher locality has seized the TPM from this locality. */
311# define TPM_CRB_LOCALITY_REG_STS_SEIZED RT_BIT(1)
312
313/** Locality interface ID register. */
314#define TPM_CRB_LOCALITY_REG_INTF_ID 0x30
315/** Interface type field. */
316# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_MASK UINT32_C(0xf)
317# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT 0
318# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SHIFT)
319/** FIFO interface as defined in PTP for TPM 2.0 is active. */
320# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_FIFO_TPM20 0x0
321/** CRB interface is active. */
322# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_CRB 0x1
323/** FIFO interface as defined in TIS 1.3 is active. */
324# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_TIS1_3 0xf
325/** Interface type field. */
326# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_MASK UINT32_C(0xf)
327# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT 4
328# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SHIFT)
329/** FIFO interface for TPM 2.0 */
330# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_FIFO 0
331/** CRB interface version 0. */
332# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_CRB 1
333/** Only locality 0 is supported when clear, set if 5 localities are supported. */
334# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_LOCALITY RT_BIT(8)
335/** @todo TPM supports ... */
336# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_CRB_IDLE_BYPASS RT_BIT(9)
337/** Maximum transfer size support. */
338# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_MASK 0x1800
339# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT 11
340# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SHIFT)
341/** Only legacy transfers supported. */
342# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_LEGACY 0x0
343/** 8B maximum transfer size. */
344# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_8B 0x1
345/** 32B maximum transfer size. */
346# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_32B 0x2
347/** 64B maximum transfer size. */
348# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B 0x3
349/** FIFO interface is supported and may be selected. */
350# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_FIFO RT_BIT(13)
351/** CRB interface is supported and may be selected. */
352# define TPM_CRB_LOCALITY_REG_INTF_ID_CAP_CRB RT_BIT(14)
353/** Interrupt polarity configuration. */
354# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_MASK 0x60000
355# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT 17
356# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SET(a) ((a) << TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
357# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_GET(a) (((a) & TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_MASK) >> TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_SHIFT)
358/** Selects the FIFO interface, takes effect on next _TPM_INIT. */
359# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_FIFO 0
360/** Selects the CRB interface, takes effect on next _TPM_INIT. */
361# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_CRB 1
362/** Locks the interface selector field and prevents further changes. */
363# define TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_LOCK RT_BIT(19)
364/** Revision ID field. */
365# define TPM_CRB_LOCALITY_REG_INTF_ID_RID_SHIFT 17
366# define TPM_CRB_LOCALITY_REG_INTF_ID_RID_SET(a) ((uint64_t)(a) << TPM_CRB_LOCALITY_REG_INTF_ID_RID_SHIFT)
367/** Vendor ID field. */
368# define TPM_CRB_LOCALITY_REG_INTF_ID_VID_SHIFT 32
369# define TPM_CRB_LOCALITY_REG_INTF_ID_VID_SET(a) ((uint64_t)(a) << TPM_CRB_LOCALITY_REG_INTF_ID_VID_SHIFT)
370/** Device ID field. */
371# define TPM_CRB_LOCALITY_REG_INTF_ID_DID_SHIFT 48
372# define TPM_CRB_LOCALITY_REG_INTF_ID_DID_SET(a) ((uint64_t)(a) << TPM_CRB_LOCALITY_REG_INTF_ID_DID_SHIFT)
373
374/** Locality CRB extension register (optional and locality 0 only). */
375#define TPM_CRB_LOCALITY_REG_CTRL_EXT 0x38
376
377/** Locality CRB request register. */
378#define TPM_CRB_LOCALITY_REG_CTRL_REQ 0x40
379/** The TPM should transition to the ready state to receive a new command. */
380# define TPM_CRB_LOCALITY_REG_CTRL_REQ_CMD_RDY RT_BIT(0)
381/** The TPM should transition to the idle state. */
382# define TPM_CRB_LOCALITY_REG_CTRL_REQ_IDLE RT_BIT(1)
383
384/** Locality CRB status register. */
385#define TPM_CRB_LOCALITY_REG_CTRL_STS 0x44
386/** This bit indicates that the TPM ran into a fatal error if set. */
387# define TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_FATAL_ERR RT_BIT(0)
388/** This bit indicates that the TPM is in the idle state. */
389# define TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_IDLE RT_BIT(1)
390
391/** Locality CRB cancel register. */
392#define TPM_CRB_LOCALITY_REG_CTRL_CANCEL 0x48
393/** Locality CRB start register. */
394#define TPM_CRB_LOCALITY_REG_CTRL_START 0x4c
395
396/** Locality interrupt enable register. */
397#define TPM_CRB_LOCALITY_REG_INT_ENABLE 0x50
398/** Enable the "TPM has executed a reqeust and response is available" interrupt. */
399# define TPM_CRB_LOCALITY_REG_INT_ENABLE_START RT_BIT(0)
400/** Enable the "TPM has transitioned to the command ready state" interrupt. */
401# define TPM_CRB_LOCALITY_REG_INT_CMD_RDY RT_BIT(1)
402/** Enable the "TPM has cleared the establishment flag" interrupt. */
403# define TPM_CRB_LOCALITY_REG_INT_ESTABLISHMENT_CLR RT_BIT(2)
404/** Enable the "active locality has changed" interrupt. */
405# define TPM_CRB_LOCALITY_REG_INT_LOC_CHANGED RT_BIT(3)
406/** Enables interrupts globally as defined by the individual bits in this register. */
407# define TPM_CRB_LOCALITY_REG_INT_GLOBAL_ENABLE RT_BIT(31)
408
409/** Locality interrupt status register. */
410#define TPM_CRB_LOCALITY_REG_INT_STS 0x54
411/** Indicates that the TPM as executed a command and the response is available for reading, writing a 1 clears the bit. */
412# define TPM_CRB_LOCALITY_REG_INT_STS_START RT_BIT(0)
413/** Indicates that the TPM has finished the transition to the ready state, writing a 1 clears this bit. */
414# define TPM_CRB_LOCALITY_REG_INT_STS_CMD_RDY RT_BIT(1)
415/** Indicates that the TPM has cleared the establishment flag, writing a 1 clears this bit. */
416# define TPM_CRB_LOCALITY_REG_INT_STS_ESTABLISHMENT_CLR RT_BIT(2)
417/** Indicates that a locality change has occurrec, writing a 1 clears this bit. */
418# define TPM_CRB_LOCALITY_REG_INT_STS_LOC_CHANGED RT_BIT(3)
419
420/** Locality command buffer size register. */
421#define TPM_CRB_LOCALITY_REG_CTRL_CMD_SZ 0x58
422/** Locality command buffer low address register. */
423#define TPM_CRB_LOCALITY_REG_CTRL_CMD_LADDR 0x5c
424/** Locality command buffer low address register. */
425#define TPM_CRB_LOCALITY_REG_CTRL_CMD_HADDR 0x60
426/** Locality response buffer size register. */
427#define TPM_CRB_LOCALITY_REG_CTRL_RSP_SZ 0x64
428/** Locality response buffer address register. */
429#define TPM_CRB_LOCALITY_REG_CTRL_RSP_ADDR 0x68
430/** Locality data buffer. */
431#define TPM_CRB_LOCALITY_REG_DATA_BUFFER 0x80
432/** @} */
433
434
435/*********************************************************************************************************************************
436* Structures and Typedefs *
437*********************************************************************************************************************************/
438
439/**
440 * Possible TPM states
441 * (see chapter 5.6.12.1 Figure 3 State Transition Diagram).
442 */
443typedef enum DEVTPMSTATE
444{
445 /** Invalid state, do not use. */
446 DEVTPMSTATE_INVALID = 0,
447 /** Idle state. */
448 DEVTPMSTATE_IDLE,
449 /** Ready to accept command data. */
450 DEVTPMSTATE_READY,
451 /** Command data being transfered. */
452 DEVTPMSTATE_CMD_RECEPTION,
453 /** Command is being executed by the TPM. */
454 DEVTPMSTATE_CMD_EXEC,
455 /** Command has completed and data can be read. */
456 DEVTPMSTATE_CMD_COMPLETION,
457 /** Command is being canceled. */
458 DEVTPMSTATE_CMD_CANCEL,
459 /** TPM ran into a fatal error and is not operational. */
460 DEVTPMSTATE_FATAL_ERROR,
461 /** Last valid state (used for saved state sanity check). */
462 DEVTPMSTATE_LAST_VALID = DEVTPMSTATE_FATAL_ERROR,
463 /** 32bit hack. */
464 DEVTPMSTATE_32BIT_HACK = 0x7fffffff
465} DEVTPMSTATE;
466
467
468/**
469 * Locality state.
470 */
471typedef struct DEVTPMLOCALITY
472{
473 /** The interrupt enable register. */
474 uint32_t uRegIntEn;
475 /** The interrupt status register. */
476 uint32_t uRegIntSts;
477} DEVTPMLOCALITY;
478/** Pointer to a locality state. */
479typedef DEVTPMLOCALITY *PDEVTPMLOCALITY;
480/** Pointer to a const locality state. */
481typedef const DEVTPMLOCALITY *PCDEVTPMLOCALITY;
482
483
484/**
485 * Shared TPM device state.
486 */
487typedef struct DEVTPM
488{
489 /** Base MMIO address of the TPM device. */
490 RTGCPHYS GCPhysMmio;
491 /** The handle of the MMIO region. */
492 IOMMMIOHANDLE hMmio;
493 /** The handle for the ring-3 task. */
494 PDMTASKHANDLE hTpmCmdTask;
495 /** The vendor ID configured. */
496 uint16_t uVenId;
497 /** The device ID configured. */
498 uint16_t uDevId;
499 /** The revision ID configured. */
500 uint8_t bRevId;
501 /** The IRQ value. */
502 uint8_t uIrq;
503 /** Flag whether CRB access mode is used. */
504 bool fCrb;
505 /** Flag whether the TPM driver below supportes other localities than 0. */
506 bool fLocChangeSup;
507 /** Flag whether the establishment bit is set. */
508 bool fEstablishmentSet;
509
510 /** Currently selected locality. */
511 uint8_t bLoc;
512 /** States of the implemented localities. */
513 DEVTPMLOCALITY aLoc[TPM_LOCALITY_COUNT];
514 /** Bitmask of localities having requested access to the TPM. */
515 uint32_t bmLocReqAcc;
516 /** Bitmask of localities having been seized access from the TPM. */
517 uint32_t bmLocSeizedAcc;
518 /** The current state of the TPM. */
519 DEVTPMSTATE enmState;
520 /** The TPM version being emulated. */
521 TPMVERSION enmTpmVers;
522
523 /** Size of the command/response buffer. */
524 uint32_t cbCmdResp;
525 /** Offset into the Command/Response buffer. */
526 uint32_t offCmdResp;
527 /** Command/Response buffer. */
528 uint8_t abCmdResp[TPM_DATA_BUFFER_SIZE_MAX];
529} DEVTPM;
530/** Pointer to the shared TPM device state. */
531typedef DEVTPM *PDEVTPM;
532
533/** The special no current locality selected value. */
534#define TPM_NO_LOCALITY_SELECTED 0xff
535
536
537/**
538 * TPM device state for ring-3.
539 */
540typedef struct DEVTPMR3
541{
542 /** Pointer to the device instance. */
543 PPDMDEVINS pDevIns;
544 /** The base interface for LUN\#0. */
545 PDMIBASE IBase;
546 /** The base interface below. */
547 R3PTRTYPE(PPDMIBASE) pDrvBase;
548 /** The TPM connector interface below. */
549 R3PTRTYPE(PPDMITPMCONNECTOR) pDrvTpm;
550} DEVTPMR3;
551/** Pointer to the TPM device state for ring-3. */
552typedef DEVTPMR3 *PDEVTPMR3;
553
554
555/**
556 * TPM device state for ring-0.
557 */
558typedef struct DEVTPMR0
559{
560 uint32_t u32Dummy;
561} DEVTPMR0;
562/** Pointer to the TPM device state for ring-0. */
563typedef DEVTPMR0 *PDEVTPMR0;
564
565
566/**
567 * TPM device state for raw-mode.
568 */
569typedef struct DEVTPMRC
570{
571 uint32_t u32Dummy;
572} DEVTPMRC;
573/** Pointer to the TPM device state for raw-mode. */
574typedef DEVTPMRC *PDEVTPMRC;
575
576/** The TPM device state for the current context. */
577typedef CTX_SUFF(DEVTPM) DEVTPMCC;
578/** Pointer to the TPM device state for the current context. */
579typedef CTX_SUFF(PDEVTPM) PDEVTPMCC;
580
581
582#ifndef VBOX_DEVICE_STRUCT_TESTCASE
583
584
585/*********************************************************************************************************************************
586* Global Variables *
587*********************************************************************************************************************************/
588#ifdef IN_RING3
589/**
590 * SSM descriptor table for the TPM structure.
591 */
592static SSMFIELD const g_aTpmFields[] =
593{
594 SSMFIELD_ENTRY(DEVTPM, fEstablishmentSet),
595 SSMFIELD_ENTRY(DEVTPM, bLoc),
596 SSMFIELD_ENTRY(DEVTPM, aLoc[0].uRegIntEn),
597 SSMFIELD_ENTRY(DEVTPM, aLoc[0].uRegIntSts),
598 SSMFIELD_ENTRY(DEVTPM, aLoc[1].uRegIntEn),
599 SSMFIELD_ENTRY(DEVTPM, aLoc[1].uRegIntSts),
600 SSMFIELD_ENTRY(DEVTPM, aLoc[2].uRegIntEn),
601 SSMFIELD_ENTRY(DEVTPM, aLoc[2].uRegIntSts),
602 SSMFIELD_ENTRY(DEVTPM, aLoc[3].uRegIntEn),
603 SSMFIELD_ENTRY(DEVTPM, aLoc[3].uRegIntSts),
604 SSMFIELD_ENTRY(DEVTPM, aLoc[4].uRegIntEn),
605 SSMFIELD_ENTRY(DEVTPM, aLoc[4].uRegIntSts),
606 SSMFIELD_ENTRY(DEVTPM, bmLocReqAcc),
607 SSMFIELD_ENTRY(DEVTPM, bmLocSeizedAcc),
608 SSMFIELD_ENTRY(DEVTPM, enmState),
609 SSMFIELD_ENTRY(DEVTPM, offCmdResp),
610 SSMFIELD_ENTRY(DEVTPM, abCmdResp),
611 SSMFIELD_ENTRY_TERM()
612};
613#endif
614
615
616/**
617 * Sets the IRQ line of the given device to the given state.
618 *
619 * @param pDevIns Pointer to the PDM device instance data.
620 * @param pThis Pointer to the shared TPM device.
621 * @param iLvl The interrupt level to set.
622 */
623DECLINLINE(void) tpmIrqReq(PPDMDEVINS pDevIns, PDEVTPM pThis, int iLvl)
624{
625 PDMDevHlpISASetIrqNoWait(pDevIns, pThis->uIrq, iLvl);
626}
627
628
629/**
630 * Updates the IRQ status of the given locality.
631 *
632 * @param pDevIns Pointer to the PDM device instance data.
633 * @param pThis Pointer to the shared TPM device.
634 * @param pLoc The locality state.
635 */
636static void tpmLocIrqUpdate(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc)
637{
638 if ( (pLoc->uRegIntEn & TPM_CRB_LOCALITY_REG_INT_GLOBAL_ENABLE) /* Aliases with TPM_FIFO_LOCALITY_REG_INT_ENABLE_GLOBAL */
639 && (pLoc->uRegIntEn & pLoc->uRegIntSts))
640 tpmIrqReq(pDevIns, pThis, 1);
641 else
642 tpmIrqReq(pDevIns, pThis, 0);
643}
644
645
646/**
647 * Sets the interrupt status for the given locality, firing an interrupt if necessary.
648 *
649 * @param pDevIns Pointer to the PDM device instance data.
650 * @param pThis Pointer to the shared TPM device.
651 * @param pLoc The locality state.
652 * @param uSts The interrupt status bit to set.
653 */
654static void tpmLocSetIntSts(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc, uint32_t uSts)
655{
656 pLoc->uRegIntSts |= uSts;
657 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
658}
659
660
661/**
662 * Selects the next locality which has requested access.
663 *
664 * @param pDevIns Pointer to the PDM device instance data.
665 * @param pThis Pointer to the shared TPM device.
666 */
667static void tpmLocSelectNext(PPDMDEVINS pDevIns, PDEVTPM pThis)
668{
669 Assert(pThis->bmLocReqAcc);
670 Assert(pThis->bLoc == TPM_NO_LOCALITY_SELECTED);
671 pThis->bLoc = (uint8_t)ASMBitLastSetU32(pThis->bmLocReqAcc) - 1; /* Select one with highest priority. */
672
673 tpmLocSetIntSts(pDevIns, pThis, &pThis->aLoc[pThis->bLoc], TPM_CRB_LOCALITY_REG_INT_STS_LOC_CHANGED);
674}
675
676
677/**
678 * Returns the given locality being accessed from the given TPM MMIO offset.
679 *
680 * @returns Locality number.
681 * @param off The offset into the TPM MMIO region.
682 */
683DECLINLINE(uint8_t) tpmGetLocalityFromOffset(RTGCPHYS off)
684{
685 return off / TPM_LOCALITY_MMIO_SIZE;
686}
687
688
689/**
690 * Returns the given register of a particular locality being accessed from the given TPM MMIO offset.
691 *
692 * @returns Register index being accessed.
693 * @param off The offset into the TPM MMIO region.
694 */
695DECLINLINE(uint32_t) tpmGetRegisterFromOffset(RTGCPHYS off)
696{
697 return off % TPM_LOCALITY_MMIO_SIZE;
698}
699
700
701/**
702 * Read from a FIFO interface register.
703 *
704 * @returns VBox strict status code.
705 * @param pDevIns Pointer to the PDM device instance data.
706 * @param pThis Pointer to the shared TPM device.
707 * @param pLoc The locality state being read from.
708 * @param bLoc The locality index.
709 * @param uReg The register offset being accessed.
710 * @param pu64 Where to store the read data.
711 * @param cb Number of bytes to read.
712 */
713static VBOXSTRICTRC tpmMmioFifoRead(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
714 uint8_t bLoc, uint32_t uReg, uint64_t *pu64, size_t cb)
715{
716 RT_NOREF(pDevIns);
717 VBOXSTRICTRC rc = VINF_SUCCESS;
718
719 /* Special path for the data buffer. */
720 if ( ( ( uReg >= TPM_FIFO_LOCALITY_REG_DATA_FIFO
721 && uReg < TPM_FIFO_LOCALITY_REG_DATA_FIFO + sizeof(uint32_t))
722 || ( uReg >= TPM_FIFO_LOCALITY_REG_XDATA_FIFO
723 && uReg < TPM_FIFO_LOCALITY_REG_XDATA_FIFO + sizeof(uint32_t)))
724 && bLoc == pThis->bLoc
725 && pThis->enmState == DEVTPMSTATE_CMD_COMPLETION)
726 {
727 if (pThis->offCmdResp <= pThis->cbCmdResp - cb)
728 {
729 memcpy(pu64, &pThis->abCmdResp[pThis->offCmdResp], cb);
730 pThis->offCmdResp += (uint32_t)cb;
731 }
732 else
733 memset(pu64, 0xff, cb);
734 return VINF_SUCCESS;
735 }
736
737 uint64_t u64;
738 switch (uReg)
739 {
740 case TPM_FIFO_LOCALITY_REG_ACCESS:
741 u64 = TPM_FIFO_LOCALITY_REG_ACCESS_VALID;
742 if (pThis->bLoc == bLoc)
743 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_ACTIVE;
744 if (pThis->bmLocSeizedAcc & RT_BIT_32(bLoc))
745 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_BEEN_SEIZED;
746 if (pThis->bmLocReqAcc & ~RT_BIT_32(bLoc))
747 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_PENDING_REQUEST;
748 if ( pThis->bLoc != bLoc
749 && pThis->bmLocReqAcc & RT_BIT_32(bLoc))
750 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_REQUEST_USE;
751 if (pThis->fEstablishmentSet)
752 u64 |= TPM_FIFO_LOCALITY_REG_ACCESS_ESTABLISHMENT;
753 break;
754 case TPM_FIFO_LOCALITY_REG_INT_ENABLE:
755 u64 = pLoc->uRegIntEn;
756 break;
757 case TPM_FIFO_LOCALITY_REG_INT_VEC:
758 u64 = pThis->uIrq;
759 break;
760 case TPM_FIFO_LOCALITY_REG_INT_STS:
761 u64 = pLoc->uRegIntSts;
762 break;
763 case TPM_FIFO_LOCALITY_REG_IF_CAP:
764 u64 = TPM_FIFO_LOCALITY_REG_IF_CAP_INT_DATA_AVAIL
765 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_STS_VALID
766 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LOCALITY_CHANGE
767 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_LVL_LOW
768 | TPM_FIFO_LOCALITY_REG_IF_CAP_INT_CMD_RDY
769 | TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_SET(TPM_FIFO_LOCALITY_REG_IF_CAP_DATA_XFER_SZ_64B); /** @todo Make some of them configurable? */
770 if (pThis->enmTpmVers == TPMVERSION_1_2)
771 u64 |= TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SET(TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3);
772 else
773 u64 |= TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_SET(TPM_FIFO_LOCALITY_REG_IF_CAP_IF_VERSION_IF_1_3_TPM2);
774 break;
775 case TPM_FIFO_LOCALITY_REG_STS:
776 if (bLoc != pThis->bLoc)
777 {
778 u64 = UINT64_MAX;
779 break;
780 }
781
782 u64 = TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_SET( pThis->enmTpmVers == TPMVERSION_1_2
783 ? TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_1_2
784 : TPM_FIFO_LOCALITY_REG_STS_TPM_FAMILY_2_0)
785 | TPM_FIFO_LOCALITY_REG_STS_BURST_CNT_SET(_1K)
786 | TPM_FIFO_LOCALITY_REG_STS_VALID;
787 if (pThis->enmState == DEVTPMSTATE_READY)
788 u64 |= TPM_FIFO_LOCALITY_REG_STS_CMD_RDY;
789 else if (pThis->enmState == DEVTPMSTATE_CMD_RECEPTION) /* When in the command reception state check whether all of the command data has been received. */
790 {
791 if ( pThis->offCmdResp < sizeof(TPMREQHDR)
792 || pThis->offCmdResp < RTTpmReqGetSz((PCTPMREQHDR)&pThis->abCmdResp[0]))
793 u64 |= TPM_FIFO_LOCALITY_REG_STS_EXPECT;
794 }
795 else if (pThis->enmState == DEVTPMSTATE_CMD_COMPLETION) /* Check whether there is more response data available. */
796 {
797 if (pThis->offCmdResp < RTTpmRespGetSz((PCTPMRESPHDR)&pThis->abCmdResp[0]))
798 u64 |= TPM_FIFO_LOCALITY_REG_STS_DATA_AVAIL;
799 }
800 break;
801 case TPM_FIFO_LOCALITY_REG_INTF_ID:
802 u64 = TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_VERS_FIFO)
803 | TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B)
804 | TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_GET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_FIFO)
805 | TPM_FIFO_LOCALITY_REG_INTF_ID_IF_SEL_LOCK
806 | TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_SET(TPM_FIFO_LOCALITY_REG_INTF_ID_IF_TYPE_TIS1_3);
807
808 if (pThis->fLocChangeSup) /* Only advertise the locality capability if the driver below supports it. */
809 u64 |= TPM_FIFO_LOCALITY_REG_INTF_ID_CAP_LOCALITY;
810 break;
811 case TPM_FIFO_LOCALITY_REG_DID_VID:
812 u64 = RT_H2BE_U32(RT_MAKE_U32(pThis->uVenId, pThis->uDevId));
813 break;
814 case TPM_FIFO_LOCALITY_REG_RID:
815 u64 = pThis->bRevId;
816 break;
817 default: /* Return ~0. */
818 u64 = UINT64_MAX;
819 break;
820 }
821
822 *pu64 = u64;
823
824 return rc;
825}
826
827
828/**
829 * Read to a FIFO interface register.
830 *
831 * @returns VBox strict status code.
832 * @param pDevIns Pointer to the PDM device instance data.
833 * @param pThis Pointer to the shared TPM device.
834 * @param pLoc The locality state being written to.
835 * @param bLoc The locality index.
836 * @param uReg The register offset being accessed.
837 * @param u64 The value to write.
838 * @param cb Number of bytes to write.
839 */
840static VBOXSTRICTRC tpmMmioFifoWrite(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
841 uint8_t bLoc, uint32_t uReg, uint64_t u64, size_t cb)
842{
843#ifdef IN_RING3
844 PDEVTPMR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMR3);
845#endif
846
847 /* Special path for the data buffer. */
848 if ( ( ( uReg >= TPM_FIFO_LOCALITY_REG_DATA_FIFO
849 && uReg < TPM_FIFO_LOCALITY_REG_DATA_FIFO + sizeof(uint32_t))
850 || ( uReg >= TPM_FIFO_LOCALITY_REG_XDATA_FIFO
851 && uReg < TPM_FIFO_LOCALITY_REG_XDATA_FIFO + sizeof(uint32_t)))
852 && bLoc == pThis->bLoc
853 && ( pThis->enmState == DEVTPMSTATE_READY
854 || pThis->enmState == DEVTPMSTATE_CMD_RECEPTION))
855 {
856 pThis->enmState = DEVTPMSTATE_CMD_RECEPTION;
857 if (pThis->offCmdResp <= pThis->cbCmdResp - cb)
858 {
859 memcpy(&pThis->abCmdResp[pThis->offCmdResp], &u64, cb);
860 pThis->offCmdResp += (uint32_t)cb;
861 }
862 return VINF_SUCCESS;
863 }
864
865 VBOXSTRICTRC rc = VINF_SUCCESS;
866 uint32_t u32 = (uint32_t)u64;
867
868 switch (uReg)
869 {
870 case TPM_FIFO_LOCALITY_REG_ACCESS:
871 u32 &= TPM_FIFO_LOCALITY_REG_ACCESS_WR_MASK;
872 /*
873 * Chapter 5.6.11, 2 states that writing to this register with more than one
874 * bit set to '1' is vendor specific, we decide to ignore such writes to make the logic
875 * below simpler.
876 */
877 if (!RT_IS_POWER_OF_TWO(u32))
878 break;
879
880 /* Seize access only if this locality has a higher priority than the currently selected one. */
881 if ( (u32 & TPM_FIFO_LOCALITY_REG_ACCESS_SEIZE)
882 && pThis->bLoc != TPM_NO_LOCALITY_SELECTED
883 && bLoc > pThis->bLoc)
884 {
885 pThis->bmLocSeizedAcc |= RT_BIT_32(pThis->bLoc);
886 /** @todo Abort command. */
887 pThis->bLoc = bLoc;
888 }
889
890 if ( (u64 & TPM_FIFO_LOCALITY_REG_ACCESS_REQUEST_USE)
891 && !(pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
892 {
893 pThis->bmLocReqAcc |= RT_BIT_32(bLoc);
894 if (pThis->bLoc == TPM_NO_LOCALITY_SELECTED)
895 {
896 pThis->bLoc = bLoc; /* Doesn't fire an interrupt. */
897 pThis->bmLocSeizedAcc &= ~RT_BIT_32(bLoc);
898 }
899 }
900
901 if ( (u64 & TPM_FIFO_LOCALITY_REG_ACCESS_ACTIVE)
902 && (pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
903 {
904 pThis->bmLocReqAcc &= ~RT_BIT_32(bLoc);
905 if (pThis->bLoc == bLoc)
906 {
907 pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
908 if (pThis->bmLocReqAcc)
909 tpmLocSelectNext(pDevIns, pThis); /* Select the next locality. */
910 }
911 }
912 break;
913 case TPM_FIFO_LOCALITY_REG_INT_ENABLE:
914 if (bLoc != pThis->bLoc)
915 break;
916 pLoc->uRegIntEn = u32;
917 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
918 break;
919 case TPM_FIFO_LOCALITY_REG_INT_STS:
920 if (bLoc != pThis->bLoc)
921 break;
922 pLoc->uRegIntSts &= ~(u32 & TPM_FIFO_LOCALITY_REG_INT_STS_WR_MASK);
923 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
924 break;
925 case TPM_FIFO_LOCALITY_REG_STS:
926 /*
927 * Writes are ignored completely if the locality being accessed is not the
928 * current active one or if the value has multiple bits set (not a power of two),
929 * see chapter 5.6.12.1.
930 */
931 if ( bLoc != pThis->bLoc
932 || !RT_IS_POWER_OF_TWO(u64))
933 break;
934
935 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_CMD_RDY)
936 && ( pThis->enmState == DEVTPMSTATE_IDLE
937 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
938 {
939 pThis->enmState = DEVTPMSTATE_READY;
940 pThis->offCmdResp = 0;
941 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_FIFO_LOCALITY_REG_INT_STS_CMD_RDY);
942 }
943
944 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_TPM_GO)
945 && pThis->enmState == DEVTPMSTATE_CMD_RECEPTION)
946 {
947 pThis->enmState = DEVTPMSTATE_CMD_EXEC;
948 rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hTpmCmdTask);
949 }
950
951 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_RST_ESTABLISHMENT)
952 && pThis->bLoc >= 3
953 && ( pThis->enmState == DEVTPMSTATE_IDLE
954 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
955 {
956#ifndef IN_RING3
957 rc = VINF_IOM_R3_MMIO_WRITE;
958 break;
959#else
960 if (pThisCC->pDrvTpm)
961 {
962 int rc2 = pThisCC->pDrvTpm->pfnResetEstablishedFlag(pThisCC->pDrvTpm, pThis->bLoc);
963 if (RT_SUCCESS(rc2))
964 pThis->fEstablishmentSet = false;
965 else
966 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
967 }
968 else
969 pThis->fEstablishmentSet = false;
970#endif
971 }
972
973 if ( (u64 & TPM_FIFO_LOCALITY_REG_STS_CMD_CANCEL)
974 && pThis->enmState == DEVTPMSTATE_CMD_EXEC)
975 {
976#ifndef IN_RING3
977 rc = VINF_IOM_R3_MMIO_WRITE;
978 break;
979#else
980 if (pThisCC->pDrvTpm)
981 {
982 pThis->enmState = DEVTPMSTATE_CMD_CANCEL;
983 int rc2 = pThisCC->pDrvTpm->pfnCmdCancel(pThisCC->pDrvTpm);
984 if (RT_FAILURE(rc2))
985 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
986 }
987#endif
988 }
989
990 break;
991 case TPM_FIFO_LOCALITY_REG_INT_VEC:
992 case TPM_FIFO_LOCALITY_REG_IF_CAP:
993 case TPM_FIFO_LOCALITY_REG_DID_VID:
994 case TPM_FIFO_LOCALITY_REG_RID:
995 default: /* Ignore. */
996 break;
997 }
998
999 return rc;
1000}
1001
1002
1003/**
1004 * Read from a CRB interface register.
1005 *
1006 * @returns VBox strict status code.
1007 * @param pDevIns Pointer to the PDM device instance data.
1008 * @param pThis Pointer to the shared TPM device.
1009 * @param pLoc The locality state being read from.
1010 * @param bLoc The locality index.
1011 * @param uReg The register offset being accessed.
1012 * @param pu64 Where to store the read data.
1013 * @param cb Size of the read in bytes.
1014 */
1015static VBOXSTRICTRC tpmMmioCrbRead(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
1016 uint8_t bLoc, uint32_t uReg, uint64_t *pu64, size_t cb)
1017{
1018 RT_NOREF(pDevIns);
1019
1020 /* Special path for the data buffer. */
1021 if ( uReg >= TPM_CRB_LOCALITY_REG_DATA_BUFFER
1022 && uReg < TPM_CRB_LOCALITY_REG_DATA_BUFFER + pThis->cbCmdResp
1023 && bLoc == pThis->bLoc
1024 && pThis->enmState == DEVTPMSTATE_CMD_COMPLETION)
1025 {
1026 memcpy(pu64, &pThis->abCmdResp[uReg - TPM_CRB_LOCALITY_REG_DATA_BUFFER], cb);
1027 return VINF_SUCCESS;
1028 }
1029
1030 VBOXSTRICTRC rc = VINF_SUCCESS;
1031 uint64_t u64 = UINT64_MAX;
1032 switch (uReg)
1033 {
1034 case TPM_CRB_LOCALITY_REG_STATE:
1035 u64 = TPM_CRB_LOCALITY_REG_STATE_VALID
1036 | ( pThis->bLoc != TPM_NO_LOCALITY_SELECTED
1037 ? TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SET(pThis->bLoc) | TPM_CRB_LOCALITY_REG_STATE_LOC_ASSIGNED
1038 : TPM_CRB_LOCALITY_REG_STATE_ACTIVE_LOC_SET(0));
1039 if (pThis->fEstablishmentSet)
1040 u64 |= TPM_CRB_LOCALITY_REG_ESTABLISHMENT;
1041 break;
1042 case TPM_CRB_LOCALITY_REG_STS:
1043 u64 = pThis->bLoc == bLoc
1044 ? TPM_CRB_LOCALITY_REG_STS_GRANTED
1045 : 0;
1046 u64 |= pThis->bmLocSeizedAcc & RT_BIT_32(bLoc)
1047 ? TPM_CRB_LOCALITY_REG_STS_SEIZED
1048 : 0;
1049 break;
1050 case TPM_CRB_LOCALITY_REG_INTF_ID:
1051 u64 = TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_SET(TPM_CRB_LOCALITY_REG_INTF_ID_IF_TYPE_CRB)
1052 | TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_SET(TPM_CRB_LOCALITY_REG_INTF_ID_IF_VERS_CRB)
1053 | TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_SET(TPM_CRB_LOCALITY_REG_INTF_ID_CAP_DATA_XFER_SZ_64B)
1054 | TPM_CRB_LOCALITY_REG_INTF_ID_CAP_CRB
1055 | TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_GET(TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_CRB)
1056 | TPM_CRB_LOCALITY_REG_INTF_ID_IF_SEL_LOCK
1057 | TPM_CRB_LOCALITY_REG_INTF_ID_RID_SET(pThis->bRevId)
1058 | TPM_CRB_LOCALITY_REG_INTF_ID_VID_SET(pThis->uVenId)
1059 | TPM_CRB_LOCALITY_REG_INTF_ID_DID_SET(pThis->uDevId);
1060
1061 if (pThis->fLocChangeSup) /* Only advertise the locality capability if the driver below supports it. */
1062 u64 |= TPM_CRB_LOCALITY_REG_INTF_ID_CAP_LOCALITY;
1063
1064 break;
1065 case TPM_CRB_LOCALITY_REG_CTRL_REQ:
1066 if (bLoc != pThis->bLoc)
1067 break;
1068 /*
1069 * Command ready and go idle are always 0 upon read
1070 * as we don't need time to transition to this state
1071 * when written by the guest.
1072 */
1073 u64 = 0;
1074 break;
1075 case TPM_CRB_LOCALITY_REG_CTRL_STS:
1076 if (bLoc != pThis->bLoc)
1077 break;
1078 if (pThis->enmState == DEVTPMSTATE_FATAL_ERROR)
1079 u64 = TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_FATAL_ERR;
1080 else if (pThis->enmState == DEVTPMSTATE_IDLE)
1081 u64 = TPM_CRB_LOCALITY_REG_CTRL_STS_TPM_IDLE;
1082 else
1083 u64 = 0;
1084 break;
1085 case TPM_CRB_LOCALITY_REG_CTRL_CANCEL:
1086 if (bLoc != pThis->bLoc)
1087 break;
1088 if (pThis->enmState == DEVTPMSTATE_CMD_CANCEL)
1089 u64 = 0x1;
1090 else
1091 u64 = 0;
1092 break;
1093 case TPM_CRB_LOCALITY_REG_CTRL_START:
1094 if (bLoc != pThis->bLoc)
1095 break;
1096 if (pThis->enmState == DEVTPMSTATE_CMD_EXEC)
1097 u64 = 0x1;
1098 else
1099 u64 = 0;
1100 break;
1101 case TPM_CRB_LOCALITY_REG_INT_ENABLE:
1102 u64 = pLoc->uRegIntEn;
1103 break;
1104 case TPM_CRB_LOCALITY_REG_INT_STS:
1105 u64 = pLoc->uRegIntSts;
1106 break;
1107 case TPM_CRB_LOCALITY_REG_CTRL_CMD_LADDR:
1108 u64 = pThis->GCPhysMmio + (bLoc * TPM_LOCALITY_MMIO_SIZE) + TPM_CRB_LOCALITY_REG_DATA_BUFFER;
1109 break;
1110 case TPM_CRB_LOCALITY_REG_CTRL_CMD_HADDR:
1111 u64 = (pThis->GCPhysMmio + (bLoc * TPM_LOCALITY_MMIO_SIZE) + TPM_CRB_LOCALITY_REG_DATA_BUFFER) >> 32;
1112 break;
1113 case TPM_CRB_LOCALITY_REG_CTRL_CMD_SZ:
1114 case TPM_CRB_LOCALITY_REG_CTRL_RSP_SZ:
1115 u64 = pThis->cbCmdResp;
1116 break;
1117 case TPM_CRB_LOCALITY_REG_CTRL_RSP_ADDR:
1118 u64 = pThis->GCPhysMmio + (bLoc * TPM_LOCALITY_MMIO_SIZE) + TPM_CRB_LOCALITY_REG_DATA_BUFFER;
1119 break;
1120 case TPM_CRB_LOCALITY_REG_CTRL: /* Writeonly */
1121 u64 = 0;
1122 break;
1123 case TPM_CRB_LOCALITY_REG_CTRL_EXT:
1124 default:
1125 break; /* Return ~0 */
1126 }
1127
1128 *pu64 = u64;
1129 return rc;
1130}
1131
1132
1133/**
1134 * Read to a CRB interface register.
1135 *
1136 * @returns VBox strict status code.
1137 * @param pDevIns Pointer to the PDM device instance data.
1138 * @param pThis Pointer to the shared TPM device.
1139 * @param pLoc The locality state being written to.
1140 * @param bLoc The locality index.
1141 * @param uReg The register offset being accessed.
1142 * @param u64 The value to write.
1143 * @param cb Size of the write in bytes.
1144 */
1145static VBOXSTRICTRC tpmMmioCrbWrite(PPDMDEVINS pDevIns, PDEVTPM pThis, PDEVTPMLOCALITY pLoc,
1146 uint8_t bLoc, uint32_t uReg, uint64_t u64, size_t cb)
1147{
1148#ifdef IN_RING3
1149 PDEVTPMR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMR3);
1150#endif
1151
1152 VBOXSTRICTRC rc = VINF_SUCCESS;
1153 uint32_t u32 = (uint32_t)u64;
1154
1155 /* Special path for the data buffer. */
1156 if ( uReg >= TPM_CRB_LOCALITY_REG_DATA_BUFFER
1157 && uReg < TPM_CRB_LOCALITY_REG_DATA_BUFFER + pThis->cbCmdResp
1158 && bLoc == pThis->bLoc
1159 && ( pThis->enmState == DEVTPMSTATE_READY
1160 || pThis->enmState == DEVTPMSTATE_CMD_RECEPTION))
1161 {
1162 pThis->enmState = DEVTPMSTATE_CMD_RECEPTION;
1163 memcpy(&pThis->abCmdResp[uReg - TPM_CRB_LOCALITY_REG_DATA_BUFFER], &u64, cb);
1164 return VINF_SUCCESS;
1165 }
1166
1167 switch (uReg)
1168 {
1169 case TPM_CRB_LOCALITY_REG_CTRL:
1170 {
1171 /* See chapter 6.5.3.2.2.1. */
1172 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_RST_ESTABLISHMENT)
1173 && pThis->bLoc >= 3
1174 && ( pThis->enmState == DEVTPMSTATE_IDLE
1175 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
1176 {
1177#ifndef IN_RING3
1178 rc = VINF_IOM_R3_MMIO_WRITE;
1179 break;
1180#else
1181 if (pThisCC->pDrvTpm)
1182 {
1183 int rc2 = pThisCC->pDrvTpm->pfnResetEstablishedFlag(pThisCC->pDrvTpm, pThis->bLoc);
1184 if (RT_SUCCESS(rc2))
1185 pThis->fEstablishmentSet = false;
1186 else
1187 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1188 }
1189 else
1190 pThis->fEstablishmentSet = false;
1191#endif
1192 }
1193
1194 /*
1195 * The following three checks should be mutually exclusive as the writer shouldn't
1196 * request, relinquish and seize access in the same write.
1197 */
1198 /* Seize access only if this locality has a higher priority than the currently selected one. */
1199 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_SEIZE)
1200 && pThis->bLoc != TPM_NO_LOCALITY_SELECTED
1201 && bLoc > pThis->bLoc)
1202 {
1203 if (pThis->enmState == DEVTPMSTATE_CMD_EXEC)
1204 {
1205#ifndef IN_RING3
1206 rc = VINF_IOM_R3_MMIO_WRITE;
1207 break;
1208#else
1209 pThis->enmState = DEVTPMSTATE_CMD_CANCEL;
1210 if (pThisCC->pDrvTpm)
1211 {
1212 int rc2 = pThisCC->pDrvTpm->pfnCmdCancel(pThisCC->pDrvTpm);
1213 if (RT_FAILURE(rc2))
1214 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1215 else
1216 {
1217 pThis->enmState = DEVTPMSTATE_CMD_COMPLETION;
1218 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_CRB_LOCALITY_REG_INT_STS_START);
1219 }
1220 }
1221#endif
1222 }
1223
1224 pThis->bmLocSeizedAcc |= RT_BIT_32(pThis->bLoc);
1225 pThis->bLoc = bLoc;
1226 }
1227
1228 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_REQ_ACCESS)
1229 && !(pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
1230 {
1231 pThis->bmLocReqAcc |= RT_BIT_32(bLoc);
1232 if (pThis->bLoc == TPM_NO_LOCALITY_SELECTED)
1233 {
1234 pThis->bLoc = bLoc; /* Doesn't fire an interrupt. */
1235 pThis->bmLocSeizedAcc &= ~RT_BIT_32(bLoc);
1236 }
1237 }
1238
1239 if ( (u64 & TPM_CRB_LOCALITY_REG_CTRL_RELINQUISH)
1240 && (pThis->bmLocReqAcc & RT_BIT_32(bLoc)))
1241 {
1242 pThis->bmLocReqAcc &= ~RT_BIT_32(bLoc);
1243 if (pThis->bLoc == bLoc)
1244 {
1245 pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
1246 if (pThis->bmLocReqAcc)
1247 tpmLocSelectNext(pDevIns, pThis); /* Select the next locality. */
1248 }
1249 }
1250 break;
1251 }
1252 case TPM_CRB_LOCALITY_REG_CTRL_REQ:
1253 if ( bLoc != pThis->bLoc
1254 || !RT_IS_POWER_OF_TWO(u32)) /* Ignore if multiple bits are set. */
1255 break;
1256 if ( (u32 & TPM_CRB_LOCALITY_REG_CTRL_REQ_CMD_RDY)
1257 && ( pThis->enmState == DEVTPMSTATE_IDLE
1258 || pThis->enmState == DEVTPMSTATE_CMD_COMPLETION))
1259 {
1260 pThis->enmState = DEVTPMSTATE_READY;
1261 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_CRB_LOCALITY_REG_INT_STS_CMD_RDY);
1262 }
1263 else if ( (u32 & TPM_CRB_LOCALITY_REG_CTRL_REQ_IDLE)
1264 && pThis->enmState != DEVTPMSTATE_CMD_EXEC)
1265 {
1266 /* Invalidate the command/response buffer. */
1267 RT_ZERO(pThis->abCmdResp);
1268 pThis->offCmdResp = 0;
1269 pThis->enmState = DEVTPMSTATE_IDLE;
1270 }
1271 break;
1272 case TPM_CRB_LOCALITY_REG_CTRL_CANCEL:
1273 if (bLoc != pThis->bLoc)
1274 break;
1275 if ( pThis->enmState == DEVTPMSTATE_CMD_EXEC
1276 && u32 == 0x1)
1277 {
1278#ifndef IN_RING3
1279 rc = VINF_IOM_R3_MMIO_WRITE;
1280 break;
1281#else
1282 pThis->enmState = DEVTPMSTATE_CMD_CANCEL;
1283 if (pThisCC->pDrvTpm)
1284 {
1285 int rc2 = pThisCC->pDrvTpm->pfnCmdCancel(pThisCC->pDrvTpm);
1286 if (RT_FAILURE(rc2))
1287 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1288 else
1289 {
1290 pThis->enmState = DEVTPMSTATE_CMD_COMPLETION;
1291 tpmLocSetIntSts(pDevIns, pThis, pLoc, TPM_CRB_LOCALITY_REG_INT_STS_START);
1292 }
1293 }
1294#endif
1295 }
1296 break;
1297 case TPM_CRB_LOCALITY_REG_CTRL_START:
1298 if (bLoc != pThis->bLoc)
1299 break;
1300 if ( pThis->enmState == DEVTPMSTATE_CMD_RECEPTION
1301 && u32 == 0x1)
1302 {
1303 pThis->enmState = DEVTPMSTATE_CMD_EXEC;
1304 rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hTpmCmdTask);
1305 }
1306 break;
1307 case TPM_CRB_LOCALITY_REG_INT_ENABLE:
1308 pLoc->uRegIntEn = u32;
1309 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
1310 break;
1311 case TPM_CRB_LOCALITY_REG_INT_STS:
1312 pLoc->uRegIntSts &= ~u32;
1313 tpmLocIrqUpdate(pDevIns, pThis, pLoc);
1314 break;
1315 case TPM_CRB_LOCALITY_REG_CTRL_EXT: /* Not implemented. */
1316 case TPM_CRB_LOCALITY_REG_STATE: /* Readonly */
1317 case TPM_CRB_LOCALITY_REG_INTF_ID:
1318 case TPM_CRB_LOCALITY_REG_CTRL_STS:
1319 case TPM_CRB_LOCALITY_REG_CTRL_CMD_LADDR:
1320 case TPM_CRB_LOCALITY_REG_CTRL_CMD_HADDR:
1321 case TPM_CRB_LOCALITY_REG_CTRL_CMD_SZ:
1322 case TPM_CRB_LOCALITY_REG_CTRL_RSP_SZ:
1323 case TPM_CRB_LOCALITY_REG_CTRL_RSP_ADDR:
1324 default: /* Ignore. */
1325 break;
1326 }
1327
1328 return rc;
1329}
1330
1331
1332/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
1333
1334/**
1335 * @callback_method_impl{FNIOMMMIONEWREAD}
1336 */
1337static DECLCALLBACK(VBOXSTRICTRC) tpmMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
1338{
1339 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1340 RT_NOREF(pvUser);
1341
1342 AssertReturn(cb <= sizeof(uint64_t), VERR_INTERNAL_ERROR);
1343
1344 RTGCPHYS offAligned = off & ~UINT64_C(0x3);
1345 uint8_t cBitsShift = (off & 0x3) * 8;
1346
1347 VBOXSTRICTRC rc = VINF_SUCCESS;
1348 uint32_t uReg = tpmGetRegisterFromOffset(offAligned);
1349 uint8_t bLoc = tpmGetLocalityFromOffset(offAligned);
1350 PDEVTPMLOCALITY pLoc = &pThis->aLoc[bLoc];
1351
1352 uint64_t u64;
1353 if (pThis->fCrb)
1354 rc = tpmMmioCrbRead(pDevIns, pThis, pLoc, bLoc, uReg, &u64, cb);
1355 else
1356 rc = tpmMmioFifoRead(pDevIns, pThis, pLoc, bLoc, uReg, &u64, cb);
1357
1358 LogFlowFunc((": %RGp %#x %#llx\n", off, cb, u64));
1359
1360 if (rc == VINF_SUCCESS)
1361 {
1362 switch (cb)
1363 {
1364 case 1: *(uint8_t *)pv = (uint8_t)(u64 >> cBitsShift); break;
1365 case 2: *(uint16_t *)pv = (uint16_t)(u64 >> cBitsShift); break;
1366 case 4: *(uint32_t *)pv = (uint32_t)(u64 >> cBitsShift); break;
1367 case 8: *(uint64_t *)pv = u64; break;
1368 default: AssertFailedBreakStmt(rc = VERR_INTERNAL_ERROR);
1369 }
1370 }
1371
1372 return rc;
1373}
1374
1375
1376/**
1377 * @callback_method_impl{FNIOMMMIONEWWRITE}
1378 */
1379static DECLCALLBACK(VBOXSTRICTRC) tpmMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
1380{
1381 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1382 RT_NOREF(pvUser);
1383
1384 Assert(!(off & (cb - 1)));
1385
1386 uint64_t u64;
1387 switch (cb)
1388 {
1389 case 1: u64 = *(const uint8_t *)pv; break;
1390 case 2: u64 = *(const uint16_t *)pv; break;
1391 case 4: u64 = *(const uint32_t *)pv; break;
1392 case 8: u64 = *(const uint64_t *)pv; break;
1393 default: AssertFailedReturn(VERR_INTERNAL_ERROR);
1394 }
1395
1396 LogFlowFunc((": %RGp %#llx\n", off, u64));
1397
1398 VBOXSTRICTRC rc = VINF_SUCCESS;
1399 uint32_t uReg = tpmGetRegisterFromOffset(off);
1400 uint8_t bLoc = tpmGetLocalityFromOffset(off);
1401 PDEVTPMLOCALITY pLoc = &pThis->aLoc[bLoc];
1402
1403 if (pThis->fCrb)
1404 rc = tpmMmioCrbWrite(pDevIns, pThis, pLoc, bLoc, uReg, u64, cb);
1405 else
1406 rc = tpmMmioFifoWrite(pDevIns, pThis, pLoc, bLoc, uReg, u64, cb);
1407
1408 return rc;
1409}
1410
1411
1412#ifdef IN_RING3
1413
1414/**
1415 * @callback_method_impl{FNPDMTASKDEV, Execute a command in ring-3}
1416 */
1417static DECLCALLBACK(void) tpmR3CmdExecWorker(PPDMDEVINS pDevIns, void *pvUser)
1418{
1419 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1420 PDEVTPMR3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMR3);
1421 RT_NOREF(pvUser);
1422 LogFlowFunc(("\n"));
1423
1424 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
1425 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
1426
1427 if (pThisCC->pDrvTpm)
1428 {
1429 size_t cbCmd = RTTpmReqGetSz((PCTPMREQHDR)&pThis->abCmdResp[0]);
1430 int rc = pThisCC->pDrvTpm->pfnCmdExec(pThisCC->pDrvTpm, pThis->bLoc, &pThis->abCmdResp[0], cbCmd,
1431 &pThis->abCmdResp[0], sizeof(pThis->abCmdResp));
1432 if (RT_SUCCESS(rc))
1433 {
1434 pThis->enmState = DEVTPMSTATE_CMD_COMPLETION;
1435 pThis->offCmdResp = 0;
1436 if (pThis->fCrb)
1437 tpmLocSetIntSts(pThisCC->pDevIns, pThis, &pThis->aLoc[pThis->bLoc], TPM_CRB_LOCALITY_REG_INT_STS_START);
1438 else
1439 tpmLocSetIntSts(pThisCC->pDevIns, pThis, &pThis->aLoc[pThis->bLoc], TPM_FIFO_LOCALITY_REG_INT_STS_DATA_AVAIL | TPM_FIFO_LOCALITY_REG_INT_STS_STS_VALID);
1440 }
1441 else
1442 {
1443 /* Set fatal error. */
1444 pThis->enmState = DEVTPMSTATE_FATAL_ERROR;
1445 }
1446 }
1447
1448 PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
1449}
1450
1451
1452/**
1453 * Resets the shared hardware TPM state.
1454 *
1455 * @param pThis Pointer to the shared TPM device.
1456 */
1457static void tpmR3HwReset(PDEVTPM pThis)
1458{
1459 pThis->enmState = DEVTPMSTATE_IDLE;
1460 pThis->bLoc = TPM_NO_LOCALITY_SELECTED;
1461 pThis->bmLocReqAcc = 0;
1462 pThis->bmLocSeizedAcc = 0;
1463 pThis->offCmdResp = 0;
1464 RT_ZERO(pThis->abCmdResp);
1465
1466 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aLoc); i++)
1467 {
1468 PDEVTPMLOCALITY pLoc = &pThis->aLoc[i];
1469 pLoc->uRegIntEn = 0;
1470 pLoc->uRegIntSts = 0;
1471 }
1472}
1473
1474
1475/* -=-=-=-=-=-=-=-=- Saved State -=-=-=-=-=-=-=-=- */
1476
1477/**
1478 * @callback_method_impl{FNSSMDEVLIVEEXEC}
1479 */
1480static DECLCALLBACK(int) tpmR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1481{
1482 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1483 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1484 RT_NOREF(uPass);
1485
1486 /* Save the part of the config used for verification purposes when restoring. */
1487 pHlp->pfnSSMPutGCPhys(pSSM, pThis->GCPhysMmio);
1488 pHlp->pfnSSMPutU16( pSSM, pThis->uVenId);
1489 pHlp->pfnSSMPutU16( pSSM, pThis->uDevId);
1490 pHlp->pfnSSMPutU8( pSSM, pThis->bRevId);
1491 pHlp->pfnSSMPutU8( pSSM, pThis->uIrq);
1492 pHlp->pfnSSMPutBool( pSSM, pThis->fLocChangeSup);
1493 pHlp->pfnSSMPutU32( pSSM, (uint32_t)pThis->enmTpmVers);
1494 pHlp->pfnSSMPutU32( pSSM, pThis->cbCmdResp);
1495
1496 return VINF_SSM_DONT_CALL_AGAIN;
1497}
1498
1499
1500/**
1501 * @callback_method_impl{FNSSMDEVSAVEEXEC}
1502 */
1503static DECLCALLBACK(int) tpmR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1504{
1505 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1506 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1507
1508 tpmR3LiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
1509
1510 int rc = pHlp->pfnSSMPutStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &g_aTpmFields[0], NULL);
1511 AssertRCReturn(rc, rc);
1512
1513 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX); /* sanity/terminator */
1514}
1515
1516
1517/**
1518 * @callback_method_impl{FNSSMDEVLOADEXEC}
1519 */
1520static DECLCALLBACK(int) tpmR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1521{
1522 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1523 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1524 uint8_t u8;
1525 uint16_t u16;
1526 uint32_t u32;
1527 bool f;
1528 RTGCPHYS GCPhysMmio;
1529 TPMVERSION enmTpmVers;
1530
1531 Assert(uPass == SSM_PASS_FINAL); RT_NOREF(uPass);
1532 AssertMsgReturn(uVersion == TPM_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1533
1534 /* Verify the config first. */
1535 int rc = pHlp->pfnSSMGetGCPhys(pSSM, &GCPhysMmio);
1536 AssertRCReturn(rc, rc);
1537 if (GCPhysMmio != pThis->GCPhysMmio)
1538 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1539 N_("Config mismatch - saved GCPhysMmio=%#RGp; configured GCPhysMmio=%#RGp"),
1540 GCPhysMmio, pThis->GCPhysMmio);
1541
1542 rc = pHlp->pfnSSMGetU16(pSSM, &u16);
1543 AssertRCReturn(rc, rc);
1544 if (u16 != pThis->uVenId)
1545 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1546 N_("Config mismatch - saved uVenId=%#RX16; configured uVenId=%#RX16"),
1547 u16, pThis->uVenId);
1548
1549 rc = pHlp->pfnSSMGetU16(pSSM, &u16);
1550 AssertRCReturn(rc, rc);
1551 if (u16 != pThis->uDevId)
1552 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1553 N_("Config mismatch - saved uDevId=%#RX16; configured uDevId=%#RX16"),
1554 u16, pThis->uDevId);
1555
1556 rc = pHlp->pfnSSMGetU8(pSSM, &u8);
1557 AssertRCReturn(rc, rc);
1558 if (u8 != pThis->bRevId)
1559 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1560 N_("Config mismatch - saved bRevId=%#RX8; configured bDevId=%#RX8"),
1561 u8, pThis->bRevId);
1562
1563 rc = pHlp->pfnSSMGetU8(pSSM, &u8);
1564 AssertRCReturn(rc, rc);
1565 if (u8 != pThis->uIrq)
1566 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1567 N_("Config mismatch - saved uIrq=%#RX8; configured uIrq=%#RX8"),
1568 u8, pThis->uIrq);
1569
1570 rc = pHlp->pfnSSMGetBool(pSSM, &f);
1571 AssertRCReturn(rc, rc);
1572 if (f != pThis->fLocChangeSup)
1573 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1574 N_("Config mismatch - saved fLocChangeSup=%RTbool; configured fLocChangeSup=%RTbool"),
1575 f, pThis->fLocChangeSup);
1576
1577 rc = pHlp->pfnSSMGetU32(pSSM, (uint32_t *)&enmTpmVers);
1578 AssertRCReturn(rc, rc);
1579 if (enmTpmVers != pThis->enmTpmVers)
1580 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1581 N_("Config mismatch - saved enmTpmVers=%RU32; configured enmTpmVers=%RU32"),
1582 enmTpmVers, pThis->enmTpmVers);
1583
1584 rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1585 AssertRCReturn(rc, rc);
1586 if (u32 != pThis->cbCmdResp)
1587 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS,
1588 N_("Config mismatch - saved cbCmdResp=%RU32; configured cbCmdResp=%RU32"),
1589 u32, pThis->cbCmdResp);
1590
1591 if (uPass == SSM_PASS_FINAL)
1592 {
1593 rc = pHlp->pfnSSMGetStructEx(pSSM, pThis, sizeof(*pThis), 0 /*fFlags*/, &g_aTpmFields[0], NULL);
1594
1595 /* The marker. */
1596 rc = pHlp->pfnSSMGetU32(pSSM, &u32);
1597 AssertRCReturn(rc, rc);
1598 AssertMsgReturn(u32 == UINT32_MAX, ("%#x\n", u32), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1599
1600 /* Verify device state sanity. */
1601 AssertLogRelMsgReturn( pThis->enmState > DEVTPMSTATE_INVALID
1602 && pThis->enmState <= DEVTPMSTATE_LAST_VALID,
1603 ("Invalid TPM state loaded from saved state: %#x\n", pThis->enmState),
1604 VERR_SSM_UNEXPECTED_DATA);
1605
1606 AssertLogRelMsgReturn(pThis->offCmdResp <= pThis->cbCmdResp,
1607 ("Invalid TPM command/response buffer offset loaded from saved state: %#x\n", pThis->offCmdResp),
1608 VERR_SSM_UNEXPECTED_DATA);
1609 }
1610
1611 return VINF_SUCCESS;
1612}
1613
1614
1615/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1616
1617/**
1618 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1619 */
1620static DECLCALLBACK(void *) tpmR3QueryInterface(PPDMIBASE pInterface, const char *pszIID)
1621{
1622 PDEVTPMCC pThisCC = RT_FROM_MEMBER(pInterface, DEVTPMCC, IBase);
1623 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
1624 //PDMIBASE_RETURN_INTERFACE(pszIID, PDMITPMPORT, &pThisCC->ITpmPort);
1625 return NULL;
1626}
1627
1628
1629/* -=-=-=-=-=-=-=-=- PDMDEVREG -=-=-=-=-=-=-=-=- */
1630
1631/**
1632 * @interface_method_impl{PDMDEVREG,pfnPowerOn}
1633 */
1634static DECLCALLBACK(void) tpmR3PowerOn(PPDMDEVINS pDevIns)
1635{
1636 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1637 PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
1638
1639 if (pThisCC->pDrvTpm)
1640 pThis->fEstablishmentSet = pThisCC->pDrvTpm->pfnGetEstablishedFlag(pThisCC->pDrvTpm);
1641}
1642
1643
1644/**
1645 * @interface_method_impl{PDMDEVREG,pfnReset}
1646 */
1647static DECLCALLBACK(void) tpmR3Reset(PPDMDEVINS pDevIns)
1648{
1649 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1650 PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
1651
1652 tpmR3HwReset(pThis);
1653 if (pThisCC->pDrvTpm)
1654 pThis->fEstablishmentSet = pThisCC->pDrvTpm->pfnGetEstablishedFlag(pThisCC->pDrvTpm);
1655}
1656
1657
1658/**
1659 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1660 */
1661static DECLCALLBACK(int) tpmR3Destruct(PPDMDEVINS pDevIns)
1662{
1663 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
1664 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1665
1666 /** @todo */
1667 RT_NOREF(pThis);
1668 return VINF_SUCCESS;
1669}
1670
1671
1672/**
1673 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1674 */
1675static DECLCALLBACK(int) tpmR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1676{
1677 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1678 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1679 PDEVTPMCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDEVTPMCC);
1680 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1681 int rc;
1682
1683 RT_NOREF(iInstance);
1684
1685 pThis->hTpmCmdTask = NIL_PDMTASKHANDLE;
1686
1687 pThisCC->pDevIns = pDevIns;
1688
1689 /* IBase */
1690 pThisCC->IBase.pfnQueryInterface = tpmR3QueryInterface;
1691
1692 /*
1693 * Validate and read the configuration.
1694 */
1695 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Irq"
1696 "|MmioBase"
1697 "|VendorId"
1698 "|DeviceId"
1699 "|RevisionId"
1700 "|Crb",
1701 "");
1702
1703 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Irq", &pThis->uIrq, 10);
1704 if (RT_FAILURE(rc))
1705 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Irq\" value"));
1706
1707 rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioBase", &pThis->GCPhysMmio, TPM_MMIO_BASE_DEFAULT);
1708 if (RT_FAILURE(rc))
1709 return PDMDEV_SET_ERROR(pDevIns, rc,
1710 N_("Configuration error: Failed to get the \"MmioBase\" value"));
1711
1712 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "VendorId", &pThis->uDevId, TPM_VID_DEFAULT);
1713 if (RT_FAILURE(rc))
1714 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"VendorId\" value"));
1715
1716 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "DeviceId", &pThis->uDevId, TPM_DID_DEFAULT);
1717 if (RT_FAILURE(rc))
1718 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"DeviceId\" value"));
1719
1720 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "RevisionId", &pThis->bRevId, TPM_RID_DEFAULT);
1721 if (RT_FAILURE(rc))
1722 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"RevisionId\" value"));
1723
1724 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Crb", &pThis->fCrb, false);
1725 if (RT_FAILURE(rc))
1726 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"Crb\" value"));
1727
1728 /*
1729 * Register the MMIO range, PDM API requests page aligned
1730 * addresses and sizes.
1731 */
1732 rc = PDMDevHlpMmioCreateAndMap(pDevIns, pThis->GCPhysMmio, TPM_MMIO_SIZE, tpmMmioWrite, tpmMmioRead,
1733 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
1734 "TPM MMIO", &pThis->hMmio);
1735 AssertRCReturn(rc, rc);
1736
1737 /*
1738 * Attach any TPM driver below.
1739 */
1740 rc = PDMDevHlpDriverAttach(pDevIns, 0 /*iLUN*/, &pThisCC->IBase, &pThisCC->pDrvBase, "TPM");
1741 if (RT_SUCCESS(rc))
1742 {
1743 pThisCC->pDrvTpm = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMITPMCONNECTOR);
1744 AssertLogRelMsgReturn(pThisCC->pDrvTpm, ("TPM#%d: Driver is missing the TPM interface.\n", iInstance), VERR_PDM_MISSING_INTERFACE);
1745
1746 pThis->cbCmdResp = RT_MIN(pThisCC->pDrvTpm->pfnGetBufferSize(pThisCC->pDrvTpm), TPM_DATA_BUFFER_SIZE_MAX);
1747 pThis->fLocChangeSup = pThisCC->pDrvTpm->pfnGetLocalityMax(pThisCC->pDrvTpm) > 0;
1748
1749 pThis->enmTpmVers = pThisCC->pDrvTpm->pfnGetVersion(pThisCC->pDrvTpm);
1750 if (pThis->enmTpmVers == TPMVERSION_UNKNOWN)
1751 return PDMDEV_SET_ERROR(pDevIns, VERR_NOT_SUPPORTED, N_("The emulated TPM version is not supported"));
1752 }
1753 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1754 {
1755 pThis->fLocChangeSup = false;
1756 pThis->fEstablishmentSet = false;
1757 pThis->cbCmdResp = TPM_DATA_BUFFER_SIZE_MAX;
1758
1759 pThisCC->pDrvBase = NULL;
1760 pThisCC->pDrvTpm = NULL;
1761 LogRel(("TPM#%d: no unit\n", iInstance));
1762 }
1763 else
1764 AssertLogRelMsgRCReturn(rc, ("TPM#%d: Failed to attach to TPM driver. rc=%Rrc\n", iInstance, rc), rc);
1765
1766 /* Create task for executing requests in ring-3. */
1767 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "TPMCmdWrk",
1768 tpmR3CmdExecWorker, NULL /*pvUser*/, &pThis->hTpmCmdTask);
1769 AssertRCReturn(rc,rc);
1770
1771 /*
1772 * Saved state.
1773 */
1774 rc = PDMDevHlpSSMRegister3(pDevIns, TPM_SAVED_STATE_VERSION, sizeof(*pThis),
1775 tpmR3LiveExec, tpmR3SaveExec, tpmR3LoadExec);
1776 AssertRCReturn(rc, rc);
1777
1778 tpmR3HwReset(pThis);
1779 return VINF_SUCCESS;
1780}
1781
1782#else /* !IN_RING3 */
1783
1784/**
1785 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1786 */
1787static DECLCALLBACK(int) tpmRZConstruct(PPDMDEVINS pDevIns)
1788{
1789 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1790 PDEVTPM pThis = PDMDEVINS_2_DATA(pDevIns, PDEVTPM);
1791
1792 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, tpmMmioWrite, tpmMmioRead, NULL /*pvUser*/);
1793 AssertRCReturn(rc, rc);
1794
1795 return VINF_SUCCESS;
1796}
1797
1798#endif /* !IN_RING3 */
1799
1800/**
1801 * The device registration structure.
1802 */
1803const PDMDEVREG g_DeviceTpm =
1804{
1805 /* .u32Version = */ PDM_DEVREG_VERSION,
1806 /* .uReserved0 = */ 0,
1807 /* .szName = */ "tpm",
1808 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
1809 /* .fClass = */ PDM_DEVREG_CLASS_SERIAL,
1810 /* .cMaxInstances = */ 1,
1811 /* .uSharedVersion = */ 42,
1812 /* .cbInstanceShared = */ sizeof(DEVTPM),
1813 /* .cbInstanceCC = */ sizeof(DEVTPMCC),
1814 /* .cbInstanceRC = */ sizeof(DEVTPMRC),
1815 /* .cMaxPciDevices = */ 0,
1816 /* .cMaxMsixVectors = */ 0,
1817 /* .pszDescription = */ "Trusted Platform Module",
1818#if defined(IN_RING3)
1819 /* .pszRCMod = */ "VBoxDDRC.rc",
1820 /* .pszR0Mod = */ "VBoxDDR0.r0",
1821 /* .pfnConstruct = */ tpmR3Construct,
1822 /* .pfnDestruct = */ tpmR3Destruct,
1823 /* .pfnRelocate = */ NULL,
1824 /* .pfnMemSetup = */ NULL,
1825 /* .pfnPowerOn = */ tpmR3PowerOn,
1826 /* .pfnReset = */ tpmR3Reset,
1827 /* .pfnSuspend = */ NULL,
1828 /* .pfnResume = */ NULL,
1829 /* .pfnAttach = */ NULL,
1830 /* .pfnDetach = */ NULL,
1831 /* .pfnQueryInterface = */ NULL,
1832 /* .pfnInitComplete = */ NULL,
1833 /* .pfnPowerOff = */ NULL,
1834 /* .pfnSoftReset = */ NULL,
1835 /* .pfnReserved0 = */ NULL,
1836 /* .pfnReserved1 = */ NULL,
1837 /* .pfnReserved2 = */ NULL,
1838 /* .pfnReserved3 = */ NULL,
1839 /* .pfnReserved4 = */ NULL,
1840 /* .pfnReserved5 = */ NULL,
1841 /* .pfnReserved6 = */ NULL,
1842 /* .pfnReserved7 = */ NULL,
1843#elif defined(IN_RING0)
1844 /* .pfnEarlyConstruct = */ NULL,
1845 /* .pfnConstruct = */ tpmRZConstruct,
1846 /* .pfnDestruct = */ NULL,
1847 /* .pfnFinalDestruct = */ NULL,
1848 /* .pfnRequest = */ NULL,
1849 /* .pfnReserved0 = */ NULL,
1850 /* .pfnReserved1 = */ NULL,
1851 /* .pfnReserved2 = */ NULL,
1852 /* .pfnReserved3 = */ NULL,
1853 /* .pfnReserved4 = */ NULL,
1854 /* .pfnReserved5 = */ NULL,
1855 /* .pfnReserved6 = */ NULL,
1856 /* .pfnReserved7 = */ NULL,
1857#elif defined(IN_RC)
1858 /* .pfnConstruct = */ tpmRZConstruct,
1859 /* .pfnReserved0 = */ NULL,
1860 /* .pfnReserved1 = */ NULL,
1861 /* .pfnReserved2 = */ NULL,
1862 /* .pfnReserved3 = */ NULL,
1863 /* .pfnReserved4 = */ NULL,
1864 /* .pfnReserved5 = */ NULL,
1865 /* .pfnReserved6 = */ NULL,
1866 /* .pfnReserved7 = */ NULL,
1867#else
1868# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1869#endif
1870 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
1871};
1872
1873#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1874
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