VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevPit-i8254.cpp@ 40754

Last change on this file since 40754 was 40280, checked in by vboxsync, 12 years ago

Corrected a bunch of HC and GC uses in status codes.
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File size: 44.8 KB
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1/* $Id: DevPit-i8254.cpp 40280 2012-02-28 19:47:00Z vboxsync $ */
2/** @file
3 * DevPIT-i8254 - Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * QEMU 8253/8254 interval timer emulation
21 *
22 * Copyright (c) 2003-2004 Fabrice Bellard
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43/*******************************************************************************
44* Header Files *
45*******************************************************************************/
46#define LOG_GROUP LOG_GROUP_DEV_PIT
47#include <VBox/vmm/pdmdev.h>
48#include <VBox/log.h>
49#include <VBox/vmm/stam.h>
50#include <iprt/assert.h>
51#include <iprt/asm-math.h>
52
53#ifdef IN_RING3
54# include <iprt/alloc.h>
55# include <iprt/string.h>
56# include <iprt/uuid.h>
57#endif /* IN_RING3 */
58
59#include "VBoxDD.h"
60
61
62/*******************************************************************************
63* Defined Constants And Macros *
64*******************************************************************************/
65/** The PIT frequency. */
66#define PIT_FREQ 1193182
67
68#define RW_STATE_LSB 1
69#define RW_STATE_MSB 2
70#define RW_STATE_WORD0 3
71#define RW_STATE_WORD1 4
72
73/** The current saved state version. */
74#define PIT_SAVED_STATE_VERSION 4
75/** The saved state version used by VirtualBox 3.1 and earlier.
76 * This did not include disable by HPET flag. */
77#define PIT_SAVED_STATE_VERSION_VBOX_31 3
78/** The saved state version used by VirtualBox 3.0 and earlier.
79 * This did not include the config part. */
80#define PIT_SAVED_STATE_VERSION_VBOX_30 2
81
82/** @def FAKE_REFRESH_CLOCK
83 * Define this to flip the 15usec refresh bit on every read.
84 * If not defined, it will be flipped correctly. */
85/* #define FAKE_REFRESH_CLOCK */
86#ifdef DOXYGEN_RUNNING
87# define FAKE_REFRESH_CLOCK
88#endif
89
90/** The effective counter mode - if bit 1 is set, bit 2 is ignored. */
91#define EFFECTIVE_MODE(x) ((x) & ~(((x) & 2) << 1))
92
93
94/**
95 * Acquires the PIT lock or returns.
96 */
97#define DEVPIT_LOCK_RETURN(a_pThis, a_rcBusy) \
98 do { \
99 int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
100 if (rcLock != VINF_SUCCESS) \
101 return rcLock; \
102 } while (0)
103
104/**
105 * Releases the PIT lock.
106 */
107#define DEVPIT_UNLOCK(a_pThis) \
108 do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
109
110
111/**
112 * Acquires the TM lock and PIT lock, returns on failure.
113 */
114#define DEVPIT_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
115 do { \
116 int rcLock = TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), (a_rcBusy)); \
117 if (rcLock != VINF_SUCCESS) \
118 return rcLock; \
119 rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
120 if (rcLock != VINF_SUCCESS) \
121 { \
122 TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
123 return rcLock; \
124 } \
125 } while (0)
126
127#if IN_RING3
128/**
129 * Acquires the TM lock and PIT lock, ignores failures.
130 */
131# define DEVPIT_R3_LOCK_BOTH(a_pThis) \
132 do { \
133 TMTimerLock((a_pThis)->channels[0].CTX_SUFF(pTimer), VERR_IGNORED); \
134 PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
135 } while (0)
136#endif /* IN_RING3 */
137
138/**
139 * Releases the PIT lock and TM lock.
140 */
141#define DEVPIT_UNLOCK_BOTH(a_pThis) \
142 do { \
143 PDMCritSectLeave(&(a_pThis)->CritSect); \
144 TMTimerUnlock((a_pThis)->channels[0].CTX_SUFF(pTimer)); \
145 } while (0)
146
147
148
149/*******************************************************************************
150* Structures and Typedefs *
151*******************************************************************************/
152typedef struct PITChannelState
153{
154 /** Pointer to the instance data - R3 Ptr. */
155 R3PTRTYPE(struct PITState *) pPitR3;
156 /** The timer - R3 Ptr. */
157 PTMTIMERR3 pTimerR3;
158 /** Pointer to the instance data - R0 Ptr. */
159 R0PTRTYPE(struct PITState *) pPitR0;
160 /** The timer - R0 Ptr. */
161 PTMTIMERR0 pTimerR0;
162 /** Pointer to the instance data - RC Ptr. */
163 RCPTRTYPE(struct PITState *) pPitRC;
164 /** The timer - RC Ptr. */
165 PTMTIMERRC pTimerRC;
166 /** The virtual time stamp at the last reload. (only used in mode 2 for now) */
167 uint64_t u64ReloadTS;
168 /** The actual time of the next tick.
169 * As apposed to the next_transition_time which contains the correct time of the next tick. */
170 uint64_t u64NextTS;
171
172 /** (count_load_time is only set by TMTimerGet() which returns uint64_t) */
173 uint64_t count_load_time;
174 /* irq handling */
175 int64_t next_transition_time;
176 int32_t irq;
177 /** Number of release log entries. Used to prevent flooding. */
178 uint32_t cRelLogEntries;
179
180 uint32_t count; /* can be 65536 */
181 uint16_t latched_count;
182 uint8_t count_latched;
183 uint8_t status_latched;
184
185 uint8_t status;
186 uint8_t read_state;
187 uint8_t write_state;
188 uint8_t write_latch;
189
190 uint8_t rw_mode;
191 uint8_t mode;
192 uint8_t bcd; /* not supported */
193 uint8_t gate; /* timer start */
194
195} PITChannelState;
196
197typedef struct PITState
198{
199 /** Channel state. Must come first? */
200 PITChannelState channels[3];
201 /** Speaker data. */
202 int32_t speaker_data_on;
203#ifdef FAKE_REFRESH_CLOCK
204 /** Speaker dummy. */
205 int32_t dummy_refresh_clock;
206#else
207 uint32_t Alignment1;
208#endif
209 /** Config: I/O port base. */
210 RTIOPORT IOPortBaseCfg;
211 /** Config: Speaker enabled. */
212 bool fSpeakerCfg;
213 bool fDisabledByHpet;
214 bool afAlignment0[HC_ARCH_BITS == 32 ? 4 : 4];
215 /** PIT port interface. */
216 PDMIHPETLEGACYNOTIFY IHpetLegacyNotify;
217 /** Pointer to the device instance. */
218 PPDMDEVINSR3 pDevIns;
219 /** Number of IRQs that's been raised. */
220 STAMCOUNTER StatPITIrq;
221 /** Profiling the timer callback handler. */
222 STAMPROFILEADV StatPITHandler;
223 /** Critical section protecting the state. */
224 PDMCRITSECT CritSect;
225} PITState;
226
227
228#ifndef VBOX_DEVICE_STRUCT_TESTCASE
229/*******************************************************************************
230* Internal Functions *
231*******************************************************************************/
232#ifdef IN_RING3
233static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now, bool in_timer);
234#endif
235
236
237
238static int pit_get_count(PITChannelState *s)
239{
240 uint64_t d;
241 int counter;
242 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
243 Assert(TMTimerIsLockOwner(pTimer));
244
245 if (EFFECTIVE_MODE(s->mode) == 2)
246 {
247 if (s->u64NextTS == UINT64_MAX)
248 {
249 d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
250 return s->count - (d % s->count); /** @todo check this value. */
251 }
252 uint64_t Interval = s->u64NextTS - s->u64ReloadTS;
253 if (!Interval)
254 return s->count - 1; /** @todo This is WRONG! But I'm too tired to fix it properly and just want to shut up a DIV/0 trap now. */
255 d = TMTimerGet(pTimer);
256 d = ASMMultU64ByU32DivByU32(d - s->u64ReloadTS, s->count, Interval);
257 if (d >= s->count)
258 return 1;
259 return s->count - d;
260 }
261 d = ASMMultU64ByU32DivByU32(TMTimerGet(pTimer) - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
262 switch(EFFECTIVE_MODE(s->mode)) {
263 case 0:
264 case 1:
265 case 4:
266 case 5:
267 counter = (s->count - d) & 0xffff;
268 break;
269 case 3:
270 /* XXX: may be incorrect for odd counts */
271 counter = s->count - ((2 * d) % s->count);
272 break;
273 default:
274 counter = s->count - (d % s->count);
275 break;
276 }
277 /** @todo check that we don't return 0, in most modes (all?) the counter shouldn't be zero. */
278 return counter;
279}
280
281/* get pit output bit */
282static int pit_get_out1(PITChannelState *s, int64_t current_time)
283{
284 uint64_t d;
285 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
286 int out;
287
288 d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
289 switch(EFFECTIVE_MODE(s->mode)) {
290 default:
291 case 0:
292 out = (d >= s->count);
293 break;
294 case 1:
295 out = (d < s->count);
296 break;
297 case 2:
298 Log2(("pit_get_out1: d=%llx c=%x %x \n", d, s->count, (unsigned)(d % s->count)));
299 if ((d % s->count) == 0 && d != 0)
300 out = 1;
301 else
302 out = 0;
303 break;
304 case 3:
305 out = (d % s->count) < ((s->count + 1) >> 1);
306 break;
307 case 4:
308 case 5:
309 out = (d != s->count);
310 break;
311 }
312 return out;
313}
314
315
316static int pit_get_out(PITState *pit, int channel, int64_t current_time)
317{
318 PITChannelState *s = &pit->channels[channel];
319 return pit_get_out1(s, current_time);
320}
321
322
323static int pit_get_gate(PITState *pit, int channel)
324{
325 PITChannelState *s = &pit->channels[channel];
326 return s->gate;
327}
328
329
330/* if already latched, do not latch again */
331static void pit_latch_count(PITChannelState *s)
332{
333 if (!s->count_latched) {
334 s->latched_count = pit_get_count(s);
335 s->count_latched = s->rw_mode;
336 LogFlow(("pit_latch_count: latched_count=%#06x / %10RU64 ns (c=%#06x m=%d)\n",
337 s->latched_count, ASMMultU64ByU32DivByU32(s->count - s->latched_count, 1000000000, PIT_FREQ), s->count, s->mode));
338 }
339}
340
341#ifdef IN_RING3
342
343/* val must be 0 or 1 */
344static void pit_set_gate(PITState *pit, int channel, int val)
345{
346 PITChannelState *s = &pit->channels[channel];
347 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
348 Assert((val & 1) == val);
349 Assert(TMTimerIsLockOwner(pTimer));
350
351 switch(EFFECTIVE_MODE(s->mode)) {
352 default:
353 case 0:
354 case 4:
355 /* XXX: just disable/enable counting */
356 break;
357 case 1:
358 case 5:
359 if (s->gate < val) {
360 /* restart counting on rising edge */
361 Log(("pit_set_gate: restarting mode %d\n", s->mode));
362 s->count_load_time = TMTimerGet(pTimer);
363 pit_irq_timer_update(s, s->count_load_time, s->count_load_time, false);
364 }
365 break;
366 case 2:
367 case 3:
368 if (s->gate < val) {
369 /* restart counting on rising edge */
370 Log(("pit_set_gate: restarting mode %d\n", s->mode));
371 s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
372 pit_irq_timer_update(s, s->count_load_time, s->count_load_time, false);
373 }
374 /* XXX: disable/enable counting */
375 break;
376 }
377 s->gate = val;
378}
379
380static void pit_load_count(PITChannelState *s, int val)
381{
382 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
383 Assert(TMTimerIsLockOwner(pTimer));
384
385 if (val == 0)
386 val = 0x10000;
387 s->count_load_time = s->u64ReloadTS = TMTimerGet(pTimer);
388 s->count = val;
389 pit_irq_timer_update(s, s->count_load_time, s->count_load_time, false);
390
391 /* log the new rate (ch 0 only). */
392 if (s->pTimerR3 /* ch 0 */)
393 {
394 if (s->cRelLogEntries++ < 32)
395 LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
396 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
397 else
398 Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=0)\n",
399 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100));
400 TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
401 }
402 else
403 Log(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d)\n",
404 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100,
405 s - &s->CTX_SUFF(pPit)->channels[0]));
406}
407
408/* return -1 if no transition will occur. */
409static int64_t pit_get_next_transition_time(PITChannelState *s,
410 uint64_t current_time)
411{
412 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
413 uint64_t d, next_time, base;
414 uint32_t period2;
415
416 d = ASMMultU64ByU32DivByU32(current_time - s->count_load_time, PIT_FREQ, TMTimerGetFreq(pTimer));
417 switch(EFFECTIVE_MODE(s->mode)) {
418 default:
419 case 0:
420 case 1:
421 if (d < s->count)
422 next_time = s->count;
423 else
424 return -1;
425 break;
426 /*
427 * Mode 2: The period is 'count' PIT ticks.
428 * When the counter reaches 1 we set the output low (for channel 0 that
429 * means lowering IRQ0). On the next tick, where we should be decrementing
430 * from 1 to 0, the count is loaded and the output goes high (channel 0
431 * means raising IRQ0 again and triggering timer interrupt).
432 *
433 * In VirtualBox we compress the pulse and flip-flop the IRQ line at the
434 * end of the period, which signals an interrupt at the exact same time.
435 */
436 case 2:
437 base = (d / s->count) * s->count;
438#ifndef VBOX /* see above */
439 if ((d - base) == 0 && d != 0)
440 next_time = base + s->count - 1;
441 else
442#endif
443 next_time = base + s->count;
444 break;
445 case 3:
446 base = (d / s->count) * s->count;
447 period2 = ((s->count + 1) >> 1);
448 if ((d - base) < period2)
449 next_time = base + period2;
450 else
451 next_time = base + s->count;
452 break;
453 /* Modes 4 and 5 generate a short pulse at the end of the time delay. This
454 * is similar to mode 2, except modes 4/5 aren't periodic. We use the same
455 * optimization - only use one timer callback and pulse the IRQ.
456 * Note: Tickless Linux kernels use PIT mode 4 with 'nolapic'.
457 */
458 case 4:
459 case 5:
460#ifdef VBOX
461 if (d <= s->count)
462 next_time = s->count;
463#else
464 if (d < s->count)
465 next_time = s->count;
466 else if (d == s->count)
467 next_time = s->count + 1;
468#endif
469 else
470 return -1;
471 break;
472 }
473 /* convert to timer units */
474 LogFlow(("PIT: next_time=%'14RU64 %'20RU64 mode=%#x count=%#06x\n", next_time,
475 ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ), s->mode, s->count));
476 next_time = s->count_load_time + ASMMultU64ByU32DivByU32(next_time, TMTimerGetFreq(pTimer), PIT_FREQ);
477 /* fix potential rounding problems */
478 if (next_time <= current_time)
479 next_time = current_time;
480 /* Add one to next_time; if we don't, integer truncation will cause
481 * the algorithm to think that at the end of each period, it's still
482 * within the first one instead of at the beginning of the next one.
483 */
484 return next_time + 1;
485}
486
487static void pit_irq_timer_update(PITChannelState *s, uint64_t current_time, uint64_t now, bool in_timer)
488{
489 int64_t expire_time;
490 int irq_level;
491 PPDMDEVINS pDevIns;
492 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
493 Assert(TMTimerIsLockOwner(pTimer));
494
495 if (!s->CTX_SUFF(pTimer))
496 return;
497 expire_time = pit_get_next_transition_time(s, current_time);
498 irq_level = pit_get_out1(s, current_time) ? PDM_IRQ_LEVEL_HIGH : PDM_IRQ_LEVEL_LOW;
499
500 /* If PIT is disabled by HPET - simply disconnect ticks from interrupt controllers,
501 * but do not modify other aspects of device operation.
502 */
503 if (!s->pPitR3->fDisabledByHpet)
504 {
505 pDevIns = s->CTX_SUFF(pPit)->pDevIns;
506
507 switch (EFFECTIVE_MODE(s->mode))
508 {
509 case 2:
510 case 4:
511 case 5:
512 /* We just flip-flop the IRQ line to save an extra timer call,
513 * which isn't generally required. However, the pulse is only
514 * generated when running on the timer callback (and thus on
515 * the trailing edge of the output signal pulse).
516 */
517 if (in_timer)
518 {
519 PDMDevHlpISASetIrq(pDevIns, s->irq, PDM_IRQ_LEVEL_FLIP_FLOP);
520 break;
521 }
522 /* Else fall through! */
523 default:
524 PDMDevHlpISASetIrq(pDevIns, s->irq, irq_level);
525 break;
526 }
527 }
528
529 if (irq_level)
530 {
531 s->u64ReloadTS = now;
532 STAM_COUNTER_INC(&s->CTX_SUFF(pPit)->StatPITIrq);
533 }
534
535 if (expire_time != -1)
536 {
537 Log3(("pit_irq_timer_update: next=%'RU64 now=%'RU64\n", expire_time, now));
538 s->u64NextTS = expire_time;
539 TMTimerSet(s->CTX_SUFF(pTimer), s->u64NextTS);
540 }
541 else
542 {
543 LogFlow(("PIT: m=%d count=%#4x irq_level=%#x stopped\n", s->mode, s->count, irq_level));
544 TMTimerStop(s->CTX_SUFF(pTimer));
545 s->u64NextTS = UINT64_MAX;
546 }
547 s->next_transition_time = expire_time;
548}
549
550#endif /* IN_RING3 */
551
552
553/**
554 * Port I/O Handler for IN operations.
555 *
556 * @returns VBox status code.
557 *
558 * @param pDevIns The device instance.
559 * @param pvUser User argument - ignored.
560 * @param Port Port number used for the IN operation.
561 * @param pu32 Where to store the result.
562 * @param cb Number of bytes read.
563 */
564PDMBOTHCBDECL(int) pitIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
565{
566 Log2(("pitIOPortRead: Port=%#x cb=%x\n", Port, cb));
567 NOREF(pvUser);
568 Port &= 3;
569 if (cb != 1 || Port == 3)
570 {
571 Log(("pitIOPortRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
572 return VERR_IOM_IOPORT_UNUSED;
573 }
574
575 PITState *pit = PDMINS_2_DATA(pDevIns, PITState *);
576 int ret;
577 PITChannelState *s = &pit->channels[Port];
578
579 DEVPIT_LOCK_RETURN(pit, VINF_IOM_R3_IOPORT_READ);
580 if (s->status_latched)
581 {
582 s->status_latched = 0;
583 ret = s->status;
584 DEVPIT_UNLOCK(pit);
585 }
586 else if (s->count_latched)
587 {
588 switch (s->count_latched)
589 {
590 default:
591 case RW_STATE_LSB:
592 ret = s->latched_count & 0xff;
593 s->count_latched = 0;
594 break;
595 case RW_STATE_MSB:
596 ret = s->latched_count >> 8;
597 s->count_latched = 0;
598 break;
599 case RW_STATE_WORD0:
600 ret = s->latched_count & 0xff;
601 s->count_latched = RW_STATE_MSB;
602 break;
603 }
604 DEVPIT_UNLOCK(pit);
605 }
606 else
607 {
608 DEVPIT_UNLOCK(pit);
609 DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_READ);
610 int count;
611 switch (s->read_state)
612 {
613 default:
614 case RW_STATE_LSB:
615 count = pit_get_count(s);
616 ret = count & 0xff;
617 break;
618 case RW_STATE_MSB:
619 count = pit_get_count(s);
620 ret = (count >> 8) & 0xff;
621 break;
622 case RW_STATE_WORD0:
623 count = pit_get_count(s);
624 ret = count & 0xff;
625 s->read_state = RW_STATE_WORD1;
626 break;
627 case RW_STATE_WORD1:
628 count = pit_get_count(s);
629 ret = (count >> 8) & 0xff;
630 s->read_state = RW_STATE_WORD0;
631 break;
632 }
633 DEVPIT_UNLOCK_BOTH(pit);
634 }
635
636 *pu32 = ret;
637 Log2(("pitIOPortRead: Port=%#x cb=%x *pu32=%#04x\n", Port, cb, *pu32));
638 return VINF_SUCCESS;
639}
640
641
642/**
643 * Port I/O Handler for OUT operations.
644 *
645 * @returns VBox status code.
646 *
647 * @param pDevIns The device instance.
648 * @param pvUser User argument - ignored.
649 * @param Port Port number used for the IN operation.
650 * @param u32 The value to output.
651 * @param cb The value size in bytes.
652 */
653PDMBOTHCBDECL(int) pitIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
654{
655 Log2(("pitIOPortWrite: Port=%#x cb=%x u32=%#04x\n", Port, cb, u32));
656 NOREF(pvUser);
657 if (cb != 1)
658 return VINF_SUCCESS;
659
660 PITState *pit = PDMINS_2_DATA(pDevIns, PITState *);
661 Port &= 3;
662 if (Port == 3)
663 {
664 /*
665 * Port 43h - Mode/Command Register.
666 * 7 6 5 4 3 2 1 0
667 * * * . . . . . . Select channel: 0 0 = Channel 0
668 * 0 1 = Channel 1
669 * 1 0 = Channel 2
670 * 1 1 = Read-back command (8254 only)
671 * (Illegal on 8253)
672 * (Illegal on PS/2 {JAM})
673 * . . * * . . . . Command/Access mode: 0 0 = Latch count value command
674 * 0 1 = Access mode: lobyte only
675 * 1 0 = Access mode: hibyte only
676 * 1 1 = Access mode: lobyte/hibyte
677 * . . . . * * * . Operating mode: 0 0 0 = Mode 0, 0 0 1 = Mode 1,
678 * 0 1 0 = Mode 2, 0 1 1 = Mode 3,
679 * 1 0 0 = Mode 4, 1 0 1 = Mode 5,
680 * 1 1 0 = Mode 2, 1 1 1 = Mode 3
681 * . . . . . . . * BCD/Binary mode: 0 = 16-bit binary, 1 = four-digit BCD
682 */
683 unsigned channel = u32 >> 6;
684 if (channel == 3)
685 {
686 /* read-back command */
687 DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
688 for (channel = 0; channel < RT_ELEMENTS(pit->channels); channel++)
689 {
690 PITChannelState *s = &pit->channels[channel];
691 if (u32 & (2 << channel)) {
692 if (!(u32 & 0x20))
693 pit_latch_count(s);
694 if (!(u32 & 0x10) && !s->status_latched)
695 {
696 /* status latch */
697 /* XXX: add BCD and null count */
698 PTMTIMER pTimer = s->CTX_SUFF(pPit)->channels[0].CTX_SUFF(pTimer);
699 s->status = (pit_get_out1(s, TMTimerGet(pTimer)) << 7)
700 | (s->rw_mode << 4)
701 | (s->mode << 1)
702 | s->bcd;
703 s->status_latched = 1;
704 }
705 }
706 }
707 DEVPIT_UNLOCK_BOTH(pit);
708 }
709 else
710 {
711 PITChannelState *s = &pit->channels[channel];
712 unsigned access = (u32 >> 4) & 3;
713 if (access == 0)
714 {
715 DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
716 pit_latch_count(s);
717 DEVPIT_UNLOCK_BOTH(pit);
718 }
719 else
720 {
721 DEVPIT_LOCK_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
722 s->rw_mode = access;
723 s->read_state = access;
724 s->write_state = access;
725
726 s->mode = (u32 >> 1) & 7;
727 s->bcd = u32 & 1;
728 /* XXX: update irq timer ? */
729 DEVPIT_UNLOCK(pit);
730 }
731 }
732 }
733 else
734 {
735#ifndef IN_RING3
736 /** @todo There is no reason not to do this in all contexts these
737 * days... */
738 return VINF_IOM_R3_IOPORT_WRITE;
739#else /* IN_RING3 */
740 /*
741 * Port 40-42h - Channel Data Ports.
742 */
743 PITChannelState *s = &pit->channels[Port];
744 uint8_t const write_state = s->write_state;
745 DEVPIT_LOCK_BOTH_RETURN(pit, VINF_IOM_R3_IOPORT_WRITE);
746 switch (s->write_state)
747 {
748 default:
749 case RW_STATE_LSB:
750 pit_load_count(s, u32);
751 break;
752 case RW_STATE_MSB:
753 pit_load_count(s, u32 << 8);
754 break;
755 case RW_STATE_WORD0:
756 s->write_latch = u32;
757 s->write_state = RW_STATE_WORD1;
758 break;
759 case RW_STATE_WORD1:
760 pit_load_count(s, s->write_latch | (u32 << 8));
761 s->write_state = RW_STATE_WORD0;
762 break;
763 }
764 DEVPIT_UNLOCK_BOTH(pit);
765#endif /* !IN_RING3 */
766 }
767 return VINF_SUCCESS;
768}
769
770
771/**
772 * Port I/O Handler for speaker IN operations.
773 *
774 * @returns VBox status code.
775 *
776 * @param pDevIns The device instance.
777 * @param pvUser User argument - ignored.
778 * @param Port Port number used for the IN operation.
779 * @param pu32 Where to store the result.
780 * @param cb Number of bytes read.
781 */
782PDMBOTHCBDECL(int) pitIOPortSpeakerRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
783{
784 NOREF(pvUser);
785 if (cb == 1)
786 {
787 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
788 DEVPIT_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_IOPORT_READ);
789
790 const uint64_t u64Now = TMTimerGet(pThis->channels[0].CTX_SUFF(pTimer));
791 Assert(TMTimerGetFreq(pThis->channels[0].CTX_SUFF(pTimer)) == 1000000000); /* lazy bird. */
792
793 /* bit 6,7 Parity error stuff. */
794 /* bit 5 - mirrors timer 2 output condition. */
795 const int fOut = pit_get_out(pThis, 2, u64Now);
796 /* bit 4 - toggled with each (DRAM?) refresh request, every 15.085 µs.
797 ASSUMES ns timer freq, see assertion above. */
798#ifndef FAKE_REFRESH_CLOCK
799 const int fRefresh = (u64Now / 15085) & 1;
800#else
801 pThis->dummy_refresh_clock ^= 1;
802 const int fRefresh = pThis->dummy_refresh_clock;
803#endif
804 /* bit 2,3 NMI / parity status stuff. */
805 /* bit 1 - speaker data status */
806 const int fSpeakerStatus = pThis->speaker_data_on;
807 /* bit 0 - timer 2 clock gate to speaker status. */
808 const int fTimer2GateStatus = pit_get_gate(pThis, 2);
809
810 DEVPIT_UNLOCK_BOTH(pThis);
811
812 *pu32 = fTimer2GateStatus
813 | (fSpeakerStatus << 1)
814 | (fRefresh << 4)
815 | (fOut << 5);
816 Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=%#x\n", Port, cb, *pu32));
817 return VINF_SUCCESS;
818 }
819 Log(("pitIOPortSpeakerRead: Port=%#x cb=%x *pu32=unused!\n", Port, cb));
820 return VERR_IOM_IOPORT_UNUSED;
821}
822
823#ifdef IN_RING3
824
825/**
826 * Port I/O Handler for speaker OUT operations.
827 *
828 * @returns VBox status code.
829 *
830 * @param pDevIns The device instance.
831 * @param pvUser User argument - ignored.
832 * @param Port Port number used for the IN operation.
833 * @param u32 The value to output.
834 * @param cb The value size in bytes.
835 */
836PDMBOTHCBDECL(int) pitIOPortSpeakerWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
837{
838 NOREF(pvUser);
839 if (cb == 1)
840 {
841 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
842 DEVPIT_LOCK_BOTH_RETURN(pThis, VERR_IGNORED);
843
844 pThis->speaker_data_on = (u32 >> 1) & 1;
845 pit_set_gate(pThis, 2, u32 & 1);
846
847 DEVPIT_UNLOCK_BOTH(pThis);
848 }
849 Log(("pitIOPortSpeakerWrite: Port=%#x cb=%x u32=%#x\n", Port, cb, u32));
850 return VINF_SUCCESS;
851}
852
853
854/**
855 * @copydoc FNSSMDEVLIVEEXEC
856 */
857static DECLCALLBACK(int) pitLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
858{
859 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
860 SSMR3PutIOPort(pSSM, pThis->IOPortBaseCfg);
861 SSMR3PutU8( pSSM, pThis->channels[0].irq);
862 SSMR3PutBool( pSSM, pThis->fSpeakerCfg);
863 return VINF_SSM_DONT_CALL_AGAIN;
864}
865
866
867/**
868 * @copydoc FNSSMDEVSAVEEXEC
869 */
870static DECLCALLBACK(int) pitSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
871{
872 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
873 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
874
875 /* The config. */
876 pitLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
877
878 /* The state. */
879 for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
880 {
881 PITChannelState *s = &pThis->channels[i];
882 SSMR3PutU32(pSSM, s->count);
883 SSMR3PutU16(pSSM, s->latched_count);
884 SSMR3PutU8(pSSM, s->count_latched);
885 SSMR3PutU8(pSSM, s->status_latched);
886 SSMR3PutU8(pSSM, s->status);
887 SSMR3PutU8(pSSM, s->read_state);
888 SSMR3PutU8(pSSM, s->write_state);
889 SSMR3PutU8(pSSM, s->write_latch);
890 SSMR3PutU8(pSSM, s->rw_mode);
891 SSMR3PutU8(pSSM, s->mode);
892 SSMR3PutU8(pSSM, s->bcd);
893 SSMR3PutU8(pSSM, s->gate);
894 SSMR3PutU64(pSSM, s->count_load_time);
895 SSMR3PutU64(pSSM, s->u64NextTS);
896 SSMR3PutU64(pSSM, s->u64ReloadTS);
897 SSMR3PutS64(pSSM, s->next_transition_time);
898 if (s->CTX_SUFF(pTimer))
899 TMR3TimerSave(s->CTX_SUFF(pTimer), pSSM);
900 }
901
902 SSMR3PutS32(pSSM, pThis->speaker_data_on);
903#ifdef FAKE_REFRESH_CLOCK
904 SSMR3PutS32(pSSM, pThis->dummy_refresh_clock);
905#else
906 SSMR3PutS32(pSSM, 0);
907#endif
908
909 SSMR3PutBool(pSSM, pThis->fDisabledByHpet);
910
911 PDMCritSectLeave(&pThis->CritSect);
912 return VINF_SUCCESS;
913}
914
915
916/**
917 * @copydoc FNSSMDEVLOADEXEC
918 */
919static DECLCALLBACK(int) pitLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
920{
921 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
922 int rc;
923
924 if ( uVersion != PIT_SAVED_STATE_VERSION
925 && uVersion != PIT_SAVED_STATE_VERSION_VBOX_30
926 && uVersion != PIT_SAVED_STATE_VERSION_VBOX_31)
927 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
928
929 /* The config. */
930 if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_30)
931 {
932 RTIOPORT IOPortBaseCfg;
933 rc = SSMR3GetIOPort(pSSM, &IOPortBaseCfg); AssertRCReturn(rc, rc);
934 if (IOPortBaseCfg != pThis->IOPortBaseCfg)
935 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - IOPortBaseCfg: saved=%RTiop config=%RTiop"),
936 IOPortBaseCfg, pThis->IOPortBaseCfg);
937
938 uint8_t u8Irq;
939 rc = SSMR3GetU8(pSSM, &u8Irq); AssertRCReturn(rc, rc);
940 if (u8Irq != pThis->channels[0].irq)
941 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - u8Irq: saved=%#x config=%#x"),
942 u8Irq, pThis->channels[0].irq);
943
944 bool fSpeakerCfg;
945 rc = SSMR3GetBool(pSSM, &fSpeakerCfg); AssertRCReturn(rc, rc);
946 if (fSpeakerCfg != pThis->fSpeakerCfg)
947 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fSpeakerCfg: saved=%RTbool config=%RTbool"),
948 fSpeakerCfg, pThis->fSpeakerCfg);
949 }
950
951 if (uPass != SSM_PASS_FINAL)
952 return VINF_SUCCESS;
953
954 /* The state. */
955 for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
956 {
957 PITChannelState *s = &pThis->channels[i];
958 SSMR3GetU32(pSSM, &s->count);
959 SSMR3GetU16(pSSM, &s->latched_count);
960 SSMR3GetU8(pSSM, &s->count_latched);
961 SSMR3GetU8(pSSM, &s->status_latched);
962 SSMR3GetU8(pSSM, &s->status);
963 SSMR3GetU8(pSSM, &s->read_state);
964 SSMR3GetU8(pSSM, &s->write_state);
965 SSMR3GetU8(pSSM, &s->write_latch);
966 SSMR3GetU8(pSSM, &s->rw_mode);
967 SSMR3GetU8(pSSM, &s->mode);
968 SSMR3GetU8(pSSM, &s->bcd);
969 SSMR3GetU8(pSSM, &s->gate);
970 SSMR3GetU64(pSSM, &s->count_load_time);
971 SSMR3GetU64(pSSM, &s->u64NextTS);
972 SSMR3GetU64(pSSM, &s->u64ReloadTS);
973 SSMR3GetS64(pSSM, &s->next_transition_time);
974 if (s->CTX_SUFF(pTimer))
975 {
976 TMR3TimerLoad(s->CTX_SUFF(pTimer), pSSM);
977 LogRel(("PIT: mode=%d count=%#x (%u) - %d.%02d Hz (ch=%d) (restore)\n",
978 s->mode, s->count, s->count, PIT_FREQ / s->count, (PIT_FREQ * 100 / s->count) % 100, i));
979 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
980 TMTimerSetFrequencyHint(s->CTX_SUFF(pTimer), PIT_FREQ / s->count);
981 PDMCritSectLeave(&pThis->CritSect);
982 }
983 pThis->channels[i].cRelLogEntries = 0;
984 }
985
986 SSMR3GetS32(pSSM, &pThis->speaker_data_on);
987#ifdef FAKE_REFRESH_CLOCK
988 SSMR3GetS32(pSSM, &pThis->dummy_refresh_clock);
989#else
990 int32_t u32Dummy;
991 SSMR3GetS32(pSSM, &u32Dummy);
992#endif
993 if (uVersion > PIT_SAVED_STATE_VERSION_VBOX_31)
994 SSMR3GetBool(pSSM, &pThis->fDisabledByHpet);
995
996 return VINF_SUCCESS;
997}
998
999
1000/**
1001 * Device timer callback function.
1002 *
1003 * @param pDevIns Device instance of the device which registered the timer.
1004 * @param pTimer The timer handle.
1005 * @param pvUser Pointer to the PIT channel state.
1006 */
1007static DECLCALLBACK(void) pitTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1008{
1009 PITChannelState *s = (PITChannelState *)pvUser;
1010 STAM_PROFILE_ADV_START(&s->CTX_SUFF(pPit)->StatPITHandler, a);
1011
1012 Log(("pitTimer\n"));
1013 Assert(PDMCritSectIsOwner(&PDMINS_2_DATA(pDevIns, PITState *)->CritSect));
1014 Assert(TMTimerIsLockOwner(pTimer));
1015
1016 pit_irq_timer_update(s, s->next_transition_time, TMTimerGet(pTimer), true);
1017
1018 STAM_PROFILE_ADV_STOP(&s->CTX_SUFF(pPit)->StatPITHandler, a);
1019}
1020
1021
1022/**
1023 * Info handler, device version.
1024 *
1025 * @param pDevIns Device instance which registered the info.
1026 * @param pHlp Callback functions for doing output.
1027 * @param pszArgs Argument string. Optional and specific to the handler.
1028 */
1029static DECLCALLBACK(void) pitInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1030{
1031 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
1032 unsigned i;
1033 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1034 {
1035 const PITChannelState *pCh = &pThis->channels[i];
1036
1037 pHlp->pfnPrintf(pHlp,
1038 "PIT (i8254) channel %d status: irq=%#x\n"
1039 " count=%08x" " latched_count=%04x count_latched=%02x\n"
1040 " status=%02x status_latched=%02x read_state=%02x\n"
1041 " write_state=%02x write_latch=%02x rw_mode=%02x\n"
1042 " mode=%02x bcd=%02x gate=%02x\n"
1043 " count_load_time=%016RX64 next_transition_time=%016RX64\n"
1044 " u64ReloadTS=%016RX64 u64NextTS=%016RX64\n"
1045 ,
1046 i, pCh->irq,
1047 pCh->count, pCh->latched_count, pCh->count_latched,
1048 pCh->status, pCh->status_latched, pCh->read_state,
1049 pCh->write_state, pCh->write_latch, pCh->rw_mode,
1050 pCh->mode, pCh->bcd, pCh->gate,
1051 pCh->count_load_time, pCh->next_transition_time,
1052 pCh->u64ReloadTS, pCh->u64NextTS);
1053 }
1054#ifdef FAKE_REFRESH_CLOCK
1055 pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x dummy_refresh_clock=%#x\n",
1056 pThis->speaker_data_on, pThis->dummy_refresh_clock);
1057#else
1058 pHlp->pfnPrintf(pHlp, "speaker_data_on=%#x\n", pThis->speaker_data_on);
1059#endif
1060 if (pThis->fDisabledByHpet)
1061 pHlp->pfnPrintf(pHlp, "Disabled by HPET\n");
1062}
1063
1064
1065/**
1066 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
1067 */
1068static DECLCALLBACK(void *) pitQueryInterface(PPDMIBASE pInterface, const char *pszIID)
1069{
1070 PPDMDEVINS pDevIns = RT_FROM_MEMBER(pInterface, PDMDEVINS, IBase);
1071 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
1072 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pDevIns->IBase);
1073 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIHPETLEGACYNOTIFY, &pThis->IHpetLegacyNotify);
1074 return NULL;
1075}
1076
1077
1078/**
1079 * @interface_method_impl{PDMIHPETLEGACYNOTIFY,pfnModeChanged}
1080 */
1081static DECLCALLBACK(void) pitNotifyHpetLegacyNotify_ModeChanged(PPDMIHPETLEGACYNOTIFY pInterface, bool fActivated)
1082{
1083 PITState *pThis = RT_FROM_MEMBER(pInterface, PITState, IHpetLegacyNotify);
1084 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1085
1086 pThis->fDisabledByHpet = fActivated;
1087
1088 PDMCritSectLeave(&pThis->CritSect);
1089}
1090
1091
1092/**
1093 * Relocation notification.
1094 *
1095 * @returns VBox status.
1096 * @param pDevIns The device instance data.
1097 * @param offDelta The delta relative to the old address.
1098 */
1099static DECLCALLBACK(void) pitRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1100{
1101 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
1102 LogFlow(("pitRelocate: \n"));
1103
1104 for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1105 {
1106 PITChannelState *pCh = &pThis->channels[i];
1107 if (pCh->pTimerR3)
1108 pCh->pTimerRC = TMTimerRCPtr(pCh->pTimerR3);
1109 pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1110 }
1111}
1112
1113
1114/**
1115 * Reset notification.
1116 *
1117 * @returns VBox status.
1118 * @param pDevIns The device instance data.
1119 */
1120static DECLCALLBACK(void) pitReset(PPDMDEVINS pDevIns)
1121{
1122 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
1123 LogFlow(("pitReset: \n"));
1124
1125 DEVPIT_R3_LOCK_BOTH(pThis);
1126
1127 pThis->fDisabledByHpet = false;
1128
1129 for (unsigned i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1130 {
1131 PITChannelState *s = &pThis->channels[i];
1132
1133#if 1 /* Set everything back to virgin state. (might not be strictly correct) */
1134 s->latched_count = 0;
1135 s->count_latched = 0;
1136 s->status_latched = 0;
1137 s->status = 0;
1138 s->read_state = 0;
1139 s->write_state = 0;
1140 s->write_latch = 0;
1141 s->rw_mode = 0;
1142 s->bcd = 0;
1143#endif
1144 s->u64NextTS = UINT64_MAX;
1145 s->cRelLogEntries = 0;
1146 s->mode = 3;
1147 s->gate = (i != 2);
1148 pit_load_count(s, 0);
1149 }
1150
1151 DEVPIT_UNLOCK_BOTH(pThis);
1152}
1153
1154
1155/**
1156 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1157 */
1158static DECLCALLBACK(int) pitConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1159{
1160 PITState *pThis = PDMINS_2_DATA(pDevIns, PITState *);
1161 int rc;
1162 uint8_t u8Irq;
1163 uint16_t u16Base;
1164 bool fSpeaker;
1165 bool fGCEnabled;
1166 bool fR0Enabled;
1167 unsigned i;
1168 Assert(iInstance == 0);
1169
1170 /*
1171 * Validate configuration.
1172 */
1173 if (!CFGMR3AreValuesValid(pCfg, "Irq\0" "Base\0" "SpeakerEnabled\0" "GCEnabled\0" "R0Enabled\0"))
1174 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
1175
1176 /*
1177 * Init the data.
1178 */
1179 rc = CFGMR3QueryU8Def(pCfg, "Irq", &u8Irq, 0);
1180 if (RT_FAILURE(rc))
1181 return PDMDEV_SET_ERROR(pDevIns, rc,
1182 N_("Configuration error: Querying \"Irq\" as a uint8_t failed"));
1183
1184 rc = CFGMR3QueryU16Def(pCfg, "Base", &u16Base, 0x40);
1185 if (RT_FAILURE(rc))
1186 return PDMDEV_SET_ERROR(pDevIns, rc,
1187 N_("Configuration error: Querying \"Base\" as a uint16_t failed"));
1188
1189 rc = CFGMR3QueryBoolDef(pCfg, "SpeakerEnabled", &fSpeaker, true);
1190 if (RT_FAILURE(rc))
1191 return PDMDEV_SET_ERROR(pDevIns, rc,
1192 N_("Configuration error: Querying \"SpeakerEnabled\" as a bool failed"));
1193
1194 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
1195 if (RT_FAILURE(rc))
1196 return PDMDEV_SET_ERROR(pDevIns, rc,
1197 N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
1198
1199 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
1200 if (RT_FAILURE(rc))
1201 return PDMDEV_SET_ERROR(pDevIns, rc,
1202 N_("Configuration error: failed to read R0Enabled as boolean"));
1203
1204 pThis->pDevIns = pDevIns;
1205 pThis->IOPortBaseCfg = u16Base;
1206 pThis->fSpeakerCfg = fSpeaker;
1207 pThis->channels[0].irq = u8Irq;
1208 for (i = 0; i < RT_ELEMENTS(pThis->channels); i++)
1209 {
1210 pThis->channels[i].pPitR3 = pThis;
1211 pThis->channels[i].pPitR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1212 pThis->channels[i].pPitRC = PDMINS_2_DATA_RCPTR(pDevIns);
1213 }
1214
1215 /*
1216 * Interfaces
1217 */
1218 /* IBase */
1219 pDevIns->IBase.pfnQueryInterface = pitQueryInterface;
1220 /* IHpetLegacyNotify */
1221 pThis->IHpetLegacyNotify.pfnModeChanged = pitNotifyHpetLegacyNotify_ModeChanged;
1222
1223 /*
1224 * We do our own locking. This must be done before creating timers.
1225 */
1226 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "pit");
1227 AssertRCReturn(rc, rc);
1228
1229 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1230 AssertRCReturn(rc, rc);
1231
1232 /*
1233 * Create the timer, make it take our critsect.
1234 */
1235 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, pitTimer, &pThis->channels[0],
1236 TMTIMER_FLAGS_NO_CRIT_SECT, "i8254 Programmable Interval Timer",
1237 &pThis->channels[0].pTimerR3);
1238 if (RT_FAILURE(rc))
1239 return rc;
1240 pThis->channels[0].pTimerRC = TMTimerRCPtr(pThis->channels[0].pTimerR3);
1241 pThis->channels[0].pTimerR0 = TMTimerR0Ptr(pThis->channels[0].pTimerR3);
1242 rc = TMR3TimerSetCritSect(pThis->channels[0].pTimerR3, &pThis->CritSect);
1243 AssertRCReturn(rc, rc);
1244
1245 /*
1246 * Register I/O ports.
1247 */
1248 rc = PDMDevHlpIOPortRegister(pDevIns, u16Base, 4, NULL, pitIOPortWrite, pitIOPortRead, NULL, NULL, "i8254 Programmable Interval Timer");
1249 if (RT_FAILURE(rc))
1250 return rc;
1251 if (fGCEnabled)
1252 {
1253 rc = PDMDevHlpIOPortRegisterRC(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1254 if (RT_FAILURE(rc))
1255 return rc;
1256 }
1257 if (fR0Enabled)
1258 {
1259 rc = PDMDevHlpIOPortRegisterR0(pDevIns, u16Base, 4, 0, "pitIOPortWrite", "pitIOPortRead", NULL, NULL, "i8254 Programmable Interval Timer");
1260 if (RT_FAILURE(rc))
1261 return rc;
1262 }
1263
1264 if (fSpeaker)
1265 {
1266 rc = PDMDevHlpIOPortRegister(pDevIns, 0x61, 1, NULL, pitIOPortSpeakerWrite, pitIOPortSpeakerRead, NULL, NULL, "PC Speaker");
1267 if (RT_FAILURE(rc))
1268 return rc;
1269 if (fGCEnabled)
1270 {
1271 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x61, 1, 0, NULL, "pitIOPortSpeakerRead", NULL, NULL, "PC Speaker");
1272 if (RT_FAILURE(rc))
1273 return rc;
1274 }
1275 }
1276
1277 /*
1278 * Saved state.
1279 */
1280 rc = PDMDevHlpSSMRegister3(pDevIns, PIT_SAVED_STATE_VERSION, sizeof(*pThis), pitLiveExec, pitSaveExec, pitLoadExec);
1281 if (RT_FAILURE(rc))
1282 return rc;
1283
1284 /*
1285 * Initialize the device state.
1286 */
1287 pitReset(pDevIns);
1288
1289 /*
1290 * Register statistics and debug info.
1291 */
1292 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITIrq, STAMTYPE_COUNTER, "/TM/PIT/Irq", STAMUNIT_OCCURENCES, "The number of times a timer interrupt was triggered.");
1293 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPITHandler, STAMTYPE_PROFILE, "/TM/PIT/Handler", STAMUNIT_TICKS_PER_CALL, "Profiling timer callback handler.");
1294
1295 PDMDevHlpDBGFInfoRegister(pDevIns, "pit", "Display PIT (i8254) status. (no arguments)", pitInfo);
1296
1297 return VINF_SUCCESS;
1298}
1299
1300
1301/**
1302 * The device registration structure.
1303 */
1304const PDMDEVREG g_DeviceI8254 =
1305{
1306 /* u32Version */
1307 PDM_DEVREG_VERSION,
1308 /* szName */
1309 "i8254",
1310 /* szRCMod */
1311 "VBoxDDGC.gc",
1312 /* szR0Mod */
1313 "VBoxDDR0.r0",
1314 /* pszDescription */
1315 "Intel 8254 Programmable Interval Timer (PIT) And Dummy Speaker Device",
1316 /* fFlags */
1317 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1318 /* fClass */
1319 PDM_DEVREG_CLASS_PIT,
1320 /* cMaxInstances */
1321 1,
1322 /* cbInstance */
1323 sizeof(PITState),
1324 /* pfnConstruct */
1325 pitConstruct,
1326 /* pfnDestruct */
1327 NULL,
1328 /* pfnRelocate */
1329 pitRelocate,
1330 /* pfnIOCtl */
1331 NULL,
1332 /* pfnPowerOn */
1333 NULL,
1334 /* pfnReset */
1335 pitReset,
1336 /* pfnSuspend */
1337 NULL,
1338 /* pfnResume */
1339 NULL,
1340 /* pfnAttach */
1341 NULL,
1342 /* pfnDetach */
1343 NULL,
1344 /* pfnQueryInterface */
1345 NULL,
1346 /* pfnInitComplete */
1347 NULL,
1348 /* pfnPowerOff */
1349 NULL,
1350 /* pfnSoftReset */
1351 NULL,
1352 /* u32VersionEnd */
1353 PDM_DEVREG_VERSION
1354};
1355
1356#endif /* IN_RING3 */
1357#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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