VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevPIC.cpp@ 40907

Last change on this file since 40907 was 40907, checked in by vboxsync, 12 years ago

Working on tracking IRQs for tracing and logging purposes.
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1/* $Id: DevPIC.cpp 40907 2012-04-13 20:50:14Z vboxsync $ */
2/** @file
3 * DevPIC - Intel 8259 Programmable Interrupt Controller (PIC) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_PIC
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/log.h>
24#include <iprt/assert.h>
25#include <iprt/string.h>
26
27#include "VBoxDD.h"
28
29
30/*******************************************************************************
31* Defined Constants And Macros *
32*******************************************************************************/
33/** @def PIC_LOCK
34 * Acquires the PDM lock. This is a NOP if locking is disabled. */
35/** @def PIC_UNLOCK
36 * Releases the PDM lock. This is a NOP if locking is disabled. */
37#define PIC_LOCK(pThis, rc) \
38 do { \
39 int rc2 = (pThis)->CTX_SUFF(pPicHlp)->pfnLock((pThis)->CTX_SUFF(pDevIns), rc); \
40 if (rc2 != VINF_SUCCESS) \
41 return rc2; \
42 } while (0)
43#define PIC_UNLOCK(pThis) \
44 (pThis)->CTX_SUFF(pPicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
45
46
47#ifndef VBOX_DEVICE_STRUCT_TESTCASE
48/*******************************************************************************
49* Internal Functions *
50*******************************************************************************/
51RT_C_DECLS_BEGIN
52
53PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc);
54PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc);
55PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
56PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
57PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
58PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
59
60RT_C_DECLS_END
61#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
62
63
64/*
65 * QEMU 8259 interrupt controller emulation
66 *
67 * Copyright (c) 2003-2004 Fabrice Bellard
68 *
69 * Permission is hereby granted, free of charge, to any person obtaining a copy
70 * of this software and associated documentation files (the "Software"), to deal
71 * in the Software without restriction, including without limitation the rights
72 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
73 * copies of the Software, and to permit persons to whom the Software is
74 * furnished to do so, subject to the following conditions:
75 *
76 * The above copyright notice and this permission notice shall be included in
77 * all copies or substantial portions of the Software.
78 *
79 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
80 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
81 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
82 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
83 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
84 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
85 * THE SOFTWARE.
86 */
87
88/* debug PIC */
89#define DEBUG_PIC
90
91/*#define DEBUG_IRQ_COUNT*/
92
93typedef struct PicState {
94 uint8_t last_irr; /* edge detection */
95 uint8_t irr; /* interrupt request register */
96 uint8_t imr; /* interrupt mask register */
97 uint8_t isr; /* interrupt service register */
98 uint8_t priority_add; /* highest irq priority */
99 uint8_t irq_base;
100 uint8_t read_reg_select;
101 uint8_t poll;
102 uint8_t special_mask;
103 uint8_t init_state;
104 uint8_t auto_eoi;
105 uint8_t rotate_on_auto_eoi;
106 uint8_t special_fully_nested_mode;
107 uint8_t init4; /* true if 4 byte init */
108 uint8_t elcr; /* PIIX edge/trigger selection*/
109 uint8_t elcr_mask;
110 /** Pointer to the device instance, R3 Ptr. */
111 PPDMDEVINSR3 pDevInsR3;
112 /** Pointer to the device instance, R0 Ptr. */
113 PPDMDEVINSR0 pDevInsR0;
114 /** Pointer to the device instance, RC Ptr. */
115 PPDMDEVINSRC pDevInsRC;
116 RTRCPTR Alignment0; /**< Structure size alignment. */
117 /** The IRQ tags and source IDs for each (tracing purposes). */
118 uint32_t auTags[8];
119
120} PicState;
121
122/**
123 * A PIC device instance data.
124 */
125typedef struct DEVPIC
126{
127 /** The two interrupt controllers. */
128 PicState aPics[2];
129 /** Pointer to the device instance - R3 Ptr. */
130 PPDMDEVINSR3 pDevInsR3;
131 /** Pointer to the PIC R3 helpers. */
132 PCPDMPICHLPR3 pPicHlpR3;
133 /** Pointer to the device instance - R0 Ptr. */
134 PPDMDEVINSR0 pDevInsR0;
135 /** Pointer to the PIC R0 helpers. */
136 PCPDMPICHLPR0 pPicHlpR0;
137 /** Pointer to the device instance - RC Ptr. */
138 PPDMDEVINSRC pDevInsRC;
139 /** Pointer to the PIC RC helpers. */
140 PCPDMPICHLPRC pPicHlpRC;
141 /** Number of release log entries. Used to prevent flooding. */
142 uint32_t cRelLogEntries;
143 uint32_t u32AlignmentPadding;
144#ifdef VBOX_WITH_STATISTICS
145 STAMCOUNTER StatSetIrqGC;
146 STAMCOUNTER StatSetIrqHC;
147 STAMCOUNTER StatClearedActiveIRQ2;
148 STAMCOUNTER StatClearedActiveMasterIRQ;
149 STAMCOUNTER StatClearedActiveSlaveIRQ;
150#endif
151} DEVPIC, *PDEVPIC;
152
153
154#ifndef VBOX_DEVICE_STRUCT_TESTCASE
155#ifdef LOG_ENABLED
156static inline void DumpPICState(PicState *s, const char *szFn)
157{
158 PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
159
160 Log2(("%s: pic%d: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
161 szFn, (&pThis->aPics[0] == s) ? 0 : 1,
162 s->elcr, s->last_irr, s->irr, s->imr, s->isr, s->irq_base));
163}
164#else
165# define DumpPICState(pThis, szFn) do { } while (0)
166#endif
167
168/* set irq level. If an edge is detected, then the IRR is set to 1 */
169static inline void pic_set_irq1(PicState *s, int irq, int level, uint32_t uTagSrc)
170{
171 int mask;
172 Log(("pic_set_irq1: irq=%d level=%d\n", irq, level));
173 mask = 1 << irq;
174 if (s->elcr & mask) {
175 /* level triggered */
176 if (level) {
177 Log2(("pic_set_irq1(ls) irr=%d irrnew=%d\n", s->irr, s->irr | mask));
178 s->irr |= mask;
179 s->last_irr |= mask;
180 } else {
181 Log2(("pic_set_irq1(lc) irr=%d irrnew=%d\n", s->irr, s->irr & ~mask));
182 s->irr &= ~mask;
183 s->last_irr &= ~mask;
184 }
185 } else {
186 /* edge triggered */
187 if (level) {
188 if ((s->last_irr & mask) == 0)
189 {
190 Log2(("pic_set_irq1 irr=%x last_irr=%x\n", s->irr | mask, s->last_irr));
191 s->irr |= mask;
192 }
193 s->last_irr |= mask;
194 } else {
195 s->irr &= ~mask;
196 s->last_irr &= ~mask;
197 }
198 }
199
200 /* Save the tag. */
201 if (level)
202 {
203 if (!s->auTags[irq])
204 s->auTags[irq] = uTagSrc;
205 else
206 s->auTags[irq] |= RT_BIT_32(31);
207 }
208
209 DumpPICState(s, "pic_set_irq1");
210}
211
212/* return the highest priority found in mask (highest = smallest
213 number). Return 8 if no irq */
214static inline int get_priority(PicState *s, int mask)
215{
216 int priority;
217 if (mask == 0)
218 return 8;
219 priority = 0;
220 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
221 priority++;
222 return priority;
223}
224
225/* return the pic wanted interrupt. return -1 if none */
226static int pic_get_irq(PicState *s)
227{
228 PicState *pics = &(PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC))->aPics[0];
229 int mask, cur_priority, priority;
230 Log(("pic_get_irq%d: mask=%x\n", (s == pics) ? 0 : 1, s->irr & ~s->imr));
231 DumpPICState(s, "pic_get_irq");
232
233 mask = s->irr & ~s->imr;
234 priority = get_priority(s, mask);
235 Log(("pic_get_irq: priority=%x\n", priority));
236 if (priority == 8)
237 return -1;
238 /* compute current priority. If special fully nested mode on the
239 master, the IRQ coming from the slave is not taken into account
240 for the priority computation. */
241 mask = s->isr;
242 if (s->special_fully_nested_mode && s == &pics[0])
243 mask &= ~(1 << 2);
244 cur_priority = get_priority(s, mask);
245 Log(("pic_get_irq%d: cur_priority=%x pending=%d\n", (s == pics) ? 0 : 1, cur_priority, (priority == 8) ? -1 : (priority + s->priority_add) & 7));
246 if (priority < cur_priority) {
247 /* higher priority found: an irq should be generated */
248 return (priority + s->priority_add) & 7;
249 } else {
250 return -1;
251 }
252}
253
254/* raise irq to CPU if necessary. must be called every time the active
255 irq may change */
256static int pic_update_irq(PDEVPIC pThis)
257{
258 PicState *pics = &pThis->aPics[0];
259 int irq2, irq;
260
261 /* first look at slave pic */
262 irq2 = pic_get_irq(&pics[1]);
263 Log(("pic_update_irq irq2=%d\n", irq2));
264 if (irq2 >= 0) {
265 /* if irq request by slave pic, signal master PIC */
266 pic_set_irq1(&pics[0], 2, 1, pics[1].auTags[irq2]);
267 } else {
268 /* If not, clear the IR on the master PIC. */
269 pic_set_irq1(&pics[0], 2, 0, 0 /*uTagSrc*/);
270 }
271 /* look at requested irq */
272 irq = pic_get_irq(&pics[0]);
273 if (irq >= 0)
274 {
275 /* If irq 2 is pending on the master pic, then there must be one pending on the slave pic too! Otherwise we'll get
276 * spurious slave interrupts in picGetInterrupt.
277 */
278 if (irq != 2 || irq2 != -1)
279 {
280#if defined(DEBUG_PIC)
281 int i;
282 for(i = 0; i < 2; i++) {
283 Log(("pic%d: imr=%x irr=%x padd=%d\n",
284 i, pics[i].imr, pics[i].irr,
285 pics[i].priority_add));
286 }
287 Log(("pic: cpu_interrupt\n"));
288#endif
289 pThis->CTX_SUFF(pPicHlp)->pfnSetInterruptFF(pThis->CTX_SUFF(pDevIns));
290 }
291 else
292 {
293 STAM_COUNTER_INC(&pThis->StatClearedActiveIRQ2);
294 Log(("pic_update_irq: irq 2 is active, but no interrupt is pending on the slave pic!!\n"));
295 /* Clear it here, so lower priority interrupts can still be dispatched. */
296
297 /* if this was the only pending irq, then we must clear the interrupt ff flag */
298 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
299
300 /** @note Is this correct? */
301 pics[0].irr &= ~(1 << 2);
302
303 /* Call ourselves again just in case other interrupts are pending */
304 return pic_update_irq(pThis);
305 }
306 }
307 else
308 {
309 Log(("pic_update_irq: no interrupt is pending!!\n"));
310
311 /* we must clear the interrupt ff flag */
312 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
313 }
314 return VINF_SUCCESS;
315}
316
317/** @note if an interrupt line state changes from unmasked to masked, then it must be deactivated when currently pending! */
318static void pic_update_imr(PDEVPIC pThis, PicState *s, uint8_t val)
319{
320 int irq, intno;
321 PicState *pActivePIC;
322
323 /* Query the current pending irq, if any. */
324 pActivePIC = &pThis->aPics[0];
325 intno = irq = pic_get_irq(pActivePIC);
326 if (irq == 2)
327 {
328 pActivePIC = &pThis->aPics[1];
329 irq = pic_get_irq(pActivePIC);
330 intno = irq + 8;
331 }
332
333 /* Update IMR */
334 s->imr = val;
335
336 /* If an interrupt is pending and now masked, then clear the FF flag. */
337 if ( irq >= 0
338 && ((1 << irq) & ~pActivePIC->imr) == 0)
339 {
340 Log(("pic_update_imr: pic0: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
341 pThis->aPics[0].elcr, pThis->aPics[0].last_irr, pThis->aPics[0].irr, pThis->aPics[0].imr, pThis->aPics[0].isr, pThis->aPics[0].irq_base));
342 Log(("pic_update_imr: pic1: elcr=%x last_irr=%x irr=%x imr=%x isr=%x irq_base=%x\n",
343 pThis->aPics[1].elcr, pThis->aPics[1].last_irr, pThis->aPics[1].irr, pThis->aPics[1].imr, pThis->aPics[1].isr, pThis->aPics[1].irq_base));
344
345 /* Clear pending IRQ 2 on master controller in case of slave interrupt. */
346 /** @todo Is this correct? */
347 if (intno > 7)
348 {
349 pThis->aPics[0].irr &= ~(1 << 2);
350 STAM_COUNTER_INC(&pThis->StatClearedActiveSlaveIRQ);
351 }
352 else
353 STAM_COUNTER_INC(&pThis->StatClearedActiveMasterIRQ);
354
355 Log(("pic_update_imr: clear pending interrupt %d\n", intno));
356 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
357 }
358}
359
360
361/**
362 * Set the an IRQ.
363 *
364 * @param pDevIns Device instance of the PICs.
365 * @param iIrq IRQ number to set.
366 * @param iLevel IRQ level.
367 * @param uTagSrc The IRQ tag and source ID (for tracing).
368 */
369PDMBOTHCBDECL(void) picSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
370{
371 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
372 Assert(pThis->CTX_SUFF(pDevIns) == pDevIns);
373 Assert(pThis->aPics[0].CTX_SUFF(pDevIns) == pDevIns);
374 Assert(pThis->aPics[1].CTX_SUFF(pDevIns) == pDevIns);
375 AssertMsg(iIrq < 16, ("iIrq=%d\n", iIrq));
376
377 Log(("picSetIrq %d %d\n", iIrq, iLevel));
378 DumpPICState(&pThis->aPics[0], "picSetIrq");
379 DumpPICState(&pThis->aPics[1], "picSetIrq");
380 STAM_COUNTER_INC(&pThis->CTXSUFF(StatSetIrq));
381 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
382 {
383 /* A flip-flop lowers the IRQ line and immediately raises it, so
384 * that a rising edge is guaranteed to occur. Note that the IRQ
385 * line must be held high for a while to avoid spurious interrupts.
386 */
387 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, 0, uTagSrc);
388 pic_update_irq(pThis);
389 }
390 pic_set_irq1(&pThis->aPics[iIrq >> 3], iIrq & 7, iLevel & PDM_IRQ_LEVEL_HIGH, uTagSrc);
391 pic_update_irq(pThis);
392}
393
394
395/* acknowledge interrupt 'irq' */
396static inline void pic_intack(PicState *s, int irq)
397{
398 if (s->auto_eoi) {
399 if (s->rotate_on_auto_eoi)
400 s->priority_add = (irq + 1) & 7;
401 } else {
402 s->isr |= (1 << irq);
403 }
404 /* We don't clear a level sensitive interrupt here */
405 if (!(s->elcr & (1 << irq)))
406 {
407 Log2(("pic_intack: irr=%x irrnew=%x\n", s->irr, s->irr & ~(1 << irq)));
408 s->irr &= ~(1 << irq);
409 }
410}
411
412
413/**
414 * Get a pending interrupt.
415 *
416 * @returns Pending interrupt number.
417 * @param pDevIns Device instance of the PICs.
418 * @param puTagSrc Where to return the IRQ tag and source ID.
419 */
420PDMBOTHCBDECL(int) picGetInterrupt(PPDMDEVINS pDevIns, uint32_t *puTagSrc)
421{
422 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
423 int irq;
424 int irq2;
425 int intno;
426
427 /* read the irq from the PIC */
428 DumpPICState(&pThis->aPics[0], "picGetInterrupt");
429 DumpPICState(&pThis->aPics[1], "picGetInterrupt");
430
431 irq = pic_get_irq(&pThis->aPics[0]);
432 if (irq >= 0)
433 {
434 pic_intack(&pThis->aPics[0], irq);
435 if (irq == 2)
436 {
437 irq2 = pic_get_irq(&pThis->aPics[1]);
438 if (irq2 >= 0) {
439 pic_intack(&pThis->aPics[1], irq2);
440 }
441 else
442 {
443 /* Interrupt went away or is now masked. */
444 Log(("picGetInterrupt: spurious IRQ on slave controller, converted to IRQ15\n"));
445 irq2 = 7;
446 }
447 intno = pThis->aPics[1].irq_base + irq2;
448 *puTagSrc = pThis->aPics[0].auTags[irq2];
449 pThis->aPics[0].auTags[irq2] = 0;
450 Log2(("picGetInterrupt1: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[1].irq_base, irq2, *puTagSrc));
451 irq = irq2 + 8;
452 }
453 else
454 {
455 intno = pThis->aPics[0].irq_base + irq;
456 *puTagSrc = pThis->aPics[0].auTags[irq];
457 pThis->aPics[0].auTags[irq] = 0;
458 Log2(("picGetInterrupt0: %x base=%x irq=%x uTagSrc=%#x\n", intno, pThis->aPics[0].irq_base, irq, *puTagSrc));
459 }
460 }
461 else
462 {
463 /* Interrupt went away or is now masked. */
464 Log(("picGetInterrupt: spurious IRQ on master controller, converted to IRQ7\n"));
465 irq = 7;
466 intno = pThis->aPics[0].irq_base + irq;
467 *puTagSrc = 0;
468 }
469 pic_update_irq(pThis);
470
471 Log(("picGetInterrupt: 0x%02x pending 0:%d 1:%d\n", intno, pic_get_irq(&pThis->aPics[0]), pic_get_irq(&pThis->aPics[1])));
472
473 return intno;
474}
475
476static void pic_reset(PicState *s)
477{
478 PPDMDEVINSR3 pDevInsR3 = s->pDevInsR3;
479 PPDMDEVINSR0 pDevInsR0 = s->pDevInsR0;
480 PPDMDEVINSRC pDevInsRC = s->pDevInsRC;
481 int elcr_mask = s->elcr_mask;
482 int elcr = s->elcr;
483
484 memset(s, 0, sizeof(PicState));
485
486 s->elcr = elcr;
487 s->elcr_mask = elcr_mask;
488 s->pDevInsRC = pDevInsRC;
489 s->pDevInsR0 = pDevInsR0;
490 s->pDevInsR3 = pDevInsR3;
491}
492
493
494static int pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
495{
496 PicState *s = (PicState*)opaque;
497 PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
498 int rc = VINF_SUCCESS;
499 int priority, cmd, irq;
500
501 Log(("pic_write: addr=0x%02x val=0x%02x\n", addr, val));
502 addr &= 1;
503 if (addr == 0) {
504 if (val & 0x10) {
505 /* init */
506 pic_reset(s);
507 /* deassert a pending interrupt */
508 pThis->CTX_SUFF(pPicHlp)->pfnClearInterruptFF(pThis->CTX_SUFF(pDevIns));
509
510 s->init_state = 1;
511 s->init4 = val & 1;
512 if (val & 0x02)
513 AssertReleaseMsgFailed(("single mode not supported"));
514 if (val & 0x08)
515 if (pThis->cRelLogEntries++ < 64)
516 LogRel(("pic_write: Level sensitive IRQ setting ignored.\n"));
517 } else if (val & 0x08) {
518 if (val & 0x04)
519 s->poll = 1;
520 if (val & 0x02)
521 s->read_reg_select = val & 1;
522 if (val & 0x40)
523 s->special_mask = (val >> 5) & 1;
524 } else {
525 cmd = val >> 5;
526 switch(cmd) {
527 case 0:
528 case 4:
529 s->rotate_on_auto_eoi = cmd >> 2;
530 break;
531 case 1: /* end of interrupt */
532 case 5:
533 {
534 priority = get_priority(s, s->isr);
535 if (priority != 8) {
536 irq = (priority + s->priority_add) & 7;
537 Log(("pic_write: EOI prio=%d irq=%d\n", priority, irq));
538 s->isr &= ~(1 << irq);
539 if (cmd == 5)
540 s->priority_add = (irq + 1) & 7;
541 rc = pic_update_irq(pThis);
542 Assert(rc == VINF_SUCCESS);
543 DumpPICState(s, "eoi");
544 }
545 break;
546 }
547 case 3:
548 {
549 irq = val & 7;
550 Log(("pic_write: EOI2 for irq %d\n", irq));
551 s->isr &= ~(1 << irq);
552 rc = pic_update_irq(pThis);
553 Assert(rc == VINF_SUCCESS);
554 DumpPICState(s, "eoi2");
555 break;
556 }
557 case 6:
558 {
559 s->priority_add = (val + 1) & 7;
560 Log(("pic_write: lowest priority %d (highest %d)\n", val & 7, s->priority_add));
561 rc = pic_update_irq(pThis);
562 Assert(rc == VINF_SUCCESS);
563 break;
564 }
565 case 7:
566 {
567 irq = val & 7;
568 Log(("pic_write: EOI3 for irq %d\n", irq));
569 s->isr &= ~(1 << irq);
570 s->priority_add = (irq + 1) & 7;
571 rc = pic_update_irq(pThis);
572 Assert(rc == VINF_SUCCESS);
573 DumpPICState(s, "eoi3");
574 break;
575 }
576 default:
577 /* no operation */
578 break;
579 }
580 }
581 } else {
582 switch(s->init_state) {
583 case 0:
584 {
585 /* normal mode */
586 pic_update_imr(pThis, s, val);
587
588 rc = pic_update_irq(pThis);
589 Assert(rc == VINF_SUCCESS);
590 break;
591 }
592 case 1:
593 s->irq_base = val & 0xf8;
594 s->init_state = 2;
595 Log(("pic_write: set irq base to %x\n", s->irq_base));
596 break;
597 case 2:
598 if (s->init4) {
599 s->init_state = 3;
600 } else {
601 s->init_state = 0;
602 }
603 break;
604 case 3:
605 s->special_fully_nested_mode = (val >> 4) & 1;
606 s->auto_eoi = (val >> 1) & 1;
607 s->init_state = 0;
608 Log(("pic_write: special_fully_nested_mode=%d auto_eoi=%d\n", s->special_fully_nested_mode, s->auto_eoi));
609 break;
610 }
611 }
612 return rc;
613}
614
615
616static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
617{
618 PDEVPIC pThis = PDMINS_2_DATA(s->CTX_SUFF(pDevIns), PDEVPIC);
619 PicState *pics = &pThis->aPics[0];
620 int ret;
621
622 ret = pic_get_irq(s);
623 if (ret >= 0) {
624 if (addr1 >> 7) {
625 Log2(("pic_poll_read: clear slave irq (isr)\n"));
626 pics[0].isr &= ~(1 << 2);
627 pics[0].irr &= ~(1 << 2);
628 }
629 Log2(("pic_poll_read: clear irq %d (isr)\n", ret));
630 s->irr &= ~(1 << ret);
631 s->isr &= ~(1 << ret);
632 if (addr1 >> 7 || ret != 2)
633 pic_update_irq(pThis);
634 } else {
635 ret = 0;
636 pic_update_irq(pThis);
637 }
638
639 return ret;
640}
641
642
643static uint32_t pic_ioport_read(void *opaque, uint32_t addr1, int *pRC)
644{
645 PicState *s = (PicState*)opaque;
646 unsigned int addr;
647 int ret;
648
649 *pRC = VINF_SUCCESS;
650
651 addr = addr1;
652 addr &= 1;
653 if (s->poll) {
654 ret = pic_poll_read(s, addr1);
655 s->poll = 0;
656 } else {
657 if (addr == 0) {
658 if (s->read_reg_select)
659 ret = s->isr;
660 else
661 ret = s->irr;
662 } else {
663 ret = s->imr;
664 }
665 }
666 Log(("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret));
667 return ret;
668}
669
670
671
672/* -=-=-=-=-=- wrappers / stuff -=-=-=-=-=- */
673
674/**
675 * Port I/O Handler for IN operations.
676 *
677 * @returns VBox status code.
678 *
679 * @param pDevIns The device instance.
680 * @param pvUser User argument - pointer to the PIC in question.
681 * @param uPort Port number used for the IN operation.
682 * @param pu32 Where to store the result.
683 * @param cb Number of bytes read.
684 */
685PDMBOTHCBDECL(int) picIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
686{
687 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
688 uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
689
690 Assert(iPic == 0 || iPic == 1);
691 if (cb == 1)
692 {
693 int rc;
694 PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_READ);
695 *pu32 = pic_ioport_read(&pThis->aPics[iPic], Port, &rc);
696 PIC_UNLOCK(pThis);
697 return rc;
698 }
699 return VERR_IOM_IOPORT_UNUSED;
700}
701
702/**
703 * Port I/O Handler for OUT operations.
704 *
705 * @returns VBox status code.
706 *
707 * @param pDevIns The device instance.
708 * @param pvUser User argument - pointer to the PIC in question.
709 * @param uPort Port number used for the IN operation.
710 * @param u32 The value to output.
711 * @param cb The value size in bytes.
712 */
713PDMBOTHCBDECL(int) picIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
714{
715 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
716 uint32_t iPic = (uint32_t)(uintptr_t)pvUser;
717
718 Assert(iPic == 0 || iPic == 1);
719
720 if (cb == 1)
721 {
722 int rc;
723 PIC_LOCK(pThis, VINF_IOM_R3_IOPORT_WRITE);
724 rc = pic_ioport_write(&pThis->aPics[iPic], Port, u32);
725 PIC_UNLOCK(pThis);
726 return rc;
727 }
728 return VINF_SUCCESS;
729}
730
731
732/**
733 * Port I/O Handler for IN operations.
734 *
735 * @returns VBox status code.
736 *
737 * @param pDevIns The device instance.
738 * @param pvUser User argument - pointer to the PIC in question.
739 * @param uPort Port number used for the IN operation.
740 * @param pu32 Where to store the result.
741 * @param cb Number of bytes read.
742 */
743PDMBOTHCBDECL(int) picIOPortElcrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
744{
745 if (cb == 1)
746 {
747 PicState *s = (PicState*)pvUser;
748 PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_READ);
749 *pu32 = s->elcr;
750 PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
751 return VINF_SUCCESS;
752 }
753 NOREF(Port);
754 return VERR_IOM_IOPORT_UNUSED;
755}
756
757/**
758 * Port I/O Handler for OUT operations.
759 *
760 * @returns VBox status code.
761 *
762 * @param pDevIns The device instance.
763 * @param pvUser User argument - pointer to the PIC in question.
764 * @param uPort Port number used for the IN operation.
765 * @param u32 The value to output.
766 * @param cb The value size in bytes.
767 */
768PDMBOTHCBDECL(int) picIOPortElcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
769{
770 if (cb == 1)
771 {
772 PicState *s = (PicState*)pvUser;
773 PIC_LOCK(PDMINS_2_DATA(pDevIns, PDEVPIC), VINF_IOM_R3_IOPORT_WRITE);
774 s->elcr = u32 & s->elcr_mask;
775 PIC_UNLOCK(PDMINS_2_DATA(pDevIns, PDEVPIC));
776 }
777 NOREF(Port);
778 return VINF_SUCCESS;
779}
780
781
782#ifdef IN_RING3
783
784/**
785 * PIC status info callback.
786 *
787 * @param pDevIns The device instance.
788 * @param pHlp The output helpers.
789 * @param pszArgs The arguments.
790 */
791static DECLCALLBACK(void) picInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
792{
793 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
794 NOREF(pszArgs);
795
796 /*
797 * Show info.
798 */
799 for (int i = 0; i < 2; i++)
800 {
801 PicState *pPic = &pThis->aPics[i];
802
803 pHlp->pfnPrintf(pHlp, "PIC%d:\n", i);
804 pHlp->pfnPrintf(pHlp, " IMR :%02x ISR :%02x IRR :%02x LIRR:%02x\n",
805 pPic->imr, pPic->isr, pPic->irr, pPic->last_irr);
806 pHlp->pfnPrintf(pHlp, " Base:%02x PriAdd:%02x RegSel:%02x\n",
807 pPic->irq_base, pPic->priority_add, pPic->read_reg_select);
808 pHlp->pfnPrintf(pHlp, " Poll:%02x SpMask:%02x IState:%02x\n",
809 pPic->poll, pPic->special_mask, pPic->init_state);
810 pHlp->pfnPrintf(pHlp, " AEOI:%02x Rotate:%02x FNest :%02x Ini4:%02x\n",
811 pPic->auto_eoi, pPic->rotate_on_auto_eoi,
812 pPic->special_fully_nested_mode, pPic->init4);
813 pHlp->pfnPrintf(pHlp, " ELCR:%02x ELMask:%02x\n", pPic->elcr, pPic->elcr_mask);
814 }
815}
816
817/**
818 * Saves a state of the programmable interrupt controller device.
819 *
820 * @returns VBox status code.
821 * @param pDevIns The device instance.
822 * @param pSSMHandle The handle to save the state to.
823 */
824static DECLCALLBACK(int) picSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
825{
826 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
827 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
828 {
829 SSMR3PutU8(pSSMHandle, pThis->aPics[i].last_irr);
830 SSMR3PutU8(pSSMHandle, pThis->aPics[i].irr);
831 SSMR3PutU8(pSSMHandle, pThis->aPics[i].imr);
832 SSMR3PutU8(pSSMHandle, pThis->aPics[i].isr);
833 SSMR3PutU8(pSSMHandle, pThis->aPics[i].priority_add);
834 SSMR3PutU8(pSSMHandle, pThis->aPics[i].irq_base);
835 SSMR3PutU8(pSSMHandle, pThis->aPics[i].read_reg_select);
836 SSMR3PutU8(pSSMHandle, pThis->aPics[i].poll);
837 SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_mask);
838 SSMR3PutU8(pSSMHandle, pThis->aPics[i].init_state);
839 SSMR3PutU8(pSSMHandle, pThis->aPics[i].auto_eoi);
840 SSMR3PutU8(pSSMHandle, pThis->aPics[i].rotate_on_auto_eoi);
841 SSMR3PutU8(pSSMHandle, pThis->aPics[i].special_fully_nested_mode);
842 SSMR3PutU8(pSSMHandle, pThis->aPics[i].init4);
843 SSMR3PutU8(pSSMHandle, pThis->aPics[i].elcr);
844 }
845 return VINF_SUCCESS;
846}
847
848
849/**
850 * Loads a saved programmable interrupt controller device state.
851 *
852 * @returns VBox status code.
853 * @param pDevIns The device instance.
854 * @param pSSMHandle The handle to the saved state.
855 * @param uVersion The data unit version number.
856 * @param uPass The data pass.
857 */
858static DECLCALLBACK(int) picLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
859{
860 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
861
862 if (uVersion != 1)
863 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
864 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
865
866 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
867 {
868 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].last_irr);
869 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irr);
870 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].imr);
871 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].isr);
872 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].priority_add);
873 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].irq_base);
874 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].read_reg_select);
875 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].poll);
876 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_mask);
877 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init_state);
878 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].auto_eoi);
879 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].rotate_on_auto_eoi);
880 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].special_fully_nested_mode);
881 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].init4);
882 SSMR3GetU8(pSSMHandle, &pThis->aPics[i].elcr);
883 }
884 return VINF_SUCCESS;
885}
886
887
888/* -=-=-=-=-=- real code -=-=-=-=-=- */
889
890/**
891 * Reset notification.
892 *
893 * @returns VBox status.
894 * @param pDevIns The device instance data.
895 */
896static DECLCALLBACK(void) picReset(PPDMDEVINS pDevIns)
897{
898 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
899 unsigned i;
900 LogFlow(("picReset:\n"));
901 pThis->pPicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
902
903 for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
904 pic_reset(&pThis->aPics[i]);
905
906 PIC_UNLOCK(pThis);
907}
908
909
910/**
911 * @copydoc FNPDMDEVRELOCATE
912 */
913static DECLCALLBACK(void) picRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
914{
915 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
916 unsigned i;
917
918 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
919 pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
920 for (i = 0; i < RT_ELEMENTS(pThis->aPics); i++)
921 pThis->aPics[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
922}
923
924
925/**
926 * @copydoc FNPDMDEVCONSTRUCT
927 */
928static DECLCALLBACK(int) picConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
929{
930 PDEVPIC pThis = PDMINS_2_DATA(pDevIns, PDEVPIC);
931 PDMPICREG PicReg;
932 int rc;
933 bool fGCEnabled;
934 bool fR0Enabled;
935 Assert(iInstance == 0);
936
937 /*
938 * Validate and read configuration.
939 */
940 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
941 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
942
943 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
944 if (RT_FAILURE(rc))
945 return PDMDEV_SET_ERROR(pDevIns, rc,
946 N_("Configuration error: failed to read GCEnabled as boolean"));
947
948 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
949 if (RT_FAILURE(rc))
950 return PDMDEV_SET_ERROR(pDevIns, rc,
951 N_("Configuration error: failed to read R0Enabled as boolean"));
952
953 Log(("DevPIC: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
954
955 /*
956 * Init the data.
957 */
958 Assert(RT_ELEMENTS(pThis->aPics) == 2);
959 pThis->pDevInsR3 = pDevIns;
960 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
961 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
962 pThis->aPics[0].elcr_mask = 0xf8;
963 pThis->aPics[1].elcr_mask = 0xde;
964 pThis->aPics[0].pDevInsR3 = pDevIns;
965 pThis->aPics[1].pDevInsR3 = pDevIns;
966 pThis->aPics[0].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
967 pThis->aPics[1].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
968 pThis->aPics[0].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
969 pThis->aPics[1].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
970 pThis->cRelLogEntries = 0;
971
972 /*
973 * Register us as the PIC with PDM.
974 */
975 PicReg.u32Version = PDM_PICREG_VERSION;
976 PicReg.pfnSetIrqR3 = picSetIrq;
977 PicReg.pfnGetInterruptR3 = picGetInterrupt;
978
979 if (fGCEnabled)
980 {
981 PicReg.pszSetIrqRC = "picSetIrq";
982 PicReg.pszGetInterruptRC = "picGetInterrupt";
983 }
984 else
985 {
986 PicReg.pszSetIrqRC = NULL;
987 PicReg.pszGetInterruptRC = NULL;
988 }
989
990 if (fR0Enabled)
991 {
992 PicReg.pszSetIrqR0 = "picSetIrq";
993 PicReg.pszGetInterruptR0 = "picGetInterrupt";
994 }
995 else
996 {
997 PicReg.pszSetIrqR0 = NULL;
998 PicReg.pszGetInterruptR0 = NULL;
999 }
1000
1001 rc = PDMDevHlpPICRegister(pDevIns, &PicReg, &pThis->pPicHlpR3);
1002 AssertLogRelMsgRCReturn(rc, ("PICRegister -> %Rrc\n", rc), rc);
1003 if (fGCEnabled)
1004 pThis->pPicHlpRC = pThis->pPicHlpR3->pfnGetRCHelpers(pDevIns);
1005 if (fR0Enabled)
1006 pThis->pPicHlpR0 = pThis->pPicHlpR3->pfnGetR0Helpers(pDevIns);
1007
1008 /*
1009 * Since the PIC helper interface provides access to the PDM lock,
1010 * we need no device level critical section.
1011 */
1012 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1013 AssertRCReturn(rc, rc);
1014
1015 /*
1016 * Register I/O ports and save state.
1017 */
1018 rc = PDMDevHlpIOPortRegister(pDevIns, 0x20, 2, (void *)0, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #0");
1019 if (RT_FAILURE(rc))
1020 return rc;
1021 rc = PDMDevHlpIOPortRegister(pDevIns, 0xa0, 2, (void *)1, picIOPortWrite, picIOPortRead, NULL, NULL, "i8259 PIC #1");
1022 if (RT_FAILURE(rc))
1023 return rc;
1024 if (fGCEnabled)
1025 {
1026 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1027 if (RT_FAILURE(rc))
1028 return rc;
1029 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1030 if (RT_FAILURE(rc))
1031 return rc;
1032 }
1033 if (fR0Enabled)
1034 {
1035 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x20, 2, 0, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #0");
1036 if (RT_FAILURE(rc))
1037 return rc;
1038 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xa0, 2, 1, "picIOPortWrite", "picIOPortRead", NULL, NULL, "i8259 PIC #1");
1039 if (RT_FAILURE(rc))
1040 return rc;
1041 }
1042
1043 rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d0, 1, &pThis->aPics[0],
1044 picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #0 - elcr");
1045 if (RT_FAILURE(rc))
1046 return rc;
1047 rc = PDMDevHlpIOPortRegister(pDevIns, 0x4d1, 1, &pThis->aPics[1],
1048 picIOPortElcrWrite, picIOPortElcrRead, NULL, NULL, "i8259 PIC #1 - elcr");
1049 if (RT_FAILURE(rc))
1050 return rc;
1051 if (fGCEnabled)
1052 {
1053 RTRCPTR pDataRC = PDMINS_2_DATA_RCPTR(pDevIns);
1054 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d0, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[0]),
1055 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1056 if (RT_FAILURE(rc))
1057 return rc;
1058 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x4d1, 1, pDataRC + RT_OFFSETOF(DEVPIC, aPics[1]),
1059 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1060 if (RT_FAILURE(rc))
1061 return rc;
1062 }
1063 if (fR0Enabled)
1064 {
1065 RTR0PTR pDataR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1066 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d0, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[0]),
1067 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #0 - elcr");
1068 if (RT_FAILURE(rc))
1069 return rc;
1070 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x4d1, 1, pDataR0 + RT_OFFSETOF(DEVPIC, aPics[1]),
1071 "picIOPortElcrWrite", "picIOPortElcrRead", NULL, NULL, "i8259 PIC #1 - elcr");
1072 if (RT_FAILURE(rc))
1073 return rc;
1074 }
1075
1076 rc = PDMDevHlpSSMRegister(pDevIns, 1 /* uVersion */, sizeof(*pThis), picSaveExec, picLoadExec);
1077 if (RT_FAILURE(rc))
1078 return rc;
1079
1080
1081 /*
1082 * Register the info item.
1083 */
1084 PDMDevHlpDBGFInfoRegister(pDevIns, "pic", "PIC info.", picInfo);
1085
1086 /*
1087 * Initialize the device state.
1088 */
1089 picReset(pDevIns);
1090
1091#ifdef VBOX_WITH_STATISTICS
1092 /*
1093 * Statistics.
1094 */
1095 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in GC.");
1096 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/PIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of PIC SetIrq calls in HC.");
1097
1098 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIRQ2, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveIRQ2", STAMUNIT_OCCURENCES, "Number of cleared irq 2.");
1099 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveMasterIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveMaster", STAMUNIT_OCCURENCES, "Number of cleared master irqs.");
1100 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveSlaveIRQ, STAMTYPE_COUNTER, "/Devices/PIC/Masked/ActiveSlave", STAMUNIT_OCCURENCES, "Number of cleared slave irqs.");
1101#endif
1102
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/**
1108 * The device registration structure.
1109 */
1110const PDMDEVREG g_DeviceI8259 =
1111{
1112 /* u32Version */
1113 PDM_DEVREG_VERSION,
1114 /* szName */
1115 "i8259",
1116 /* szRCMod */
1117 "VBoxDDGC.gc",
1118 /* szR0Mod */
1119 "VBoxDDR0.r0",
1120 /* pszDescription */
1121 "Intel 8259 Programmable Interrupt Controller (PIC) Device.",
1122 /* fFlags */
1123 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1124 /* fClass */
1125 PDM_DEVREG_CLASS_PIC,
1126 /* cMaxInstances */
1127 1,
1128 /* cbInstance */
1129 sizeof(DEVPIC),
1130 /* pfnConstruct */
1131 picConstruct,
1132 /* pfnDestruct */
1133 NULL,
1134 /* pfnRelocate */
1135 picRelocate,
1136 /* pfnIOCtl */
1137 NULL,
1138 /* pfnPowerOn */
1139 NULL,
1140 /* pfnReset */
1141 picReset,
1142 /* pfnSuspend */
1143 NULL,
1144 /* pfnResume */
1145 NULL,
1146 /* pfnAttach */
1147 NULL,
1148 /* pfnDetach */
1149 NULL,
1150 /* pfnQueryInterface. */
1151 NULL,
1152 /* pfnInitComplete */
1153 NULL,
1154 /* pfnPowerOff */
1155 NULL,
1156 /* pfnSoftReset */
1157 NULL,
1158 /* u32VersionEnd */
1159 PDM_DEVREG_VERSION
1160};
1161
1162#endif /* IN_RING3 */
1163#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1164
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