1 | /* $Id: DevLpc.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
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2 | /** @file
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3 | * DevLPC - Minimal ICH9 LPC device emulation.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2018-2023 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * SPDX-License-Identifier: GPL-3.0-only
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #define LOG_GROUP LOG_GROUP_DEV_LPC
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33 | #include <VBox/vmm/pdmdev.h>
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34 | #include <VBox/vmm/stam.h>
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35 | #include <VBox/log.h>
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36 |
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37 | #include <iprt/assert.h>
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38 | #include <iprt/string.h>
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39 |
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40 | #include "VBoxDD.h"
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41 |
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42 |
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43 | /*********************************************************************************************************************************
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44 | * Defined Constants And Macros *
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45 | *********************************************************************************************************************************/
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46 | #define LPC_REG_HPET_CONFIG_POINTER 0x3404
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47 | #define LPC_REG_GCS 0x3410
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48 |
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49 |
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50 | /*********************************************************************************************************************************
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51 | * Structures and Typedefs *
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52 | *********************************************************************************************************************************/
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53 | /**
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54 | * The ICH9 LPC state.
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55 | */
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56 | typedef struct LPCSTATE
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57 | {
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58 | /** The root complex base address. */
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59 | RTGCPHYS32 GCPhys32Rcba;
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60 | /** The ICH version (7 or 9). */
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61 | uint8_t uIchVersion;
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62 | /** Explicit padding. */
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63 | uint8_t abPadding[HC_ARCH_BITS == 32 ? 3 : 7];
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64 |
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65 | /** Number of MMIO reads. */
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66 | STAMCOUNTER StatMmioReads;
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67 | /** Number of MMIO writes. */
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68 | STAMCOUNTER StatMmioWrites;
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69 | /** Number of PCI config space reads. */
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70 | STAMCOUNTER StatPciCfgReads;
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71 | /** Number of PCI config space writes. */
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72 | STAMCOUNTER StatPciCfgWrites;
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73 |
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74 | /** Handle to the MMIO region. */
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75 | IOMMMIOHANDLE hMmio;
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76 | } LPCSTATE;
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77 | /** Pointer to the LPC state. */
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78 | typedef LPCSTATE *PLPCSTATE;
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79 |
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80 |
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81 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
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82 |
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83 | /**
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84 | * @callback_method_impl{FNIOMMMIONEWREAD}
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85 | */
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86 | static DECLCALLBACK(VBOXSTRICTRC) lpcMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
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87 | {
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88 | RT_NOREF(pvUser, cb);
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89 | PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
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90 | Assert(cb == 4); Assert(!(off & 3)); /* IOMMMIO_FLAGS_READ_DWORD should make sure of this */
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91 |
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92 | uint32_t *puValue = (uint32_t *)pv;
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93 | if (off == LPC_REG_HPET_CONFIG_POINTER)
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94 | {
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95 | *puValue = 0xf0;
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96 | Log(("lpcMmioRead: HPET_CONFIG_POINTER: %#x\n", *puValue));
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97 | }
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98 | else if (off == LPC_REG_GCS)
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99 | {
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100 | *puValue = 0;
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101 | Log(("lpcMmioRead: GCS: %#x\n", *puValue));
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102 | }
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103 | else
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104 | {
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105 | *puValue = 0;
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106 | Log(("lpcMmioRead: WARNING! Unknown register %#RGp!\n", off));
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107 | }
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108 |
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109 | STAM_REL_COUNTER_INC(&pThis->StatMmioReads);
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110 | return VINF_SUCCESS;
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111 | }
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112 |
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113 |
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114 | /**
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115 | * @callback_method_impl{FNIOMMMIONEWWRITE}
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116 | */
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117 | static DECLCALLBACK(VBOXSTRICTRC) lpcMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
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118 | {
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119 | PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
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120 | RT_NOREF(pvUser, pv);
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121 |
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122 | if (cb == 4)
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123 | {
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124 | if (off == LPC_REG_GCS)
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125 | Log(("lpcMmioWrite: Ignorning write to GCS: %.*Rhxs\n", cb, pv));
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126 | else
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127 | Log(("lpcMmioWrite: Ignorning write to unknown register %#RGp: %.*Rhxs\n", off, cb, pv));
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128 | }
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129 | else
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130 | Log(("lpcMmioWrite: WARNING! Ignoring non-DWORD write to off=%#RGp: %.*Rhxs\n", off, cb, pv));
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131 |
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132 | STAM_REL_COUNTER_INC(&pThis->StatMmioWrites);
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133 | return VINF_SUCCESS;
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134 | }
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135 |
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136 | #ifdef IN_RING3
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137 |
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138 | /**
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139 | * @callback_method_impl{FNPCICONFIGREAD}
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140 | */
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141 | static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
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142 | uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
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143 | {
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144 | PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
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145 | Assert(pPciDev == pDevIns->apPciDevs[0]);
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146 |
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147 | STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
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148 | VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
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149 | switch (cb)
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150 | {
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151 | case 1: Log(("lpcR3PciConfigRead: %#04x -> %#04x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
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152 | case 2: Log(("lpcR3PciConfigRead: %#04x -> %#06x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
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153 | case 4: Log(("lpcR3PciConfigRead: %#04x -> %#010x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
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154 | }
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155 | return rcStrict;
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156 | }
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157 |
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158 |
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159 | /**
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160 | * @callback_method_impl{FNPCICONFIGWRITE}
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161 | */
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162 | static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
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163 | uint32_t uAddress, unsigned cb, uint32_t u32Value)
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164 | {
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165 | PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
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166 | Assert(pPciDev == pDevIns->apPciDevs[0]);
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167 |
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168 | STAM_REL_COUNTER_INC(&pThis->StatPciCfgWrites);
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169 | switch (cb)
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170 | {
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171 | case 1: Log(("lpcR3PciConfigWrite: %#04x <- %#04x\n", uAddress, u32Value)); break;
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172 | case 2: Log(("lpcR3PciConfigWrite: %#04x <- %#06x\n", uAddress, u32Value)); break;
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173 | case 4: Log(("lpcR3PciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
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174 | }
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175 |
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176 | return PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
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177 | }
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178 |
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179 |
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180 | /**
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181 | * Info handler, device version.
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182 | *
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183 | * @param pDevIns Device instance which registered the info.
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184 | * @param pHlp Callback functions for doing output.
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185 | * @param pszArgs Argument string. Optional and specific to the handler.
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186 | */
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187 | static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
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188 | {
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189 | PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
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190 | PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
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191 | RT_NOREF(pszArgs);
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192 |
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193 | if (pThis->uIchVersion == 7)
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194 | {
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195 | uint8_t b1 = PDMPciDevGetByte(pPciDev, 0xde);
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196 | uint8_t b2 = PDMPciDevGetByte(pPciDev, 0xad);
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197 | if ( b1 == 0xbe
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198 | && b2 == 0xef)
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199 | pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
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200 | else
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201 | pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", b1, b2);
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202 | }
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203 |
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204 | for (unsigned iLine = 0; iLine < 8; iLine++)
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205 | {
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206 | unsigned offBase = iLine < 4 ? 0x60 : 0x68 - 4;
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207 | uint8_t bMap = PDMPciDevGetByte(pPciDev, offBase + iLine);
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208 | if (bMap & 0x80)
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209 | pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT disabled\n", 'A' + iLine);
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210 | else
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211 | pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT -> IRQ%d\n", 'A' + iLine, bMap & 0xf);
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212 | }
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213 | }
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214 |
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215 |
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216 | /**
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217 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
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218 | */
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219 | static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
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220 | {
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221 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
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222 | PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
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223 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
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224 | Assert(iInstance == 0); RT_NOREF(iInstance);
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225 |
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226 | /*
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227 | * Read configuration.
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228 | */
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229 | PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RCBA|ICHVersion", "");
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230 |
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231 | int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ICHVersion", &pThis->uIchVersion, 7 /** @todo 9 */);
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232 | if (RT_FAILURE(rc))
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233 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ICHVersion\""));
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234 | if ( pThis->uIchVersion != 7
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235 | && pThis->uIchVersion != 9)
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236 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Invalid \"ICHVersion\" value (must be 7 or 9)"));
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237 |
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238 | rc = pHlp->pfnCFGMQueryU32Def(pCfg, "RCBA", &pThis->GCPhys32Rcba, UINT32_C(0xfed1c000));
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239 | if (RT_FAILURE(rc))
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240 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RCBA\""));
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241 |
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242 |
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243 | /*
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244 | * Register the PCI device.
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245 | *
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246 | * See sections 13.1 (page 371) and section 13.8.1 (page 429) in the ICH9
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247 | * specification.
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248 | *
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249 | * We set these up so they don't need much/any configuration from the
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250 | * guest. This is quite possibly wrong, but at the moment we just need to
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251 | * have this device working w/o lots of firmware fun.
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252 | */
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253 | PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
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254 | PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
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255 |
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256 | PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
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257 | if (pThis->uIchVersion == 7)
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258 | PDMPciDevSetDeviceId(pPciDev, 0x27b9);
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259 | else if (pThis->uIchVersion == 9)
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260 | PDMPciDevSetDeviceId(pPciDev, 0x2918); /** @todo unsure if 0x2918 is the right PCI ID... */
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261 | else
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262 | AssertFailedReturn(VERR_INTERNAL_ERROR_3);
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263 | PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
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264 | PDMPciDevSetStatus(pPciDev, 0x0210); /* Note! Used to be 0x0200 for ICH7. */
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265 | PDMPciDevSetRevisionId(pPciDev, 0x02);
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266 | PDMPciDevSetClassSub(pPciDev, 0x01); /* PCI-to-ISA bridge */
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267 | PDMPciDevSetClassBase(pPciDev, 0x06); /* bridge */
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268 | PDMPciDevSetHeaderType(pPciDev, 0x80); /* Normal, multifunction device (so that other devices can be its functions) */
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269 | if (pThis->uIchVersion == 7)
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270 | {
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271 | PDMPciDevSetSubSystemVendorId(pPciDev, 0x8086);
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272 | PDMPciDevSetSubSystemId(pPciDev, 0x7270);
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273 | }
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274 | else if (pThis->uIchVersion == 9)
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275 | {
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276 | PDMPciDevSetSubSystemVendorId(pPciDev, 0x0000); /** @todo docs stays subsystem IDs are zero, check real HW */
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277 | PDMPciDevSetSubSystemId(pPciDev, 0x0000);
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278 | }
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279 | PDMPciDevSetInterruptPin(pPciDev, 0x00); /* The LPC device itself generates no interrupts */
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280 | PDMPciDevSetDWord(pPciDev, 0x40, 0x00008001); /* PMBASE: ACPI base address; (PM_PORT_BASE (?) * 2 | PCI_ADDRESS_SPACE_IO) */
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281 | PDMPciDevSetByte(pPciDev, 0x44, 0x80); /* ACPI_CNTL: SCI is IRQ9, ACPI enabled */ /** @todo documented as defaulting to 0x00. */
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282 | PDMPciDevSetDWord(pPciDev, 0x48, 0x00000001); /* GPIOBASE (note: used to be zero) */
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283 | PDMPciDevSetByte(pPciDev, 0x4c, 0x4d); /* GC - GPIO control: ??? */ /** @todo documented as defaulting to 0x00. */
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284 | if (pThis->uIchVersion == 7)
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285 | PDMPciDevSetByte(pPciDev, 0x4e, 0x03); /* ??? */
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286 | PDMPciDevSetByte(pPciDev, 0x60, 0x0b); /* PIRQA_ROUT: PCI A -> IRQ 11 (documented default is 0x80) */
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287 | PDMPciDevSetByte(pPciDev, 0x61, 0x09); /* PIRQB_ROUT: PCI B -> IRQ 9 (documented default is 0x80) */
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288 | PDMPciDevSetByte(pPciDev, 0x62, 0x0b); /* PIRQC_ROUT: PCI C -> IRQ 11 (documented default is 0x80) */
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289 | PDMPciDevSetByte(pPciDev, 0x63, 0x09); /* PIRQD_ROUT: PCI D -> IRQ 9 (documented default is 0x80) */
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290 | PDMPciDevSetByte(pPciDev, 0x64, 0x10); /* SIRQ_CNTL: Serial IRQ Control 10h R/W, RO */
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291 | PDMPciDevSetByte(pPciDev, 0x68, 0x80); /* PIRQE_ROUT */
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292 | PDMPciDevSetByte(pPciDev, 0x69, 0x80); /* PIRQF_ROUT */
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293 | PDMPciDevSetByte(pPciDev, 0x6a, 0x80); /* PIRQG_ROUT */
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294 | PDMPciDevSetByte(pPciDev, 0x6b, 0x80); /* PIRQH_ROUT */
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295 | PDMPciDevSetWord(pPciDev, 0x6c, 0x00f8); /* IPC_IBDF: IOxAPIC bus:device:function. (Note! Used to be zero.) */
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296 | if (pThis->uIchVersion == 7)
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297 | {
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298 | /* No idea what this is/was yet: */
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299 | PDMPciDevSetByte(pPciDev, 0x70, 0x80);
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300 | PDMPciDevSetByte(pPciDev, 0x76, 0x0c);
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301 | PDMPciDevSetByte(pPciDev, 0x77, 0x0c);
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302 | PDMPciDevSetByte(pPciDev, 0x78, 0x02);
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303 | PDMPciDevSetByte(pPciDev, 0x79, 0x00);
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304 | }
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305 | PDMPciDevSetWord(pPciDev, 0x80, 0x0000); /* LPC_I/O_DEC: I/O decode ranges. */
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306 | PDMPciDevSetWord(pPciDev, 0x82, 0x0000); /* LPC_EN: LPC I/F enables. */
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307 | PDMPciDevSetDWord(pPciDev, 0x84, 0x00000000); /* GEN1_DEC: LPC I/F generic decode range 1. */
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308 | PDMPciDevSetDWord(pPciDev, 0x88, 0x00000000); /* GEN2_DEC: LPC I/F generic decode range 2. */
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309 | PDMPciDevSetDWord(pPciDev, 0x8c, 0x00000000); /* GEN3_DEC: LPC I/F generic decode range 3. */
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310 | PDMPciDevSetDWord(pPciDev, 0x90, 0x00000000); /* GEN4_DEC: LPC I/F generic decode range 4. */
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311 |
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312 | PDMPciDevSetWord(pPciDev, 0xa0, 0x0008); /* GEN_PMCON_1: Documented default is 0x0000 */
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313 | PDMPciDevSetByte(pPciDev, 0xa2, 0x00); /* GEN_PMON_2: */
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314 | PDMPciDevSetByte(pPciDev, 0xa4, 0x00); /* GEN_PMON_3: */
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315 | PDMPciDevSetByte(pPciDev, 0xa6, 0x00); /* GEN_PMON_LOCK: Configuration lock. */
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316 | if (pThis->uIchVersion == 7)
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317 | PDMPciDevSetByte(pPciDev, 0xa8, 0x0f); /* Is this part of GEN_PMON_LOCK? */
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318 | PDMPciDevSetByte(pPciDev, 0xab, 0x00); /* BM_BREAK_EN */
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319 | PDMPciDevSetDWord(pPciDev, 0xac, 0x00000000); /* PMIR: Power */
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320 | PDMPciDevSetDWord(pPciDev, 0xb8, 0x00000000); /* GPI_ROUT: GPI Route Control */
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321 | if (pThis->uIchVersion == 9)
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322 | {
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323 | /** @todo the next two values looks bogus. */
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324 | PDMPciDevSetDWord(pPciDev, 0xd0, 0x00112233); /* FWH_SEL1: Firmware Hub Select 1 */
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325 | PDMPciDevSetWord(pPciDev, 0xd4, 0x4567); /* FWH_SEL2: Firmware Hub Select 2 */
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326 | PDMPciDevSetWord(pPciDev, 0xd8, 0xffcf); /* FWH_DEC_EN1: Firmware Hub Decode Enable 1 */
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327 | PDMPciDevSetByte(pPciDev, 0xdc, 0x00); /* BIOS_CNTL: BIOS control */
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328 | PDMPciDevSetWord(pPciDev, 0xe0, 0x0009); /* FDCAP: Feature Detection Capability ID */
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329 | PDMPciDevSetByte(pPciDev, 0xe2, 0x0c); /* FDLEN: Feature Detection Capability Length */
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330 | PDMPciDevSetByte(pPciDev, 0xe3, 0x10); /* FDVER: Feature Detection Version */
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331 | PDMPciDevSetByte(pPciDev, 0xe4, 0x20); /* FDVCT[0]: 5=SATA RAID 0/1/5/10 capability (1=disabled) */
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332 | PDMPciDevSetByte(pPciDev, 0xe5, 0x00); /* FDVCT[1]: */
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333 | PDMPciDevSetByte(pPciDev, 0xe6, 0x00); /* FDVCT[2]: */
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334 | PDMPciDevSetByte(pPciDev, 0xe7, 0x00); /* FDVCT[3]: */
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335 | PDMPciDevSetByte(pPciDev, 0xe8, 0xc0); /* FDVCT[4]: 6-7=Intel active magament technology capability (11=disabled). */
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336 | PDMPciDevSetByte(pPciDev, 0xe9, 0x00); /* FDVCT[5]: */
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337 | PDMPciDevSetByte(pPciDev, 0xea, 0x00); /* FDVCT[6]: */
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338 | PDMPciDevSetByte(pPciDev, 0xeb, 0x00); /* FDVCT[7]: */
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339 | PDMPciDevSetByte(pPciDev, 0xec, 0x00); /* FDVCT[8]: */
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340 | PDMPciDevSetByte(pPciDev, 0xed, 0x00); /* FDVCT[9]: */
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341 | PDMPciDevSetByte(pPciDev, 0xee, 0x00); /* FDVCT[a]: */
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342 | PDMPciDevSetByte(pPciDev, 0xef, 0x00); /* FDVCT[b]: */
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343 | }
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344 |
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345 | /* RCBA: Root complex base address (documented default is 0x00000000). Bit 0 is enable bit. */
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346 | Assert(!(pThis->GCPhys32Rcba & 0x3fff)); /* 16KB aligned */
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347 | PDMPciDevSetDWord(pPciDev, 0xf0, pThis->GCPhys32Rcba | 1);
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348 |
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349 | rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_NOT_MANDATORY_NO, 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
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350 | AssertRCReturn(rc, rc);
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351 | rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, lpcR3PciConfigRead, lpcR3PciConfigWrite);
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352 | AssertRCReturn(rc, rc);
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353 |
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354 | /*
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355 | * Register the MMIO regions.
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356 | */
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357 | /** @todo This should actually be done when RCBA is enabled, but was
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358 | * mentioned above we just want this working. */
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359 | rc = PDMDevHlpMmioCreateAndMap(pDevIns, pThis->GCPhys32Rcba, 0x4000, lpcMmioWrite, lpcMmioRead,
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360 | IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
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361 | "LPC Memory", &pThis->hMmio);
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362 | AssertRCReturn(rc, rc);
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363 |
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364 |
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365 | /*
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366 | * Debug info and stats.
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367 | */
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368 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReads, STAMTYPE_COUNTER, "MMIOReads", STAMUNIT_OCCURENCES, "MMIO reads");
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369 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWrites, STAMTYPE_COUNTER, "MMIOWrites", STAMUNIT_OCCURENCES, "MMIO writes");
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370 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgReads, STAMTYPE_COUNTER, "ConfigReads", STAMUNIT_OCCURENCES, "PCI config reads");
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371 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgWrites, STAMTYPE_COUNTER, "ConfigWrites", STAMUNIT_OCCURENCES, "PCI config writes");
|
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372 |
|
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373 | PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
|
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374 |
|
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375 | return VINF_SUCCESS;
|
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376 | }
|
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377 |
|
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378 | #endif /* IN_RING3 */
|
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379 |
|
---|
380 | /**
|
---|
381 | * The device registration structure.
|
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382 | */
|
---|
383 | const PDMDEVREG g_DeviceLPC =
|
---|
384 | {
|
---|
385 | /* .u32Version = */ PDM_DEVREG_VERSION,
|
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386 | /* .uReserved0 = */ 0,
|
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387 | /* .szName = */ "lpc",
|
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388 | /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_NEW_STYLE,
|
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389 | /* .fClass = */ PDM_DEVREG_CLASS_MISC,
|
---|
390 | /* .cMaxInstances = */ 1,
|
---|
391 | /* .uSharedVersion = */ 42,
|
---|
392 | /* .cbInstanceShared = */ sizeof(LPCSTATE),
|
---|
393 | /* .cbInstanceCC = */ 0,
|
---|
394 | /* .cbInstanceRC = */ 0,
|
---|
395 | /* .cMaxPciDevices = */ 1,
|
---|
396 | /* .cMaxMsixVectors = */ 0,
|
---|
397 | /* .pszDescription = */ "Low Pin Count (LPC) Bus",
|
---|
398 | #if defined(IN_RING3)
|
---|
399 | /* .pszRCMod = */ "",
|
---|
400 | /* .pszR0Mod = */ "",
|
---|
401 | /* .pfnConstruct = */ lpcConstruct,
|
---|
402 | /* .pfnDestruct = */ NULL,
|
---|
403 | /* .pfnRelocate = */ NULL,
|
---|
404 | /* .pfnMemSetup = */ NULL,
|
---|
405 | /* .pfnPowerOn = */ NULL,
|
---|
406 | /* .pfnReset = */ NULL,
|
---|
407 | /* .pfnSuspend = */ NULL,
|
---|
408 | /* .pfnResume = */ NULL,
|
---|
409 | /* .pfnAttach = */ NULL,
|
---|
410 | /* .pfnDetach = */ NULL,
|
---|
411 | /* .pfnQueryInterface = */ NULL,
|
---|
412 | /* .pfnInitComplete = */ NULL,
|
---|
413 | /* .pfnPowerOff = */ NULL,
|
---|
414 | /* .pfnSoftReset = */ NULL,
|
---|
415 | /* .pfnReserved0 = */ NULL,
|
---|
416 | /* .pfnReserved1 = */ NULL,
|
---|
417 | /* .pfnReserved2 = */ NULL,
|
---|
418 | /* .pfnReserved3 = */ NULL,
|
---|
419 | /* .pfnReserved4 = */ NULL,
|
---|
420 | /* .pfnReserved5 = */ NULL,
|
---|
421 | /* .pfnReserved6 = */ NULL,
|
---|
422 | /* .pfnReserved7 = */ NULL,
|
---|
423 | #elif defined(IN_RING0)
|
---|
424 | /* .pfnEarlyConstruct = */ NULL,
|
---|
425 | /* .pfnConstruct = */ NULL,
|
---|
426 | /* .pfnDestruct = */ NULL,
|
---|
427 | /* .pfnFinalDestruct = */ NULL,
|
---|
428 | /* .pfnRequest = */ NULL,
|
---|
429 | /* .pfnReserved0 = */ NULL,
|
---|
430 | /* .pfnReserved1 = */ NULL,
|
---|
431 | /* .pfnReserved2 = */ NULL,
|
---|
432 | /* .pfnReserved3 = */ NULL,
|
---|
433 | /* .pfnReserved4 = */ NULL,
|
---|
434 | /* .pfnReserved5 = */ NULL,
|
---|
435 | /* .pfnReserved6 = */ NULL,
|
---|
436 | /* .pfnReserved7 = */ NULL,
|
---|
437 | #elif defined(IN_RC)
|
---|
438 | /* .pfnConstruct = */ NULL,
|
---|
439 | /* .pfnReserved0 = */ NULL,
|
---|
440 | /* .pfnReserved1 = */ NULL,
|
---|
441 | /* .pfnReserved2 = */ NULL,
|
---|
442 | /* .pfnReserved3 = */ NULL,
|
---|
443 | /* .pfnReserved4 = */ NULL,
|
---|
444 | /* .pfnReserved5 = */ NULL,
|
---|
445 | /* .pfnReserved6 = */ NULL,
|
---|
446 | /* .pfnReserved7 = */ NULL,
|
---|
447 | #else
|
---|
448 | # error "Not in IN_RING3, IN_RING0 or IN_RC!"
|
---|
449 | #endif
|
---|
450 | /* .u32VersionEnd = */ PDM_DEVREG_VERSION
|
---|
451 | };
|
---|
452 |
|
---|
453 | #endif /* VBOX_DEVICE_STRUCT_TESTCASE */
|
---|
454 |
|
---|