VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevLpc.cpp

Last change on this file was 106061, checked in by vboxsync, 6 weeks ago

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[71829]1/* $Id: DevLpc.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * DevLPC - Minimal ICH9 LPC device emulation.
4 */
5
6/*
[106061]7 * Copyright (C) 2018-2024 Oracle and/or its affiliates.
[71829]8 *
[96407]9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
[71829]26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_LPC
33#include <VBox/vmm/pdmdev.h>
34#include <VBox/vmm/stam.h>
35#include <VBox/log.h>
36
37#include <iprt/assert.h>
38#include <iprt/string.h>
39
40#include "VBoxDD.h"
41
42
43/*********************************************************************************************************************************
44* Defined Constants And Macros *
45*********************************************************************************************************************************/
46#define LPC_REG_HPET_CONFIG_POINTER 0x3404
47#define LPC_REG_GCS 0x3410
48
49
50/*********************************************************************************************************************************
51* Structures and Typedefs *
52*********************************************************************************************************************************/
53/**
54 * The ICH9 LPC state.
55 */
56typedef struct LPCSTATE
57{
58 /** The root complex base address. */
59 RTGCPHYS32 GCPhys32Rcba;
60 /** The ICH version (7 or 9). */
61 uint8_t uIchVersion;
62 /** Explicit padding. */
[81933]63 uint8_t abPadding[HC_ARCH_BITS == 32 ? 3 : 7];
[71829]64
65 /** Number of MMIO reads. */
66 STAMCOUNTER StatMmioReads;
67 /** Number of MMIO writes. */
68 STAMCOUNTER StatMmioWrites;
69 /** Number of PCI config space reads. */
70 STAMCOUNTER StatPciCfgReads;
71 /** Number of PCI config space writes. */
72 STAMCOUNTER StatPciCfgWrites;
[81933]73
74 /** Handle to the MMIO region. */
75 IOMMMIOHANDLE hMmio;
[71829]76} LPCSTATE;
77/** Pointer to the LPC state. */
78typedef LPCSTATE *PLPCSTATE;
79
80
81#ifndef VBOX_DEVICE_STRUCT_TESTCASE
82
83/**
[81933]84 * @callback_method_impl{FNIOMMMIONEWREAD}
[71829]85 */
[81933]86static DECLCALLBACK(VBOXSTRICTRC) lpcMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
[71829]87{
[71831]88 RT_NOREF(pvUser, cb);
[81591]89 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
[81933]90 Assert(cb == 4); Assert(!(off & 3)); /* IOMMMIO_FLAGS_READ_DWORD should make sure of this */
[71829]91
92 uint32_t *puValue = (uint32_t *)pv;
[81933]93 if (off == LPC_REG_HPET_CONFIG_POINTER)
[71829]94 {
95 *puValue = 0xf0;
96 Log(("lpcMmioRead: HPET_CONFIG_POINTER: %#x\n", *puValue));
97 }
[81933]98 else if (off == LPC_REG_GCS)
[71829]99 {
100 *puValue = 0;
101 Log(("lpcMmioRead: GCS: %#x\n", *puValue));
102 }
103 else
104 {
105 *puValue = 0;
[81933]106 Log(("lpcMmioRead: WARNING! Unknown register %#RGp!\n", off));
[71829]107 }
108
109 STAM_REL_COUNTER_INC(&pThis->StatMmioReads);
110 return VINF_SUCCESS;
111}
112
113
114/**
[81933]115 * @callback_method_impl{FNIOMMMIONEWWRITE}
[71829]116 */
[81933]117static DECLCALLBACK(VBOXSTRICTRC) lpcMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
[71829]118{
[81933]119 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
[104289]120 RT_NOREF(pvUser, pv, cb);
121 Assert(cb == 4); Assert(!(off & 3)); /* IOMMMIO_FLAGS_WRITE_DWORD_xxx should make sure of this */
[71829]122
[104289]123 if (off == LPC_REG_GCS)
124 Log(("lpcMmioWrite: Ignorning write to GCS: %.*Rhxs\n", cb, pv));
[71829]125 else
[104289]126 Log(("lpcMmioWrite: Ignorning write to unknown register %#RGp: %.*Rhxs\n", off, cb, pv));
[71829]127
128 STAM_REL_COUNTER_INC(&pThis->StatMmioWrites);
129 return VINF_SUCCESS;
130}
131
132#ifdef IN_RING3
133
134/**
135 * @callback_method_impl{FNPCICONFIGREAD}
136 */
[80943]137static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
138 uint32_t uAddress, unsigned cb, uint32_t *pu32Value)
[71829]139{
[81591]140 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
[81031]141 Assert(pPciDev == pDevIns->apPciDevs[0]);
[71829]142
143 STAM_REL_COUNTER_INC(&pThis->StatPciCfgReads);
[80943]144 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
[71829]145 switch (cb)
146 {
[80943]147 case 1: Log(("lpcR3PciConfigRead: %#04x -> %#04x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
148 case 2: Log(("lpcR3PciConfigRead: %#04x -> %#06x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
149 case 4: Log(("lpcR3PciConfigRead: %#04x -> %#010x (%Rrc)\n", uAddress, *pu32Value, VBOXSTRICTRC_VAL(rcStrict))); break;
[71829]150 }
[80943]151 return rcStrict;
[71829]152}
153
154
155/**
156 * @callback_method_impl{FNPCICONFIGWRITE}
157 */
[80943]158static DECLCALLBACK(VBOXSTRICTRC) lpcR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
159 uint32_t uAddress, unsigned cb, uint32_t u32Value)
[71829]160{
[81591]161 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
[81031]162 Assert(pPciDev == pDevIns->apPciDevs[0]);
[71829]163
164 STAM_REL_COUNTER_INC(&pThis->StatPciCfgWrites);
165 switch (cb)
166 {
[80943]167 case 1: Log(("lpcR3PciConfigWrite: %#04x <- %#04x\n", uAddress, u32Value)); break;
168 case 2: Log(("lpcR3PciConfigWrite: %#04x <- %#06x\n", uAddress, u32Value)); break;
169 case 4: Log(("lpcR3PciConfigWrite: %#04x <- %#010x\n", uAddress, u32Value)); break;
[71829]170 }
171
[80943]172 return PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
[71829]173}
174
175
176/**
177 * Info handler, device version.
178 *
179 * @param pDevIns Device instance which registered the info.
180 * @param pHlp Callback functions for doing output.
181 * @param pszArgs Argument string. Optional and specific to the handler.
182 */
183static DECLCALLBACK(void) lpcInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
184{
[81591]185 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
[81031]186 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
[71829]187 RT_NOREF(pszArgs);
188
189 if (pThis->uIchVersion == 7)
190 {
[81031]191 uint8_t b1 = PDMPciDevGetByte(pPciDev, 0xde);
192 uint8_t b2 = PDMPciDevGetByte(pPciDev, 0xad);
[71829]193 if ( b1 == 0xbe
194 && b2 == 0xef)
195 pHlp->pfnPrintf(pHlp, "APIC backdoor activated\n");
196 else
197 pHlp->pfnPrintf(pHlp, "APIC backdoor closed: %02x %02x\n", b1, b2);
198 }
199
200 for (unsigned iLine = 0; iLine < 8; iLine++)
201 {
202 unsigned offBase = iLine < 4 ? 0x60 : 0x68 - 4;
[81031]203 uint8_t bMap = PDMPciDevGetByte(pPciDev, offBase + iLine);
[71829]204 if (bMap & 0x80)
205 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT disabled\n", 'A' + iLine);
206 else
207 pHlp->pfnPrintf(pHlp, "PIRQ%c_ROUT -> IRQ%d\n", 'A' + iLine, bMap & 0xf);
208 }
209}
210
211
212/**
213 * @interface_method_impl{PDMDEVREG,pfnConstruct}
214 */
215static DECLCALLBACK(int) lpcConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
216{
217 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
[81933]218 PLPCSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PLPCSTATE);
219 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
[71829]220 Assert(iInstance == 0); RT_NOREF(iInstance);
221
222 /*
223 * Read configuration.
224 */
[81933]225 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RCBA|ICHVersion", "");
[71829]226
[81933]227 int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ICHVersion", &pThis->uIchVersion, 7 /** @todo 9 */);
[71829]228 if (RT_FAILURE(rc))
229 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"ICHVersion\""));
230 if ( pThis->uIchVersion != 7
231 && pThis->uIchVersion != 9)
232 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Invalid \"ICHVersion\" value (must be 7 or 9)"));
233
[81933]234 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "RCBA", &pThis->GCPhys32Rcba, UINT32_C(0xfed1c000));
[71829]235 if (RT_FAILURE(rc))
236 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query boolean value \"RCBA\""));
237
238
239 /*
240 * Register the PCI device.
241 *
242 * See sections 13.1 (page 371) and section 13.8.1 (page 429) in the ICH9
243 * specification.
244 *
245 * We set these up so they don't need much/any configuration from the
246 * guest. This is quite possibly wrong, but at the moment we just need to
247 * have this device working w/o lots of firmware fun.
248 */
[81031]249 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
250 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
251
252 PDMPciDevSetVendorId(pPciDev, 0x8086); /* Intel */
[71829]253 if (pThis->uIchVersion == 7)
[81031]254 PDMPciDevSetDeviceId(pPciDev, 0x27b9);
[71829]255 else if (pThis->uIchVersion == 9)
[81031]256 PDMPciDevSetDeviceId(pPciDev, 0x2918); /** @todo unsure if 0x2918 is the right PCI ID... */
[71829]257 else
258 AssertFailedReturn(VERR_INTERNAL_ERROR_3);
[81031]259 PDMPciDevSetCommand(pPciDev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
260 PDMPciDevSetStatus(pPciDev, 0x0210); /* Note! Used to be 0x0200 for ICH7. */
261 PDMPciDevSetRevisionId(pPciDev, 0x02);
262 PDMPciDevSetClassSub(pPciDev, 0x01); /* PCI-to-ISA bridge */
263 PDMPciDevSetClassBase(pPciDev, 0x06); /* bridge */
264 PDMPciDevSetHeaderType(pPciDev, 0x80); /* Normal, multifunction device (so that other devices can be its functions) */
[71829]265 if (pThis->uIchVersion == 7)
266 {
[81031]267 PDMPciDevSetSubSystemVendorId(pPciDev, 0x8086);
268 PDMPciDevSetSubSystemId(pPciDev, 0x7270);
[71829]269 }
270 else if (pThis->uIchVersion == 9)
271 {
[81031]272 PDMPciDevSetSubSystemVendorId(pPciDev, 0x0000); /** @todo docs stays subsystem IDs are zero, check real HW */
273 PDMPciDevSetSubSystemId(pPciDev, 0x0000);
[71829]274 }
[81031]275 PDMPciDevSetInterruptPin(pPciDev, 0x00); /* The LPC device itself generates no interrupts */
276 PDMPciDevSetDWord(pPciDev, 0x40, 0x00008001); /* PMBASE: ACPI base address; (PM_PORT_BASE (?) * 2 | PCI_ADDRESS_SPACE_IO) */
277 PDMPciDevSetByte(pPciDev, 0x44, 0x80); /* ACPI_CNTL: SCI is IRQ9, ACPI enabled */ /** @todo documented as defaulting to 0x00. */
278 PDMPciDevSetDWord(pPciDev, 0x48, 0x00000001); /* GPIOBASE (note: used to be zero) */
279 PDMPciDevSetByte(pPciDev, 0x4c, 0x4d); /* GC - GPIO control: ??? */ /** @todo documented as defaulting to 0x00. */
[71829]280 if (pThis->uIchVersion == 7)
[81031]281 PDMPciDevSetByte(pPciDev, 0x4e, 0x03); /* ??? */
282 PDMPciDevSetByte(pPciDev, 0x60, 0x0b); /* PIRQA_ROUT: PCI A -> IRQ 11 (documented default is 0x80) */
283 PDMPciDevSetByte(pPciDev, 0x61, 0x09); /* PIRQB_ROUT: PCI B -> IRQ 9 (documented default is 0x80) */
284 PDMPciDevSetByte(pPciDev, 0x62, 0x0b); /* PIRQC_ROUT: PCI C -> IRQ 11 (documented default is 0x80) */
285 PDMPciDevSetByte(pPciDev, 0x63, 0x09); /* PIRQD_ROUT: PCI D -> IRQ 9 (documented default is 0x80) */
286 PDMPciDevSetByte(pPciDev, 0x64, 0x10); /* SIRQ_CNTL: Serial IRQ Control 10h R/W, RO */
287 PDMPciDevSetByte(pPciDev, 0x68, 0x80); /* PIRQE_ROUT */
288 PDMPciDevSetByte(pPciDev, 0x69, 0x80); /* PIRQF_ROUT */
289 PDMPciDevSetByte(pPciDev, 0x6a, 0x80); /* PIRQG_ROUT */
290 PDMPciDevSetByte(pPciDev, 0x6b, 0x80); /* PIRQH_ROUT */
291 PDMPciDevSetWord(pPciDev, 0x6c, 0x00f8); /* IPC_IBDF: IOxAPIC bus:device:function. (Note! Used to be zero.) */
[71829]292 if (pThis->uIchVersion == 7)
293 {
294 /* No idea what this is/was yet: */
[81031]295 PDMPciDevSetByte(pPciDev, 0x70, 0x80);
296 PDMPciDevSetByte(pPciDev, 0x76, 0x0c);
297 PDMPciDevSetByte(pPciDev, 0x77, 0x0c);
298 PDMPciDevSetByte(pPciDev, 0x78, 0x02);
299 PDMPciDevSetByte(pPciDev, 0x79, 0x00);
[71829]300 }
[81031]301 PDMPciDevSetWord(pPciDev, 0x80, 0x0000); /* LPC_I/O_DEC: I/O decode ranges. */
302 PDMPciDevSetWord(pPciDev, 0x82, 0x0000); /* LPC_EN: LPC I/F enables. */
303 PDMPciDevSetDWord(pPciDev, 0x84, 0x00000000); /* GEN1_DEC: LPC I/F generic decode range 1. */
304 PDMPciDevSetDWord(pPciDev, 0x88, 0x00000000); /* GEN2_DEC: LPC I/F generic decode range 2. */
305 PDMPciDevSetDWord(pPciDev, 0x8c, 0x00000000); /* GEN3_DEC: LPC I/F generic decode range 3. */
306 PDMPciDevSetDWord(pPciDev, 0x90, 0x00000000); /* GEN4_DEC: LPC I/F generic decode range 4. */
[71829]307
[81031]308 PDMPciDevSetWord(pPciDev, 0xa0, 0x0008); /* GEN_PMCON_1: Documented default is 0x0000 */
309 PDMPciDevSetByte(pPciDev, 0xa2, 0x00); /* GEN_PMON_2: */
310 PDMPciDevSetByte(pPciDev, 0xa4, 0x00); /* GEN_PMON_3: */
311 PDMPciDevSetByte(pPciDev, 0xa6, 0x00); /* GEN_PMON_LOCK: Configuration lock. */
[71829]312 if (pThis->uIchVersion == 7)
[81031]313 PDMPciDevSetByte(pPciDev, 0xa8, 0x0f); /* Is this part of GEN_PMON_LOCK? */
314 PDMPciDevSetByte(pPciDev, 0xab, 0x00); /* BM_BREAK_EN */
315 PDMPciDevSetDWord(pPciDev, 0xac, 0x00000000); /* PMIR: Power */
316 PDMPciDevSetDWord(pPciDev, 0xb8, 0x00000000); /* GPI_ROUT: GPI Route Control */
[71829]317 if (pThis->uIchVersion == 9)
318 {
319 /** @todo the next two values looks bogus. */
[81031]320 PDMPciDevSetDWord(pPciDev, 0xd0, 0x00112233); /* FWH_SEL1: Firmware Hub Select 1 */
321 PDMPciDevSetWord(pPciDev, 0xd4, 0x4567); /* FWH_SEL2: Firmware Hub Select 2 */
322 PDMPciDevSetWord(pPciDev, 0xd8, 0xffcf); /* FWH_DEC_EN1: Firmware Hub Decode Enable 1 */
323 PDMPciDevSetByte(pPciDev, 0xdc, 0x00); /* BIOS_CNTL: BIOS control */
324 PDMPciDevSetWord(pPciDev, 0xe0, 0x0009); /* FDCAP: Feature Detection Capability ID */
325 PDMPciDevSetByte(pPciDev, 0xe2, 0x0c); /* FDLEN: Feature Detection Capability Length */
326 PDMPciDevSetByte(pPciDev, 0xe3, 0x10); /* FDVER: Feature Detection Version */
327 PDMPciDevSetByte(pPciDev, 0xe4, 0x20); /* FDVCT[0]: 5=SATA RAID 0/1/5/10 capability (1=disabled) */
328 PDMPciDevSetByte(pPciDev, 0xe5, 0x00); /* FDVCT[1]: */
329 PDMPciDevSetByte(pPciDev, 0xe6, 0x00); /* FDVCT[2]: */
330 PDMPciDevSetByte(pPciDev, 0xe7, 0x00); /* FDVCT[3]: */
331 PDMPciDevSetByte(pPciDev, 0xe8, 0xc0); /* FDVCT[4]: 6-7=Intel active magament technology capability (11=disabled). */
332 PDMPciDevSetByte(pPciDev, 0xe9, 0x00); /* FDVCT[5]: */
333 PDMPciDevSetByte(pPciDev, 0xea, 0x00); /* FDVCT[6]: */
334 PDMPciDevSetByte(pPciDev, 0xeb, 0x00); /* FDVCT[7]: */
335 PDMPciDevSetByte(pPciDev, 0xec, 0x00); /* FDVCT[8]: */
336 PDMPciDevSetByte(pPciDev, 0xed, 0x00); /* FDVCT[9]: */
337 PDMPciDevSetByte(pPciDev, 0xee, 0x00); /* FDVCT[a]: */
338 PDMPciDevSetByte(pPciDev, 0xef, 0x00); /* FDVCT[b]: */
[71829]339 }
340
341 /* RCBA: Root complex base address (documented default is 0x00000000). Bit 0 is enable bit. */
342 Assert(!(pThis->GCPhys32Rcba & 0x3fff)); /* 16KB aligned */
[81031]343 PDMPciDevSetDWord(pPciDev, 0xf0, pThis->GCPhys32Rcba | 1);
[71829]344
[81031]345 rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, PDMPCIDEVREG_F_NOT_MANDATORY_NO, 31 /*uPciDevNo*/, 0 /*uPciFunNo*/, "lpc");
[71829]346 AssertRCReturn(rc, rc);
[81031]347 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, lpcR3PciConfigRead, lpcR3PciConfigWrite);
[80943]348 AssertRCReturn(rc, rc);
[71829]349
350 /*
351 * Register the MMIO regions.
352 */
353 /** @todo This should actually be done when RCBA is enabled, but was
354 * mentioned above we just want this working. */
[81933]355 rc = PDMDevHlpMmioCreateAndMap(pDevIns, pThis->GCPhys32Rcba, 0x4000, lpcMmioWrite, lpcMmioRead,
[104289]356 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
[81933]357 "LPC Memory", &pThis->hMmio);
[71829]358 AssertRCReturn(rc, rc);
359
360
361 /*
362 * Debug info and stats.
363 */
[81933]364 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReads, STAMTYPE_COUNTER, "MMIOReads", STAMUNIT_OCCURENCES, "MMIO reads");
365 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWrites, STAMTYPE_COUNTER, "MMIOWrites", STAMUNIT_OCCURENCES, "MMIO writes");
366 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgReads, STAMTYPE_COUNTER, "ConfigReads", STAMUNIT_OCCURENCES, "PCI config reads");
367 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPciCfgWrites, STAMTYPE_COUNTER, "ConfigWrites", STAMUNIT_OCCURENCES, "PCI config writes");
[71829]368
369 PDMDevHlpDBGFInfoRegister(pDevIns, "lpc", "Display LPC status. (no arguments)", lpcInfo);
370
371 return VINF_SUCCESS;
372}
373
[80531]374#endif /* IN_RING3 */
[71829]375
376/**
377 * The device registration structure.
378 */
379const PDMDEVREG g_DeviceLPC =
380{
[80531]381 /* .u32Version = */ PDM_DEVREG_VERSION,
382 /* .uReserved0 = */ 0,
383 /* .szName = */ "lpc",
[81933]384 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_NEW_STYLE,
[80531]385 /* .fClass = */ PDM_DEVREG_CLASS_MISC,
386 /* .cMaxInstances = */ 1,
387 /* .uSharedVersion = */ 42,
388 /* .cbInstanceShared = */ sizeof(LPCSTATE),
389 /* .cbInstanceCC = */ 0,
390 /* .cbInstanceRC = */ 0,
[80701]391 /* .cMaxPciDevices = */ 1,
[80704]392 /* .cMaxMsixVectors = */ 0,
[80531]393 /* .pszDescription = */ "Low Pin Count (LPC) Bus",
394#if defined(IN_RING3)
395 /* .pszRCMod = */ "",
396 /* .pszR0Mod = */ "",
397 /* .pfnConstruct = */ lpcConstruct,
398 /* .pfnDestruct = */ NULL,
399 /* .pfnRelocate = */ NULL,
400 /* .pfnMemSetup = */ NULL,
401 /* .pfnPowerOn = */ NULL,
402 /* .pfnReset = */ NULL,
403 /* .pfnSuspend = */ NULL,
404 /* .pfnResume = */ NULL,
405 /* .pfnAttach = */ NULL,
406 /* .pfnDetach = */ NULL,
407 /* .pfnQueryInterface = */ NULL,
408 /* .pfnInitComplete = */ NULL,
409 /* .pfnPowerOff = */ NULL,
410 /* .pfnSoftReset = */ NULL,
411 /* .pfnReserved0 = */ NULL,
412 /* .pfnReserved1 = */ NULL,
413 /* .pfnReserved2 = */ NULL,
414 /* .pfnReserved3 = */ NULL,
415 /* .pfnReserved4 = */ NULL,
416 /* .pfnReserved5 = */ NULL,
417 /* .pfnReserved6 = */ NULL,
418 /* .pfnReserved7 = */ NULL,
419#elif defined(IN_RING0)
420 /* .pfnEarlyConstruct = */ NULL,
421 /* .pfnConstruct = */ NULL,
422 /* .pfnDestruct = */ NULL,
423 /* .pfnFinalDestruct = */ NULL,
424 /* .pfnRequest = */ NULL,
425 /* .pfnReserved0 = */ NULL,
426 /* .pfnReserved1 = */ NULL,
427 /* .pfnReserved2 = */ NULL,
428 /* .pfnReserved3 = */ NULL,
429 /* .pfnReserved4 = */ NULL,
430 /* .pfnReserved5 = */ NULL,
431 /* .pfnReserved6 = */ NULL,
432 /* .pfnReserved7 = */ NULL,
433#elif defined(IN_RC)
434 /* .pfnConstruct = */ NULL,
435 /* .pfnReserved0 = */ NULL,
436 /* .pfnReserved1 = */ NULL,
437 /* .pfnReserved2 = */ NULL,
438 /* .pfnReserved3 = */ NULL,
439 /* .pfnReserved4 = */ NULL,
440 /* .pfnReserved5 = */ NULL,
441 /* .pfnReserved6 = */ NULL,
442 /* .pfnReserved7 = */ NULL,
443#else
444# error "Not in IN_RING3, IN_RING0 or IN_RC!"
445#endif
446 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
[71829]447};
448
449#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
450
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