1 | /* $Id: DevIoApic.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
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2 | /** @file
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3 | * IO APIC - Input/Output Advanced Programmable Interrupt Controller.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2016-2024 Oracle and/or its affiliates.
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8 | *
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9 | * This file is part of VirtualBox base platform packages, as
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10 | * available from https://www.virtualbox.org.
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11 | *
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12 | * This program is free software; you can redistribute it and/or
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13 | * modify it under the terms of the GNU General Public License
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14 | * as published by the Free Software Foundation, in version 3 of the
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15 | * License.
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16 | *
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17 | * This program is distributed in the hope that it will be useful, but
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18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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20 | * General Public License for more details.
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21 | *
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22 | * You should have received a copy of the GNU General Public License
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23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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24 | *
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25 | * SPDX-License-Identifier: GPL-3.0-only
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #define LOG_GROUP LOG_GROUP_DEV_IOAPIC
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33 | #include <VBox/log.h>
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34 | #include <VBox/vmm/hm.h>
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35 | #include <VBox/msi.h>
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36 | #include <VBox/pci.h>
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37 | #include <VBox/vmm/pdmdev.h>
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38 |
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39 | #include "VBoxDD.h"
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40 | #include <iprt/x86.h>
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41 | #include <iprt/string.h>
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42 |
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43 |
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44 | /*********************************************************************************************************************************
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45 | * Defined Constants And Macros *
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46 | *********************************************************************************************************************************/
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47 | /** The current IO APIC saved state version. */
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48 | #define IOAPIC_SAVED_STATE_VERSION 3
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49 | /** The current IO APIC saved state version. */
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50 | #define IOAPIC_SAVED_STATE_VERSION_NO_FLIPFLOP_MAP 2
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51 | /** The saved state version used by VirtualBox 5.0 and
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52 | * earlier. */
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53 | #define IOAPIC_SAVED_STATE_VERSION_VBOX_50 1
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54 |
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55 | /** Implementation specified by the "Intel I/O Controller Hub 9
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56 | * (ICH9) Family" */
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57 | #define IOAPIC_VERSION_ICH9 0x20
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58 | /** Implementation specified by the "82093AA I/O Advanced Programmable Interrupt
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59 | Controller" */
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60 | #define IOAPIC_VERSION_82093AA 0x11
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61 |
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62 | /** The default MMIO base physical address. */
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63 | #define IOAPIC_MMIO_BASE_PHYSADDR UINT64_C(0xfec00000)
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64 | /** The size of the MMIO range. */
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65 | #define IOAPIC_MMIO_SIZE X86_PAGE_4K_SIZE
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66 | /** The mask for getting direct registers from physical address. */
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67 | #define IOAPIC_MMIO_REG_MASK 0xff
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68 |
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69 | /** The number of interrupt input pins. */
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70 | #define IOAPIC_NUM_INTR_PINS 24
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71 | /** Maximum redirection entires. */
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72 | #define IOAPIC_MAX_RTE_INDEX (IOAPIC_NUM_INTR_PINS - 1)
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73 | /** Reduced RTEs used by SIO.A (82379AB). */
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74 | #define IOAPIC_REDUCED_MAX_RTE_INDEX (16 - 1)
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75 |
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76 | /** Version register - Gets the version. */
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77 | #define IOAPIC_VER_GET_VER(a_Reg) ((a_Reg) & 0xff)
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78 | /** Version register - Gets the maximum redirection entry. */
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79 | #define IOAPIC_VER_GET_MRE(a_Reg) (((a_Reg) >> 16) & 0xff)
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80 | /** Version register - Gets whether Pin Assertion Register (PRQ) is
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81 | * supported. */
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82 | #define IOAPIC_VER_HAS_PRQ(a_Reg) RT_BOOL((a_Reg) & RT_BIT_32(15))
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83 |
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84 | /** Index register - Valid write mask. */
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85 | #define IOAPIC_INDEX_VALID_WRITE_MASK UINT32_C(0xff)
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86 |
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87 | /** Arbitration register - Gets the ID. */
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88 | #define IOAPIC_ARB_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xf)
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89 |
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90 | /** ID register - Gets the ID. */
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91 | #define IOAPIC_ID_GET_ID(a_Reg) ((a_Reg) >> 24 & 0xff)
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92 |
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93 | /** Redirection table entry - Vector. */
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94 | #define IOAPIC_RTE_VECTOR UINT64_C(0xff)
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95 | /** Redirection table entry - Delivery mode. */
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96 | #define IOAPIC_RTE_DELIVERY_MODE (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
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97 | /** Redirection table entry - Destination mode. */
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98 | #define IOAPIC_RTE_DEST_MODE RT_BIT_64(11)
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99 | /** Redirection table entry - Delivery status. */
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100 | #define IOAPIC_RTE_DELIVERY_STATUS RT_BIT_64(12)
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101 | /** Redirection table entry - Interrupt input pin polarity. */
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102 | #define IOAPIC_RTE_POLARITY RT_BIT_64(13)
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103 | /** Redirection table entry - Remote IRR. */
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104 | #define IOAPIC_RTE_REMOTE_IRR RT_BIT_64(14)
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105 | /** Redirection table entry - Trigger Mode. */
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106 | #define IOAPIC_RTE_TRIGGER_MODE RT_BIT_64(15)
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107 | /** Redirection table entry - Number of bits to shift to get the Mask. */
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108 | #define IOAPIC_RTE_MASK_BIT 16
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109 | /** Redirection table entry - The Mask. */
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110 | #define IOAPIC_RTE_MASK RT_BIT_64(IOAPIC_RTE_MASK_BIT)
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111 | /** Redirection table entry - Extended Destination ID. */
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112 | #define IOAPIC_RTE_EXT_DEST_ID UINT64_C(0x00ff000000000000)
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113 | /** Redirection table entry - Destination. */
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114 | #define IOAPIC_RTE_DEST UINT64_C(0xff00000000000000)
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115 |
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116 | /** Redirection table entry - Gets the destination. */
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117 | #define IOAPIC_RTE_GET_DEST(a_Reg) ((a_Reg) >> 56 & 0xff)
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118 | /** Redirection table entry - Gets the mask flag. */
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119 | #define IOAPIC_RTE_GET_MASK(a_Reg) (((a_Reg) >> IOAPIC_RTE_MASK_BIT) & 0x1)
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120 | /** Redirection table entry - Checks whether it's masked. */
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121 | #define IOAPIC_RTE_IS_MASKED(a_Reg) ((a_Reg) & IOAPIC_RTE_MASK)
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122 | /** Redirection table entry - Gets the trigger mode. */
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123 | #define IOAPIC_RTE_GET_TRIGGER_MODE(a_Reg) (((a_Reg) >> 15) & 0x1)
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124 | /** Redirection table entry - Gets the remote IRR flag. */
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125 | #define IOAPIC_RTE_GET_REMOTE_IRR(a_Reg) (((a_Reg) >> 14) & 0x1)
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126 | /** Redirection table entry - Gets the interrupt pin polarity. */
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127 | #define IOAPIC_RTE_GET_POLARITY(a_Reg) (((a_Reg) >> 13) & 0x1)
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128 | /** Redirection table entry - Gets the delivery status. */
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129 | #define IOAPIC_RTE_GET_DELIVERY_STATUS(a_Reg) (((a_Reg) >> 12) & 0x1)
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130 | /** Redirection table entry - Gets the destination mode. */
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131 | #define IOAPIC_RTE_GET_DEST_MODE(a_Reg) (((a_Reg) >> 11) & 0x1)
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132 | /** Redirection table entry - Gets the delivery mode. */
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133 | #define IOAPIC_RTE_GET_DELIVERY_MODE(a_Reg) (((a_Reg) >> 8) & 0x7)
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134 | /** Redirection table entry - Gets the vector. */
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135 | #define IOAPIC_RTE_GET_VECTOR(a_Reg) ((a_Reg) & IOAPIC_RTE_VECTOR)
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136 |
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137 | /** @name DMAR variant interpretation of RTE fields.
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138 | * @{ */
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139 | /** Redirection table entry - Number of bits to shift to get Interrupt
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140 | * Index[14:0]. */
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141 | #define IOAPIC_RTE_INTR_INDEX_LO_BIT 49
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142 | /** Redirection table entry - Interrupt Index[14:0]. */
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143 | #define IOAPIC_RTE_INTR_INDEX_LO UINT64_C(0xfffe000000000000)
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144 | /** Redirection table entry - Number of bits to shift to get interrupt format. */
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145 | #define IOAPIC_RTE_INTR_FORMAT_BIT 48
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146 | /** Redirection table entry - Interrupt format. */
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147 | #define IOAPIC_RTE_INTR_FORMAT RT_BIT_64(IOAPIC_RTE_INTR_FORMAT_BIT)
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148 | /** Redirection table entry - Number of bits to shift to get Interrupt Index[15]. */
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149 | #define IOAPIC_RTE_INTR_INDEX_HI_BIT 11
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150 | /** Redirection table entry - Interrupt Index[15]. */
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151 | #define IOAPIC_RTE_INTR_INDEX_HI RT_BIT_64(11)
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152 |
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153 | /** Redirection table entry - Gets the Interrupt Index[14:0]. */
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154 | #define IOAPIC_RTE_GET_INTR_INDEX_LO(a_Reg) ((a_Reg) >> IOAPIC_RTE_INTR_INDEX_LO_BIT)
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155 | /** Redirection table entry - Gets the Interrupt format. */
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156 | #define IOAPIC_RTE_GET_INTR_FORMAT(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_FORMAT_BIT) & 0x1)
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157 | /** Redirection table entry - Gets the Interrupt Index[15]. */
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158 | #define IOAPIC_RTE_GET_INTR_INDEX_HI(a_Reg) (((a_Reg) >> IOAPIC_RTE_INTR_INDEX_HI_BIT) & 0x1)
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159 | /** @} */
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160 |
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161 | /** Redirection table entry - Valid write mask for 82093AA. */
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162 | #define IOAPIC_RTE_VALID_WRITE_MASK_82093AA ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
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163 | | IOAPIC_RTE_POLARITY | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE \
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164 | | IOAPIC_RTE_VECTOR)
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165 | /** Redirection table entry - Valid read mask for 82093AA. */
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166 | #define IOAPIC_RTE_VALID_READ_MASK_82093AA ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
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167 | | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY | IOAPIC_RTE_DELIVERY_STATUS \
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168 | | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
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169 |
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170 | /** Redirection table entry - Valid write mask for ICH9. */
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171 | /** @note The remote IRR bit has been reverted to read-only as it turns out the
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172 | * ICH9 spec. is wrong, see @bugref{8386#c46}. */
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173 | #define IOAPIC_RTE_VALID_WRITE_MASK_ICH9 ( IOAPIC_RTE_DEST | IOAPIC_RTE_MASK | IOAPIC_RTE_TRIGGER_MODE \
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174 | /*| IOAPIC_RTE_REMOTE_IRR */| IOAPIC_RTE_POLARITY | IOAPIC_RTE_DEST_MODE \
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175 | | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
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176 | /** Redirection table entry - Valid read mask (incl. ExtDestID) for ICH9. */
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177 | #define IOAPIC_RTE_VALID_READ_MASK_ICH9 ( IOAPIC_RTE_DEST | IOAPIC_RTE_EXT_DEST_ID | IOAPIC_RTE_MASK \
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178 | | IOAPIC_RTE_TRIGGER_MODE | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY \
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179 | | IOAPIC_RTE_DELIVERY_STATUS | IOAPIC_RTE_DEST_MODE | IOAPIC_RTE_DELIVERY_MODE \
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180 | | IOAPIC_RTE_VECTOR)
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181 |
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182 | /** Redirection table entry - Valid write mask for DMAR variant. */
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183 | #define IOAPIC_RTE_VALID_WRITE_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO | IOAPIC_RTE_INTR_FORMAT | IOAPIC_RTE_MASK \
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184 | | IOAPIC_RTE_TRIGGER_MODE | IOAPIC_RTE_POLARITY | IOAPIC_RTE_INTR_INDEX_HI \
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185 | | IOAPIC_RTE_DELIVERY_MODE | IOAPIC_RTE_VECTOR)
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186 | /** Redirection table entry - Valid read mask for DMAR variant. */
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187 | #define IOAPIC_RTE_VALID_READ_MASK_DMAR ( IOAPIC_RTE_INTR_INDEX_LO | IOAPIC_RTE_INTR_FORMAT | IOAPIC_RTE_MASK \
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188 | | IOAPIC_RTE_TRIGGER_MODE | IOAPIC_RTE_REMOTE_IRR | IOAPIC_RTE_POLARITY \
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189 | | IOAPIC_RTE_DELIVERY_STATUS | IOAPIC_RTE_INTR_INDEX_HI | IOAPIC_RTE_DELIVERY_MODE \
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190 | | IOAPIC_RTE_VECTOR)
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191 |
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192 | /** Redirection table entry - Trigger mode edge. */
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193 | #define IOAPIC_RTE_TRIGGER_MODE_EDGE 0
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194 | /** Redirection table entry - Trigger mode level. */
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195 | #define IOAPIC_RTE_TRIGGER_MODE_LEVEL 1
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196 | /** Redirection table entry - Destination mode physical. */
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197 | #define IOAPIC_RTE_DEST_MODE_PHYSICAL 0
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198 | /** Redirection table entry - Destination mode logical. */
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199 | #define IOAPIC_RTE_DEST_MODE_LOGICAL 1
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200 |
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201 |
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202 | /** Index of indirect registers in the I/O APIC register table. */
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203 | #define IOAPIC_INDIRECT_INDEX_ID 0x0
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204 | #define IOAPIC_INDIRECT_INDEX_VERSION 0x1
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205 | #define IOAPIC_INDIRECT_INDEX_ARB 0x2 /* Older I/O APIC only. */
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206 | #define IOAPIC_INDIRECT_INDEX_REDIR_TBL_START 0x10 /* First valid RTE register index. */
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207 | #define IOAPIC_INDIRECT_INDEX_RTE_END 0x3F /* Last valid RTE register index (24 RTEs). */
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208 | #define IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END 0x2F /* Last valid RTE register index (16 RTEs). */
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209 |
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210 | /** Offset of direct registers in the I/O APIC MMIO space. */
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211 | #define IOAPIC_DIRECT_OFF_INDEX 0x00
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212 | #define IOAPIC_DIRECT_OFF_DATA 0x10
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213 | #define IOAPIC_DIRECT_OFF_EOI 0x40 /* Newer I/O APIC only. */
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214 |
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215 | /* Use PDM critsect for now for I/O APIC locking, see @bugref{8245#c121}. */
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216 | #define IOAPIC_WITH_PDM_CRITSECT
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217 | #ifdef IOAPIC_WITH_PDM_CRITSECT
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218 | # define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) (a_pThisCC)->pIoApicHlp->pfnLock((a_pDevIns), (rcBusy))
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219 | # define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnUnlock((a_pDevIns))
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220 | # define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) (a_pThisCC)->pIoApicHlp->pfnLockIsOwner((a_pDevIns))
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221 | #else
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222 | # define IOAPIC_LOCK(a_pDevIns, a_pThis, a_pThisCC, rcBusy) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, (rcBusy))
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223 | # define IOAPIC_UNLOCK(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect)
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224 | # define IOAPIC_LOCK_IS_OWNER(a_pDevIns, a_pThis, a_pThisCC) PDMDevHlpCritSectIsOwner((a_pDevIns), &(a_pThis)->CritSect)
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225 | #endif
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226 |
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227 |
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228 | /*********************************************************************************************************************************
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229 | * Structures and Typedefs *
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230 | *********************************************************************************************************************************/
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231 | /**
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232 | * I/O APIC chipset (and variants) we support.
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233 | */
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234 | typedef enum IOAPICTYPE
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235 | {
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236 | IOAPICTYPE_ICH9 = 1,
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237 | IOAPICTYPE_DMAR,
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238 | IOAPICTYPE_82093AA,
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239 | IOAPICTYPE_82379AB,
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240 | IOAPICTYPE_32BIT_HACK = 0x7fffffff
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241 | } IOAPICTYPE;
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242 | AssertCompileSize(IOAPICTYPE, 4);
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243 |
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244 | /**
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245 | * The shared I/O APIC device state.
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246 | */
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247 | typedef struct IOAPIC
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248 | {
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249 | /** The ID register. */
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250 | uint8_t volatile u8Id;
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251 | /** The index register. */
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252 | uint8_t volatile u8Index;
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253 | /** Number of CPUs. */
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254 | uint8_t cCpus;
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255 | /** I/O APIC version. */
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256 | uint8_t u8ApicVer;
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257 | /** I/O APIC ID mask. */
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258 | uint8_t u8IdMask;
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259 | /** Maximum Redirection Table Entry (RTE) Entry. */
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260 | uint8_t u8MaxRte;
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261 | /** Last valid RTE indirect register index. */
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262 | uint8_t u8LastRteRegIdx;
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263 | /* Alignment padding. */
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264 | uint8_t u8Padding0[1];
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265 | /** Redirection table entry - Valid write mask. */
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266 | uint64_t u64RteWriteMask;
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267 | /** Redirection table entry - Valid read mask. */
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268 | uint64_t u64RteReadMask;
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269 |
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270 | /** The redirection table registers. */
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271 | uint64_t au64RedirTable[IOAPIC_NUM_INTR_PINS];
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272 | /** The IRQ tags and source IDs for each pin (tracing purposes). */
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273 | uint32_t au32TagSrc[IOAPIC_NUM_INTR_PINS];
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274 | /** Bitmap keeping the flip-flop-ness of pending interrupts.
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275 | * The information held here is only relevan between SetIrq and the
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276 | * delivery, thus no real need to initialize or reset this. */
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277 | uint64_t bmFlipFlop[(IOAPIC_NUM_INTR_PINS + 63) / 64];
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278 |
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279 | /** The internal IRR reflecting state of the interrupt lines. */
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280 | uint32_t uIrr;
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281 | /** The I/O APIC chipset type. */
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282 | IOAPICTYPE enmType;
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283 | /** The I/O APIC PCI address. */
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284 | PCIBDF uPciAddress;
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285 | /** Padding. */
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286 | uint32_t uPadding0;
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287 |
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288 | #ifndef IOAPIC_WITH_PDM_CRITSECT
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289 | /** The critsect for updating to the RTEs. */
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290 | PDMCRITSECT CritSect;
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291 | #endif
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292 |
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293 | /** The MMIO region. */
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294 | IOMMMIOHANDLE hMmio;
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295 |
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296 | #ifdef VBOX_WITH_STATISTICS
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297 | /** Number of MMIO reads in RZ. */
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298 | STAMCOUNTER StatMmioReadRZ;
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299 | /** Number of MMIO reads in R3. */
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300 | STAMCOUNTER StatMmioReadR3;
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301 |
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302 | /** Number of MMIO writes in RZ. */
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303 | STAMCOUNTER StatMmioWriteRZ;
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304 | /** Number of MMIO writes in R3. */
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305 | STAMCOUNTER StatMmioWriteR3;
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306 |
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307 | /** Number of SetIrq calls in RZ. */
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308 | STAMCOUNTER StatSetIrqRZ;
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309 | /** Number of SetIrq calls in R3. */
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310 | STAMCOUNTER StatSetIrqR3;
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311 |
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312 | /** Number of SetEoi calls in RZ. */
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313 | STAMCOUNTER StatSetEoiRZ;
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314 | /** Number of SetEoi calls in R3. */
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315 | STAMCOUNTER StatSetEoiR3;
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316 |
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317 | /** Number of redundant edge-triggered interrupts. */
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318 | STAMCOUNTER StatRedundantEdgeIntr;
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319 | /** Number of redundant level-triggered interrupts. */
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320 | STAMCOUNTER StatRedundantLevelIntr;
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321 | /** Number of suppressed level-triggered interrupts (by remote IRR). */
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322 | STAMCOUNTER StatSuppressedLevelIntr;
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323 | /** Number of IOMMU remapped interrupts (signaled by RTE). */
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324 | STAMCOUNTER StatIommuRemappedIntr;
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325 | /** Number of IOMMU discarded interrupts (signaled by RTE). */
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326 | STAMCOUNTER StatIommuDiscardedIntr;
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327 | /** Number of IOMMU remapped MSIs. */
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328 | STAMCOUNTER StatIommuRemappedMsi;
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329 | /** Number of IOMMU denied or failed MSIs. */
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330 | STAMCOUNTER StatIommuDiscardedMsi;
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331 | /** Number of returns to ring-3 due to Set RTE lock contention. */
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332 | STAMCOUNTER StatSetRteContention;
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333 | /** Number of level-triggered interrupts dispatched to the local APIC(s). */
|
---|
334 | STAMCOUNTER StatLevelIrqSent;
|
---|
335 | /** Number of EOIs received for level-triggered interrupts from the local
|
---|
336 | * APIC(s). */
|
---|
337 | STAMCOUNTER StatEoiReceived;
|
---|
338 | /** The time an interrupt level spent in the pending state. */
|
---|
339 | STAMPROFILEADV aStatLevelAct[IOAPIC_NUM_INTR_PINS];
|
---|
340 | #endif
|
---|
341 | /** Per-vector stats. */
|
---|
342 | STAMCOUNTER aStatVectors[256];
|
---|
343 | } IOAPIC;
|
---|
344 | AssertCompileMemberAlignment(IOAPIC, au64RedirTable, 8);
|
---|
345 | /** Pointer to shared IOAPIC data. */
|
---|
346 | typedef IOAPIC *PIOAPIC;
|
---|
347 | /** Pointer to const shared IOAPIC data. */
|
---|
348 | typedef IOAPIC const *PCIOAPIC;
|
---|
349 |
|
---|
350 |
|
---|
351 | /**
|
---|
352 | * The I/O APIC device state for ring-3.
|
---|
353 | */
|
---|
354 | typedef struct IOAPICR3
|
---|
355 | {
|
---|
356 | /** The IOAPIC helpers. */
|
---|
357 | R3PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
|
---|
358 | } IOAPICR3;
|
---|
359 | /** Pointer to the I/O APIC device state for ring-3. */
|
---|
360 | typedef IOAPICR3 *PIOAPICR3;
|
---|
361 |
|
---|
362 |
|
---|
363 | /**
|
---|
364 | * The I/O APIC device state for ring-0.
|
---|
365 | */
|
---|
366 | typedef struct IOAPICR0
|
---|
367 | {
|
---|
368 | /** The IOAPIC helpers. */
|
---|
369 | R0PTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
|
---|
370 | } IOAPICR0;
|
---|
371 | /** Pointer to the I/O APIC device state for ring-0. */
|
---|
372 | typedef IOAPICR0 *PIOAPICR0;
|
---|
373 |
|
---|
374 |
|
---|
375 | /**
|
---|
376 | * The I/O APIC device state for raw-mode.
|
---|
377 | */
|
---|
378 | typedef struct IOAPICRC
|
---|
379 | {
|
---|
380 | /** The IOAPIC helpers. */
|
---|
381 | RCPTRTYPE(PCPDMIOAPICHLP) pIoApicHlp;
|
---|
382 | } IOAPICRC;
|
---|
383 | /** Pointer to the I/O APIC device state for raw-mode. */
|
---|
384 | typedef IOAPICRC *PIOAPICRC;
|
---|
385 |
|
---|
386 |
|
---|
387 | /** The I/O APIC device state for the current context. */
|
---|
388 | typedef CTX_SUFF(IOAPIC) IOAPICCC;
|
---|
389 | /** Pointer to the I/O APIC device state for the current context. */
|
---|
390 | typedef CTX_SUFF(PIOAPIC) PIOAPICCC;
|
---|
391 |
|
---|
392 |
|
---|
393 | /**
|
---|
394 | * xAPIC interrupt.
|
---|
395 | */
|
---|
396 | typedef struct XAPICINTR
|
---|
397 | {
|
---|
398 | /** The interrupt vector. */
|
---|
399 | uint8_t u8Vector;
|
---|
400 | /** The destination (mask or ID). */
|
---|
401 | uint8_t u8Dest;
|
---|
402 | /** The destination mode. */
|
---|
403 | uint8_t u8DestMode;
|
---|
404 | /** Delivery mode. */
|
---|
405 | uint8_t u8DeliveryMode;
|
---|
406 | /** Trigger mode. */
|
---|
407 | uint8_t u8TriggerMode;
|
---|
408 | /** Redirection hint. */
|
---|
409 | uint8_t u8RedirHint;
|
---|
410 | /** Polarity. */
|
---|
411 | uint8_t u8Polarity;
|
---|
412 | /** Padding. */
|
---|
413 | uint8_t abPadding0;
|
---|
414 | } XAPICINTR;
|
---|
415 | /** Pointer to an I/O xAPIC interrupt struct. */
|
---|
416 | typedef XAPICINTR *PXAPICINTR;
|
---|
417 | /** Pointer to a const xAPIC interrupt struct. */
|
---|
418 | typedef XAPICINTR const *PCXAPICINTR;
|
---|
419 |
|
---|
420 |
|
---|
421 | #ifndef VBOX_DEVICE_STRUCT_TESTCASE
|
---|
422 |
|
---|
423 | /**
|
---|
424 | * Gets the arbitration register.
|
---|
425 | *
|
---|
426 | * @returns The arbitration.
|
---|
427 | */
|
---|
428 | DECLINLINE(uint32_t) ioapicGetArb(void)
|
---|
429 | {
|
---|
430 | Log2(("IOAPIC: ioapicGetArb: returns 0\n"));
|
---|
431 | return 0;
|
---|
432 | }
|
---|
433 |
|
---|
434 |
|
---|
435 | /**
|
---|
436 | * Gets the version register.
|
---|
437 | *
|
---|
438 | * @returns The version.
|
---|
439 | */
|
---|
440 | DECLINLINE(uint32_t) ioapicGetVersion(PCIOAPIC pThis)
|
---|
441 | {
|
---|
442 | uint32_t uValue = RT_MAKE_U32(pThis->u8ApicVer, pThis->u8MaxRte);
|
---|
443 | Log2(("IOAPIC: ioapicGetVersion: returns %#RX32\n", uValue));
|
---|
444 | return uValue;
|
---|
445 | }
|
---|
446 |
|
---|
447 |
|
---|
448 | /**
|
---|
449 | * Sets the ID register.
|
---|
450 | *
|
---|
451 | * @param pThis The shared I/O APIC device state.
|
---|
452 | * @param uValue The value to set.
|
---|
453 | */
|
---|
454 | DECLINLINE(void) ioapicSetId(PIOAPIC pThis, uint32_t uValue)
|
---|
455 | {
|
---|
456 | Log2(("IOAPIC: ioapicSetId: uValue=%#RX32\n", uValue));
|
---|
457 | ASMAtomicWriteU8(&pThis->u8Id, (uValue >> 24) & pThis->u8IdMask);
|
---|
458 | }
|
---|
459 |
|
---|
460 |
|
---|
461 | /**
|
---|
462 | * Gets the ID register.
|
---|
463 | *
|
---|
464 | * @returns The ID.
|
---|
465 | * @param pThis The shared I/O APIC device state.
|
---|
466 | */
|
---|
467 | DECLINLINE(uint32_t) ioapicGetId(PCIOAPIC pThis)
|
---|
468 | {
|
---|
469 | uint32_t uValue = (uint32_t)pThis->u8Id << 24;
|
---|
470 | Log2(("IOAPIC: ioapicGetId: returns %#RX32\n", uValue));
|
---|
471 | return uValue;
|
---|
472 | }
|
---|
473 |
|
---|
474 |
|
---|
475 | /**
|
---|
476 | * Sets the index register.
|
---|
477 | *
|
---|
478 | * @param pThis The shared I/O APIC device state.
|
---|
479 | * @param uValue The value to set.
|
---|
480 | */
|
---|
481 | DECLINLINE(void) ioapicSetIndex(PIOAPIC pThis, uint32_t uValue)
|
---|
482 | {
|
---|
483 | LogFlow(("IOAPIC: ioapicSetIndex: uValue=%#RX32\n", uValue));
|
---|
484 | ASMAtomicWriteU8(&pThis->u8Index, uValue & IOAPIC_INDEX_VALID_WRITE_MASK);
|
---|
485 | }
|
---|
486 |
|
---|
487 |
|
---|
488 | /**
|
---|
489 | * Gets the index register.
|
---|
490 | *
|
---|
491 | * @returns The index value.
|
---|
492 | */
|
---|
493 | DECLINLINE(uint32_t) ioapicGetIndex(PCIOAPIC pThis)
|
---|
494 | {
|
---|
495 | uint32_t const uValue = pThis->u8Index;
|
---|
496 | LogFlow(("IOAPIC: ioapicGetIndex: returns %#x\n", uValue));
|
---|
497 | return uValue;
|
---|
498 | }
|
---|
499 |
|
---|
500 |
|
---|
501 | /**
|
---|
502 | * Converts an MSI message to an APIC interrupt.
|
---|
503 | *
|
---|
504 | * @param pMsi The MSI message to convert.
|
---|
505 | * @param pIntr Where to store the APIC interrupt.
|
---|
506 | */
|
---|
507 | DECLINLINE(void) ioapicGetApicIntrFromMsi(PCMSIMSG pMsi, PXAPICINTR pIntr)
|
---|
508 | {
|
---|
509 | /*
|
---|
510 | * Parse the message from the physical address and data.
|
---|
511 | * Do -not- zero out other fields in the APIC interrupt.
|
---|
512 | *
|
---|
513 | * See Intel spec. 10.11.1 "Message Address Register Format".
|
---|
514 | * See Intel spec. 10.11.2 "Message Data Register Format".
|
---|
515 | */
|
---|
516 | pIntr->u8Dest = pMsi->Addr.n.u8DestId;
|
---|
517 | pIntr->u8DestMode = pMsi->Addr.n.u1DestMode;
|
---|
518 | pIntr->u8RedirHint = pMsi->Addr.n.u1RedirHint;
|
---|
519 |
|
---|
520 | pIntr->u8Vector = pMsi->Data.n.u8Vector;
|
---|
521 | pIntr->u8TriggerMode = pMsi->Data.n.u1TriggerMode;
|
---|
522 | pIntr->u8DeliveryMode = pMsi->Data.n.u3DeliveryMode;
|
---|
523 | }
|
---|
524 |
|
---|
525 |
|
---|
526 | #if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
|
---|
527 | /**
|
---|
528 | * Convert an RTE into an MSI message.
|
---|
529 | *
|
---|
530 | * @param u64Rte The RTE to convert.
|
---|
531 | * @param enmType The I/O APIC chipset type.
|
---|
532 | * @param pMsi Where to store the MSI message.
|
---|
533 | */
|
---|
534 | DECLINLINE(void) ioapicGetMsiFromRte(uint64_t u64Rte, IOAPICTYPE enmType, PMSIMSG pMsi)
|
---|
535 | {
|
---|
536 | bool const fRemappable = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
|
---|
537 | if (!fRemappable)
|
---|
538 | {
|
---|
539 | pMsi->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
|
---|
540 | pMsi->Addr.n.u8DestId = IOAPIC_RTE_GET_DEST(u64Rte);
|
---|
541 | pMsi->Addr.n.u1RedirHint = 0;
|
---|
542 | pMsi->Addr.n.u1DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
|
---|
543 |
|
---|
544 | pMsi->Data.n.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
|
---|
545 | pMsi->Data.n.u3DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
|
---|
546 | pMsi->Data.n.u1TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
|
---|
547 | /* pMsi->Data.n.u1Level = ??? */
|
---|
548 | /** @todo r=ramshankar: Level triggered MSIs don't make much sense though
|
---|
549 | * possible in theory? Maybe document this more explicitly... */
|
---|
550 | }
|
---|
551 | else
|
---|
552 | {
|
---|
553 | Assert(enmType == IOAPICTYPE_DMAR);
|
---|
554 | NOREF(enmType);
|
---|
555 |
|
---|
556 | /*
|
---|
557 | * The spec. mentions that SHV will be 0 when delivery mode is 0 (fixed), but
|
---|
558 | * not what SHV will be if delivery mode is not 0. I ASSUME copying delivery
|
---|
559 | * mode into SHV here is what hardware actually does.
|
---|
560 | *
|
---|
561 | * See Intel VT-d spec. 5.1.5.1 "I/OxAPIC Programming".
|
---|
562 | */
|
---|
563 | pMsi->Addr.dmar_remap.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
|
---|
564 | pMsi->Addr.dmar_remap.u14IntrIndexLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
|
---|
565 | pMsi->Addr.dmar_remap.fIntrFormat = 1;
|
---|
566 | pMsi->Addr.dmar_remap.fShv = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
|
---|
567 | pMsi->Addr.dmar_remap.u1IntrIndexHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
|
---|
568 |
|
---|
569 | pMsi->Data.dmar_remap.u16SubHandle = 0;
|
---|
570 | }
|
---|
571 | }
|
---|
572 | #endif
|
---|
573 |
|
---|
574 |
|
---|
575 | /**
|
---|
576 | * Signals the next pending interrupt for the specified Redirection Table Entry
|
---|
577 | * (RTE).
|
---|
578 | *
|
---|
579 | * @param pDevIns The device instance.
|
---|
580 | * @param pThis The shared I/O APIC device state.
|
---|
581 | * @param pThisCC The I/O APIC device state for the current context.
|
---|
582 | * @param idxRte The index of the RTE (validated).
|
---|
583 | *
|
---|
584 | * @remarks It is the responsibility of the caller to verify that an interrupt is
|
---|
585 | * pending for the pin corresponding to the RTE before calling this
|
---|
586 | * function.
|
---|
587 | */
|
---|
588 | static void ioapicSignalIntrForRte(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint8_t idxRte)
|
---|
589 | {
|
---|
590 | Assert(IOAPIC_LOCK_IS_OWNER(pDevIns, pThis, pThisCC));
|
---|
591 |
|
---|
592 | /*
|
---|
593 | * Ensure the interrupt isn't masked.
|
---|
594 | */
|
---|
595 | uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
|
---|
596 | if (!IOAPIC_RTE_IS_MASKED(u64Rte))
|
---|
597 | { /* likely */ }
|
---|
598 | else
|
---|
599 | return;
|
---|
600 |
|
---|
601 | /* We cannot accept another level-triggered interrupt until remote IRR has been cleared. */
|
---|
602 | uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte);
|
---|
603 | if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
|
---|
604 | {
|
---|
605 | uint8_t const u8RemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
|
---|
606 | if (u8RemoteIrr)
|
---|
607 | {
|
---|
608 | STAM_COUNTER_INC(&pThis->StatSuppressedLevelIntr);
|
---|
609 | return;
|
---|
610 | }
|
---|
611 | }
|
---|
612 |
|
---|
613 | XAPICINTR ApicIntr;
|
---|
614 | RT_ZERO(ApicIntr);
|
---|
615 | ApicIntr.u8Vector = IOAPIC_RTE_GET_VECTOR(u64Rte);
|
---|
616 | ApicIntr.u8Dest = IOAPIC_RTE_GET_DEST(u64Rte);
|
---|
617 | ApicIntr.u8DestMode = IOAPIC_RTE_GET_DEST_MODE(u64Rte);
|
---|
618 | ApicIntr.u8DeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
|
---|
619 | ApicIntr.u8Polarity = IOAPIC_RTE_GET_POLARITY(u64Rte);
|
---|
620 | ApicIntr.u8TriggerMode = u8TriggerMode;
|
---|
621 | //ApicIntr.u8RedirHint = 0;
|
---|
622 |
|
---|
623 | /** @todo We might be able to release the IOAPIC(PDM) lock here and re-acquire it
|
---|
624 | * before setting the remote IRR bit below. The APIC and IOMMU should not
|
---|
625 | * require the caller to hold the PDM lock. */
|
---|
626 |
|
---|
627 | #if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
|
---|
628 | /*
|
---|
629 | * The interrupt may need to be remapped (or discarded) if an IOMMU is present.
|
---|
630 | * For line-based interrupts we must use the southbridge I/O APIC's BDF as
|
---|
631 | * the origin of the interrupt, see @bugref{9654#c74}.
|
---|
632 | */
|
---|
633 | MSIMSG MsiIn;
|
---|
634 | RT_ZERO(MsiIn);
|
---|
635 | ioapicGetMsiFromRte(u64Rte, pThis->enmType, &MsiIn);
|
---|
636 |
|
---|
637 | MSIMSG MsiOut;
|
---|
638 | int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, pThis->uPciAddress, &MsiIn, &MsiOut);
|
---|
639 | if ( rcRemap == VERR_IOMMU_NOT_PRESENT
|
---|
640 | || rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
|
---|
641 | { /* likely - assuming majority of VMs don't have IOMMU configured. */ }
|
---|
642 | else if (RT_SUCCESS(rcRemap))
|
---|
643 | {
|
---|
644 | /* Update the APIC interrupt with the remapped data. */
|
---|
645 | ioapicGetApicIntrFromMsi(&MsiOut, &ApicIntr);
|
---|
646 |
|
---|
647 | /* Ensure polarity hasn't changed (trigger mode might change with Intel IOMMUs). */
|
---|
648 | Assert(ApicIntr.u8Polarity == IOAPIC_RTE_GET_POLARITY(u64Rte));
|
---|
649 | STAM_COUNTER_INC(&pThis->StatIommuRemappedIntr);
|
---|
650 | }
|
---|
651 | else
|
---|
652 | {
|
---|
653 | STAM_COUNTER_INC(&pThis->StatIommuDiscardedIntr);
|
---|
654 | return;
|
---|
655 | }
|
---|
656 | #endif
|
---|
657 |
|
---|
658 | uint32_t const u32TagSrc = pThis->au32TagSrc[idxRte];
|
---|
659 | Log2(("IOAPIC: Signaling %s-triggered interrupt. Dest=%#x DestMode=%s Vector=%#x (%u)\n",
|
---|
660 | ApicIntr.u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE ? "edge" : "level", ApicIntr.u8Dest,
|
---|
661 | ApicIntr.u8DestMode == IOAPIC_RTE_DEST_MODE_PHYSICAL ? "physical" : "logical",
|
---|
662 | ApicIntr.u8Vector, ApicIntr.u8Vector));
|
---|
663 |
|
---|
664 | /*
|
---|
665 | * Deliver to the local APIC via the system/3-wire-APIC bus.
|
---|
666 | */
|
---|
667 | int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
|
---|
668 | ApicIntr.u8Dest,
|
---|
669 | ApicIntr.u8DestMode,
|
---|
670 | ApicIntr.u8DeliveryMode,
|
---|
671 | ApicIntr.u8Vector,
|
---|
672 | ApicIntr.u8Polarity,
|
---|
673 | ApicIntr.u8TriggerMode,
|
---|
674 | u32TagSrc);
|
---|
675 | /* Can't reschedule to R3. */
|
---|
676 | Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED);
|
---|
677 | #ifdef DEBUG_ramshankar
|
---|
678 | if (rc == VERR_APIC_INTR_DISCARDED)
|
---|
679 | AssertMsgFailed(("APIC: Interrupt discarded u8Vector=%#x (%u) u64Rte=%#RX64\n", u8Vector, u8Vector, u64Rte));
|
---|
680 | #endif
|
---|
681 |
|
---|
682 | if (rc == VINF_SUCCESS)
|
---|
683 | {
|
---|
684 | /*
|
---|
685 | * For level-triggered interrupts, we set the remote IRR bit to indicate
|
---|
686 | * the local APIC has accepted the interrupt.
|
---|
687 | *
|
---|
688 | * For edge-triggered interrupts, we should not clear the IRR bit as it
|
---|
689 | * should remain intact to reflect the state of the interrupt line.
|
---|
690 | * The device will explicitly transition to inactive state via the
|
---|
691 | * ioapicSetIrq() callback.
|
---|
692 | */
|
---|
693 | if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL)
|
---|
694 | {
|
---|
695 | Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
|
---|
696 | pThis->au64RedirTable[idxRte] |= IOAPIC_RTE_REMOTE_IRR;
|
---|
697 | STAM_COUNTER_INC(&pThis->StatLevelIrqSent);
|
---|
698 | STAM_PROFILE_ADV_START(&pThis->aStatLevelAct[idxRte], a);
|
---|
699 | }
|
---|
700 | /*
|
---|
701 | * Edge-triggered flip-flops gets cleaned up here as the device code will
|
---|
702 | * not do any explicit ioapicSetIrq and we won't receive any EOI either.
|
---|
703 | */
|
---|
704 | else if (ASMBitTest(pThis->bmFlipFlop, idxRte))
|
---|
705 | {
|
---|
706 | Log2(("IOAPIC: Clearing IRR for edge flip-flop %#x uTagSrc=%#x\n", idxRte, pThis->au32TagSrc[idxRte]));
|
---|
707 | pThis->au32TagSrc[idxRte] = 0;
|
---|
708 | pThis->uIrr &= ~RT_BIT_32(idxRte);
|
---|
709 | }
|
---|
710 | }
|
---|
711 | }
|
---|
712 |
|
---|
713 |
|
---|
714 | /**
|
---|
715 | * Gets the redirection table entry.
|
---|
716 | *
|
---|
717 | * @returns The redirection table entry.
|
---|
718 | * @param pThis The shared I/O APIC device state.
|
---|
719 | * @param uIndex The index value.
|
---|
720 | */
|
---|
721 | DECLINLINE(uint32_t) ioapicGetRedirTableEntry(PCIOAPIC pThis, uint32_t uIndex)
|
---|
722 | {
|
---|
723 | uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
|
---|
724 | AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
|
---|
725 | ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
|
---|
726 | UINT32_MAX);
|
---|
727 | uint32_t uValue;
|
---|
728 | if (!(uIndex & 1))
|
---|
729 | uValue = RT_LO_U32(pThis->au64RedirTable[idxRte]) & RT_LO_U32(pThis->u64RteReadMask);
|
---|
730 | else
|
---|
731 | uValue = RT_HI_U32(pThis->au64RedirTable[idxRte]) & RT_HI_U32(pThis->u64RteReadMask);
|
---|
732 |
|
---|
733 | LogFlow(("IOAPIC: ioapicGetRedirTableEntry: uIndex=%#RX32 idxRte=%u returns %#RX32\n", uIndex, idxRte, uValue));
|
---|
734 | return uValue;
|
---|
735 | }
|
---|
736 |
|
---|
737 |
|
---|
738 | /**
|
---|
739 | * Sets the redirection table entry.
|
---|
740 | *
|
---|
741 | * @returns Strict VBox status code (VINF_IOM_R3_MMIO_WRITE / VINF_SUCCESS).
|
---|
742 | * @param pDevIns The device instance.
|
---|
743 | * @param pThis The shared I/O APIC device state.
|
---|
744 | * @param pThisCC The I/O APIC device state for the current context.
|
---|
745 | * @param uIndex The index value.
|
---|
746 | * @param uValue The value to set.
|
---|
747 | */
|
---|
748 | static VBOXSTRICTRC ioapicSetRedirTableEntry(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC,
|
---|
749 | uint32_t uIndex, uint32_t uValue)
|
---|
750 | {
|
---|
751 | uint8_t const idxRte = (uIndex - IOAPIC_INDIRECT_INDEX_REDIR_TBL_START) >> 1;
|
---|
752 | AssertMsgReturn(idxRte < RT_ELEMENTS(pThis->au64RedirTable),
|
---|
753 | ("Invalid index %u, expected < %u\n", idxRte, RT_ELEMENTS(pThis->au64RedirTable)),
|
---|
754 | VINF_SUCCESS);
|
---|
755 |
|
---|
756 | VBOXSTRICTRC rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_IOM_R3_MMIO_WRITE);
|
---|
757 | if (rc == VINF_SUCCESS)
|
---|
758 | {
|
---|
759 | /*
|
---|
760 | * Write the low or high 32-bit value into the specified 64-bit RTE register,
|
---|
761 | * update only the valid, writable bits.
|
---|
762 | *
|
---|
763 | * We need to preserve the read-only bits as it can have dire consequences
|
---|
764 | * otherwise, see @bugref{8386#c24}.
|
---|
765 | */
|
---|
766 | uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
|
---|
767 | if (!(uIndex & 1))
|
---|
768 | {
|
---|
769 | uint32_t const u32RtePreserveLo = RT_LO_U32(u64Rte) & ~RT_LO_U32(pThis->u64RteWriteMask);
|
---|
770 | uint32_t const u32RteNewLo = (uValue & RT_LO_U32(pThis->u64RteWriteMask)) | u32RtePreserveLo;
|
---|
771 | uint64_t const u64RteHi = u64Rte & UINT64_C(0xffffffff00000000);
|
---|
772 | pThis->au64RedirTable[idxRte] = u64RteHi | u32RteNewLo;
|
---|
773 | }
|
---|
774 | else
|
---|
775 | {
|
---|
776 | uint32_t const u32RtePreserveHi = RT_HI_U32(u64Rte) & ~RT_HI_U32(pThis->u64RteWriteMask);
|
---|
777 | uint32_t const u32RteLo = RT_LO_U32(u64Rte);
|
---|
778 | uint64_t const u64RteNewHi = ((uint64_t)((uValue & RT_HI_U32(pThis->u64RteWriteMask)) | u32RtePreserveHi) << 32);
|
---|
779 | pThis->au64RedirTable[idxRte] = u64RteNewHi | u32RteLo;
|
---|
780 | }
|
---|
781 |
|
---|
782 | LogFlow(("IOAPIC: ioapicSetRedirTableEntry: uIndex=%#RX32 idxRte=%u uValue=%#RX32\n", uIndex, idxRte, uValue));
|
---|
783 |
|
---|
784 | /*
|
---|
785 | * Signal the next pending interrupt for this RTE.
|
---|
786 | */
|
---|
787 | uint32_t const uPinMask = UINT32_C(1) << idxRte;
|
---|
788 | if (pThis->uIrr & uPinMask)
|
---|
789 | {
|
---|
790 | LogFlow(("IOAPIC: ioapicSetRedirTableEntry: Signalling pending interrupt. idxRte=%u\n", idxRte));
|
---|
791 | ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
|
---|
792 | }
|
---|
793 |
|
---|
794 | IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
|
---|
795 | }
|
---|
796 | else
|
---|
797 | STAM_COUNTER_INC(&pThis->StatSetRteContention);
|
---|
798 |
|
---|
799 | return rc;
|
---|
800 | }
|
---|
801 |
|
---|
802 |
|
---|
803 | /**
|
---|
804 | * Gets the data register.
|
---|
805 | *
|
---|
806 | * @returns The data value.
|
---|
807 | * @param pThis The shared I/O APIC device state.
|
---|
808 | */
|
---|
809 | static uint32_t ioapicGetData(PCIOAPIC pThis)
|
---|
810 | {
|
---|
811 | uint8_t const uIndex = pThis->u8Index;
|
---|
812 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
813 | if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
|
---|
814 | && uIndex <= pThis->u8LastRteRegIdx)
|
---|
815 | return ioapicGetRedirTableEntry(pThis, uIndex);
|
---|
816 |
|
---|
817 | uint32_t uValue;
|
---|
818 | switch (uIndex)
|
---|
819 | {
|
---|
820 | case IOAPIC_INDIRECT_INDEX_ID:
|
---|
821 | uValue = ioapicGetId(pThis);
|
---|
822 | break;
|
---|
823 |
|
---|
824 | case IOAPIC_INDIRECT_INDEX_VERSION:
|
---|
825 | uValue = ioapicGetVersion(pThis);
|
---|
826 | break;
|
---|
827 |
|
---|
828 | case IOAPIC_INDIRECT_INDEX_ARB:
|
---|
829 | if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
|
---|
830 | {
|
---|
831 | uValue = ioapicGetArb();
|
---|
832 | break;
|
---|
833 | }
|
---|
834 | RT_FALL_THRU();
|
---|
835 |
|
---|
836 | default:
|
---|
837 | uValue = UINT32_C(0xffffffff);
|
---|
838 | Log2(("IOAPIC: Attempt to read register at invalid index %#x\n", uIndex));
|
---|
839 | break;
|
---|
840 | }
|
---|
841 | return uValue;
|
---|
842 | }
|
---|
843 |
|
---|
844 |
|
---|
845 | /**
|
---|
846 | * Sets the data register.
|
---|
847 | *
|
---|
848 | * @returns Strict VBox status code.
|
---|
849 | * @param pDevIns The device instance.
|
---|
850 | * @param pThis The shared I/O APIC device state.
|
---|
851 | * @param pThisCC The I/O APIC device state for the current context.
|
---|
852 | * @param uValue The value to set.
|
---|
853 | */
|
---|
854 | static VBOXSTRICTRC ioapicSetData(PPDMDEVINS pDevIns, PIOAPIC pThis, PIOAPICCC pThisCC, uint32_t uValue)
|
---|
855 | {
|
---|
856 | uint8_t const uIndex = pThis->u8Index;
|
---|
857 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
858 | LogFlow(("IOAPIC: ioapicSetData: uIndex=%#x uValue=%#RX32\n", uIndex, uValue));
|
---|
859 |
|
---|
860 | if ( uIndex >= IOAPIC_INDIRECT_INDEX_REDIR_TBL_START
|
---|
861 | && uIndex <= pThis->u8LastRteRegIdx)
|
---|
862 | return ioapicSetRedirTableEntry(pDevIns, pThis, pThisCC, uIndex, uValue);
|
---|
863 |
|
---|
864 | if (uIndex == IOAPIC_INDIRECT_INDEX_ID)
|
---|
865 | ioapicSetId(pThis, uValue);
|
---|
866 | else
|
---|
867 | Log2(("IOAPIC: ioapicSetData: Invalid index %#RX32, ignoring write request with uValue=%#RX32\n", uIndex, uValue));
|
---|
868 |
|
---|
869 | return VINF_SUCCESS;
|
---|
870 | }
|
---|
871 |
|
---|
872 |
|
---|
873 | /**
|
---|
874 | * @interface_method_impl{PDMIOAPICREG,pfnSetEoi}
|
---|
875 | */
|
---|
876 | static DECLCALLBACK(void) ioapicSetEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
|
---|
877 | {
|
---|
878 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
879 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
880 |
|
---|
881 | LogFlow(("IOAPIC: ioapicSetEoi: u8Vector=%#x (%u)\n", u8Vector, u8Vector));
|
---|
882 | STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetEoi));
|
---|
883 |
|
---|
884 | bool fRemoteIrrCleared = false;
|
---|
885 | int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
|
---|
886 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, NULL, rc);
|
---|
887 |
|
---|
888 | for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
|
---|
889 | {
|
---|
890 | uint64_t const u64Rte = pThis->au64RedirTable[idxRte];
|
---|
891 | /** @todo r=bird: bugref:10073: I've changed it to ignore edge triggered
|
---|
892 | * entries here since the APIC will only call us for those? Not doing so
|
---|
893 | * confuses ended up with spurious HPET/RTC IRQs in SMP linux because of it
|
---|
894 | * sharing the vector with a level-triggered IRQ (like vboxguest) delivered on a
|
---|
895 | * different CPU.
|
---|
896 | *
|
---|
897 | * Maybe we should also/instead filter on the source APIC number? */
|
---|
898 | if ( IOAPIC_RTE_GET_VECTOR(u64Rte) == u8Vector
|
---|
899 | && IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte) != IOAPIC_RTE_TRIGGER_MODE_EDGE)
|
---|
900 | {
|
---|
901 | #ifdef DEBUG_ramshankar
|
---|
902 | /* This assertion may trigger when restoring saved-states created using the old, incorrect I/O APIC code. */
|
---|
903 | Assert(IOAPIC_RTE_GET_REMOTE_IRR(u64Rte));
|
---|
904 | #endif
|
---|
905 | pThis->au64RedirTable[idxRte] &= ~IOAPIC_RTE_REMOTE_IRR;
|
---|
906 | fRemoteIrrCleared = true;
|
---|
907 | STAM_PROFILE_ADV_STOP(&pThis->aStatLevelAct[idxRte], a);
|
---|
908 | STAM_COUNTER_INC(&pThis->StatEoiReceived);
|
---|
909 | Log2(("IOAPIC: ioapicSetEoi: Cleared remote IRR, idxRte=%u vector=%#x (%u)\n", idxRte, u8Vector, u8Vector));
|
---|
910 |
|
---|
911 | /*
|
---|
912 | * Signal the next pending interrupt for this RTE.
|
---|
913 | */
|
---|
914 | uint32_t const uPinMask = UINT32_C(1) << idxRte;
|
---|
915 | if (pThis->uIrr & uPinMask)
|
---|
916 | ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, idxRte);
|
---|
917 | }
|
---|
918 | }
|
---|
919 |
|
---|
920 | IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
|
---|
921 |
|
---|
922 | #ifndef VBOX_WITH_IOMMU_AMD
|
---|
923 | AssertMsg(fRemoteIrrCleared, ("Failed to clear remote IRR for vector %#x (%u)\n", u8Vector, u8Vector));
|
---|
924 | #endif
|
---|
925 | }
|
---|
926 |
|
---|
927 |
|
---|
928 | /**
|
---|
929 | * @interface_method_impl{PDMIOAPICREG,pfnSetIrq}
|
---|
930 | */
|
---|
931 | static DECLCALLBACK(void) ioapicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
|
---|
932 | {
|
---|
933 | RT_NOREF(uBusDevFn); /** @todo r=ramshankar: Remove this argument if it's also unnecessary with Intel IOMMU. */
|
---|
934 | #define IOAPIC_ASSERT_IRQ(a_uBusDevFn, a_idxRte, a_PinMask, a_fForceTag) do { \
|
---|
935 | pThis->au32TagSrc[(a_idxRte)] = (a_fForceTag) || !pThis->au32TagSrc[(a_idxRte)] ? uTagSrc : RT_BIT_32(31); \
|
---|
936 | pThis->uIrr |= a_PinMask; \
|
---|
937 | ioapicSignalIntrForRte(pDevIns, pThis, pThisCC, (a_idxRte)); \
|
---|
938 | } while (0)
|
---|
939 |
|
---|
940 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
941 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
942 | LogFlow(("IOAPIC: ioapicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
|
---|
943 |
|
---|
944 | STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatSetIrq));
|
---|
945 |
|
---|
946 | if (RT_LIKELY((unsigned)iIrq < RT_ELEMENTS(pThis->au64RedirTable)))
|
---|
947 | {
|
---|
948 | int rc = IOAPIC_LOCK(pDevIns, pThis, pThisCC, VINF_SUCCESS);
|
---|
949 | PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, NULL, rc);
|
---|
950 |
|
---|
951 | uint8_t const idxRte = iIrq;
|
---|
952 | uint32_t const uPinMask = UINT32_C(1) << idxRte;
|
---|
953 | uint32_t const u32RteLo = RT_LO_U32(pThis->au64RedirTable[idxRte]);
|
---|
954 | uint8_t const u8TriggerMode = IOAPIC_RTE_GET_TRIGGER_MODE(u32RteLo);
|
---|
955 |
|
---|
956 | bool fActive = RT_BOOL(iLevel & 1);
|
---|
957 | /** @todo Polarity is busted elsewhere, we need to fix that
|
---|
958 | * first. See @bugref{8386#c7}. */
|
---|
959 | #if 0
|
---|
960 | uint8_t const u8Polarity = IOAPIC_RTE_GET_POLARITY(u32RteLo);
|
---|
961 | fActive ^= u8Polarity; */
|
---|
962 | #endif
|
---|
963 | if (!fActive)
|
---|
964 | {
|
---|
965 | pThis->uIrr &= ~uPinMask;
|
---|
966 | pThis->au32TagSrc[idxRte] = 0;
|
---|
967 | IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
|
---|
968 | return;
|
---|
969 | }
|
---|
970 |
|
---|
971 | bool const fFlipFlop = ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP);
|
---|
972 | if (!fFlipFlop)
|
---|
973 | {
|
---|
974 | ASMBitClear(pThis->bmFlipFlop, idxRte);
|
---|
975 |
|
---|
976 | uint32_t const uPrevIrr = pThis->uIrr & uPinMask;
|
---|
977 | if (u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_EDGE)
|
---|
978 | {
|
---|
979 | /*
|
---|
980 | * For edge-triggered interrupts, we need to act only on a low to high edge transition.
|
---|
981 | * See ICH9 spec. 13.5.7 "REDIR_TBL: Redirection Table (LPC I/F-D31:F0)".
|
---|
982 | */
|
---|
983 | if (!uPrevIrr)
|
---|
984 | IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, false);
|
---|
985 | else
|
---|
986 | {
|
---|
987 | STAM_COUNTER_INC(&pThis->StatRedundantEdgeIntr);
|
---|
988 | Log2(("IOAPIC: Redundant edge-triggered interrupt %#x (%u)\n", idxRte, idxRte));
|
---|
989 | }
|
---|
990 | }
|
---|
991 | else
|
---|
992 | {
|
---|
993 | Assert(u8TriggerMode == IOAPIC_RTE_TRIGGER_MODE_LEVEL);
|
---|
994 |
|
---|
995 | /*
|
---|
996 | * For level-triggered interrupts, redundant interrupts are not a problem
|
---|
997 | * and will eventually be delivered anyway after an EOI, but our PDM devices
|
---|
998 | * should not typically call us with no change to the level.
|
---|
999 | */
|
---|
1000 | if (!uPrevIrr)
|
---|
1001 | { /* likely */ }
|
---|
1002 | else
|
---|
1003 | {
|
---|
1004 | STAM_COUNTER_INC(&pThis->StatRedundantLevelIntr);
|
---|
1005 | Log2(("IOAPIC: Redundant level-triggered interrupt %#x (%u)\n", idxRte, idxRte));
|
---|
1006 | }
|
---|
1007 |
|
---|
1008 | IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, false);
|
---|
1009 | }
|
---|
1010 | }
|
---|
1011 | else
|
---|
1012 | {
|
---|
1013 | /*
|
---|
1014 | * The device is flip-flopping the interrupt line, which implies we should de-assert
|
---|
1015 | * and assert the interrupt line. The interrupt line is left in the asserted state
|
---|
1016 | * after a flip-flop request. The de-assert is a NOP wrts to signaling an interrupt
|
---|
1017 | * hence just the assert is done.
|
---|
1018 | *
|
---|
1019 | * Update @bugref{10073}: We now de-assert the interrupt line once it has been
|
---|
1020 | * delivered to the APIC to prevent it from getting re-delivered by accident (e.g.
|
---|
1021 | * on RTE write or by buggy EOI code). The XT-PIC works differently because of the
|
---|
1022 | * INTA, so it's set IRQ function will do what's described above: first lower the
|
---|
1023 | * interrupt line and then immediately raising it again, leaving the IRR flag set
|
---|
1024 | * most of the time. (How a real HPET/IOAPIC does this is a really good question
|
---|
1025 | * and would be observable if we could get at the IRR register of the IOAPIC...
|
---|
1026 | * Maybe by modifying the RTE? Our code will retrigger the interrupt that way.) */
|
---|
1027 | ASMBitSet(pThis->bmFlipFlop, idxRte);
|
---|
1028 | IOAPIC_ASSERT_IRQ(uBusDevFn, idxRte, uPinMask, true);
|
---|
1029 | }
|
---|
1030 |
|
---|
1031 | IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
|
---|
1032 | }
|
---|
1033 | #undef IOAPIC_ASSERT_IRQ
|
---|
1034 | }
|
---|
1035 |
|
---|
1036 |
|
---|
1037 | /**
|
---|
1038 | * @interface_method_impl{PDMIOAPICREG,pfnSendMsi}
|
---|
1039 | */
|
---|
1040 | static DECLCALLBACK(void) ioapicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
|
---|
1041 | {
|
---|
1042 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
1043 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1044 | LogFlow(("IOAPIC: ioapicSendMsi: uBusDevFn=%#x Addr=%#RX64 Data=%#RX32 uTagSrc=%#x\n",
|
---|
1045 | uBusDevFn, pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
|
---|
1046 |
|
---|
1047 | XAPICINTR ApicIntr;
|
---|
1048 | RT_ZERO(ApicIntr);
|
---|
1049 |
|
---|
1050 | #if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
|
---|
1051 | /*
|
---|
1052 | * The MSI may need to be remapped (or discarded) if an IOMMU is present.
|
---|
1053 | *
|
---|
1054 | * If the Bus:Dev:Fn isn't valid, it is ASSUMED the device generating the
|
---|
1055 | * MSI is the IOMMU itself and hence isn't subjected to remapping. This
|
---|
1056 | * is the case with Intel IOMMUs.
|
---|
1057 | *
|
---|
1058 | * AMD IOMMUs are full fledged PCI devices, hence the BDF will be a
|
---|
1059 | * valid PCI slot, but interrupts generated by the IOMMU will be handled
|
---|
1060 | * by VERR_IOMMU_CANNOT_CALL_SELF case.
|
---|
1061 | */
|
---|
1062 | MSIMSG MsiOut;
|
---|
1063 | if (PCIBDF_IS_VALID(uBusDevFn))
|
---|
1064 | {
|
---|
1065 | int const rcRemap = pThisCC->pIoApicHlp->pfnIommuMsiRemap(pDevIns, uBusDevFn, pMsi, &MsiOut);
|
---|
1066 | if ( rcRemap == VERR_IOMMU_NOT_PRESENT
|
---|
1067 | || rcRemap == VERR_IOMMU_CANNOT_CALL_SELF)
|
---|
1068 | { /* likely - assuming majority of VMs don't have IOMMU configured. */ }
|
---|
1069 | else if (RT_SUCCESS(rcRemap))
|
---|
1070 | {
|
---|
1071 | STAM_COUNTER_INC(&pThis->StatIommuRemappedMsi);
|
---|
1072 | pMsi = &MsiOut;
|
---|
1073 | }
|
---|
1074 | else
|
---|
1075 | {
|
---|
1076 | STAM_COUNTER_INC(&pThis->StatIommuDiscardedMsi);
|
---|
1077 | return;
|
---|
1078 | }
|
---|
1079 | }
|
---|
1080 | #else
|
---|
1081 | NOREF(uBusDevFn);
|
---|
1082 | #endif
|
---|
1083 |
|
---|
1084 | ioapicGetApicIntrFromMsi(pMsi, &ApicIntr);
|
---|
1085 |
|
---|
1086 | /*
|
---|
1087 | * Deliver to the local APIC via the system/3-wire-APIC bus.
|
---|
1088 | */
|
---|
1089 | STAM_REL_COUNTER_INC(&pThis->aStatVectors[ApicIntr.u8Vector]);
|
---|
1090 |
|
---|
1091 | int rc = pThisCC->pIoApicHlp->pfnApicBusDeliver(pDevIns,
|
---|
1092 | ApicIntr.u8Dest,
|
---|
1093 | ApicIntr.u8DestMode,
|
---|
1094 | ApicIntr.u8DeliveryMode,
|
---|
1095 | ApicIntr.u8Vector,
|
---|
1096 | 0 /* u8Polarity - N/A */,
|
---|
1097 | ApicIntr.u8TriggerMode,
|
---|
1098 | uTagSrc);
|
---|
1099 | /* Can't reschedule to R3. */
|
---|
1100 | Assert(rc == VINF_SUCCESS || rc == VERR_APIC_INTR_DISCARDED); NOREF(rc);
|
---|
1101 | }
|
---|
1102 |
|
---|
1103 |
|
---|
1104 | /**
|
---|
1105 | * @callback_method_impl{FNIOMMMIONEWREAD}
|
---|
1106 | */
|
---|
1107 | static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
|
---|
1108 | {
|
---|
1109 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1110 | STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
|
---|
1111 | Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
|
---|
1112 | RT_NOREF_PV(pvUser);
|
---|
1113 |
|
---|
1114 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
1115 | uint32_t *puValue = (uint32_t *)pv;
|
---|
1116 | uint32_t offReg = off & IOAPIC_MMIO_REG_MASK;
|
---|
1117 | switch (offReg)
|
---|
1118 | {
|
---|
1119 | case IOAPIC_DIRECT_OFF_INDEX:
|
---|
1120 | *puValue = ioapicGetIndex(pThis);
|
---|
1121 | break;
|
---|
1122 |
|
---|
1123 | case IOAPIC_DIRECT_OFF_DATA:
|
---|
1124 | *puValue = ioapicGetData(pThis);
|
---|
1125 | break;
|
---|
1126 |
|
---|
1127 | default:
|
---|
1128 | Log2(("IOAPIC: ioapicMmioRead: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
|
---|
1129 | rc = VINF_IOM_MMIO_UNUSED_FF;
|
---|
1130 | break;
|
---|
1131 | }
|
---|
1132 |
|
---|
1133 | LogFlow(("IOAPIC: ioapicMmioRead: offReg=%#x, returns %#RX32\n", offReg, *puValue));
|
---|
1134 | return rc;
|
---|
1135 | }
|
---|
1136 |
|
---|
1137 |
|
---|
1138 | /**
|
---|
1139 | * @callback_method_impl{FNIOMMMIONEWWRITE}
|
---|
1140 | */
|
---|
1141 | static DECLCALLBACK(VBOXSTRICTRC) ioapicMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
|
---|
1142 | {
|
---|
1143 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1144 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
1145 | RT_NOREF_PV(pvUser);
|
---|
1146 |
|
---|
1147 | STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
|
---|
1148 |
|
---|
1149 | Assert(!(off & 3));
|
---|
1150 | Assert(cb == 4); RT_NOREF_PV(cb); /* registered for dwords only */
|
---|
1151 |
|
---|
1152 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
1153 | uint32_t const uValue = *(uint32_t const *)pv;
|
---|
1154 | uint32_t const offReg = off & IOAPIC_MMIO_REG_MASK;
|
---|
1155 |
|
---|
1156 | LogFlow(("IOAPIC: ioapicMmioWrite: pThis=%p off=%#RGp cb=%u uValue=%#RX32\n", pThis, off, cb, uValue));
|
---|
1157 | switch (offReg)
|
---|
1158 | {
|
---|
1159 | case IOAPIC_DIRECT_OFF_INDEX:
|
---|
1160 | ioapicSetIndex(pThis, uValue);
|
---|
1161 | break;
|
---|
1162 |
|
---|
1163 | case IOAPIC_DIRECT_OFF_DATA:
|
---|
1164 | rc = ioapicSetData(pDevIns, pThis, pThisCC, uValue);
|
---|
1165 | break;
|
---|
1166 |
|
---|
1167 | case IOAPIC_DIRECT_OFF_EOI:
|
---|
1168 | if (pThis->u8ApicVer == IOAPIC_VERSION_ICH9)
|
---|
1169 | ioapicSetEoi(pDevIns, uValue);
|
---|
1170 | else
|
---|
1171 | Log(("IOAPIC: ioapicMmioWrite: Write to EOI register ignored!\n"));
|
---|
1172 | break;
|
---|
1173 |
|
---|
1174 | default:
|
---|
1175 | Log2(("IOAPIC: ioapicMmioWrite: Invalid offset. off=%#RGp offReg=%#x\n", off, offReg));
|
---|
1176 | break;
|
---|
1177 | }
|
---|
1178 |
|
---|
1179 | return rc;
|
---|
1180 | }
|
---|
1181 |
|
---|
1182 |
|
---|
1183 | #ifdef IN_RING3
|
---|
1184 |
|
---|
1185 | /** @interface_method_impl{DBGFREGDESC,pfnGet} */
|
---|
1186 | static DECLCALLBACK(int) ioapicR3DbgReg_GetIndex(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
|
---|
1187 | {
|
---|
1188 | RT_NOREF(pDesc);
|
---|
1189 | pValue->u32 = ioapicGetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC));
|
---|
1190 | return VINF_SUCCESS;
|
---|
1191 | }
|
---|
1192 |
|
---|
1193 |
|
---|
1194 | /** @interface_method_impl{DBGFREGDESC,pfnSet} */
|
---|
1195 | static DECLCALLBACK(int) ioapicR3DbgReg_SetIndex(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
|
---|
1196 | {
|
---|
1197 | RT_NOREF(pDesc, pfMask);
|
---|
1198 | ioapicSetIndex(PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC), pValue->u8);
|
---|
1199 | return VINF_SUCCESS;
|
---|
1200 | }
|
---|
1201 |
|
---|
1202 |
|
---|
1203 | /** @interface_method_impl{DBGFREGDESC,pfnGet} */
|
---|
1204 | static DECLCALLBACK(int) ioapicR3DbgReg_GetData(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
|
---|
1205 | {
|
---|
1206 | RT_NOREF(pDesc);
|
---|
1207 | pValue->u32 = ioapicGetData((PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC)));
|
---|
1208 | return VINF_SUCCESS;
|
---|
1209 | }
|
---|
1210 |
|
---|
1211 |
|
---|
1212 | /** @interface_method_impl{DBGFREGDESC,pfnSet} */
|
---|
1213 | static DECLCALLBACK(int) ioapicR3DbgReg_SetData(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
|
---|
1214 | {
|
---|
1215 | PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
|
---|
1216 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1217 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
1218 | RT_NOREF(pDesc, pfMask);
|
---|
1219 | return VBOXSTRICTRC_VAL(ioapicSetData(pDevIns, pThis, pThisCC, pValue->u32));
|
---|
1220 | }
|
---|
1221 |
|
---|
1222 |
|
---|
1223 | /** @interface_method_impl{DBGFREGDESC,pfnGet} */
|
---|
1224 | static DECLCALLBACK(int) ioapicR3DbgReg_GetVersion(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
|
---|
1225 | {
|
---|
1226 | PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
|
---|
1227 | RT_NOREF(pDesc);
|
---|
1228 | pValue->u32 = ioapicGetVersion(pThis);
|
---|
1229 | return VINF_SUCCESS;
|
---|
1230 | }
|
---|
1231 |
|
---|
1232 |
|
---|
1233 | /** @interface_method_impl{DBGFREGDESC,pfnGet} */
|
---|
1234 | static DECLCALLBACK(int) ioapicR3DbgReg_GetArb(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
|
---|
1235 | {
|
---|
1236 | RT_NOREF(pvUser, pDesc);
|
---|
1237 | pValue->u32 = ioapicGetArb();
|
---|
1238 | return VINF_SUCCESS;
|
---|
1239 | }
|
---|
1240 |
|
---|
1241 |
|
---|
1242 | /** @interface_method_impl{DBGFREGDESC,pfnGet} */
|
---|
1243 | static DECLCALLBACK(int) ioapicR3DbgReg_GetRte(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
|
---|
1244 | {
|
---|
1245 | PCIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PCIOAPIC);
|
---|
1246 | Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
|
---|
1247 | pValue->u64 = pThis->au64RedirTable[pDesc->offRegister];
|
---|
1248 | return VINF_SUCCESS;
|
---|
1249 | }
|
---|
1250 |
|
---|
1251 |
|
---|
1252 | /** @interface_method_impl{DBGFREGDESC,pfnSet} */
|
---|
1253 | static DECLCALLBACK(int) ioapicR3DbgReg_SetRte(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
|
---|
1254 | {
|
---|
1255 | RT_NOREF(pfMask);
|
---|
1256 | PIOAPIC pThis = PDMDEVINS_2_DATA((PPDMDEVINS)pvUser, PIOAPIC);
|
---|
1257 | /* No locks, no checks, just do it. */
|
---|
1258 | Assert(pDesc->offRegister < RT_ELEMENTS(pThis->au64RedirTable));
|
---|
1259 | pThis->au64RedirTable[pDesc->offRegister] = pValue->u64;
|
---|
1260 | return VINF_SUCCESS;
|
---|
1261 | }
|
---|
1262 |
|
---|
1263 |
|
---|
1264 | /** IOREDTBLn sub fields. */
|
---|
1265 | static DBGFREGSUBFIELD const g_aRteSubs[] =
|
---|
1266 | {
|
---|
1267 | { "vector", 0, 8, 0, 0, NULL, NULL },
|
---|
1268 | { "dlvr_mode", 8, 3, 0, 0, NULL, NULL },
|
---|
1269 | { "dest_mode", 11, 1, 0, 0, NULL, NULL },
|
---|
1270 | { "dlvr_status", 12, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
|
---|
1271 | { "polarity", 13, 1, 0, 0, NULL, NULL },
|
---|
1272 | { "remote_irr", 14, 1, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
|
---|
1273 | { "trigger_mode", 15, 1, 0, 0, NULL, NULL },
|
---|
1274 | { "mask", 16, 1, 0, 0, NULL, NULL },
|
---|
1275 | { "ext_dest_id", 48, 8, 0, DBGFREGSUBFIELD_FLAGS_READ_ONLY, NULL, NULL },
|
---|
1276 | { "dest", 56, 8, 0, 0, NULL, NULL },
|
---|
1277 | DBGFREGSUBFIELD_TERMINATOR()
|
---|
1278 | };
|
---|
1279 |
|
---|
1280 |
|
---|
1281 | /** Register descriptors for DBGF. */
|
---|
1282 | static DBGFREGDESC const g_aRegDesc[] =
|
---|
1283 | {
|
---|
1284 | { "index", DBGFREG_END, DBGFREGVALTYPE_U8, 0, 0, ioapicR3DbgReg_GetIndex, ioapicR3DbgReg_SetIndex, NULL, NULL },
|
---|
1285 | { "data", DBGFREG_END, DBGFREGVALTYPE_U32, 0, 0, ioapicR3DbgReg_GetData, ioapicR3DbgReg_SetData, NULL, NULL },
|
---|
1286 | { "version", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetVersion, NULL, NULL, NULL },
|
---|
1287 | { "arb", DBGFREG_END, DBGFREGVALTYPE_U32, DBGFREG_FLAGS_READ_ONLY, 0, ioapicR3DbgReg_GetArb, NULL, NULL, NULL },
|
---|
1288 | { "rte0", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 0, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1289 | { "rte1", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 1, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1290 | { "rte2", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 2, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1291 | { "rte3", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 3, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1292 | { "rte4", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 4, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1293 | { "rte5", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 5, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1294 | { "rte6", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 6, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1295 | { "rte7", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 7, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1296 | { "rte8", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 8, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1297 | { "rte9", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 9, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1298 | { "rte10", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 10, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1299 | { "rte11", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 11, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1300 | { "rte12", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 12, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1301 | { "rte13", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 13, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1302 | { "rte14", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 14, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1303 | { "rte15", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 15, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1304 | { "rte16", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 16, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1305 | { "rte17", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 17, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1306 | { "rte18", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 18, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1307 | { "rte19", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 19, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1308 | { "rte20", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 20, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1309 | { "rte21", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 21, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1310 | { "rte22", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 22, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1311 | { "rte23", DBGFREG_END, DBGFREGVALTYPE_U64, 0, 23, ioapicR3DbgReg_GetRte, ioapicR3DbgReg_SetRte, NULL, &g_aRteSubs[0] },
|
---|
1312 | DBGFREGDESC_TERMINATOR()
|
---|
1313 | };
|
---|
1314 |
|
---|
1315 |
|
---|
1316 | /**
|
---|
1317 | * @callback_method_impl{FNDBGFHANDLERDEV}
|
---|
1318 | */
|
---|
1319 | static DECLCALLBACK(void) ioapicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
1320 | {
|
---|
1321 | RT_NOREF(pszArgs);
|
---|
1322 | PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1323 | LogFlow(("IOAPIC: ioapicR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
|
---|
1324 |
|
---|
1325 | bool const fLegacy = RTStrCmp(pszArgs, "legacy") == 0;
|
---|
1326 |
|
---|
1327 | static const char * const s_apszDeliveryModes[] =
|
---|
1328 | {
|
---|
1329 | " fixed",
|
---|
1330 | "lowpri",
|
---|
1331 | " smi",
|
---|
1332 | " rsvd",
|
---|
1333 | " nmi",
|
---|
1334 | " init",
|
---|
1335 | " rsvd",
|
---|
1336 | "extint"
|
---|
1337 | };
|
---|
1338 | static const char * const s_apszDestMode[] = { "phys", "log " };
|
---|
1339 | static const char * const s_apszTrigMode[] = { " edge", "level" };
|
---|
1340 | static const char * const s_apszPolarity[] = { "acthi", "actlo" };
|
---|
1341 | static const char * const s_apszDeliveryStatus[] = { "idle", "pend" };
|
---|
1342 |
|
---|
1343 | pHlp->pfnPrintf(pHlp, "I/O APIC at %#010x:\n", IOAPIC_MMIO_BASE_PHYSADDR);
|
---|
1344 |
|
---|
1345 | uint32_t const uId = ioapicGetId(pThis);
|
---|
1346 | pHlp->pfnPrintf(pHlp, " ID = %#RX32\n", uId);
|
---|
1347 | pHlp->pfnPrintf(pHlp, " ID = %#x\n", IOAPIC_ID_GET_ID(uId));
|
---|
1348 |
|
---|
1349 | uint32_t const uVer = ioapicGetVersion(pThis);
|
---|
1350 | pHlp->pfnPrintf(pHlp, " Version = %#RX32\n", uVer);
|
---|
1351 | pHlp->pfnPrintf(pHlp, " Version = %#x\n", IOAPIC_VER_GET_VER(uVer));
|
---|
1352 | pHlp->pfnPrintf(pHlp, " Pin Assert Reg. Support = %RTbool\n", IOAPIC_VER_HAS_PRQ(uVer));
|
---|
1353 | pHlp->pfnPrintf(pHlp, " Max. Redirection Entry = %u\n", IOAPIC_VER_GET_MRE(uVer));
|
---|
1354 |
|
---|
1355 | if (pThis->u8ApicVer == IOAPIC_VERSION_82093AA)
|
---|
1356 | {
|
---|
1357 | uint32_t const uArb = ioapicGetArb();
|
---|
1358 | pHlp->pfnPrintf(pHlp, " Arbitration = %#RX32\n", uArb);
|
---|
1359 | pHlp->pfnPrintf(pHlp, " Arbitration ID = %#x\n", IOAPIC_ARB_GET_ID(uArb));
|
---|
1360 | }
|
---|
1361 |
|
---|
1362 | pHlp->pfnPrintf(pHlp, " Current index = %#x\n", ioapicGetIndex(pThis));
|
---|
1363 |
|
---|
1364 | pHlp->pfnPrintf(pHlp, " I/O Redirection Table and IRR:\n");
|
---|
1365 | if ( pThis->enmType != IOAPICTYPE_DMAR
|
---|
1366 | || fLegacy)
|
---|
1367 | {
|
---|
1368 | pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
|
---|
1369 | pHlp->pfnPrintf(pHlp, " ---------------------------------------------------------------------------------------------\n");
|
---|
1370 |
|
---|
1371 | uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
|
---|
1372 | for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
|
---|
1373 | {
|
---|
1374 | const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
|
---|
1375 | const char *pszDestMode = s_apszDestMode[IOAPIC_RTE_GET_DEST_MODE(u64Rte)];
|
---|
1376 | const uint8_t uDest = IOAPIC_RTE_GET_DEST(u64Rte);
|
---|
1377 | const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
|
---|
1378 | const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
|
---|
1379 | const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
|
---|
1380 | const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
|
---|
1381 | const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
|
---|
1382 | const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
|
---|
1383 | Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
|
---|
1384 | const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
|
---|
1385 | const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
|
---|
1386 |
|
---|
1387 | pHlp->pfnPrintf(pHlp, " %02d %s %02x %u %u %s %u %s %s %s %3u (%016llx)\n",
|
---|
1388 | idxRte,
|
---|
1389 | pszDestMode,
|
---|
1390 | uDest,
|
---|
1391 | uMask,
|
---|
1392 | (pThis->uIrr >> idxRte) & 1,
|
---|
1393 | pszTriggerMode,
|
---|
1394 | uRemoteIrr,
|
---|
1395 | pszPolarity,
|
---|
1396 | pszDeliveryStatus,
|
---|
1397 | pszDeliveryMode,
|
---|
1398 | uVector,
|
---|
1399 | u64Rte);
|
---|
1400 | }
|
---|
1401 | }
|
---|
1402 | else
|
---|
1403 | {
|
---|
1404 | pHlp->pfnPrintf(pHlp, " idx intr_idx fmt mask irr trigger rirr polar dlvr_st dlvr_mode vector rte\n");
|
---|
1405 | pHlp->pfnPrintf(pHlp, " ----------------------------------------------------------------------------------------\n");
|
---|
1406 |
|
---|
1407 | uint8_t const idxMaxRte = RT_MIN(pThis->u8MaxRte, RT_ELEMENTS(pThis->au64RedirTable) - 1);
|
---|
1408 | for (uint8_t idxRte = 0; idxRte <= idxMaxRte; idxRte++)
|
---|
1409 | {
|
---|
1410 | const uint64_t u64Rte = pThis->au64RedirTable[idxRte];
|
---|
1411 | const uint16_t idxIntrLo = IOAPIC_RTE_GET_INTR_INDEX_LO(u64Rte);
|
---|
1412 | const uint8_t fIntrFormat = IOAPIC_RTE_GET_INTR_FORMAT(u64Rte);
|
---|
1413 | const uint8_t uMask = IOAPIC_RTE_GET_MASK(u64Rte);
|
---|
1414 | const char *pszTriggerMode = s_apszTrigMode[IOAPIC_RTE_GET_TRIGGER_MODE(u64Rte)];
|
---|
1415 | const uint8_t uRemoteIrr = IOAPIC_RTE_GET_REMOTE_IRR(u64Rte);
|
---|
1416 | const char *pszPolarity = s_apszPolarity[IOAPIC_RTE_GET_POLARITY(u64Rte)];
|
---|
1417 | const char *pszDeliveryStatus = s_apszDeliveryStatus[IOAPIC_RTE_GET_DELIVERY_STATUS(u64Rte)];
|
---|
1418 | const uint8_t uDeliveryMode = IOAPIC_RTE_GET_DELIVERY_MODE(u64Rte);
|
---|
1419 | Assert(uDeliveryMode < RT_ELEMENTS(s_apszDeliveryModes));
|
---|
1420 | const char *pszDeliveryMode = s_apszDeliveryModes[uDeliveryMode];
|
---|
1421 | const uint16_t idxIntrHi = IOAPIC_RTE_GET_INTR_INDEX_HI(u64Rte);
|
---|
1422 | const uint8_t uVector = IOAPIC_RTE_GET_VECTOR(u64Rte);
|
---|
1423 | const uint16_t idxIntr = idxIntrLo | (idxIntrHi << 15);
|
---|
1424 | pHlp->pfnPrintf(pHlp, " %02d %4u %u %u %u %s %u %s %s %s %3u (%016llx)\n",
|
---|
1425 | idxRte,
|
---|
1426 | idxIntr,
|
---|
1427 | fIntrFormat,
|
---|
1428 | uMask,
|
---|
1429 | (pThis->uIrr >> idxRte) & 1,
|
---|
1430 | pszTriggerMode,
|
---|
1431 | uRemoteIrr,
|
---|
1432 | pszPolarity,
|
---|
1433 | pszDeliveryStatus,
|
---|
1434 | pszDeliveryMode,
|
---|
1435 | uVector,
|
---|
1436 | u64Rte);
|
---|
1437 | }
|
---|
1438 | }
|
---|
1439 | }
|
---|
1440 |
|
---|
1441 |
|
---|
1442 | /**
|
---|
1443 | * @copydoc FNSSMDEVSAVEEXEC
|
---|
1444 | */
|
---|
1445 | static DECLCALLBACK(int) ioapicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
1446 | {
|
---|
1447 | PCIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PCIOAPIC);
|
---|
1448 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
1449 | LogFlow(("IOAPIC: ioapicR3SaveExec\n"));
|
---|
1450 |
|
---|
1451 | pHlp->pfnSSMPutU32(pSSM, pThis->uIrr);
|
---|
1452 | pHlp->pfnSSMPutU8(pSSM, pThis->u8Id);
|
---|
1453 | pHlp->pfnSSMPutU8(pSSM, pThis->u8Index);
|
---|
1454 | for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
|
---|
1455 | pHlp->pfnSSMPutU64(pSSM, pThis->au64RedirTable[idxRte]);
|
---|
1456 |
|
---|
1457 | for (uint8_t idx = 0; idx < RT_ELEMENTS(pThis->bmFlipFlop); idx++)
|
---|
1458 | pHlp->pfnSSMPutU64(pSSM, pThis->bmFlipFlop[idx]);
|
---|
1459 |
|
---|
1460 | return VINF_SUCCESS;
|
---|
1461 | }
|
---|
1462 |
|
---|
1463 |
|
---|
1464 | /**
|
---|
1465 | * @copydoc FNSSMDEVLOADEXEC
|
---|
1466 | */
|
---|
1467 | static DECLCALLBACK(int) ioapicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
1468 | {
|
---|
1469 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1470 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
1471 | LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
|
---|
1472 |
|
---|
1473 | Assert(uPass == SSM_PASS_FINAL);
|
---|
1474 | NOREF(uPass);
|
---|
1475 |
|
---|
1476 | /* Weed out invalid versions. */
|
---|
1477 | if ( uVersion != IOAPIC_SAVED_STATE_VERSION
|
---|
1478 | && uVersion != IOAPIC_SAVED_STATE_VERSION_NO_FLIPFLOP_MAP
|
---|
1479 | && uVersion != IOAPIC_SAVED_STATE_VERSION_VBOX_50)
|
---|
1480 | {
|
---|
1481 | LogRel(("IOAPIC: ioapicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
|
---|
1482 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
1483 | }
|
---|
1484 |
|
---|
1485 | if (uVersion >= IOAPIC_SAVED_STATE_VERSION_NO_FLIPFLOP_MAP)
|
---|
1486 | pHlp->pfnSSMGetU32(pSSM, &pThis->uIrr);
|
---|
1487 |
|
---|
1488 | pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Id);
|
---|
1489 | pHlp->pfnSSMGetU8V(pSSM, &pThis->u8Index);
|
---|
1490 | for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
|
---|
1491 | pHlp->pfnSSMGetU64(pSSM, &pThis->au64RedirTable[idxRte]);
|
---|
1492 |
|
---|
1493 | if (uVersion > IOAPIC_SAVED_STATE_VERSION_NO_FLIPFLOP_MAP)
|
---|
1494 | for (uint8_t idx = 0; idx < RT_ELEMENTS(pThis->bmFlipFlop); idx++)
|
---|
1495 | pHlp->pfnSSMGetU64(pSSM, &pThis->bmFlipFlop[idx]);
|
---|
1496 |
|
---|
1497 | return VINF_SUCCESS;
|
---|
1498 | }
|
---|
1499 |
|
---|
1500 |
|
---|
1501 | /**
|
---|
1502 | * @interface_method_impl{PDMDEVREG,pfnReset}
|
---|
1503 | */
|
---|
1504 | static DECLCALLBACK(void) ioapicR3Reset(PPDMDEVINS pDevIns)
|
---|
1505 | {
|
---|
1506 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1507 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
1508 | LogFlow(("IOAPIC: ioapicR3Reset: pThis=%p\n", pThis));
|
---|
1509 |
|
---|
1510 | /* There might be devices threads calling ioapicSetIrq() in parallel, hence the lock. */
|
---|
1511 | IOAPIC_LOCK(pDevIns, pThis, pThisCC, VERR_IGNORED);
|
---|
1512 |
|
---|
1513 | pThis->uIrr = 0;
|
---|
1514 | pThis->u8Index = 0;
|
---|
1515 | pThis->u8Id = 0;
|
---|
1516 |
|
---|
1517 | for (uint8_t idxRte = 0; idxRte < RT_ELEMENTS(pThis->au64RedirTable); idxRte++)
|
---|
1518 | {
|
---|
1519 | pThis->au64RedirTable[idxRte] = IOAPIC_RTE_MASK;
|
---|
1520 | pThis->au32TagSrc[idxRte] = 0;
|
---|
1521 | }
|
---|
1522 |
|
---|
1523 | IOAPIC_UNLOCK(pDevIns, pThis, pThisCC);
|
---|
1524 | }
|
---|
1525 |
|
---|
1526 |
|
---|
1527 | /**
|
---|
1528 | * @interface_method_impl{PDMDEVREG,pfnRelocate}
|
---|
1529 | */
|
---|
1530 | static DECLCALLBACK(void) ioapicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
|
---|
1531 | {
|
---|
1532 | PIOAPICRC pThisRC = PDMINS_2_DATA_RC(pDevIns, PIOAPICRC);
|
---|
1533 | LogFlow(("IOAPIC: ioapicR3Relocate: pThis=%p offDelta=%RGi\n", PDMDEVINS_2_DATA(pDevIns, PIOAPIC), offDelta));
|
---|
1534 |
|
---|
1535 | pThisRC->pIoApicHlp += offDelta;
|
---|
1536 | }
|
---|
1537 |
|
---|
1538 |
|
---|
1539 | /**
|
---|
1540 | * @interface_method_impl{PDMDEVREG,pfnDestruct}
|
---|
1541 | */
|
---|
1542 | static DECLCALLBACK(int) ioapicR3Destruct(PPDMDEVINS pDevIns)
|
---|
1543 | {
|
---|
1544 | PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
|
---|
1545 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1546 | LogFlow(("IOAPIC: ioapicR3Destruct: pThis=%p\n", pThis));
|
---|
1547 |
|
---|
1548 | # ifndef IOAPIC_WITH_PDM_CRITSECT
|
---|
1549 | /*
|
---|
1550 | * Destroy the RTE critical section.
|
---|
1551 | */
|
---|
1552 | if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->CritSect))
|
---|
1553 | PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
|
---|
1554 | # else
|
---|
1555 | RT_NOREF_PV(pThis);
|
---|
1556 | # endif
|
---|
1557 |
|
---|
1558 | return VINF_SUCCESS;
|
---|
1559 | }
|
---|
1560 |
|
---|
1561 |
|
---|
1562 | /**
|
---|
1563 | * @interface_method_impl{PDMDEVREG,pfnConstruct}
|
---|
1564 | */
|
---|
1565 | static DECLCALLBACK(int) ioapicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
|
---|
1566 | {
|
---|
1567 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
1568 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1569 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
1570 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
1571 | LogFlow(("IOAPIC: ioapicR3Construct: pThis=%p iInstance=%d\n", pThis, iInstance));
|
---|
1572 | Assert(iInstance == 0); RT_NOREF(iInstance);
|
---|
1573 |
|
---|
1574 | /*
|
---|
1575 | * Validate and read the configuration.
|
---|
1576 | */
|
---|
1577 | PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "NumCPUs|ChipType|PCIAddress", "");
|
---|
1578 |
|
---|
1579 | /* The number of CPUs is currently unused, but left in CFGM and saved-state in case an ID of 0
|
---|
1580 | upsets some guest which we haven't yet been tested. */
|
---|
1581 | uint32_t cCpus;
|
---|
1582 | int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "NumCPUs", &cCpus, 1);
|
---|
1583 | if (RT_FAILURE(rc))
|
---|
1584 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query integer value \"NumCPUs\""));
|
---|
1585 | pThis->cCpus = (uint8_t)cCpus;
|
---|
1586 |
|
---|
1587 | char szChipType[16];
|
---|
1588 | rc = pHlp->pfnCFGMQueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "ICH9");
|
---|
1589 | if (RT_FAILURE(rc))
|
---|
1590 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query string value \"ChipType\""));
|
---|
1591 |
|
---|
1592 | rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
|
---|
1593 | if (RT_FAILURE(rc))
|
---|
1594 | return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
|
---|
1595 |
|
---|
1596 | if (!strcmp(szChipType, "ICH9"))
|
---|
1597 | {
|
---|
1598 | /* Newer 2007-ish I/O APIC integrated into ICH southbridges. */
|
---|
1599 | pThis->enmType = IOAPICTYPE_ICH9;
|
---|
1600 | pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
|
---|
1601 | pThis->u8IdMask = 0xff;
|
---|
1602 | pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
|
---|
1603 | pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
|
---|
1604 | pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_ICH9;
|
---|
1605 | pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_ICH9;
|
---|
1606 | }
|
---|
1607 | else if (!strcmp(szChipType, "DMAR"))
|
---|
1608 | {
|
---|
1609 | /* Intel DMAR compatible I/O APIC integrated into ICH southbridges. */
|
---|
1610 | /* Identical to ICH9, but interprets RTEs and MSI address and data fields differently. */
|
---|
1611 | pThis->enmType = IOAPICTYPE_DMAR;
|
---|
1612 | pThis->u8ApicVer = IOAPIC_VERSION_ICH9;
|
---|
1613 | pThis->u8IdMask = 0xff;
|
---|
1614 | pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
|
---|
1615 | pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
|
---|
1616 | pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_DMAR;
|
---|
1617 | pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_DMAR;
|
---|
1618 | }
|
---|
1619 | else if (!strcmp(szChipType, "82093AA"))
|
---|
1620 | {
|
---|
1621 | /* Older 1995-ish discrete I/O APIC, used in P6 class systems. */
|
---|
1622 | pThis->enmType = IOAPICTYPE_82093AA;
|
---|
1623 | pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
|
---|
1624 | pThis->u8IdMask = 0x0f;
|
---|
1625 | pThis->u8MaxRte = IOAPIC_MAX_RTE_INDEX;
|
---|
1626 | pThis->u8LastRteRegIdx = IOAPIC_INDIRECT_INDEX_RTE_END;
|
---|
1627 | pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
|
---|
1628 | pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
|
---|
1629 | }
|
---|
1630 | else if (!strcmp(szChipType, "82379AB"))
|
---|
1631 | {
|
---|
1632 | /* Even older 1993-ish I/O APIC built into SIO.A, used in EISA and early PCI systems. */
|
---|
1633 | /* Exact same version and behavior as 82093AA, only the number of RTEs is different. */
|
---|
1634 | pThis->enmType = IOAPICTYPE_82379AB;
|
---|
1635 | pThis->u8ApicVer = IOAPIC_VERSION_82093AA;
|
---|
1636 | pThis->u8IdMask = 0x0f;
|
---|
1637 | pThis->u8MaxRte = IOAPIC_REDUCED_MAX_RTE_INDEX;
|
---|
1638 | pThis->u8LastRteRegIdx = IOAPIC_REDUCED_INDIRECT_INDEX_RTE_END;
|
---|
1639 | pThis->u64RteWriteMask = IOAPIC_RTE_VALID_WRITE_MASK_82093AA;
|
---|
1640 | pThis->u64RteReadMask = IOAPIC_RTE_VALID_READ_MASK_82093AA;
|
---|
1641 | }
|
---|
1642 | else
|
---|
1643 | return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
|
---|
1644 | N_("I/O APIC configuration error: The \"ChipType\" value \"%s\" is unsupported"), szChipType);
|
---|
1645 | Log2(("IOAPIC: cCpus=%u fRZEnabled=%RTbool szChipType=%s\n", cCpus, pDevIns->fR0Enabled | pDevIns->fRCEnabled, szChipType));
|
---|
1646 |
|
---|
1647 | /*
|
---|
1648 | * We will use our own critical section for the IOAPIC device.
|
---|
1649 | */
|
---|
1650 | rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
|
---|
1651 | AssertRCReturn(rc, rc);
|
---|
1652 |
|
---|
1653 | # ifndef IOAPIC_WITH_PDM_CRITSECT
|
---|
1654 | /*
|
---|
1655 | * Setup the critical section to protect concurrent writes to the RTEs.
|
---|
1656 | */
|
---|
1657 | rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "IOAPIC");
|
---|
1658 | AssertRCReturn(rc, rc);
|
---|
1659 | # endif
|
---|
1660 |
|
---|
1661 | /*
|
---|
1662 | * Register the IOAPIC.
|
---|
1663 | */
|
---|
1664 | PDMIOAPICREG IoApicReg;
|
---|
1665 | IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
|
---|
1666 | IoApicReg.pfnSetIrq = ioapicSetIrq;
|
---|
1667 | IoApicReg.pfnSendMsi = ioapicSendMsi;
|
---|
1668 | IoApicReg.pfnSetEoi = ioapicSetEoi;
|
---|
1669 | IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
|
---|
1670 | rc = PDMDevHlpIoApicRegister(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
|
---|
1671 | AssertRCReturn(rc, rc);
|
---|
1672 | AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
|
---|
1673 | AssertPtr(pThisCC->pIoApicHlp->pfnLock);
|
---|
1674 | AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
|
---|
1675 | AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
|
---|
1676 | AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
|
---|
1677 |
|
---|
1678 | /*
|
---|
1679 | * Register MMIO region.
|
---|
1680 | */
|
---|
1681 | rc = PDMDevHlpMmioCreateAndMap(pDevIns, IOAPIC_MMIO_BASE_PHYSADDR, IOAPIC_MMIO_SIZE, ioapicMmioWrite, ioapicMmioRead,
|
---|
1682 | IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "I/O APIC", &pThis->hMmio);
|
---|
1683 | AssertRCReturn(rc, rc);
|
---|
1684 |
|
---|
1685 | /*
|
---|
1686 | * Register the saved state.
|
---|
1687 | */
|
---|
1688 | rc = PDMDevHlpSSMRegister(pDevIns, IOAPIC_SAVED_STATE_VERSION, sizeof(*pThis), ioapicR3SaveExec, ioapicR3LoadExec);
|
---|
1689 | AssertRCReturn(rc, rc);
|
---|
1690 |
|
---|
1691 | /*
|
---|
1692 | * Register debugger info item.
|
---|
1693 | */
|
---|
1694 | rc = PDMDevHlpDBGFInfoRegister(pDevIns, "ioapic", "Display IO APIC state.", ioapicR3DbgInfo);
|
---|
1695 | AssertRCReturn(rc, rc);
|
---|
1696 |
|
---|
1697 | /*
|
---|
1698 | * Register debugger register access.
|
---|
1699 | */
|
---|
1700 | rc = PDMDevHlpDBGFRegRegister(pDevIns, g_aRegDesc);
|
---|
1701 | AssertRCReturn(rc, rc);
|
---|
1702 |
|
---|
1703 | # ifdef VBOX_WITH_STATISTICS
|
---|
1704 | /*
|
---|
1705 | * Statistics.
|
---|
1706 | */
|
---|
1707 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in RZ.");
|
---|
1708 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in RZ.");
|
---|
1709 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqRZ, STAMTYPE_COUNTER, "RZ/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in RZ.");
|
---|
1710 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiRZ, STAMTYPE_COUNTER, "RZ/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in RZ.");
|
---|
1711 |
|
---|
1712 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in R3");
|
---|
1713 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in R3.");
|
---|
1714 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetIrqR3, STAMTYPE_COUNTER, "R3/SetIrq", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in R3.");
|
---|
1715 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetEoiR3, STAMTYPE_COUNTER, "R3/SetEoi", STAMUNIT_OCCURENCES, "Number of IOAPIC SetEoi calls in R3.");
|
---|
1716 |
|
---|
1717 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantEdgeIntr, STAMTYPE_COUNTER, "RedundantEdgeIntr", STAMUNIT_OCCURENCES, "Number of redundant edge-triggered interrupts (no IRR change).");
|
---|
1718 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRedundantLevelIntr, STAMTYPE_COUNTER, "RedundantLevelIntr", STAMUNIT_OCCURENCES, "Number of redundant level-triggered interrupts (no IRR change).");
|
---|
1719 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSuppressedLevelIntr, STAMTYPE_COUNTER, "SuppressedLevelIntr", STAMUNIT_OCCURENCES, "Number of suppressed level-triggered interrupts by remote IRR.");
|
---|
1720 |
|
---|
1721 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedIntr, STAMTYPE_COUNTER, "Iommu/RemappedIntr", STAMUNIT_OCCURENCES, "Number of interrupts remapped by the IOMMU.");
|
---|
1722 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuRemappedMsi, STAMTYPE_COUNTER, "Iommu/RemappedMsi", STAMUNIT_OCCURENCES, "Number of MSIs remapped by the IOMMU.");
|
---|
1723 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedIntr, STAMTYPE_COUNTER, "Iommu/DiscardedIntr", STAMUNIT_OCCURENCES, "Number of interrupts discarded by the IOMMU.");
|
---|
1724 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIommuDiscardedMsi, STAMTYPE_COUNTER, "Iommu/DiscardedMsi", STAMUNIT_OCCURENCES, "Number of MSIs discarded by the IOMMU.");
|
---|
1725 |
|
---|
1726 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatSetRteContention, STAMTYPE_COUNTER, "CritSect/ContentionSetRte", STAMUNIT_OCCURENCES, "Number of times the critsect is busy during RTE writes causing trips to R3.");
|
---|
1727 |
|
---|
1728 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLevelIrqSent, STAMTYPE_COUNTER, "LevelIntr/Sent", STAMUNIT_OCCURENCES, "Number of level-triggered interrupts sent to the local APIC(s).");
|
---|
1729 | PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEoiReceived, STAMTYPE_COUNTER, "LevelIntr/Recv", STAMUNIT_OCCURENCES, "Number of EOIs received for level-triggered interrupts from the local APIC(s).");
|
---|
1730 |
|
---|
1731 | for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatLevelAct); ++i)
|
---|
1732 | PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatLevelAct[i], STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Time spent in the level active state", "IntPending/%02x", i);
|
---|
1733 | # endif
|
---|
1734 | for (size_t i = 0; i < RT_ELEMENTS(pThis->aStatVectors); i++)
|
---|
1735 | PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatVectors[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
|
---|
1736 | "Number of ioapicSendMsi/pfnApicBusDeliver calls for the vector.", "Vectors/%02x", i);
|
---|
1737 |
|
---|
1738 | /*
|
---|
1739 | * Init. the device state.
|
---|
1740 | */
|
---|
1741 | LogRel(("IOAPIC: Version=%d.%d ChipType=%s\n", pThis->u8ApicVer >> 4, pThis->u8ApicVer & 0x0f, szChipType));
|
---|
1742 | ioapicR3Reset(pDevIns);
|
---|
1743 |
|
---|
1744 | return VINF_SUCCESS;
|
---|
1745 | }
|
---|
1746 |
|
---|
1747 | #else /* !IN_RING3 */
|
---|
1748 |
|
---|
1749 | /**
|
---|
1750 | * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
|
---|
1751 | */
|
---|
1752 | static DECLCALLBACK(int) ioapicRZConstruct(PPDMDEVINS pDevIns)
|
---|
1753 | {
|
---|
1754 | PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
|
---|
1755 | PIOAPIC pThis = PDMDEVINS_2_DATA(pDevIns, PIOAPIC);
|
---|
1756 | PIOAPICCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOAPICCC);
|
---|
1757 |
|
---|
1758 | int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
|
---|
1759 | AssertRCReturn(rc, rc);
|
---|
1760 |
|
---|
1761 | PDMIOAPICREG IoApicReg;
|
---|
1762 | IoApicReg.u32Version = PDM_IOAPICREG_VERSION;
|
---|
1763 | IoApicReg.pfnSetIrq = ioapicSetIrq;
|
---|
1764 | IoApicReg.pfnSendMsi = ioapicSendMsi;
|
---|
1765 | IoApicReg.pfnSetEoi = ioapicSetEoi;
|
---|
1766 | IoApicReg.u32TheEnd = PDM_IOAPICREG_VERSION;
|
---|
1767 | rc = PDMDevHlpIoApicSetUpContext(pDevIns, &IoApicReg, &pThisCC->pIoApicHlp);
|
---|
1768 | AssertRCReturn(rc, rc);
|
---|
1769 | AssertPtr(pThisCC->pIoApicHlp->pfnApicBusDeliver);
|
---|
1770 | AssertPtr(pThisCC->pIoApicHlp->pfnLock);
|
---|
1771 | AssertPtr(pThisCC->pIoApicHlp->pfnUnlock);
|
---|
1772 | AssertPtr(pThisCC->pIoApicHlp->pfnLockIsOwner);
|
---|
1773 | AssertPtr(pThisCC->pIoApicHlp->pfnIommuMsiRemap);
|
---|
1774 |
|
---|
1775 | rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, ioapicMmioWrite, ioapicMmioRead, NULL /*pvUser*/);
|
---|
1776 | AssertRCReturn(rc, rc);
|
---|
1777 |
|
---|
1778 | return VINF_SUCCESS;
|
---|
1779 | }
|
---|
1780 |
|
---|
1781 | #endif /* !IN_RING3 */
|
---|
1782 |
|
---|
1783 | /**
|
---|
1784 | * IO APIC device registration structure.
|
---|
1785 | */
|
---|
1786 | const PDMDEVREG g_DeviceIOAPIC =
|
---|
1787 | {
|
---|
1788 | /* .u32Version = */ PDM_DEVREG_VERSION,
|
---|
1789 | /* .uReserved0 = */ 0,
|
---|
1790 | /* .szName = */ "ioapic",
|
---|
1791 | /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE
|
---|
1792 | | PDM_DEVREG_FLAGS_REQUIRE_R0 | PDM_DEVREG_FLAGS_REQUIRE_RC,
|
---|
1793 | /* .fClass = */ PDM_DEVREG_CLASS_PIC,
|
---|
1794 | /* .cMaxInstances = */ 1,
|
---|
1795 | /* .uSharedVersion = */ 42,
|
---|
1796 | /* .cbInstanceShared = */ sizeof(IOAPIC),
|
---|
1797 | /* .cbInstanceCC = */ sizeof(IOAPICCC),
|
---|
1798 | /* .cbInstanceRC = */ sizeof(IOAPICRC),
|
---|
1799 | /* .cMaxPciDevices = */ 0,
|
---|
1800 | /* .cMaxMsixVectors = */ 0,
|
---|
1801 | /* .pszDescription = */ "I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
|
---|
1802 | #if defined(IN_RING3)
|
---|
1803 | /* .pszRCMod = */ "VBoxDDRC.rc",
|
---|
1804 | /* .pszR0Mod = */ "VBoxDDR0.r0",
|
---|
1805 | /* .pfnConstruct = */ ioapicR3Construct,
|
---|
1806 | /* .pfnDestruct = */ ioapicR3Destruct,
|
---|
1807 | /* .pfnRelocate = */ ioapicR3Relocate,
|
---|
1808 | /* .pfnMemSetup = */ NULL,
|
---|
1809 | /* .pfnPowerOn = */ NULL,
|
---|
1810 | /* .pfnReset = */ ioapicR3Reset,
|
---|
1811 | /* .pfnSuspend = */ NULL,
|
---|
1812 | /* .pfnResume = */ NULL,
|
---|
1813 | /* .pfnAttach = */ NULL,
|
---|
1814 | /* .pfnDetach = */ NULL,
|
---|
1815 | /* .pfnQueryInterface = */ NULL,
|
---|
1816 | /* .pfnInitComplete = */ NULL,
|
---|
1817 | /* .pfnPowerOff = */ NULL,
|
---|
1818 | /* .pfnSoftReset = */ NULL,
|
---|
1819 | /* .pfnReserved0 = */ NULL,
|
---|
1820 | /* .pfnReserved1 = */ NULL,
|
---|
1821 | /* .pfnReserved2 = */ NULL,
|
---|
1822 | /* .pfnReserved3 = */ NULL,
|
---|
1823 | /* .pfnReserved4 = */ NULL,
|
---|
1824 | /* .pfnReserved5 = */ NULL,
|
---|
1825 | /* .pfnReserved6 = */ NULL,
|
---|
1826 | /* .pfnReserved7 = */ NULL,
|
---|
1827 | #elif defined(IN_RING0)
|
---|
1828 | /* .pfnEarlyConstruct = */ NULL,
|
---|
1829 | /* .pfnConstruct = */ ioapicRZConstruct,
|
---|
1830 | /* .pfnDestruct = */ NULL,
|
---|
1831 | /* .pfnFinalDestruct = */ NULL,
|
---|
1832 | /* .pfnRequest = */ NULL,
|
---|
1833 | /* .pfnReserved0 = */ NULL,
|
---|
1834 | /* .pfnReserved1 = */ NULL,
|
---|
1835 | /* .pfnReserved2 = */ NULL,
|
---|
1836 | /* .pfnReserved3 = */ NULL,
|
---|
1837 | /* .pfnReserved4 = */ NULL,
|
---|
1838 | /* .pfnReserved5 = */ NULL,
|
---|
1839 | /* .pfnReserved6 = */ NULL,
|
---|
1840 | /* .pfnReserved7 = */ NULL,
|
---|
1841 | #elif defined(IN_RC)
|
---|
1842 | /* .pfnConstruct = */ ioapicRZConstruct,
|
---|
1843 | /* .pfnReserved0 = */ NULL,
|
---|
1844 | /* .pfnReserved1 = */ NULL,
|
---|
1845 | /* .pfnReserved2 = */ NULL,
|
---|
1846 | /* .pfnReserved3 = */ NULL,
|
---|
1847 | /* .pfnReserved4 = */ NULL,
|
---|
1848 | /* .pfnReserved5 = */ NULL,
|
---|
1849 | /* .pfnReserved6 = */ NULL,
|
---|
1850 | /* .pfnReserved7 = */ NULL,
|
---|
1851 | #else
|
---|
1852 | # error "Not in IN_RING3, IN_RING0 or IN_RC!"
|
---|
1853 | #endif
|
---|
1854 | /* .u32VersionEnd = */ PDM_DEVREG_VERSION
|
---|
1855 | };
|
---|
1856 |
|
---|
1857 |
|
---|
1858 | #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
|
---|
1859 |
|
---|