VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevFwCommon.cpp@ 82781

Last change on this file since 82781 was 81925, checked in by vboxsync, 5 years ago

DevPcBios: Set the new-style device flag. Nits. bugref:9218
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1/* $Id: DevFwCommon.cpp 81925 2019-11-18 00:28:12Z vboxsync $ */
2/** @file
3 * FwCommon - Shared firmware code (used by DevPcBios & DevEFI).
4 */
5
6/*
7 * Copyright (C) 2009-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV
23#include <VBox/vmm/pdmdev.h>
24
25#include <VBox/log.h>
26#include <VBox/err.h>
27#include <VBox/param.h>
28
29#include <iprt/asm.h>
30#include <iprt/assert.h>
31#include <iprt/buildconfig.h>
32#include <iprt/file.h>
33#include <iprt/mem.h>
34#include <iprt/string.h>
35#include <iprt/uuid.h>
36#include <iprt/system.h>
37#include <iprt/cdefs.h>
38
39#include "VBoxDD.h"
40#include "VBoxDD2.h"
41#include "DevFwCommon.h"
42
43
44/*********************************************************************************************************************************
45* Defined Constants And Macros *
46*********************************************************************************************************************************/
47
48/*
49 * Default DMI data (legacy).
50 * Don't change this information otherwise Windows guests might demand re-activation!
51 */
52
53/* type 0 -- DMI BIOS information */
54static const int32_t g_iDefDmiBIOSReleaseMajor = 0;
55static const int32_t g_iDefDmiBIOSReleaseMinor = 0;
56static const int32_t g_iDefDmiBIOSFirmwareMajor = 0;
57static const int32_t g_iDefDmiBIOSFirmwareMinor = 0;
58static const char *g_pszDefDmiBIOSVendor = "innotek GmbH";
59static const char *g_pszDefDmiBIOSVersion = "VirtualBox";
60static const char *g_pszDefDmiBIOSReleaseDate = "12/01/2006";
61/* type 1 -- DMI system information */
62static const char *g_pszDefDmiSystemVendor = "innotek GmbH";
63static const char *g_pszDefDmiSystemProduct = "VirtualBox";
64static const char *g_pszDefDmiSystemVersion = "1.2";
65static const char *g_pszDefDmiSystemSerial = "0";
66static const char *g_pszDefDmiSystemSKU = "";
67static const char *g_pszDefDmiSystemFamily = "Virtual Machine";
68/* type 2 -- DMI board information */
69static const char *g_pszDefDmiBoardVendor = "Oracle Corporation";
70static const char *g_pszDefDmiBoardProduct = "VirtualBox";
71static const char *g_pszDefDmiBoardVersion = "1.2";
72static const char *g_pszDefDmiBoardSerial = "0";
73static const char *g_pszDefDmiBoardAssetTag = "";
74static const char *g_pszDefDmiBoardLocInChass = "";
75static const int32_t g_iDefDmiBoardBoardType = 0x0A; /* Motherboard */
76/* type 3 -- DMI chassis information */
77static const char *g_pszDefDmiChassisVendor = "Oracle Corporation";
78static const int32_t g_iDefDmiChassisType = 0x01; /* ''other'', no chassis lock present */
79static const char *g_pszDefDmiChassisVersion = "";
80static const char *g_pszDefDmiChassisSerial = "";
81static const char *g_pszDefDmiChassisAssetTag = "";
82/* type 4 -- DMI processor information */
83static const char *g_pszDefDmiProcManufacturer= "GenuineIntel";
84static const char *g_pszDefDmiProcVersion = "Pentium(R) III";
85
86/** The host DMI system product value, for DmiUseHostInfo=1. */
87static char g_szHostDmiSystemProduct[64];
88/** The host DMI system version value, for DmiUseHostInfo=1. */
89static char g_szHostDmiSystemVersion[64];
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95#pragma pack(1)
96
97typedef struct SMBIOSHDR
98{
99 uint8_t au8Signature[4];
100 uint8_t u8Checksum;
101 uint8_t u8Eps;
102 uint8_t u8VersionMajor;
103 uint8_t u8VersionMinor;
104 uint16_t u16MaxStructureSize;
105 uint8_t u8EntryPointRevision;
106 uint8_t u8Pad[5];
107} *SMBIOSHDRPTR;
108AssertCompileSize(SMBIOSHDR, 16);
109
110typedef struct DMIMAINHDR
111{
112 uint8_t au8Signature[5];
113 uint8_t u8Checksum;
114 uint16_t u16TablesLength;
115 uint32_t u32TableBase;
116 uint16_t u16TableEntries;
117 uint8_t u8TableVersion;
118} *DMIMAINHDRPTR;
119AssertCompileSize(DMIMAINHDR, 15);
120
121AssertCompile(sizeof(SMBIOSHDR) + sizeof(DMIMAINHDR) <= VBOX_DMI_HDR_SIZE);
122
123/** DMI header */
124typedef struct DMIHDR
125{
126 uint8_t u8Type;
127 uint8_t u8Length;
128 uint16_t u16Handle;
129} *PDMIHDR;
130AssertCompileSize(DMIHDR, 4);
131
132/** DMI BIOS information (Type 0) */
133typedef struct DMIBIOSINF
134{
135 DMIHDR header;
136 uint8_t u8Vendor;
137 uint8_t u8Version;
138 uint16_t u16Start;
139 uint8_t u8Release;
140 uint8_t u8ROMSize;
141 uint64_t u64Characteristics;
142 uint8_t u8CharacteristicsByte1;
143 uint8_t u8CharacteristicsByte2;
144 uint8_t u8ReleaseMajor;
145 uint8_t u8ReleaseMinor;
146 uint8_t u8FirmwareMajor;
147 uint8_t u8FirmwareMinor;
148} *PDMIBIOSINF;
149AssertCompileSize(DMIBIOSINF, 0x18);
150
151/** DMI system information (Type 1) */
152typedef struct DMISYSTEMINF
153{
154 DMIHDR header;
155 uint8_t u8Manufacturer;
156 uint8_t u8ProductName;
157 uint8_t u8Version;
158 uint8_t u8SerialNumber;
159 uint8_t au8Uuid[16];
160 uint8_t u8WakeupType;
161 uint8_t u8SKUNumber;
162 uint8_t u8Family;
163} *PDMISYSTEMINF;
164AssertCompileSize(DMISYSTEMINF, 0x1b);
165
166/** DMI board (or module) information (Type 2) */
167typedef struct DMIBOARDINF
168{
169 DMIHDR header;
170 uint8_t u8Manufacturer;
171 uint8_t u8Product;
172 uint8_t u8Version;
173 uint8_t u8SerialNumber;
174 uint8_t u8AssetTag;
175 uint8_t u8FeatureFlags;
176 uint8_t u8LocationInChass;
177 uint16_t u16ChassisHandle;
178 uint8_t u8BoardType;
179 uint8_t u8cObjectHandles;
180} *PDMIBOARDINF;
181AssertCompileSize(DMIBOARDINF, 0x0f);
182
183/** DMI system enclosure or chassis type (Type 3) */
184typedef struct DMICHASSIS
185{
186 DMIHDR header;
187 uint8_t u8Manufacturer;
188 uint8_t u8Type;
189 uint8_t u8Version;
190 uint8_t u8SerialNumber;
191 uint8_t u8AssetTag;
192 uint8_t u8BootupState;
193 uint8_t u8PowerSupplyState;
194 uint8_t u8ThermalState;
195 uint8_t u8SecurityStatus;
196 /* v2.3+, currently not supported */
197 uint32_t u32OEMdefined;
198 uint8_t u8Height;
199 uint8_t u8NumPowerChords;
200 uint8_t u8ContElems;
201 uint8_t u8ContElemRecLen;
202} *PDMICHASSIS;
203AssertCompileSize(DMICHASSIS, 0x15);
204
205/** DMI processor information (Type 4) */
206typedef struct DMIPROCESSORINF
207{
208 DMIHDR header;
209 uint8_t u8SocketDesignation;
210 uint8_t u8ProcessorType;
211 uint8_t u8ProcessorFamily;
212 uint8_t u8ProcessorManufacturer;
213 uint64_t u64ProcessorID;
214 uint8_t u8ProcessorVersion;
215 uint8_t u8Voltage;
216 uint16_t u16ExternalClock;
217 uint16_t u16MaxSpeed;
218 uint16_t u16CurrentSpeed;
219 uint8_t u8Status;
220 uint8_t u8ProcessorUpgrade;
221 /* v2.1+ */
222 uint16_t u16L1CacheHandle;
223 uint16_t u16L2CacheHandle;
224 uint16_t u16L3CacheHandle;
225 /* v2.3+ */
226 uint8_t u8SerialNumber;
227 uint8_t u8AssetTag;
228 uint8_t u8PartNumber;
229 /* v2.5+ */
230 uint8_t u8CoreCount;
231 uint8_t u8CoreEnabled;
232 uint8_t u8ThreadCount;
233 uint16_t u16ProcessorCharacteristics;
234 /* v2.6+ */
235 uint16_t u16ProcessorFamily2;
236} *PDMIPROCESSORINF;
237AssertCompileSize(DMIPROCESSORINF, 0x2a);
238
239/** DMI OEM strings (Type 11) */
240typedef struct DMIOEMSTRINGS
241{
242 DMIHDR header;
243 uint8_t u8Count;
244 uint8_t u8VBoxVersion;
245 uint8_t u8VBoxRevision;
246} *PDMIOEMSTRINGS;
247AssertCompileSize(DMIOEMSTRINGS, 0x7);
248
249/** DMI OEM-specific table (Type 128) */
250typedef struct DMIOEMSPECIFIC
251{
252 DMIHDR header;
253 uint32_t u32CpuFreqKHz;
254} *PDMIOEMSPECIFIC;
255AssertCompileSize(DMIOEMSPECIFIC, 0x8);
256
257/** Physical memory array (Type 16) */
258typedef struct DMIRAMARRAY
259{
260 DMIHDR header;
261 uint8_t u8Location;
262 uint8_t u8Use;
263 uint8_t u8MemErrorCorrection;
264 uint32_t u32MaxCapacity;
265 uint16_t u16MemErrorHandle;
266 uint16_t u16NumberOfMemDevices;
267} *PDMIRAMARRAY;
268AssertCompileSize(DMIRAMARRAY, 15);
269
270/** DMI Memory Device (Type 17) */
271typedef struct DMIMEMORYDEV
272{
273 DMIHDR header;
274 uint16_t u16PhysMemArrayHandle;
275 uint16_t u16MemErrHandle;
276 uint16_t u16TotalWidth;
277 uint16_t u16DataWidth;
278 uint16_t u16Size;
279 uint8_t u8FormFactor;
280 uint8_t u8DeviceSet;
281 uint8_t u8DeviceLocator;
282 uint8_t u8BankLocator;
283 uint8_t u8MemoryType;
284 uint16_t u16TypeDetail;
285 uint16_t u16Speed;
286 uint8_t u8Manufacturer;
287 uint8_t u8SerialNumber;
288 uint8_t u8AssetTag;
289 uint8_t u8PartNumber;
290 /* v2.6+ */
291 uint8_t u8Attributes;
292} *PDMIMEMORYDEV;
293AssertCompileSize(DMIMEMORYDEV, 28);
294
295/** MPS floating pointer structure */
296typedef struct MPSFLOATPTR
297{
298 uint8_t au8Signature[4];
299 uint32_t u32MPSAddr;
300 uint8_t u8Length;
301 uint8_t u8SpecRev;
302 uint8_t u8Checksum;
303 uint8_t au8Feature[5];
304} *PMPSFLOATPTR;
305AssertCompileSize(MPSFLOATPTR, 16);
306
307/** MPS config table header */
308typedef struct MPSCFGTBLHEADER
309{
310 uint8_t au8Signature[4];
311 uint16_t u16Length;
312 uint8_t u8SpecRev;
313 uint8_t u8Checksum;
314 uint8_t au8OemId[8];
315 uint8_t au8ProductId[12];
316 uint32_t u32OemTablePtr;
317 uint16_t u16OemTableSize;
318 uint16_t u16EntryCount;
319 uint32_t u32AddrLocalApic;
320 uint16_t u16ExtTableLength;
321 uint8_t u8ExtTableChecksum;
322 uint8_t u8Reserved;
323} *PMPSCFGTBLHEADER;
324AssertCompileSize(MPSCFGTBLHEADER, 0x2c);
325
326/** MPS processor entry */
327typedef struct MPSPROCENTRY
328{
329 uint8_t u8EntryType;
330 uint8_t u8LocalApicId;
331 uint8_t u8LocalApicVersion;
332 uint8_t u8CPUFlags;
333 uint32_t u32CPUSignature;
334 uint32_t u32CPUFeatureFlags;
335 uint32_t u32Reserved[2];
336} *PMPSPROCENTRY;
337AssertCompileSize(MPSPROCENTRY, 20);
338
339/** MPS bus entry */
340typedef struct MPSBUSENTRY
341{
342 uint8_t u8EntryType;
343 uint8_t u8BusId;
344 uint8_t au8BusTypeStr[6];
345} *PMPSBUSENTRY;
346AssertCompileSize(MPSBUSENTRY, 8);
347
348/** MPS I/O-APIC entry */
349typedef struct MPSIOAPICENTRY
350{
351 uint8_t u8EntryType;
352 uint8_t u8Id;
353 uint8_t u8Version;
354 uint8_t u8Flags;
355 uint32_t u32Addr;
356} *PMPSIOAPICENTRY;
357AssertCompileSize(MPSIOAPICENTRY, 8);
358
359/** MPS I/O-Interrupt entry */
360typedef struct MPSIOINTERRUPTENTRY
361{
362 uint8_t u8EntryType;
363 uint8_t u8Type;
364 uint16_t u16Flags;
365 uint8_t u8SrcBusId;
366 uint8_t u8SrcBusIrq;
367 uint8_t u8DstIOAPICId;
368 uint8_t u8DstIOAPICInt;
369} *PMPSIOIRQENTRY;
370AssertCompileSize(MPSIOINTERRUPTENTRY, 8);
371
372#pragma pack()
373
374
375/**
376 * Calculate a simple checksum for the MPS table.
377 *
378 * @param au8Data data
379 * @param u32Length size of data
380 */
381static uint8_t fwCommonChecksum(const uint8_t * const au8Data, uint32_t u32Length)
382{
383 uint8_t u8Sum = 0;
384 for (size_t i = 0; i < u32Length; ++i)
385 u8Sum += au8Data[i];
386 return -u8Sum;
387}
388
389#if 0 /* unused */
390static bool fwCommonChecksumOk(const uint8_t * const au8Data, uint32_t u32Length)
391{
392 uint8_t u8Sum = 0;
393 for (size_t i = 0; i < u32Length; i++)
394 u8Sum += au8Data[i];
395 return (u8Sum == 0);
396}
397#endif
398
399/**
400 * Try fetch the DMI strings from the system.
401 */
402static void fwCommonUseHostDMIStrings(void)
403{
404 int rc;
405
406 rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME,
407 g_szHostDmiSystemProduct, sizeof(g_szHostDmiSystemProduct));
408 if (RT_SUCCESS(rc))
409 {
410 g_pszDefDmiSystemProduct = g_szHostDmiSystemProduct;
411 LogRel(("DMI: Using DmiSystemProduct from host: %s\n", g_szHostDmiSystemProduct));
412 }
413
414 rc = RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_VERSION,
415 g_szHostDmiSystemVersion, sizeof(g_szHostDmiSystemVersion));
416 if (RT_SUCCESS(rc))
417 {
418 g_pszDefDmiSystemVersion = g_szHostDmiSystemVersion;
419 LogRel(("DMI: Using DmiSystemVersion from host: %s\n", g_szHostDmiSystemVersion));
420 }
421}
422
423/**
424 * Construct the DMI table.
425 *
426 * @returns VBox status code.
427 * @param pDevIns The device instance.
428 * @param pTable Where to create the DMI table.
429 * @param cbMax The maximum size of the DMI table.
430 * @param pUuid Pointer to the UUID to use if the DmiUuid
431 * configuration string isn't present.
432 * @param pCfg The handle to our config node.
433 * @param cCpus Number of VCPUs.
434 * @param pcbDmiTables Size of DMI data in bytes.
435 * @param pcDmiTables Number of DMI tables.
436 */
437int FwCommonPlantDMITable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, PCRTUUID pUuid, PCFGMNODE pCfg, uint16_t cCpus,
438 uint16_t *pcbDmiTables, uint16_t *pcDmiTables)
439{
440 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
441
442 /*
443 * CFGM Hint!
444 *
445 * The macros below makes it a bit hard to figure out the config options
446 * available here. To get a quick hint, take a look a the CFGM
447 * validation in the calling code (DevEFI.cpp and DevPcBios.cpp).
448 *
449 * 32-bit signed integer CFGM options are read by DMI_READ_CFG_S32, the 2nd
450 * parameter is the CFGM value name.
451 *
452 * Strings are read by DMI_READ_CFG_STR and DMI_READ_CFG_STR_DEF, the 2nd parameter is
453 * the CFGM value name.
454 */
455#define DMI_CHECK_SIZE(cbWant) \
456 { \
457 size_t cbNeed = (size_t)(pszStr + cbWant - (char *)pTable) + 5; /* +1 for strtab terminator +4 for end-of-table entry */ \
458 if (cbNeed > cbMax) \
459 { \
460 if (fHideErrors) \
461 { \
462 LogRel(("One of the DMI strings is too long -- using default DMI data!\n")); \
463 continue; \
464 } \
465 return PDMDevHlpVMSetError(pDevIns, VERR_TOO_MUCH_DATA, RT_SRC_POS, \
466 N_("One of the DMI strings is too long. Check all bios/Dmi* configuration entries. At least %zu bytes are needed but there is no space for more than %d bytes"), cbNeed, cbMax); \
467 } \
468 }
469
470#define DMI_READ_CFG_STR_DEF(variable, name, default_value) \
471 { \
472 if (fForceDefault) \
473 pszTmp = default_value; \
474 else \
475 { \
476 rc = pHlp->pfnCFGMQueryStringDef(pCfg, name, szBuf, sizeof(szBuf), default_value); \
477 if (RT_FAILURE(rc)) \
478 { \
479 if (fHideErrors) \
480 { \
481 LogRel(("Configuration error: Querying \"" name "\" as a string failed -- using default DMI data!\n")); \
482 continue; \
483 } \
484 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
485 N_("Configuration error: Querying \"" name "\" as a string failed")); \
486 } \
487 else if (!strcmp(szBuf, "<EMPTY>")) \
488 pszTmp = ""; \
489 else \
490 pszTmp = szBuf; \
491 } \
492 if (!pszTmp[0]) \
493 variable = 0; /* empty string */ \
494 else \
495 { \
496 variable = iStrNr++; \
497 size_t cStr = strlen(pszTmp) + 1; \
498 DMI_CHECK_SIZE(cStr); \
499 memcpy(pszStr, pszTmp, cStr); \
500 pszStr += cStr ; \
501 } \
502 }
503
504#define DMI_READ_CFG_STR(variable, name) \
505 DMI_READ_CFG_STR_DEF(variable, # name, g_pszDef ## name)
506
507#define DMI_READ_CFG_S32(variable, name) \
508 { \
509 if (fForceDefault) \
510 variable = g_iDef ## name; \
511 else \
512 { \
513 rc = pHlp->pfnCFGMQueryS32Def(pCfg, # name, & variable, g_iDef ## name); \
514 if (RT_FAILURE(rc)) \
515 { \
516 if (fHideErrors) \
517 { \
518 LogRel(("Configuration error: Querying \"" # name "\" as an int failed -- using default DMI data!\n")); \
519 continue; \
520 } \
521 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS, \
522 N_("Configuration error: Querying \"" # name "\" as an int failed")); \
523 } \
524 } \
525 }
526
527#define DMI_START_STRUCT(tbl) \
528 pszStr = (char *)(tbl + 1); \
529 iStrNr = 1;
530
531#define DMI_TERM_STRUCT \
532 { \
533 *pszStr++ = '\0'; /* terminate set of text strings */ \
534 if (iStrNr == 1) \
535 *pszStr++ = '\0'; /* terminate a structure without strings */ \
536 }
537
538 bool fForceDefault = false;
539#ifdef VBOX_BIOS_DMI_FALLBACK
540 /*
541 * There will be two passes. If an error occurs during the first pass, a
542 * message will be written to the release log and we fall back to default
543 * DMI data and start a second pass.
544 */
545 bool fHideErrors = true;
546#else
547 /*
548 * There will be one pass, every error is fatal and will prevent the VM
549 * from starting.
550 */
551 bool fHideErrors = false;
552#endif
553
554 uint8_t fDmiUseHostInfo;
555 int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DmiUseHostInfo", &fDmiUseHostInfo, 0);
556 if (RT_FAILURE (rc))
557 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"DmiUseHostInfo\""));
558
559 /* Sync up with host default DMI values */
560 if (fDmiUseHostInfo)
561 fwCommonUseHostDMIStrings();
562
563 uint8_t fDmiExposeMemoryTable;
564 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DmiExposeMemoryTable", &fDmiExposeMemoryTable, 0);
565 if (RT_FAILURE (rc))
566 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"DmiExposeMemoryTable\""));
567 uint8_t fDmiExposeProcessorInf;
568 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "DmiExposeProcInf", &fDmiExposeProcessorInf, 0);
569 if (RT_FAILURE (rc))
570 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"DmiExposeProcInf\""));
571
572 for (;; fForceDefault = true, fHideErrors = false)
573 {
574 int iStrNr;
575 char szBuf[256];
576 char *pszStr = (char *)pTable;
577 char szDmiSystemUuid[64];
578 char *pszDmiSystemUuid;
579 const char *pszTmp;
580
581 if (fForceDefault)
582 pszDmiSystemUuid = NULL;
583 else
584 {
585 rc = pHlp->pfnCFGMQueryString(pCfg, "DmiSystemUuid", szDmiSystemUuid, sizeof(szDmiSystemUuid));
586 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
587 pszDmiSystemUuid = NULL;
588 else if (RT_FAILURE(rc))
589 {
590 if (fHideErrors)
591 {
592 LogRel(("Configuration error: Querying \"DmiSystemUuid\" as a string failed, using default DMI data\n"));
593 continue;
594 }
595 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
596 N_("Configuration error: Querying \"DmiSystemUuid\" as a string failed"));
597 }
598 else
599 pszDmiSystemUuid = szDmiSystemUuid;
600 }
601
602 /*********************************
603 * DMI BIOS information (Type 0) *
604 *********************************/
605 PDMIBIOSINF pBIOSInf = (PDMIBIOSINF)pszStr;
606 DMI_CHECK_SIZE(sizeof(*pBIOSInf));
607
608 pszStr = (char *)&pBIOSInf->u8ReleaseMajor;
609 pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8ReleaseMajor);
610
611 /* don't set these fields by default for legacy compatibility */
612 int iDmiBIOSReleaseMajor, iDmiBIOSReleaseMinor;
613 DMI_READ_CFG_S32(iDmiBIOSReleaseMajor, DmiBIOSReleaseMajor);
614 DMI_READ_CFG_S32(iDmiBIOSReleaseMinor, DmiBIOSReleaseMinor);
615 if (iDmiBIOSReleaseMajor != 0 || iDmiBIOSReleaseMinor != 0)
616 {
617 pszStr = (char *)&pBIOSInf->u8FirmwareMajor;
618 pBIOSInf->header.u8Length = RT_OFFSETOF(DMIBIOSINF, u8FirmwareMajor);
619 pBIOSInf->u8ReleaseMajor = iDmiBIOSReleaseMajor;
620 pBIOSInf->u8ReleaseMinor = iDmiBIOSReleaseMinor;
621
622 int iDmiBIOSFirmwareMajor, iDmiBIOSFirmwareMinor;
623 DMI_READ_CFG_S32(iDmiBIOSFirmwareMajor, DmiBIOSFirmwareMajor);
624 DMI_READ_CFG_S32(iDmiBIOSFirmwareMinor, DmiBIOSFirmwareMinor);
625 if (iDmiBIOSFirmwareMajor != 0 || iDmiBIOSFirmwareMinor != 0)
626 {
627 pszStr = (char *)(pBIOSInf + 1);
628 pBIOSInf->header.u8Length = sizeof(DMIBIOSINF);
629 pBIOSInf->u8FirmwareMajor = iDmiBIOSFirmwareMajor;
630 pBIOSInf->u8FirmwareMinor = iDmiBIOSFirmwareMinor;
631 }
632 }
633
634 iStrNr = 1;
635 pBIOSInf->header.u8Type = 0; /* BIOS Information */
636 pBIOSInf->header.u16Handle = 0x0000;
637 DMI_READ_CFG_STR(pBIOSInf->u8Vendor, DmiBIOSVendor);
638 DMI_READ_CFG_STR(pBIOSInf->u8Version, DmiBIOSVersion);
639 pBIOSInf->u16Start = 0xE000;
640 DMI_READ_CFG_STR(pBIOSInf->u8Release, DmiBIOSReleaseDate);
641 pBIOSInf->u8ROMSize = 1; /* 128K */
642 pBIOSInf->u64Characteristics = RT_BIT(4) /* ISA is supported */
643 | RT_BIT(7) /* PCI is supported */
644 | RT_BIT(15) /* Boot from CD is supported */
645 | RT_BIT(16) /* Selectable Boot is supported */
646 | RT_BIT(27) /* Int 9h, 8042 Keyboard services supported */
647 | RT_BIT(30) /* Int 10h, CGA/Mono Video Services supported */
648 /* any more?? */
649 ;
650 pBIOSInf->u8CharacteristicsByte1 = RT_BIT(0) /* ACPI is supported */
651 /* any more?? */
652 ;
653 pBIOSInf->u8CharacteristicsByte2 = 0
654 /* any more?? */
655 ;
656 DMI_TERM_STRUCT;
657
658 /***********************************
659 * DMI system information (Type 1) *
660 ***********************************/
661 PDMISYSTEMINF pSystemInf = (PDMISYSTEMINF)pszStr;
662 DMI_CHECK_SIZE(sizeof(*pSystemInf));
663 DMI_START_STRUCT(pSystemInf);
664 pSystemInf->header.u8Type = 1; /* System Information */
665 pSystemInf->header.u8Length = sizeof(*pSystemInf);
666 pSystemInf->header.u16Handle = 0x0001;
667 DMI_READ_CFG_STR(pSystemInf->u8Manufacturer, DmiSystemVendor);
668 DMI_READ_CFG_STR(pSystemInf->u8ProductName, DmiSystemProduct);
669 DMI_READ_CFG_STR(pSystemInf->u8Version, DmiSystemVersion);
670 DMI_READ_CFG_STR(pSystemInf->u8SerialNumber, DmiSystemSerial);
671
672 RTUUID uuid;
673 if (pszDmiSystemUuid)
674 {
675 rc = RTUuidFromStr(&uuid, pszDmiSystemUuid);
676 if (RT_FAILURE(rc))
677 {
678 if (fHideErrors)
679 {
680 LogRel(("Configuration error: Invalid UUID for DMI tables specified, using default DMI data\n"));
681 continue;
682 }
683 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
684 N_("Configuration error: Invalid UUID for DMI tables specified"));
685 }
686 uuid.Gen.u32TimeLow = RT_H2BE_U32(uuid.Gen.u32TimeLow);
687 uuid.Gen.u16TimeMid = RT_H2BE_U16(uuid.Gen.u16TimeMid);
688 uuid.Gen.u16TimeHiAndVersion = RT_H2BE_U16(uuid.Gen.u16TimeHiAndVersion);
689 pUuid = &uuid;
690 }
691 memcpy(pSystemInf->au8Uuid, pUuid, sizeof(RTUUID));
692
693 pSystemInf->u8WakeupType = 6; /* Power Switch */
694 DMI_READ_CFG_STR(pSystemInf->u8SKUNumber, DmiSystemSKU);
695 DMI_READ_CFG_STR(pSystemInf->u8Family, DmiSystemFamily);
696 DMI_TERM_STRUCT;
697
698 /**********************************
699 * DMI board information (Type 2) *
700 **********************************/
701 PDMIBOARDINF pBoardInf = (PDMIBOARDINF)pszStr;
702 DMI_CHECK_SIZE(sizeof(*pBoardInf));
703 DMI_START_STRUCT(pBoardInf);
704 int iDmiBoardBoardType;
705 pBoardInf->header.u8Type = 2; /* Board Information */
706 pBoardInf->header.u8Length = sizeof(*pBoardInf);
707 pBoardInf->header.u16Handle = 0x0008;
708 DMI_READ_CFG_STR(pBoardInf->u8Manufacturer, DmiBoardVendor);
709 DMI_READ_CFG_STR(pBoardInf->u8Product, DmiBoardProduct);
710 DMI_READ_CFG_STR(pBoardInf->u8Version, DmiBoardVersion);
711 DMI_READ_CFG_STR(pBoardInf->u8SerialNumber, DmiBoardSerial);
712 DMI_READ_CFG_STR(pBoardInf->u8AssetTag, DmiBoardAssetTag);
713 pBoardInf->u8FeatureFlags = RT_BIT(0) /* hosting board, e.g. motherboard */
714 ;
715 DMI_READ_CFG_STR(pBoardInf->u8LocationInChass, DmiBoardLocInChass);
716 pBoardInf->u16ChassisHandle = 0x0003; /* see type 3 */
717 DMI_READ_CFG_S32(iDmiBoardBoardType, DmiBoardBoardType);
718 pBoardInf->u8BoardType = iDmiBoardBoardType;
719 pBoardInf->u8cObjectHandles = 0;
720
721 DMI_TERM_STRUCT;
722
723 /********************************************
724 * DMI System Enclosure or Chassis (Type 3) *
725 ********************************************/
726 PDMICHASSIS pChassis = (PDMICHASSIS)pszStr;
727 DMI_CHECK_SIZE(sizeof(*pChassis));
728 pszStr = (char*)&pChassis->u32OEMdefined;
729 iStrNr = 1;
730#ifdef VBOX_WITH_DMI_CHASSIS
731 pChassis->header.u8Type = 3; /* System Enclosure or Chassis */
732#else
733 pChassis->header.u8Type = 0x7e; /* inactive */
734#endif
735 pChassis->header.u8Length = RT_OFFSETOF(DMICHASSIS, u32OEMdefined);
736 pChassis->header.u16Handle = 0x0003;
737 DMI_READ_CFG_STR(pChassis->u8Manufacturer, DmiChassisVendor);
738 int iDmiChassisType;
739 DMI_READ_CFG_S32(iDmiChassisType, DmiChassisType);
740 pChassis->u8Type = iDmiChassisType;
741 DMI_READ_CFG_STR(pChassis->u8Version, DmiChassisVersion);
742 DMI_READ_CFG_STR(pChassis->u8SerialNumber, DmiChassisSerial);
743 DMI_READ_CFG_STR(pChassis->u8AssetTag, DmiChassisAssetTag);
744 pChassis->u8BootupState = 0x03; /* safe */
745 pChassis->u8PowerSupplyState = 0x03; /* safe */
746 pChassis->u8ThermalState = 0x03; /* safe */
747 pChassis->u8SecurityStatus = 0x03; /* none XXX */
748# if 0
749 /* v2.3+, currently not supported */
750 pChassis->u32OEMdefined = 0;
751 pChassis->u8Height = 0; /* unspecified */
752 pChassis->u8NumPowerChords = 0; /* unspecified */
753 pChassis->u8ContElems = 0; /* no contained elements */
754 pChassis->u8ContElemRecLen = 0; /* no contained elements */
755# endif
756 DMI_TERM_STRUCT;
757
758 /**************************************
759 * DMI Processor Information (Type 4) *
760 **************************************/
761
762 /*
763 * This is just a dummy processor. Should we expose the real guest CPU features
764 * here? Accessing this information at this point is difficult.
765 */
766 char szSocket[32];
767 PDMIPROCESSORINF pProcessorInf = (PDMIPROCESSORINF)pszStr;
768 DMI_CHECK_SIZE(sizeof(*pProcessorInf));
769 DMI_START_STRUCT(pProcessorInf);
770 if (fDmiExposeProcessorInf)
771 pProcessorInf->header.u8Type = 4; /* Processor Information */
772 else
773 pProcessorInf->header.u8Type = 126; /* inactive structure */
774 pProcessorInf->header.u8Length = sizeof(*pProcessorInf);
775 pProcessorInf->header.u16Handle = 0x0007;
776 RTStrPrintf(szSocket, sizeof(szSocket), "Socket #%u", 0);
777 pProcessorInf->u8SocketDesignation = iStrNr++;
778 {
779 size_t cStr = strlen(szSocket) + 1;
780 DMI_CHECK_SIZE(cStr);
781 memcpy(pszStr, szSocket, cStr);
782 pszStr += cStr;
783 }
784 pProcessorInf->u8ProcessorType = 0x03; /* Central Processor */
785 pProcessorInf->u8ProcessorFamily = 0xB1; /* Pentium III with Intel SpeedStep(TM) */
786 DMI_READ_CFG_STR(pProcessorInf->u8ProcessorManufacturer, DmiProcManufacturer);
787
788 pProcessorInf->u64ProcessorID = UINT64_C(0x0FEBFBFF00010676);
789 /* Ext Family ID = 0
790 * Ext Model ID = 2
791 * Processor Type = 0
792 * Family ID = 6
793 * Model = 7
794 * Stepping = 6
795 * Features: FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, CX8,
796 * APIC, SEP, MTRR, PGE, MCA, CMOV, PAT, PSE-36,
797 * CFLSH, DS, ACPI, MMX, FXSR, SSE, SSE2, SS */
798 DMI_READ_CFG_STR(pProcessorInf->u8ProcessorVersion, DmiProcVersion);
799 pProcessorInf->u8Voltage = 0x02; /* 3.3V */
800 pProcessorInf->u16ExternalClock = 0x00; /* unknown */
801 pProcessorInf->u16MaxSpeed = 3000; /* 3GHz */
802 pProcessorInf->u16CurrentSpeed = 3000; /* 3GHz */
803 pProcessorInf->u8Status = RT_BIT(6) /* CPU socket populated */
804 | RT_BIT(0) /* CPU enabled */
805 ;
806 pProcessorInf->u8ProcessorUpgrade = 0x04; /* ZIF Socket */
807 pProcessorInf->u16L1CacheHandle = 0xFFFF; /* not specified */
808 pProcessorInf->u16L2CacheHandle = 0xFFFF; /* not specified */
809 pProcessorInf->u16L3CacheHandle = 0xFFFF; /* not specified */
810 pProcessorInf->u8SerialNumber = 0; /* not specified */
811 pProcessorInf->u8AssetTag = 0; /* not specified */
812 pProcessorInf->u8PartNumber = 0; /* not specified */
813 pProcessorInf->u8CoreCount = cCpus; /* */
814 pProcessorInf->u8CoreEnabled = cCpus;
815 pProcessorInf->u8ThreadCount = 1;
816 pProcessorInf->u16ProcessorCharacteristics
817 = RT_BIT(2); /* 64-bit capable */
818 pProcessorInf->u16ProcessorFamily2 = 0;
819 DMI_TERM_STRUCT;
820
821 /***************************************
822 * DMI Physical Memory Array (Type 16) *
823 ***************************************/
824 uint64_t const cbRamSize = MMR3PhysGetRamSize(PDMDevHlpGetVM(pDevIns));
825
826 PDMIRAMARRAY pMemArray = (PDMIRAMARRAY)pszStr;
827 DMI_CHECK_SIZE(sizeof(*pMemArray));
828 DMI_START_STRUCT(pMemArray);
829 if (fDmiExposeMemoryTable)
830 pMemArray->header.u8Type = 16; /* Physical Memory Array */
831 else
832 pMemArray->header.u8Type = 126; /* inactive structure */
833 pMemArray->header.u8Length = sizeof(*pMemArray);
834 pMemArray->header.u16Handle = 0x0005;
835 pMemArray->u8Location = 0x03; /* Motherboard */
836 pMemArray->u8Use = 0x03; /* System memory */
837 pMemArray->u8MemErrorCorrection = 0x01; /* Other */
838 if (cbRamSize / _1K > INT32_MAX)
839 {
840 /** @todo 2TB-1K limit. In such cases we probably need to provide multiple type-16 descriptors.
841 * Or use 0x8000'0000 = 'capacity unknown'? */
842 AssertLogRelMsgFailed(("DMI: RAM size %#RX64 does not fit into type-16 descriptor, clipping to %#RX64\n",
843 cbRamSize, (uint64_t)INT32_MAX * _1K));
844 pMemArray->u32MaxCapacity = INT32_MAX;
845 }
846 else
847 pMemArray->u32MaxCapacity = (int32_t)(cbRamSize / _1K); /* RAM size in K */
848 pMemArray->u16MemErrorHandle = 0xfffe; /* No error info structure */
849 pMemArray->u16NumberOfMemDevices = 1;
850 DMI_TERM_STRUCT;
851
852 /***************************************
853 * DMI Memory Device (Type 17) *
854 ***************************************/
855 PDMIMEMORYDEV pMemDev = (PDMIMEMORYDEV)pszStr;
856 DMI_CHECK_SIZE(sizeof(*pMemDev));
857 DMI_START_STRUCT(pMemDev);
858 if (fDmiExposeMemoryTable)
859 pMemDev->header.u8Type = 17; /* Memory Device */
860 else
861 pMemDev->header.u8Type = 126; /* inactive structure */
862 pMemDev->header.u8Length = sizeof(*pMemDev);
863 pMemDev->header.u16Handle = 0x0006;
864 pMemDev->u16PhysMemArrayHandle = 0x0005; /* handle of array we belong to */
865 pMemDev->u16MemErrHandle = 0xfffe; /* system doesn't provide this information */
866 pMemDev->u16TotalWidth = 0xffff; /* Unknown */
867 pMemDev->u16DataWidth = 0xffff; /* Unknown */
868 int16_t u16RamSizeM;
869 if (cbRamSize / _1M > INT16_MAX)
870 {
871 /** @todo 32G-1M limit. Provide multiple type-17 descriptors.
872 * The highest bit of u16Size must be 0 to specify 'GB' units / 1 would be 'KB' */
873 AssertLogRelMsgFailed(("DMI: RAM size %#RX64 too big for one type-17 descriptor, clipping to %#RX64\n",
874 cbRamSize, (uint64_t)INT16_MAX * _1M));
875 u16RamSizeM = INT16_MAX;
876 }
877 else
878 u16RamSizeM = (uint16_t)(cbRamSize / _1M);
879 if (u16RamSizeM == 0)
880 u16RamSizeM = 0x400; /* 1G */
881 pMemDev->u16Size = u16RamSizeM; /* RAM size */
882 pMemDev->u8FormFactor = 0x09; /* DIMM */
883 pMemDev->u8DeviceSet = 0x00; /* Not part of a device set */
884 DMI_READ_CFG_STR_DEF(pMemDev->u8DeviceLocator, " ", "DIMM 0");
885 DMI_READ_CFG_STR_DEF(pMemDev->u8BankLocator, " ", "Bank 0");
886 pMemDev->u8MemoryType = 0x03; /* DRAM */
887 pMemDev->u16TypeDetail = 0; /* Nothing special */
888 pMemDev->u16Speed = 1600; /* Unknown, shall be speed in MHz */
889 DMI_READ_CFG_STR(pMemDev->u8Manufacturer, DmiSystemVendor);
890 DMI_READ_CFG_STR_DEF(pMemDev->u8SerialNumber, " ", "00000000");
891 DMI_READ_CFG_STR_DEF(pMemDev->u8AssetTag, " ", "00000000");
892 DMI_READ_CFG_STR_DEF(pMemDev->u8PartNumber, " ", "00000000");
893 pMemDev->u8Attributes = 0; /* Unknown */
894 DMI_TERM_STRUCT;
895
896 /*****************************
897 * DMI OEM strings (Type 11) *
898 *****************************/
899 PDMIOEMSTRINGS pOEMStrings = (PDMIOEMSTRINGS)pszStr;
900 DMI_CHECK_SIZE(sizeof(*pOEMStrings));
901 DMI_START_STRUCT(pOEMStrings);
902#ifdef VBOX_WITH_DMI_OEMSTRINGS
903 pOEMStrings->header.u8Type = 0xb; /* OEM Strings */
904#else
905 pOEMStrings->header.u8Type = 126; /* inactive structure */
906#endif
907 pOEMStrings->header.u8Length = sizeof(*pOEMStrings);
908 pOEMStrings->header.u16Handle = 0x0002;
909 pOEMStrings->u8Count = 2;
910
911 char szTmp[64];
912 RTStrPrintf(szTmp, sizeof(szTmp), "vboxVer_%u.%u.%u",
913 RTBldCfgVersionMajor(), RTBldCfgVersionMinor(), RTBldCfgVersionBuild());
914 DMI_READ_CFG_STR_DEF(pOEMStrings->u8VBoxVersion, "DmiOEMVBoxVer", szTmp);
915 RTStrPrintf(szTmp, sizeof(szTmp), "vboxRev_%u", RTBldCfgRevision());
916 DMI_READ_CFG_STR_DEF(pOEMStrings->u8VBoxRevision, "DmiOEMVBoxRev", szTmp);
917 DMI_TERM_STRUCT;
918
919 /*************************************
920 * DMI OEM specific table (Type 128) *
921 ************************************/
922 PDMIOEMSPECIFIC pOEMSpecific = (PDMIOEMSPECIFIC)pszStr;
923 DMI_CHECK_SIZE(sizeof(*pOEMSpecific));
924 DMI_START_STRUCT(pOEMSpecific);
925 pOEMSpecific->header.u8Type = 0x80; /* OEM specific */
926 pOEMSpecific->header.u8Length = sizeof(*pOEMSpecific);
927 pOEMSpecific->header.u16Handle = 0x0008; /* Just next free handle */
928 pOEMSpecific->u32CpuFreqKHz = RT_H2LE_U32((uint32_t)((uint64_t)TMCpuTicksPerSecond(PDMDevHlpGetVM(pDevIns)) / 1000));
929 DMI_TERM_STRUCT;
930
931 /* End-of-table marker - includes padding to account for fixed table size. */
932 PDMIHDR pEndOfTable = (PDMIHDR)pszStr;
933 pszStr = (char *)(pEndOfTable + 1);
934 pEndOfTable->u8Type = 0x7f;
935
936 pEndOfTable->u8Length = sizeof(*pEndOfTable);
937 pEndOfTable->u16Handle = 0xFEFF;
938 *pcbDmiTables = ((uintptr_t)pszStr - (uintptr_t)pTable) + 2;
939
940 /* We currently plant 10 DMI tables. Update this if tables number changed. */
941 *pcDmiTables = 10;
942
943 /* If more fields are added here, fix the size check in DMI_READ_CFG_STR */
944
945 /* Success! */
946 break;
947 }
948
949#undef DMI_READ_CFG_STR
950#undef DMI_READ_CFG_S32
951#undef DMI_CHECK_SIZE
952 return VINF_SUCCESS;
953}
954
955/**
956 * Construct the SMBIOS and DMI headers table pointer at VM construction and
957 * reset.
958 *
959 * @param pDevIns The device instance data.
960 * @param pHdr Pointer to the header destination.
961 * @param cbDmiTables Size of all DMI tables planted in bytes.
962 * @param cNumDmiTables Number of DMI tables planted.
963 */
964void FwCommonPlantSmbiosAndDmiHdrs(PPDMDEVINS pDevIns, uint8_t *pHdr, uint16_t cbDmiTables, uint16_t cNumDmiTables)
965{
966 RT_NOREF(pDevIns);
967
968 struct
969 {
970 struct SMBIOSHDR smbios;
971 struct DMIMAINHDR dmi;
972 }
973 aBiosHeaders =
974 {
975 // The SMBIOS header
976 {
977 { 0x5f, 0x53, 0x4d, 0x5f}, // "_SM_" signature
978 0x00, // checksum
979 0x1f, // EPS length, defined by standard
980 VBOX_SMBIOS_MAJOR_VER, // SMBIOS major version
981 VBOX_SMBIOS_MINOR_VER, // SMBIOS minor version
982 VBOX_SMBIOS_MAXSS, // Maximum structure size
983 0x00, // Entry point revision
984 { 0x00, 0x00, 0x00, 0x00, 0x00 } // padding
985 },
986 // The DMI header
987 {
988 { 0x5f, 0x44, 0x4d, 0x49, 0x5f }, // "_DMI_" signature
989 0x00, // checksum
990 0, // DMI tables length
991 VBOX_DMI_TABLE_BASE, // DMI tables base
992 0, // DMI tables entries
993 VBOX_DMI_TABLE_VER, // DMI version
994 }
995 };
996
997 aBiosHeaders.dmi.u16TablesLength = cbDmiTables;
998 aBiosHeaders.dmi.u16TableEntries = cNumDmiTables;
999 /* NB: The _SM_ table checksum technically covers both the _SM_ part (16 bytes) and the _DMI_ part
1000 * (further 15 bytes). However, because the _DMI_ checksum must be zero, the _SM_ checksum can
1001 * be calculated independently.
1002 */
1003 aBiosHeaders.smbios.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.smbios, sizeof(aBiosHeaders.smbios));
1004 aBiosHeaders.dmi.u8Checksum = fwCommonChecksum((uint8_t*)&aBiosHeaders.dmi, sizeof(aBiosHeaders.dmi));
1005
1006 memcpy(pHdr, &aBiosHeaders, sizeof(aBiosHeaders));
1007}
1008
1009/**
1010 * Construct the MPS table for implanting as a ROM page.
1011 *
1012 * Only applicable if IOAPIC is active!
1013 *
1014 * See ``MultiProcessor Specification Version 1.4 (May 1997)'':
1015 * ``1.3 Scope
1016 * ...
1017 * The hardware required to implement the MP specification is kept to a
1018 * minimum, as follows:
1019 * * One or more processors that are Intel architecture instruction set
1020 * compatible, such as the CPUs in the Intel486 or Pentium processor
1021 * family.
1022 * * One or more APICs, such as the Intel 82489DX Advanced Programmable
1023 * Interrupt Controller or the integrated APIC, such as that on the
1024 * Intel Pentium 735\\90 and 815\\100 processors, together with a discrete
1025 * I/O APIC unit.''
1026 * and later:
1027 * ``4.3.3 I/O APIC Entries
1028 * The configuration table contains one or more entries for I/O APICs.
1029 * ...
1030 * I/O APIC FLAGS: EN 3:0 1 If zero, this I/O APIC is unusable, and the
1031 * operating system should not attempt to access
1032 * this I/O APIC.
1033 * At least one I/O APIC must be enabled.''
1034 *
1035 * @param pDevIns The device instance data.
1036 * @param pTable Where to write the table.
1037 * @param cbMax The maximum size of the MPS table.
1038 * @param cCpus The number of guest CPUs.
1039 */
1040void FwCommonPlantMpsTable(PPDMDEVINS pDevIns, uint8_t *pTable, unsigned cbMax, uint16_t cCpus)
1041{
1042 RT_NOREF1(cbMax);
1043
1044 /* configuration table */
1045 PMPSCFGTBLHEADER pCfgTab = (MPSCFGTBLHEADER*)pTable;
1046 memcpy(pCfgTab->au8Signature, "PCMP", 4);
1047 pCfgTab->u8SpecRev = 4; /* 1.4 */
1048 memcpy(pCfgTab->au8OemId, "VBOXCPU ", 8);
1049 memcpy(pCfgTab->au8ProductId, "VirtualBox ", 12);
1050 pCfgTab->u32OemTablePtr = 0;
1051 pCfgTab->u16OemTableSize = 0;
1052 pCfgTab->u16EntryCount = 0; /* Incremented as we go. */
1053 pCfgTab->u32AddrLocalApic = 0xfee00000;
1054 pCfgTab->u16ExtTableLength = 0;
1055 pCfgTab->u8ExtTableChecksum = 0;
1056 pCfgTab->u8Reserved = 0;
1057
1058 uint32_t u32Eax, u32Ebx, u32Ecx, u32Edx;
1059 uint32_t u32CPUSignature = 0x0520; /* default: Pentium 100 */
1060 uint32_t u32FeatureFlags = 0x0001; /* default: FPU */
1061 PDMDevHlpGetCpuId(pDevIns, 0, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1062 if (u32Eax >= 1)
1063 {
1064 PDMDevHlpGetCpuId(pDevIns, 1, &u32Eax, &u32Ebx, &u32Ecx, &u32Edx);
1065 u32CPUSignature = u32Eax & 0xfff;
1066 /* Local APIC will be enabled later so override it here. Since we provide
1067 * an MP table we have an IOAPIC and therefore a Local APIC. */
1068 u32FeatureFlags = u32Edx | X86_CPUID_FEATURE_EDX_APIC;
1069 }
1070 /* Construct MPS table for each VCPU. */
1071 PMPSPROCENTRY pProcEntry = (PMPSPROCENTRY)(pCfgTab+1);
1072 for (int i = 0; i < cCpus; i++)
1073 {
1074 pProcEntry->u8EntryType = 0; /* processor entry */
1075 pProcEntry->u8LocalApicId = i;
1076 pProcEntry->u8LocalApicVersion = 0x14;
1077 pProcEntry->u8CPUFlags = (i == 0 ? 2 /* bootstrap processor */ : 0 /* application processor */) | 1 /* enabled */;
1078 pProcEntry->u32CPUSignature = u32CPUSignature;
1079 pProcEntry->u32CPUFeatureFlags = u32FeatureFlags;
1080 pProcEntry->u32Reserved[0] =
1081 pProcEntry->u32Reserved[1] = 0;
1082 pProcEntry++;
1083 pCfgTab->u16EntryCount++;
1084 }
1085
1086 uint32_t iBusIdIsa = 0;
1087 uint32_t iBusIdPci0 = 1;
1088
1089 /* ISA bus */
1090 PMPSBUSENTRY pBusEntry = (PMPSBUSENTRY)pProcEntry;
1091 pBusEntry->u8EntryType = 1; /* bus entry */
1092 pBusEntry->u8BusId = iBusIdIsa; /* this ID is referenced by the interrupt entries */
1093 memcpy(pBusEntry->au8BusTypeStr, "ISA ", 6);
1094 pBusEntry++;
1095 pCfgTab->u16EntryCount++;
1096
1097 /* PCI bus */
1098 pBusEntry->u8EntryType = 1; /* bus entry */
1099 pBusEntry->u8BusId = iBusIdPci0; /* this ID can be referenced by the interrupt entries */
1100 memcpy(pBusEntry->au8BusTypeStr, "PCI ", 6);
1101 pBusEntry++;
1102 pCfgTab->u16EntryCount++;
1103
1104
1105 /* I/O-APIC.
1106 * MP spec: "The configuration table contains one or more entries for I/O APICs.
1107 * ... At least one I/O APIC must be enabled." */
1108 PMPSIOAPICENTRY pIOAPICEntry = (PMPSIOAPICENTRY)(pBusEntry);
1109 uint16_t iApicId = 0;
1110 pIOAPICEntry->u8EntryType = 2; /* I/O-APIC entry */
1111 pIOAPICEntry->u8Id = iApicId; /* this ID is referenced by the interrupt entries */
1112 pIOAPICEntry->u8Version = 0x11;
1113 pIOAPICEntry->u8Flags = 1 /* enable */;
1114 pIOAPICEntry->u32Addr = 0xfec00000;
1115 pCfgTab->u16EntryCount++;
1116
1117 /* Interrupt tables */
1118 /* Bus vectors */
1119 /* Note: The PIC is currently not routed to the I/O APIC. Therefore we skip
1120 * pin 0 on the I/O APIC.
1121 */
1122 PMPSIOIRQENTRY pIrqEntry = (PMPSIOIRQENTRY)(pIOAPICEntry+1);
1123 for (int iPin = 1; iPin < 16; iPin++, pIrqEntry++)
1124 {
1125 pIrqEntry->u8EntryType = 3; /* I/O interrupt entry */
1126 /*
1127 * 0 - INT, vectored interrupt,
1128 * 3 - ExtINT, vectored interrupt provided by PIC
1129 * As we emulate system with both APIC and PIC, it's needed for their coexistence.
1130 */
1131 pIrqEntry->u8Type = (iPin == 0) ? 3 : 0;
1132 pIrqEntry->u16Flags = 0; /* polarity of APIC I/O input signal = conforms to bus,
1133 trigger mode = conforms to bus */
1134 pIrqEntry->u8SrcBusId = iBusIdIsa; /* ISA bus */
1135 /* IRQ0 mapped to pin 2, other are identity mapped */
1136 /* If changing, also update PDMIsaSetIrq() and MADT */
1137 pIrqEntry->u8SrcBusIrq = (iPin == 2) ? 0 : iPin; /* IRQ on the bus */
1138 pIrqEntry->u8DstIOAPICId = iApicId; /* destination IO-APIC */
1139 pIrqEntry->u8DstIOAPICInt = iPin; /* pin on destination IO-APIC */
1140 pCfgTab->u16EntryCount++;
1141 }
1142 /* Local delivery */
1143 pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
1144 pIrqEntry->u8Type = 3; /* ExtINT */
1145 pIrqEntry->u16Flags = (1 << 2) | 1; /* active-high, edge-triggered */
1146 pIrqEntry->u8SrcBusId = iBusIdIsa;
1147 pIrqEntry->u8SrcBusIrq = 0;
1148 pIrqEntry->u8DstIOAPICId = 0xff;
1149 pIrqEntry->u8DstIOAPICInt = 0;
1150 pIrqEntry++;
1151 pCfgTab->u16EntryCount++;
1152 pIrqEntry->u8EntryType = 4; /* Local interrupt entry */
1153 pIrqEntry->u8Type = 1; /* NMI */
1154 pIrqEntry->u16Flags = (1 << 2) | 1; /* active-high, edge-triggered */
1155 pIrqEntry->u8SrcBusId = iBusIdIsa;
1156 pIrqEntry->u8SrcBusIrq = 0;
1157 pIrqEntry->u8DstIOAPICId = 0xff;
1158 pIrqEntry->u8DstIOAPICInt = 1;
1159 pIrqEntry++;
1160 pCfgTab->u16EntryCount++;
1161
1162 pCfgTab->u16Length = (uint8_t*)pIrqEntry - pTable;
1163 pCfgTab->u8Checksum = fwCommonChecksum(pTable, pCfgTab->u16Length);
1164
1165 AssertMsg(pCfgTab->u16Length < cbMax,
1166 ("VBOX_MPS_TABLE_SIZE=%d, maximum allowed size is %d",
1167 pCfgTab->u16Length, cbMax));
1168}
1169
1170/**
1171 * Construct the MPS table pointer at VM construction and reset.
1172 *
1173 * Only applicable if IOAPIC is active!
1174 *
1175 * @param pDevIns The device instance data.
1176 * @param u32MpTableAddr The MP table physical address.
1177 */
1178void FwCommonPlantMpsFloatPtr(PPDMDEVINS pDevIns, uint32_t u32MpTableAddr)
1179{
1180 MPSFLOATPTR floatPtr;
1181 floatPtr.au8Signature[0] = '_';
1182 floatPtr.au8Signature[1] = 'M';
1183 floatPtr.au8Signature[2] = 'P';
1184 floatPtr.au8Signature[3] = '_';
1185 floatPtr.u32MPSAddr = u32MpTableAddr;
1186 floatPtr.u8Length = 1; /* structure size in paragraphs */
1187 floatPtr.u8SpecRev = 4; /* MPS revision 1.4 */
1188 floatPtr.u8Checksum = 0;
1189 floatPtr.au8Feature[0] = 0;
1190 floatPtr.au8Feature[1] = 0;
1191 floatPtr.au8Feature[2] = 0;
1192 floatPtr.au8Feature[3] = 0;
1193 floatPtr.au8Feature[4] = 0;
1194 floatPtr.u8Checksum = fwCommonChecksum((uint8_t*)&floatPtr, 16);
1195 PDMDevHlpPhysWrite(pDevIns, 0x9fff0, &floatPtr, 16);
1196}
1197
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