[81089] | 1 | /* $Id: virtio.c 98103 2023-01-17 14:15:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VirtIO-SCSI host adapter driver to boot from disks.
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2019-2023 Oracle and/or its affiliates.
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[81089] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[81089] | 26 | */
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| 27 |
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| 28 | #include <stdint.h>
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| 29 | #include <string.h>
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| 30 | #include "biosint.h"
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| 31 | #include "ebda.h"
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| 32 | #include "inlines.h"
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| 33 | #include "pciutil.h"
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| 34 | #include "vds.h"
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[81407] | 35 | #include "scsi.h"
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[81089] | 36 |
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[82164] | 37 | //#define DEBUG_VIRTIO 1
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[81089] | 38 | #if DEBUG_VIRTIO
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| 39 | # define DBG_VIRTIO(...) BX_INFO(__VA_ARGS__)
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| 40 | #else
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| 41 | # define DBG_VIRTIO(...)
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| 42 | #endif
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| 43 |
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[81129] | 44 | /* The maximum CDB size. */
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| 45 | #define VIRTIO_SCSI_CDB_SZ 16
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| 46 | /** Maximum sense data to return. */
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| 47 | #define VIRTIO_SCSI_SENSE_SZ 32
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| 48 |
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[81135] | 49 | #define VIRTIO_SCSI_RING_ELEM 3
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| 50 |
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[81089] | 51 | /**
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[81129] | 52 | * VirtIO queue descriptor.
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[81089] | 53 | */
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| 54 | typedef struct
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| 55 | {
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[81129] | 56 | /** 64bit guest physical address of the buffer, split into high and low part because we work in real mode. */
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| 57 | uint32_t GCPhysBufLow;
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| 58 | uint32_t GCPhysBufHigh;
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| 59 | /** Length of the buffer in bytes. */
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| 60 | uint32_t cbBuf;
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| 61 | /** Flags for the buffer. */
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| 62 | uint16_t fFlags;
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| 63 | /** Next field where the buffer is continued if _NEXT flag is set. */
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| 64 | uint16_t idxNext;
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| 65 | } virtio_q_desc_t;
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| 66 |
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| 67 | #define VIRTIO_Q_DESC_F_NEXT 0x1
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| 68 | #define VIRTIO_Q_DESC_F_WRITE 0x2
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| 69 | #define VIRTIO_Q_DESC_F_INDIRECT 0x4
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| 70 |
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| 71 | /**
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| 72 | * VirtIO available ring.
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| 73 | */
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| 74 | typedef struct
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| 75 | {
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| 76 | /** Flags. */
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[82174] | 77 | volatile uint16_t fFlags;
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[81129] | 78 | /** Next index to write an available buffer by the driver. */
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[82174] | 79 | volatile uint16_t idxNextFree;
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[81129] | 80 | /** The ring - we only provide one entry. */
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[82174] | 81 | volatile uint16_t au16Ring[VIRTIO_SCSI_RING_ELEM];
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[81129] | 82 | /** Used event index. */
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[82174] | 83 | volatile uint16_t u16EvtUsed;
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[81129] | 84 | } virtio_q_avail_t;
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| 85 |
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| 86 | /**
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| 87 | * VirtIO queue used element.
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| 88 | */
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| 89 | typedef struct
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| 90 | {
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| 91 | /** Index of the start of the descriptor chain. */
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| 92 | uint32_t u32Id;
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| 93 | /** Number of bytes used in the descriptor chain. */
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| 94 | uint32_t cbUsed;
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| 95 | } virtio_q_used_elem_t;
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| 96 |
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| 97 | /**
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| 98 | * VirtIo used ring.
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| 99 | */
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| 100 | typedef struct
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| 101 | {
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| 102 | /** Flags. */
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[81135] | 103 | volatile uint16_t fFlags;
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[81129] | 104 | /** Index where the next entry would be written by the device. */
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[81135] | 105 | volatile uint16_t idxNextUsed;
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[81129] | 106 | /** The used ring. */
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[81135] | 107 | virtio_q_used_elem_t aRing[VIRTIO_SCSI_RING_ELEM];
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[81129] | 108 | } virtio_q_used_t;
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| 109 |
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| 110 | /**
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| 111 | * VirtIO queue structure we are using, needs to be aligned on a 16byte boundary.
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| 112 | */
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| 113 | typedef struct
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| 114 | {
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[89364] | 115 | /** The descriptor table, using 3 max. */
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| 116 | virtio_q_desc_t aDescTbl[3];
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[81129] | 117 | /** Available ring. */
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| 118 | virtio_q_avail_t AvailRing;
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| 119 | /** Used ring. */
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| 120 | virtio_q_used_t UsedRing;
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[81135] | 121 | /** The notification offset for the queue. */
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| 122 | uint32_t offNotify;
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[81129] | 123 | } virtio_q_t;
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| 124 |
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| 125 | /**
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| 126 | * VirtIO SCSI request structure passed in the queue.
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| 127 | */
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| 128 | typedef struct
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| 129 | {
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| 130 | /** The LUN to address. */
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| 131 | uint8_t au8Lun[8];
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| 132 | /** Request ID - split into low and high part. */
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| 133 | uint32_t u32IdLow;
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| 134 | uint32_t u32IdHigh;
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| 135 | /** Task attributes. */
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| 136 | uint8_t u8TaskAttr;
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| 137 | /** Priority. */
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| 138 | uint8_t u8Prio;
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| 139 | /** CRN value, usually 0. */
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| 140 | uint8_t u8Crn;
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| 141 | /** The CDB. */
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| 142 | uint8_t abCdb[VIRTIO_SCSI_CDB_SZ];
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| 143 | } virtio_scsi_req_hdr_t;
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| 144 |
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| 145 | /**
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| 146 | * VirtIO SCSI status structure filled by the device.
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| 147 | */
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| 148 | typedef struct
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| 149 | {
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| 150 | /** Returned sense length. */
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| 151 | uint32_t cbSense;
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| 152 | /** Residual amount of bytes left. */
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| 153 | uint32_t cbResidual;
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| 154 | /** Status qualifier. */
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| 155 | uint16_t u16StatusQual;
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| 156 | /** Status code. */
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| 157 | uint8_t u8Status;
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| 158 | /** Response code. */
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| 159 | uint8_t u8Response;
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| 160 | /** Sense data. */
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| 161 | uint8_t abSense[VIRTIO_SCSI_SENSE_SZ];
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| 162 | } virtio_scsi_req_sts_t;
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| 163 |
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| 164 | /**
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| 165 | * VirtIO config for the different data structures.
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| 166 | */
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| 167 | typedef struct
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| 168 | {
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[81089] | 169 | /** BAR where to find it. */
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| 170 | uint8_t u8Bar;
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| 171 | /** Padding. */
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| 172 | uint8_t abPad[3];
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| 173 | /** Offset within the bar. */
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| 174 | uint32_t u32Offset;
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| 175 | /** Length of the structure in bytes. */
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| 176 | uint32_t u32Length;
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[81129] | 177 | } virtio_bar_cfg_t;
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[81089] | 178 |
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| 179 | /**
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[81129] | 180 | * VirtIO PCI capability structure.
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[81089] | 181 | */
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| 182 | typedef struct
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| 183 | {
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[81129] | 184 | /** Capability typem should always be PCI_CAP_ID_VNDR*/
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| 185 | uint8_t u8PciCapId;
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| 186 | /** Offset where to find the next capability or 0 if last capability. */
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| 187 | uint8_t u8PciCapNext;
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| 188 | /** Size of the capability in bytes. */
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| 189 | uint8_t u8PciCapLen;
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| 190 | /** VirtIO capability type. */
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| 191 | uint8_t u8VirtIoCfgType;
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[81089] | 192 | /** BAR where to find it. */
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| 193 | uint8_t u8Bar;
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| 194 | /** Padding. */
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| 195 | uint8_t abPad[3];
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| 196 | /** Offset within the bar. */
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| 197 | uint32_t u32Offset;
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| 198 | /** Length of the structure in bytes. */
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| 199 | uint32_t u32Length;
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[81129] | 200 | } virtio_pci_cap_t;
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[81089] | 201 |
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| 202 | /**
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| 203 | * VirtIO-SCSI controller data.
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| 204 | */
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| 205 | typedef struct
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| 206 | {
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[81129] | 207 | /** The queue used - must be first for alignment reasons. */
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| 208 | virtio_q_t Queue;
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[81089] | 209 | /** The BAR configs read from the PCI configuration space, see VIRTIO_PCI_CAP_*_CFG,
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| 210 | * only use 4 because VIRTIO_PCI_CAP_PCI_CFG is not part of this. */
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| 211 | virtio_bar_cfg_t aBarCfgs[4];
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| 212 | /** The start offset in the PCI configuration space where to find the VIRTIO_PCI_CAP_PCI_CFG
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| 213 | * capability for the alternate access method to the registers. */
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| 214 | uint8_t u8PciCfgOff;
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[81135] | 215 | /** The notification offset multiplier. */
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| 216 | uint32_t u32NotifyOffMult;
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[81089] | 217 | /** PCI bus where the device is located. */
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| 218 | uint8_t u8Bus;
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| 219 | /** Device/Function number. */
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| 220 | uint8_t u8DevFn;
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[81135] | 221 | /** The current executed command structure. */
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| 222 | virtio_scsi_req_hdr_t ScsiReqHdr;
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| 223 | virtio_scsi_req_sts_t ScsiReqSts;
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[81089] | 224 | } virtio_t;
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| 225 |
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[81129] | 226 | /* The VirtIO specific data must fit into 1KB (statically allocated). */
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[81089] | 227 | ct_assert(sizeof(virtio_t) <= 1024);
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| 228 |
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| 229 | /** PCI configuration fields. */
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| 230 | #define PCI_CONFIG_CAP 0x34
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| 231 |
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| 232 | #define PCI_CAP_ID_VNDR 0x09
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| 233 |
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| 234 | #define VBOX_VIRTIO_NIL_CFG 0xff
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| 235 |
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| 236 | #define VIRTIO_PCI_CAP_COMMON_CFG 0x01
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| 237 | #define VIRTIO_PCI_CAP_NOTIFY_CFG 0x02
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| 238 | #define VIRTIO_PCI_CAP_ISR_CFG 0x03
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| 239 | #define VIRTIO_PCI_CAP_DEVICE_CFG 0x04
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| 240 | #define VIRTIO_PCI_CAP_PCI_CFG 0x05
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| 241 |
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| 242 | #define RT_BIT_32(bit) ((uint32_t)(1L << (bit)))
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| 243 |
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[81129] | 244 | #define VIRTIO_COMMON_REG_DEV_FEAT_SLCT 0x00
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| 245 | #define VIRTIO_COMMON_REG_DEV_FEAT 0x04
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| 246 | # define VIRTIO_CMN_REG_DEV_FEAT_SCSI_INOUT 0x01
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| 247 | #define VIRTIO_COMMON_REG_DRV_FEAT_SLCT 0x08
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| 248 | #define VIRTIO_COMMON_REG_DRV_FEAT 0x0c
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| 249 | #define VIRTIO_COMMON_REG_MSIX_CFG 0x10
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| 250 | #define VIRTIO_COMMON_REG_NUM_QUEUES 0x12
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| 251 | #define VIRTIO_COMMON_REG_DEV_STS 0x14
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| 252 | # define VIRTIO_CMN_REG_DEV_STS_F_RST 0x00
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| 253 | # define VIRTIO_CMN_REG_DEV_STS_F_ACK 0x01
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| 254 | # define VIRTIO_CMN_REG_DEV_STS_F_DRV 0x02
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| 255 | # define VIRTIO_CMN_REG_DEV_STS_F_DRV_OK 0x04
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| 256 | # define VIRTIO_CMN_REG_DEV_STS_F_FEAT_OK 0x08
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| 257 | # define VIRTIO_CMN_REG_DEV_STS_F_DEV_RST 0x40
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| 258 | # define VIRTIO_CMN_REG_DEV_STS_F_FAILED 0x80
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| 259 | #define VIRTIO_COMMON_REG_CFG_GEN 0x15
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[81089] | 260 |
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[81129] | 261 | #define VIRTIO_COMMON_REG_Q_SELECT 0x16
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| 262 | #define VIRTIO_COMMON_REG_Q_SIZE 0x18
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| 263 | #define VIRTIO_COMMON_REG_Q_MSIX_VEC 0x1a
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| 264 | #define VIRTIO_COMMON_REG_Q_ENABLE 0x1c
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| 265 | #define VIRTIO_COMMON_REG_Q_NOTIFY_OFF 0x1e
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| 266 | #define VIRTIO_COMMON_REG_Q_DESC 0x20
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| 267 | #define VIRTIO_COMMON_REG_Q_DRIVER 0x28
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| 268 | #define VIRTIO_COMMON_REG_Q_DEVICE 0x30
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[81089] | 269 |
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[81129] | 270 | #define VIRTIO_DEV_CFG_REG_Q_NUM 0x00
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| 271 | #define VIRTIO_DEV_CFG_REG_SEG_MAX 0x04
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| 272 | #define VIRTIO_DEV_CFG_REG_SECT_MAX 0x08
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| 273 | #define VIRTIO_DEV_CFG_REG_CMD_PER_LUN 0x0c
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| 274 | #define VIRTIO_DEV_CFG_REG_EVT_INFO_SZ 0x10
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| 275 | #define VIRTIO_DEV_CFG_REG_SENSE_SZ 0x14
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| 276 | #define VIRTIO_DEV_CFG_REG_CDB_SZ 0x18
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| 277 | #define VIRTIO_DEV_CFG_REG_MAX_CHANNEL 0x1c
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| 278 | #define VIRTIO_DEV_CFG_REG_MAX_TGT 0x1e
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| 279 | #define VIRTIO_DEV_CFG_REG_MAX_LUN 0x20
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[81089] | 280 |
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[81129] | 281 | #define VIRTIO_SCSI_Q_CONTROL 0x00
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| 282 | #define VIRTIO_SCSI_Q_EVENT 0x01
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| 283 | #define VIRTIO_SCSI_Q_REQUEST 0x02
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| 284 |
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[82164] | 285 | #define VIRTIO_SCSI_STS_RESPONSE_OK 0x00
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| 286 |
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[81135] | 287 | static void virtio_reg_set_bar_offset_length(virtio_t __far *virtio, uint8_t u8Bar, uint32_t offReg, uint32_t cb)
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[81129] | 288 | {
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| 289 | pci_write_config_byte(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + 4, u8Bar);
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| 290 | pci_write_config_dword(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + 8, offReg);
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[81135] | 291 | pci_write_config_dword(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + 12, cb);
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[81129] | 292 | }
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| 293 |
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[81135] | 294 | static void virtio_reg_common_access_prepare(virtio_t __far *virtio, uint16_t offReg, uint32_t cbAcc)
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[81129] | 295 | {
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| 296 | virtio_reg_set_bar_offset_length(virtio,
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| 297 | virtio->aBarCfgs[VIRTIO_PCI_CAP_COMMON_CFG - 1].u8Bar,
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| 298 | virtio->aBarCfgs[VIRTIO_PCI_CAP_COMMON_CFG - 1].u32Offset + offReg,
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| 299 | cbAcc);
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| 300 | }
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| 301 |
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[81135] | 302 | static void virtio_reg_dev_access_prepare(virtio_t __far *virtio, uint16_t offReg, uint32_t cbAcc)
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[81129] | 303 | {
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| 304 | virtio_reg_set_bar_offset_length(virtio,
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| 305 | virtio->aBarCfgs[VIRTIO_PCI_CAP_DEVICE_CFG - 1].u8Bar,
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| 306 | virtio->aBarCfgs[VIRTIO_PCI_CAP_DEVICE_CFG - 1].u32Offset + offReg,
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| 307 | cbAcc);
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| 308 | }
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| 309 |
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[81135] | 310 | static void virtio_reg_notify_access_prepare(virtio_t __far *virtio, uint16_t offReg, uint32_t cbAcc)
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| 311 | {
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| 312 | virtio_reg_set_bar_offset_length(virtio,
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| 313 | virtio->aBarCfgs[VIRTIO_PCI_CAP_NOTIFY_CFG - 1].u8Bar,
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| 314 | virtio->aBarCfgs[VIRTIO_PCI_CAP_NOTIFY_CFG - 1].u32Offset + offReg,
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| 315 | cbAcc);
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| 316 | }
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| 317 |
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[82164] | 318 | static void virtio_reg_isr_prepare(virtio_t __far *virtio, uint32_t cbAcc)
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| 319 | {
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| 320 | virtio_reg_set_bar_offset_length(virtio,
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| 321 | virtio->aBarCfgs[VIRTIO_PCI_CAP_ISR_CFG - 1].u8Bar,
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| 322 | virtio->aBarCfgs[VIRTIO_PCI_CAP_ISR_CFG - 1].u32Offset,
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| 323 | cbAcc);
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| 324 | }
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| 325 |
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[81129] | 326 | static uint8_t virtio_reg_common_read_u8(virtio_t __far *virtio, uint16_t offReg)
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| 327 | {
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| 328 | virtio_reg_common_access_prepare(virtio, offReg, sizeof(uint8_t));
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| 329 | return pci_read_config_byte(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t));
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| 330 | }
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| 331 |
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| 332 | static void virtio_reg_common_write_u8(virtio_t __far *virtio, uint16_t offReg, uint8_t u8Val)
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| 333 | {
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| 334 | virtio_reg_common_access_prepare(virtio, offReg, sizeof(uint8_t));
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| 335 | pci_write_config_byte(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t), u8Val);
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| 336 | }
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| 337 |
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| 338 | static uint16_t virtio_reg_common_read_u16(virtio_t __far *virtio, uint16_t offReg)
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| 339 | {
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| 340 | virtio_reg_common_access_prepare(virtio, offReg, sizeof(uint16_t));
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| 341 | return pci_read_config_word(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t));
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| 342 | }
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| 343 |
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| 344 | static void virtio_reg_common_write_u16(virtio_t __far *virtio, uint16_t offReg, uint16_t u16Val)
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| 345 | {
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| 346 | virtio_reg_common_access_prepare(virtio, offReg, sizeof(uint16_t));
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| 347 | pci_write_config_word(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t), u16Val);
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| 348 | }
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| 349 |
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| 350 | static void virtio_reg_common_write_u32(virtio_t __far *virtio, uint16_t offReg, uint32_t u32Val)
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| 351 | {
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| 352 | virtio_reg_common_access_prepare(virtio, offReg, sizeof(uint32_t));
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| 353 | pci_write_config_dword(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t), u32Val);
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| 354 | }
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| 355 |
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| 356 | static uint32_t virtio_reg_dev_cfg_read_u32(virtio_t __far *virtio, uint16_t offReg)
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| 357 | {
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| 358 | virtio_reg_dev_access_prepare(virtio, offReg, sizeof(uint32_t));
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| 359 | return pci_read_config_dword(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t));
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| 360 | }
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| 361 |
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| 362 | static void virtio_reg_dev_cfg_write_u32(virtio_t __far *virtio, uint16_t offReg, uint32_t u32Val)
|
---|
| 363 | {
|
---|
| 364 | virtio_reg_dev_access_prepare(virtio, offReg, sizeof(uint32_t));
|
---|
| 365 | pci_write_config_dword(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t), u32Val);
|
---|
| 366 | }
|
---|
| 367 |
|
---|
[81135] | 368 | static void virtio_reg_notify_write_u16(virtio_t __far *virtio, uint16_t offReg, uint16_t u16Val)
|
---|
| 369 | {
|
---|
| 370 | virtio_reg_notify_access_prepare(virtio, offReg, sizeof(uint16_t));
|
---|
| 371 | pci_write_config_word(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t), u16Val);
|
---|
| 372 | }
|
---|
| 373 |
|
---|
[82164] | 374 | static uint8_t virtio_reg_isr_read_u8(virtio_t __far *virtio)
|
---|
| 375 | {
|
---|
| 376 | virtio_reg_isr_prepare(virtio, sizeof(uint8_t));
|
---|
| 377 | return pci_read_config_byte(virtio->u8Bus, virtio->u8DevFn, virtio->u8PciCfgOff + sizeof(virtio_pci_cap_t));
|
---|
| 378 | }
|
---|
| 379 |
|
---|
[81089] | 380 | /**
|
---|
[81129] | 381 | * Converts a segment:offset pair into a 32bit physical address.
|
---|
| 382 | */
|
---|
| 383 | static uint32_t virtio_addr_to_phys(void __far *ptr)
|
---|
| 384 | {
|
---|
| 385 | return ((uint32_t)FP_SEG(ptr) << 4) + FP_OFF(ptr);
|
---|
| 386 | }
|
---|
| 387 |
|
---|
[89168] | 388 | int virtio_scsi_cmd_data_out(void __far *pvHba, uint8_t idTgt, uint8_t __far *aCDB,
|
---|
| 389 | uint8_t cbCDB, uint8_t __far *buffer, uint32_t length)
|
---|
[82164] | 390 | {
|
---|
[89168] | 391 | virtio_t __far *virtio = (virtio_t __far *)pvHba;
|
---|
[82164] | 392 | uint16_t idxUsedOld = virtio->Queue.UsedRing.idxNextUsed;
|
---|
| 393 |
|
---|
| 394 | _fmemset(&virtio->ScsiReqHdr, 0, sizeof(virtio->ScsiReqHdr));
|
---|
| 395 | _fmemset(&virtio->ScsiReqSts, 0, sizeof(virtio->ScsiReqSts));
|
---|
| 396 |
|
---|
| 397 | virtio->ScsiReqHdr.au8Lun[0] = 0x1;
|
---|
| 398 | virtio->ScsiReqHdr.au8Lun[1] = idTgt;
|
---|
| 399 | virtio->ScsiReqHdr.au8Lun[2] = 0;
|
---|
| 400 | virtio->ScsiReqHdr.au8Lun[3] = 0;
|
---|
| 401 | _fmemcpy(&virtio->ScsiReqHdr.abCdb[0], aCDB, cbCDB);
|
---|
| 402 |
|
---|
| 403 | /* Fill in the descriptors. */
|
---|
| 404 | virtio->Queue.aDescTbl[0].GCPhysBufLow = virtio_addr_to_phys(&virtio->ScsiReqHdr);
|
---|
| 405 | virtio->Queue.aDescTbl[0].GCPhysBufHigh = 0;
|
---|
| 406 | virtio->Queue.aDescTbl[0].cbBuf = sizeof(virtio->ScsiReqHdr);
|
---|
| 407 | virtio->Queue.aDescTbl[0].fFlags = VIRTIO_Q_DESC_F_NEXT;
|
---|
| 408 | virtio->Queue.aDescTbl[0].idxNext = 1;
|
---|
| 409 |
|
---|
| 410 | virtio->Queue.aDescTbl[1].GCPhysBufLow = virtio_addr_to_phys(buffer);
|
---|
| 411 | virtio->Queue.aDescTbl[1].GCPhysBufHigh = 0;
|
---|
| 412 | virtio->Queue.aDescTbl[1].cbBuf = length;
|
---|
| 413 | virtio->Queue.aDescTbl[1].fFlags = VIRTIO_Q_DESC_F_NEXT;
|
---|
[82174] | 414 | virtio->Queue.aDescTbl[1].idxNext = 2;
|
---|
[82164] | 415 |
|
---|
[82174] | 416 | virtio->Queue.aDescTbl[2].GCPhysBufLow = virtio_addr_to_phys(&virtio->ScsiReqSts);
|
---|
| 417 | virtio->Queue.aDescTbl[2].GCPhysBufHigh = 0;
|
---|
| 418 | virtio->Queue.aDescTbl[2].cbBuf = sizeof(virtio->ScsiReqSts);
|
---|
| 419 | virtio->Queue.aDescTbl[2].fFlags = VIRTIO_Q_DESC_F_WRITE; /* End of chain. */
|
---|
| 420 | virtio->Queue.aDescTbl[2].idxNext = 0;
|
---|
[82164] | 421 |
|
---|
| 422 | /* Put it into the queue. */
|
---|
[82176] | 423 | virtio->Queue.AvailRing.au16Ring[virtio->Queue.AvailRing.idxNextFree % VIRTIO_SCSI_RING_ELEM] = 0;
|
---|
[82164] | 424 | virtio->Queue.AvailRing.idxNextFree++;
|
---|
| 425 |
|
---|
| 426 | /* Notify the device about the new command. */
|
---|
| 427 | DBG_VIRTIO("VirtIO: Submitting new request, Queue.offNotify=0x%x\n", virtio->Queue.offNotify);
|
---|
[82174] | 428 | virtio_reg_notify_write_u16(virtio, virtio->Queue.offNotify, VIRTIO_SCSI_Q_REQUEST);
|
---|
[82164] | 429 |
|
---|
| 430 | /* Wait for it to complete. */
|
---|
| 431 | while (idxUsedOld == virtio->Queue.UsedRing.idxNextUsed);
|
---|
| 432 |
|
---|
| 433 | DBG_VIRTIO("VirtIO: Request complete u8Response=%u\n", virtio->ScsiReqSts.u8Response);
|
---|
| 434 |
|
---|
[82174] | 435 | /* Read ISR register to de-assert the interrupt, don't need to do anything with it. */
|
---|
[82164] | 436 | virtio_reg_isr_read_u8(virtio);
|
---|
| 437 |
|
---|
| 438 | if (virtio->ScsiReqSts.u8Response != VIRTIO_SCSI_STS_RESPONSE_OK)
|
---|
| 439 | return 4;
|
---|
| 440 |
|
---|
| 441 | return 0;
|
---|
| 442 | }
|
---|
| 443 |
|
---|
[89168] | 444 | int virtio_scsi_cmd_data_in(void __far *pvHba, uint8_t idTgt, uint8_t __far *aCDB,
|
---|
[89364] | 445 | uint8_t cbCDB, uint8_t __far *buffer, uint32_t length)
|
---|
[81135] | 446 | {
|
---|
[89168] | 447 | virtio_t __far *virtio = (virtio_t __far *)pvHba;
|
---|
[81135] | 448 | uint16_t idxUsedOld = virtio->Queue.UsedRing.idxNextUsed;
|
---|
| 449 |
|
---|
| 450 | _fmemset(&virtio->ScsiReqHdr, 0, sizeof(virtio->ScsiReqHdr));
|
---|
| 451 | _fmemset(&virtio->ScsiReqSts, 0, sizeof(virtio->ScsiReqSts));
|
---|
| 452 |
|
---|
| 453 | virtio->ScsiReqHdr.au8Lun[0] = 0x1;
|
---|
| 454 | virtio->ScsiReqHdr.au8Lun[1] = idTgt;
|
---|
| 455 | virtio->ScsiReqHdr.au8Lun[2] = 0;
|
---|
| 456 | virtio->ScsiReqHdr.au8Lun[3] = 0;
|
---|
| 457 | _fmemcpy(&virtio->ScsiReqHdr.abCdb[0], aCDB, cbCDB);
|
---|
| 458 |
|
---|
| 459 | /* Fill in the descriptors. */
|
---|
[89364] | 460 | virtio->Queue.aDescTbl[0].GCPhysBufLow = virtio_addr_to_phys(&virtio->ScsiReqHdr);
|
---|
| 461 | virtio->Queue.aDescTbl[0].GCPhysBufHigh = 0;
|
---|
| 462 | virtio->Queue.aDescTbl[0].cbBuf = sizeof(virtio->ScsiReqHdr);
|
---|
| 463 | virtio->Queue.aDescTbl[0].fFlags = VIRTIO_Q_DESC_F_NEXT;
|
---|
| 464 | virtio->Queue.aDescTbl[0].idxNext = 1;
|
---|
[81135] | 465 |
|
---|
| 466 | /* No data out buffer, the status comes right after this in the next descriptor. */
|
---|
[89364] | 467 | virtio->Queue.aDescTbl[1].GCPhysBufLow = virtio_addr_to_phys(&virtio->ScsiReqSts);
|
---|
| 468 | virtio->Queue.aDescTbl[1].GCPhysBufHigh = 0;
|
---|
| 469 | virtio->Queue.aDescTbl[1].cbBuf = sizeof(virtio->ScsiReqSts);
|
---|
| 470 | virtio->Queue.aDescTbl[1].fFlags = VIRTIO_Q_DESC_F_WRITE | VIRTIO_Q_DESC_F_NEXT;
|
---|
| 471 | virtio->Queue.aDescTbl[1].idxNext = 2;
|
---|
[81135] | 472 |
|
---|
[89364] | 473 | virtio->Queue.aDescTbl[2].GCPhysBufLow = virtio_addr_to_phys(buffer);
|
---|
| 474 | virtio->Queue.aDescTbl[2].GCPhysBufHigh = 0;
|
---|
| 475 | virtio->Queue.aDescTbl[2].cbBuf = length;
|
---|
| 476 | virtio->Queue.aDescTbl[2].fFlags = VIRTIO_Q_DESC_F_WRITE; /* End of chain. */
|
---|
| 477 | virtio->Queue.aDescTbl[2].idxNext = 0;
|
---|
[81135] | 478 |
|
---|
[82176] | 479 | /* Put it into the queue, the index is supposed to be free-running and clipped to the ring size
|
---|
| 480 | * internally. The free running index is what the driver sees. */
|
---|
| 481 | virtio->Queue.AvailRing.au16Ring[virtio->Queue.AvailRing.idxNextFree % VIRTIO_SCSI_RING_ELEM] = 0;
|
---|
[81135] | 482 | virtio->Queue.AvailRing.idxNextFree++;
|
---|
| 483 |
|
---|
| 484 | /* Notify the device about the new command. */
|
---|
| 485 | DBG_VIRTIO("VirtIO: Submitting new request, Queue.offNotify=0x%x\n", virtio->Queue.offNotify);
|
---|
[82174] | 486 | virtio_reg_notify_write_u16(virtio, virtio->Queue.offNotify, VIRTIO_SCSI_Q_REQUEST);
|
---|
[81135] | 487 |
|
---|
| 488 | /* Wait for it to complete. */
|
---|
| 489 | while (idxUsedOld == virtio->Queue.UsedRing.idxNextUsed);
|
---|
| 490 |
|
---|
[82164] | 491 | DBG_VIRTIO("VirtIO: Request complete u8Response=%u\n", virtio->ScsiReqSts.u8Response);
|
---|
[81135] | 492 |
|
---|
[82174] | 493 | /* Read ISR register to de-assert the interrupt, don't need to do anything with it. */
|
---|
[82164] | 494 | virtio_reg_isr_read_u8(virtio);
|
---|
| 495 |
|
---|
| 496 | if (virtio->ScsiReqSts.u8Response != VIRTIO_SCSI_STS_RESPONSE_OK)
|
---|
| 497 | return 4;
|
---|
| 498 |
|
---|
[81135] | 499 | return 0;
|
---|
| 500 | }
|
---|
| 501 |
|
---|
[82164] | 502 | /**
|
---|
[81089] | 503 | * Initializes the VirtIO SCSI HBA and detects attached devices.
|
---|
| 504 | */
|
---|
[89168] | 505 | static int virtio_scsi_hba_init(virtio_t __far *virtio, uint8_t u8Bus, uint8_t u8DevFn, uint8_t u8PciCapOffVirtIo)
|
---|
[81089] | 506 | {
|
---|
[89168] | 507 | uint8_t u8PciCapOff;
|
---|
| 508 | uint8_t u8DevStat;
|
---|
[81089] | 509 |
|
---|
| 510 | virtio->u8Bus = u8Bus;
|
---|
| 511 | virtio->u8DevFn = u8DevFn;
|
---|
| 512 |
|
---|
| 513 | /*
|
---|
| 514 | * Go through the config space again, read the complete config capabilities
|
---|
| 515 | * this time and fill in the data.
|
---|
| 516 | */
|
---|
[81129] | 517 | u8PciCapOff = u8PciCapOffVirtIo;
|
---|
[81089] | 518 | while (u8PciCapOff != 0)
|
---|
| 519 | {
|
---|
| 520 | uint8_t u8PciCapId = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
|
---|
| 521 | uint8_t cbPciCap = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 2); /* Capability length. */
|
---|
| 522 |
|
---|
[81129] | 523 | DBG_VIRTIO("Capability ID 0x%x at 0x%x\n", u8PciCapId, u8PciCapOff);
|
---|
| 524 |
|
---|
[81089] | 525 | if ( u8PciCapId == PCI_CAP_ID_VNDR
|
---|
[81129] | 526 | && cbPciCap >= sizeof(virtio_pci_cap_t))
|
---|
[81089] | 527 | {
|
---|
| 528 | /* Read in the config type and see what we got. */
|
---|
[81129] | 529 | uint8_t u8PciVirtioCfg = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 3);
|
---|
[81089] | 530 |
|
---|
[81129] | 531 | DBG_VIRTIO("VirtIO: CFG ID 0x%x\n", u8PciVirtioCfg);
|
---|
| 532 | switch (u8PciVirtioCfg)
|
---|
[81089] | 533 | {
|
---|
| 534 | case VIRTIO_PCI_CAP_COMMON_CFG:
|
---|
| 535 | case VIRTIO_PCI_CAP_NOTIFY_CFG:
|
---|
| 536 | case VIRTIO_PCI_CAP_ISR_CFG:
|
---|
| 537 | case VIRTIO_PCI_CAP_DEVICE_CFG:
|
---|
| 538 | {
|
---|
[81129] | 539 | virtio_bar_cfg_t __far *pBarCfg = &virtio->aBarCfgs[u8PciVirtioCfg - 1];
|
---|
[81089] | 540 |
|
---|
[81129] | 541 | pBarCfg->u8Bar = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 4);
|
---|
| 542 | pBarCfg->u32Offset = pci_read_config_dword(u8Bus, u8DevFn, u8PciCapOff + 8);
|
---|
| 543 | pBarCfg->u32Length = pci_read_config_dword(u8Bus, u8DevFn, u8PciCapOff + 12);
|
---|
[81135] | 544 | if (u8PciVirtioCfg == VIRTIO_PCI_CAP_NOTIFY_CFG)
|
---|
| 545 | {
|
---|
| 546 | virtio->u32NotifyOffMult = pci_read_config_dword(u8Bus, u8DevFn, u8PciCapOff + 16);
|
---|
| 547 | DBG_VIRTIO("VirtIO: u32NotifyOffMult 0x%x\n", virtio->u32NotifyOffMult);
|
---|
| 548 | }
|
---|
[81089] | 549 | break;
|
---|
| 550 | }
|
---|
| 551 | case VIRTIO_PCI_CAP_PCI_CFG:
|
---|
| 552 | virtio->u8PciCfgOff = u8PciCapOff;
|
---|
[81129] | 553 | DBG_VIRTIO("VirtIO PCI CAP window offset: %x\n", u8PciCapOff);
|
---|
[81089] | 554 | break;
|
---|
| 555 | default:
|
---|
[81129] | 556 | DBG_VIRTIO("VirtIO SCSI HBA with unknown PCI capability type 0x%x\n", u8PciVirtioCfg);
|
---|
[82174] | 557 | break;
|
---|
[81089] | 558 | }
|
---|
[81129] | 559 | }
|
---|
[81089] | 560 |
|
---|
[81129] | 561 | u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
|
---|
[81089] | 562 | }
|
---|
| 563 |
|
---|
[81129] | 564 | /* Reset the device. */
|
---|
| 565 | u8DevStat = VIRTIO_CMN_REG_DEV_STS_F_RST;
|
---|
| 566 | virtio_reg_common_write_u8(virtio, VIRTIO_COMMON_REG_DEV_STS, u8DevStat);
|
---|
| 567 | /* Acknowledge presence. */
|
---|
| 568 | u8DevStat |= VIRTIO_CMN_REG_DEV_STS_F_ACK;
|
---|
| 569 | virtio_reg_common_write_u8(virtio, VIRTIO_COMMON_REG_DEV_STS, u8DevStat);
|
---|
[81407] | 570 | /* Our driver knows how to operate the device. */
|
---|
[81129] | 571 | u8DevStat |= VIRTIO_CMN_REG_DEV_STS_F_DRV;
|
---|
| 572 | virtio_reg_common_write_u8(virtio, VIRTIO_COMMON_REG_DEV_STS, u8DevStat);
|
---|
[81089] | 573 |
|
---|
[81407] | 574 | #if 0
|
---|
[81129] | 575 | /* Read the feature bits and only program the VIRTIO_CMN_REG_DEV_FEAT_SCSI_INOUT bit if available. */
|
---|
| 576 | fFeatures = virtio_reg_common_read_u32(virtio, VIRTIO_COMMON_REG_DEV_FEAT);
|
---|
| 577 | fFeatures &= VIRTIO_CMN_REG_DEV_FEAT_SCSI_INOUT;
|
---|
[81407] | 578 | #endif
|
---|
[81129] | 579 |
|
---|
| 580 | /* Check that the device is sane. */
|
---|
| 581 | if ( virtio_reg_dev_cfg_read_u32(virtio, VIRTIO_DEV_CFG_REG_Q_NUM) < 1
|
---|
| 582 | || virtio_reg_dev_cfg_read_u32(virtio, VIRTIO_DEV_CFG_REG_CDB_SZ) < 16
|
---|
| 583 | || virtio_reg_dev_cfg_read_u32(virtio, VIRTIO_DEV_CFG_REG_SENSE_SZ) < 32
|
---|
| 584 | || virtio_reg_dev_cfg_read_u32(virtio, VIRTIO_DEV_CFG_REG_SECT_MAX) < 1)
|
---|
| 585 | {
|
---|
| 586 | DBG_VIRTIO("VirtIO-SCSI: Invalid SCSI device configuration, ignoring device\n");
|
---|
[89168] | 587 | return 1;
|
---|
[81129] | 588 | }
|
---|
| 589 |
|
---|
[81407] | 590 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_DRV_FEAT, VIRTIO_CMN_REG_DEV_FEAT_SCSI_INOUT);
|
---|
[81129] | 591 |
|
---|
| 592 | /* Set the features OK bit. */
|
---|
| 593 | u8DevStat |= VIRTIO_CMN_REG_DEV_STS_F_FEAT_OK;
|
---|
| 594 | virtio_reg_common_write_u8(virtio, VIRTIO_COMMON_REG_DEV_STS, u8DevStat);
|
---|
| 595 |
|
---|
| 596 | /* Read again and check the the okay bit is still set. */
|
---|
| 597 | if (!(virtio_reg_common_read_u8(virtio, VIRTIO_COMMON_REG_DEV_STS) & VIRTIO_CMN_REG_DEV_STS_F_FEAT_OK))
|
---|
| 598 | {
|
---|
| 599 | DBG_VIRTIO("VirtIO-SCSI: Device doesn't accept our feature set, ignoring device\n");
|
---|
[89168] | 600 | return 1;
|
---|
[81129] | 601 | }
|
---|
| 602 |
|
---|
| 603 | /* Disable event and control queue. */
|
---|
| 604 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_SELECT, VIRTIO_SCSI_Q_CONTROL);
|
---|
| 605 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_SIZE, 0);
|
---|
| 606 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_ENABLE, 0);
|
---|
| 607 |
|
---|
| 608 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_SELECT, VIRTIO_SCSI_Q_EVENT);
|
---|
| 609 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_SIZE, 0);
|
---|
| 610 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_ENABLE, 0);
|
---|
| 611 |
|
---|
| 612 | /* Setup the request queue. */
|
---|
| 613 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_SELECT, VIRTIO_SCSI_Q_REQUEST);
|
---|
[81135] | 614 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_SIZE, VIRTIO_SCSI_RING_ELEM);
|
---|
[81129] | 615 | virtio_reg_common_write_u16(virtio, VIRTIO_COMMON_REG_Q_ENABLE, 1);
|
---|
| 616 |
|
---|
| 617 | /* Set queue area addresses (only low part, leave high part 0). */
|
---|
| 618 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_Q_DESC, virtio_addr_to_phys(&virtio->Queue.aDescTbl[0]));
|
---|
| 619 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_Q_DESC + 4, 0);
|
---|
| 620 |
|
---|
| 621 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_Q_DRIVER, virtio_addr_to_phys(&virtio->Queue.AvailRing));
|
---|
| 622 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_Q_DRIVER + 4, 0);
|
---|
| 623 |
|
---|
| 624 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_Q_DEVICE, virtio_addr_to_phys(&virtio->Queue.UsedRing));
|
---|
| 625 | virtio_reg_common_write_u32(virtio, VIRTIO_COMMON_REG_Q_DEVICE + 4, 0);
|
---|
| 626 |
|
---|
| 627 | virtio_reg_dev_cfg_write_u32(virtio, VIRTIO_DEV_CFG_REG_CDB_SZ, VIRTIO_SCSI_CDB_SZ);
|
---|
| 628 | virtio_reg_dev_cfg_write_u32(virtio, VIRTIO_DEV_CFG_REG_SENSE_SZ, VIRTIO_SCSI_SENSE_SZ);
|
---|
| 629 |
|
---|
[81135] | 630 | DBG_VIRTIO("VirtIO: Q notify offset 0x%x\n", virtio_reg_common_read_u16(virtio, VIRTIO_COMMON_REG_Q_NOTIFY_OFF));
|
---|
| 631 | virtio->Queue.offNotify = virtio_reg_common_read_u16(virtio, VIRTIO_COMMON_REG_Q_NOTIFY_OFF) * virtio->u32NotifyOffMult;
|
---|
| 632 |
|
---|
[81129] | 633 | /* Bring the device into operational mode. */
|
---|
| 634 | u8DevStat |= VIRTIO_CMN_REG_DEV_STS_F_DRV_OK;
|
---|
| 635 | virtio_reg_common_write_u8(virtio, VIRTIO_COMMON_REG_DEV_STS, u8DevStat);
|
---|
| 636 |
|
---|
[89168] | 637 | return 0;
|
---|
[81089] | 638 | }
|
---|
| 639 |
|
---|
| 640 | /**
|
---|
| 641 | * Init the VirtIO SCSI driver and detect attached disks.
|
---|
| 642 | */
|
---|
[89364] | 643 | int virtio_scsi_init(void __far *pvHba, uint8_t u8Bus, uint8_t u8DevFn)
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[81089] | 644 | {
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[89168] | 645 | virtio_t __far *virtio = (virtio_t __far *)pvHba;
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| 646 | uint8_t u8PciCapOff;
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| 647 | uint8_t u8PciCapOffVirtIo = VBOX_VIRTIO_NIL_CFG;
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| 648 | uint8_t u8PciCapVirtioSeen = 0;
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[81089] | 649 |
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[89168] | 650 | /* Examine the capability list and search for the VirtIO specific capabilities. */
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| 651 | u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, PCI_CONFIG_CAP);
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| 652 |
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| 653 | while (u8PciCapOff != 0)
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[81089] | 654 | {
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[89168] | 655 | uint8_t u8PciCapId = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
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| 656 | uint8_t cbPciCap = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 2); /* Capability length. */
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[81089] | 657 |
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[89168] | 658 | DBG_VIRTIO("Capability ID 0x%x at 0x%x\n", u8PciCapId, u8PciCapOff);
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[81089] | 659 |
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[89168] | 660 | if ( u8PciCapId == PCI_CAP_ID_VNDR
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| 661 | && cbPciCap >= sizeof(virtio_pci_cap_t))
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[81089] | 662 | {
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[89168] | 663 | /* Read in the config type and see what we got. */
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| 664 | uint8_t u8PciVirtioCfg = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 3);
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[81089] | 665 |
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[89168] | 666 | if (u8PciCapOffVirtIo == VBOX_VIRTIO_NIL_CFG)
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| 667 | u8PciCapOffVirtIo = u8PciCapOff;
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[81089] | 668 |
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[89168] | 669 | DBG_VIRTIO("VirtIO: CFG ID 0x%x\n", u8PciVirtioCfg);
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| 670 | switch (u8PciVirtioCfg)
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[81089] | 671 | {
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[89168] | 672 | case VIRTIO_PCI_CAP_COMMON_CFG:
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| 673 | case VIRTIO_PCI_CAP_NOTIFY_CFG:
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| 674 | case VIRTIO_PCI_CAP_ISR_CFG:
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| 675 | case VIRTIO_PCI_CAP_DEVICE_CFG:
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| 676 | case VIRTIO_PCI_CAP_PCI_CFG:
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| 677 | u8PciCapVirtioSeen |= 1 << (u8PciVirtioCfg - 1);
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| 678 | break;
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| 679 | default:
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| 680 | DBG_VIRTIO("VirtIO SCSI HBA with unknown PCI capability type 0x%x\n", u8PciVirtioCfg);
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[81089] | 681 | }
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| 682 | }
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| 683 |
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[89168] | 684 | u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
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| 685 | }
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[81089] | 686 |
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[89168] | 687 | /* Initialize the controller if all required PCI capabilities where found. */
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| 688 | if ( u8PciCapOffVirtIo != VBOX_VIRTIO_NIL_CFG
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| 689 | && u8PciCapVirtioSeen == 0x1f)
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| 690 | {
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| 691 | DBG_VIRTIO("VirtIO SCSI HBA with all required capabilities at 0x%x\n", u8PciCapOffVirtIo);
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[81089] | 692 |
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[89168] | 693 | /* Enable PCI memory, I/O, bus mastering access in command register. */
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| 694 | pci_write_config_word(u8Bus, u8DevFn, 4, 0x7);
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| 695 | return virtio_scsi_hba_init(virtio, u8Bus, u8DevFn, u8PciCapOffVirtIo);
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[81089] | 696 | }
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| 697 | else
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[89168] | 698 | DBG_VIRTIO("VirtIO SCSI HBA with no usable PCI config access!\n");
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| 699 |
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| 700 | return 1;
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[81089] | 701 | }
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